cellaigs: fix function argument evaluation order

kernel/cellaigs.cc

@@ -185,50 +185,68 @@ struct AigMaker
 
 	int or_gate(int A, int B)
 	{
-		return nand_gate(not_gate(A), not_gate(B));
+		int not_a = not_gate(A);
+		int not_b = not_gate(B);
+		return nand_gate(not_a, not_b);
 	}
 
 	int nor_gate(int A, int B)
 	{
-		return and_gate(not_gate(A), not_gate(B));
+		int not_a = not_gate(A);
+		int not_b = not_gate(B);
+		return and_gate(not_a, not_b);
 	}
 
 	int xor_gate(int A, int B)
 	{
-		return nor_gate(and_gate(A, B), nor_gate(A, B));
+		int a_and_b = and_gate(A, B);
+		int a_nor_b = nor_gate(A, B);
+		return nor_gate(a_and_b, a_nor_b);
 	}
 
 	int xnor_gate(int A, int B)
 	{
-		return or_gate(and_gate(A, B), nor_gate(A, B));
+		int a_and_b = and_gate(A, B);
+		int a_nor_b = nor_gate(A, B);
+		return or_gate(a_and_b, a_nor_b);
 	}
 
 	int andnot_gate(int A, int B)
 	{
-		return and_gate(A, not_gate(B));
+		int not_b = not_gate(B);
+		return and_gate(A, not_b);
 	}
 
 	int ornot_gate(int A, int B)
 	{
-		return or_gate(A, not_gate(B));
+		int not_b = not_gate(B);
+		return or_gate(A, not_b);
 	}
 
 	int mux_gate(int A, int B, int S)
 	{
-		return or_gate(and_gate(A, not_gate(S)), and_gate(B, S));
+		int not_s = not_gate(S);
+		int a_active = and_gate(A, not_s);
+		int b_active = and_gate(B, S);
+		return or_gate(a_active, b_active);
 	}
 
-	vector<int> adder(const vector<int> &A, const vector<int> &B, int carry, vector<int> *X = nullptr, vector<int> *CO = nullptr)
+	vector<int> adder(const vector<int> &A, const vector<int> &B, int carry_in, vector<int> *X = nullptr, vector<int> *CO = nullptr)
 	{
 		vector<int> Y(GetSize(A));
 		log_assert(GetSize(A) == GetSize(B));
 		for (int i = 0; i < GetSize(A); i++) {
-			Y[i] = xor_gate(xor_gate(A[i], B[i]), carry);
-			carry = or_gate(and_gate(A[i], B[i]), and_gate(or_gate(A[i], B[i]), carry));
+			int a_xor_b = xor_gate(A[i], B[i]);
+			int a_or_b = or_gate(A[i], B[i]);
+			int a_and_b = and_gate(A[i], B[i]);
+			Y[i] = xor_gate(a_xor_b, carry_in);
+			int tmp = and_gate(a_or_b, carry_in);
+			int carry_out = or_gate(a_and_b, tmp);
 			if (X != nullptr)
-				X->at(i) = xor_gate(A[i], B[i]);
+				X->at(i) = a_xor_b;
 			if (CO != nullptr)
-				CO->at(i) = carry;
+				CO->at(i) = carry_out;
+			carry_in = carry_out;
 		}
 		return Y;
 	}
@@ -307,13 +325,13 @@ Aig::Aig(Cell *cell)
 			int A = mk.inport(ID::A, i);
 			int B = mk.inport(ID::B, i);
 			int Y = cell->type.in(ID($and), ID($_AND_))   ? mk.and_gate(A, B) :
-			        cell->type.in(ID($_NAND_))          ? mk.nand_gate(A, B) :
+			        cell->type.in(ID($_NAND_))            ? mk.nand_gate(A, B) :
 			        cell->type.in(ID($or), ID($_OR_))     ? mk.or_gate(A, B) :
-			        cell->type.in(ID($_NOR_))           ? mk.nor_gate(A, B) :
+			        cell->type.in(ID($_NOR_))             ? mk.nor_gate(A, B) :
 			        cell->type.in(ID($xor), ID($_XOR_))   ? mk.xor_gate(A, B) :
 			        cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) :
-			        cell->type.in(ID($_ANDNOT_))        ? mk.andnot_gate(A, B) :
-			        cell->type.in(ID($_ORNOT_))         ? mk.ornot_gate(A, B) : -1;
+			        cell->type.in(ID($_ANDNOT_))          ? mk.andnot_gate(A, B) :
+			        cell->type.in(ID($_ORNOT_))           ? mk.ornot_gate(A, B) : -1;
 			mk.outport(Y, ID::Y, i);
 		}
 		goto optimize;
@@ -465,7 +483,8 @@ Aig::Aig(Cell *cell)
 		int B = mk.inport(ID::B);
 		int C = mk.inport(ID::C);
 		int D = mk.inport(ID::D);
-		int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D));
+		int a_and_b = mk.and_gate(A, B);
+		int Y = mk.nor_gate(a_and_b, mk.and_gate(C, D));
 		mk.outport(Y, ID::Y);
 		goto optimize;
 	}
@@ -476,7 +495,8 @@ Aig::Aig(Cell *cell)
 		int B = mk.inport(ID::B);
 		int C = mk.inport(ID::C);
 		int D = mk.inport(ID::D);
-		int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
+		int a_or_b = mk.or_gate(A, B);
+		int Y = mk.nand_gate(a_or_b, mk.or_gate(C, D));
 		mk.outport(Y, ID::Y);
 		goto optimize;
 	}

passes/tests/test_cell.cc

@@ -1143,7 +1143,29 @@ struct TestCellPass : public Pass {
 				else
 					uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
 				if (!write_prefix.empty()) {
-					Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i));
+					string writer = "write_rtlil";
+					string suffix = "il";
+					if (techmap_cmd.compare("aigmap") == 0) {
+						// try to convert to aiger
+						Pass::call(design, techmap_cmd);
+						bool is_unconverted = false;
+						for (auto *mod : design->selected_modules())
+							for (auto *cell : mod->selected_cells())
+								if (!cell->type.in(ID::$_NOT_, ID::$_AND_)) {
+									is_unconverted = true;
+									break;
+								}
+						if (is_unconverted) {
+							// skip unconverted cells
+							log_warning("Skipping %s\n", cell_type);
+							delete design;
+							break;
+						} else {
+							writer = "write_aiger -ascii";
+							suffix = "aag";
+						}
+					}
+					Pass::call(design, stringf("%s %s_%s_%05d.%s", writer, write_prefix, cell_type.c_str()+1, i, suffix));
 				} else if (edges) {
 					Pass::call(design, "dump gold");
 					run_edges_test(design, verbose);

tests/aiger/.gitignore

@@ -1,2 +1,3 @@
 /*_ref.v
 /neg.out/
+/gate/

tests/aiger/gold/__ANDNOT__00000.aag

@@ -0,0 +1,7 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 5 2
+c
+Generated by Yosys

tests/aiger/gold/__AND__00000.aag

@@ -0,0 +1,7 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 4 2
+c
+Generated by Yosys

tests/aiger/gold/__AOI3__00000.aag

@@ -0,0 +1,9 @@
+aag 5 3 0 1 2
+2
+4
+6
+10
+8 4 2
+10 9 7
+c
+Generated by Yosys

tests/aiger/gold/__AOI4__00000.aag

@@ -0,0 +1,11 @@
+aag 7 4 0 1 3
+2
+4
+6
+8
+14
+10 4 2
+12 8 6
+14 13 11
+c
+Generated by Yosys

tests/aiger/gold/__BUF__00000.aag

@@ -0,0 +1,5 @@
+aag 1 1 0 1 0
+2
+2
+c
+Generated by Yosys

tests/aiger/gold/__MUX__00000.aag

@@ -0,0 +1,10 @@
+aag 6 3 0 1 3
+2
+4
+6
+13
+8 7 2
+10 6 4
+12 11 9
+c
+Generated by Yosys

tests/aiger/gold/__NAND__00000.aag

@@ -0,0 +1,7 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 4 2
+c
+Generated by Yosys

tests/aiger/gold/__NMUX__00000.aag

@@ -0,0 +1,10 @@
+aag 6 3 0 1 3
+2
+4
+6
+12
+8 7 2
+10 6 4
+12 11 9
+c
+Generated by Yosys

tests/aiger/gold/__NOR__00000.aag

@@ -0,0 +1,7 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 5 3
+c
+Generated by Yosys

tests/aiger/gold/__NOT__00000.aag

@@ -0,0 +1,5 @@
+aag 1 1 0 1 0
+2
+3
+c
+Generated by Yosys

tests/aiger/gold/__OAI3__00000.aag

@@ -0,0 +1,9 @@
+aag 5 3 0 1 2
+2
+4
+6
+11
+8 5 3
+10 9 6
+c
+Generated by Yosys

tests/aiger/gold/__OAI4__00000.aag

@@ -0,0 +1,11 @@
+aag 7 4 0 1 3
+2
+4
+6
+8
+15
+10 5 3
+12 9 7
+14 13 11
+c
+Generated by Yosys

tests/aiger/gold/__ORNOT__00000.aag

@@ -0,0 +1,7 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 4 3
+c
+Generated by Yosys

tests/aiger/gold/__OR__00000.aag

@@ -0,0 +1,7 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 5 3
+c
+Generated by Yosys

tests/aiger/gold/__XNOR__00000.aag

@@ -0,0 +1,9 @@
+aag 5 2 0 1 3
+2
+4
+11
+6 4 2
+8 5 3
+10 9 7
+c
+Generated by Yosys

tests/aiger/gold/__XOR__00000.aag

@@ -0,0 +1,9 @@
+aag 5 2 0 1 3
+2
+4
+10
+6 4 2
+8 5 3
+10 9 7
+c
+Generated by Yosys

tests/aiger/gold/_add_00000.aag

@@ -0,0 +1,62 @@
+aag 51 4 0 8 47
+2
+4
+6
+8
+14
+30
+42
+54
+66
+78
+90
+102
+10 6 2
+12 7 3
+14 13 11
+16 6 2
+18 8 4
+20 9 5
+22 21 19
+24 22 16
+26 21 19
+28 27 11
+30 29 25
+32 21 16
+34 33 19
+36 35 22
+38 33 19
+40 38 27
+42 41 37
+44 35 21
+46 45 19
+48 47 22
+50 45 19
+52 50 27
+54 53 49
+56 47 21
+58 57 19
+60 59 22
+62 57 19
+64 62 27
+66 65 61
+68 59 21
+70 69 19
+72 71 22
+74 69 19
+76 74 27
+78 77 73
+80 71 21
+82 81 19
+84 83 22
+86 81 19
+88 86 27
+90 89 85
+92 83 21
+94 93 19
+96 95 22
+98 93 19
+100 98 27
+102 101 97
+c
+Generated by Yosys