proc_mux: use assignment action locations for mux src

backends/cxxrtl/cxxrtl_backend.cc

@@ -494,8 +494,8 @@ struct FlowGraph {
 	void add_case_rule_defs_uses(Node *node, const RTLIL::CaseRule *case_)
 	{
 		for (auto &action : case_->actions) {
-			add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
-			add_uses(node, action.second);
+			add_defs(node, action.lhs, /*is_ff=*/false, /*inlinable=*/false);
+			add_uses(node, action.rhs);
 		}
 		for (auto sub_switch : case_->switches) {
 			add_uses(node, sub_switch->signal);
@@ -512,10 +512,10 @@ struct FlowGraph {
 		for (auto sync : process->syncs) {
 			for (auto &action : sync->actions) {
 				if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
-					add_defs(node, action.first, /*is_ff=*/true,  /*inlinable=*/false);
+					add_defs(node, action.lhs, /*is_ff=*/true,  /*inlinable=*/false);
 				else
-					add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
-				add_uses(node, action.second);
+					add_defs(node, action.lhs, /*is_ff=*/false, /*inlinable=*/false);
+				add_uses(node, action.rhs);
 			}
 			for (auto &memwr : sync->mem_write_actions) {
 				add_uses(node, memwr.address);
@@ -1609,12 +1609,12 @@ struct CxxrtlWorker {
 				collect_sigspec_rhs(port.second, for_debug, cells);
 	}
 
-	void dump_assign(const RTLIL::SigSig &sigsig, bool for_debug = false)
+	void dump_assign(const RTLIL::SyncAction &action, bool for_debug = false)
 	{
 		f << indent;
-		dump_sigspec_lhs(sigsig.first, for_debug);
+		dump_sigspec_lhs(action.lhs, for_debug);
 		f << " = ";
-		dump_sigspec_rhs(sigsig.second, for_debug);
+		dump_sigspec_rhs(action.rhs, for_debug);
 		f << ";\n";
 	}
 

backends/rtlil/rtlil_backend.cc

@@ -193,7 +193,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
 
 void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
 {
-	for (const auto& [lhs, rhs] : cs->actions) {
+	for (const auto& [lhs, rhs, _] : cs->actions) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, lhs);
 		f << stringf(" ");
@@ -247,7 +247,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
 	case RTLIL::STi: f << stringf("init\n"); break;
 	}
 
-	for (const auto& [lhs, rhs] : sy->actions) {
+	for (const auto& [lhs, rhs, _] : sy->actions) {
 		f << stringf("%s  update ", indent);
 		dump_sigspec(f, lhs);
 		f << stringf(" ");
@@ -379,8 +379,11 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
 		for (auto* module : design->modules()) {
 			if (design->selected_whole_module(module->name))
 				flag_m = true;
-			if (design->selected(module))
+			if (design->selected(module)) {
 				count_selected_mods++;
+				if (module->has_processes())
+					log_warning("Module %s contains processes. Case action sources attributes will be lost.\n", log_id(module));
+			}
 		}
 		if (count_selected_mods > 1)
 			flag_m = true;

backends/verilog/verilog_backend.cc

@@ -2131,13 +2131,14 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs)
 {
 	for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
-		if (it->first.size() == 0)
+		if (it->lhs.size() == 0)
 			continue;
 		f << stringf("%s  ", indent);
-		dump_sigspec(f, it->first);
+		dump_sigspec(f, it->lhs);
 		f << stringf(" = ");
-		dump_sigspec(f, it->second);
+		dump_sigspec(f, it->rhs);
 		f << stringf(";\n");
+		// TODO
 	}
 }
 
@@ -2268,7 +2269,7 @@ void case_body_find_regs(RTLIL::CaseRule *cs)
 		case_body_find_regs(*it2);
 
 	for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
-		for (auto &c : it->first.chunks())
+		for (auto &c : it->lhs.chunks())
 			if (c.wire != NULL)
 				reg_wires.insert(c.wire->name);
 	}
@@ -2280,7 +2281,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 		case_body_find_regs(&proc->root_case);
 		for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
 		for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
-			for (auto &c : it2->first.chunks())
+			for (auto &c : it2->lhs.chunks())
 				if (c.wire != NULL)
 					reg_wires.insert(c.wire->name);
 		}
@@ -2337,12 +2338,12 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 		}
 
 		for (auto it = sync->actions.begin(); it != sync->actions.end(); ++it) {
-			if (it->first.size() == 0)
+			if (it->lhs.size() == 0)
 				continue;
 			f << stringf("%s  ", indent);
-			dump_sigspec(f, it->first);
+			dump_sigspec(f, it->lhs);
 			f << stringf(" <= ");
-			dump_sigspec(f, it->second);
+			dump_sigspec(f, it->rhs);
 			f << stringf(";\n");
 		}
 

docs/source/cell/word_mux.rst

@@ -16,7 +16,7 @@ value from the ``B`` input is sent to the output. So the `$mux` cell implements
 the function :verilog:`Y = S ? B : A`.
 
 The `$pmux` cell is used to multiplex between many inputs using a one-hot select
-signal. Cells of this type have a ``WIDTH`` and a ``S_WIDTH`` parameter and
+signal. Cells of this type have a ``WIDTH`` and an ``S_WIDTH`` parameter and
 inputs ``A``, ``B``, and ``S`` and an output ``Y``. The ``S`` input is
 ``S_WIDTH`` bits wide. The ``A`` input and the output are both ``WIDTH`` bits
 wide and the ``B`` input is ``WIDTH*S_WIDTH`` bits wide. When all bits of ``S``

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -300,7 +300,7 @@ example, calling :yoscrypt:`dump $2` after the :yoscrypt:`cd example` above:
 
 .. literalinclude:: /code_examples/show/example.out
    :language: RTLIL
-   :start-after: yosys [example]> dump
+   :start-after: Warning: Module example contains processes. Case action sources attributes will be lost.
    :end-before: yosys [example]> cd
    :dedent:
    :caption: Output of :yoscrypt:`dump $2` after :numref:`lscd`

frontends/ast/genrtlil.cc

@@ -382,7 +382,7 @@ struct AST_INTERNAL::ProcessGenerator
 		if (found_anyedge_syncs) {
 			if (found_global_syncs)
 				always->input_error("Found non-synthesizable event list!\n");
-			log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string());
+			log("Note: Assuming pure combinatorial block at %s in\n", always->location.to_string());
 			log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
 			log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
 		}
@@ -402,22 +402,22 @@ struct AST_INTERNAL::ProcessGenerator
 				syncrule->signal = child->children[0]->genRTLIL();
 				if (GetSize(syncrule->signal) != 1)
 					always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n");
-				addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
+				addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, child.get(), true);
 				proc->syncs.push_back(syncrule);
 			}
 		if (proc->syncs.empty()) {
 			RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
 			syncrule->type = found_global_syncs ? RTLIL::STg : RTLIL::STa;
 			syncrule->signal = RTLIL::SigSpec();
-			addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
+			addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, always.get(), true);
 			proc->syncs.push_back(syncrule);
 		}
 
 		// create initial assignments for the temporary signals
 		if ((flag_nolatches || always->get_bool_attribute(ID::nolatches) || current_module->get_bool_attribute(ID::nolatches)) && !found_clocked_sync) {
 			subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
 		} else {
-			addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
+			addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from, always.get());
 		}
 
 		// process the AST
@@ -441,7 +441,8 @@ struct AST_INTERNAL::ProcessGenerator
 				RTLIL::SigSpec lhs = init_lvalue_c;
 				RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
 				remove_unwanted_lvalue_bits(lhs, rhs);
-				sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
+				// TODO
+				sync->actions.push_back({lhs, rhs, Const("")});
 				offset += lhs.size();
 			}
 		}
@@ -548,7 +549,7 @@ struct AST_INTERNAL::ProcessGenerator
 	void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
 	{
 		for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
-			it->first.remove2(pattern, &it->second);
+			it->lhs.remove2(pattern, &it->rhs);
 
 		for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
 			for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
@@ -557,7 +558,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 	// add an assignment (aka "action") but split it up in chunks. this way huge assignments
 	// are avoided and the generated $mux cells have a more "natural" size.
-	void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
+	void addChunkActions(std::vector<RTLIL::SyncAction> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, AstNode* ast, bool inSyncRule = false)
 	{
 		if (inSyncRule && initSyncSignals.size() > 0) {
 			init_lvalue.append(lvalue.extract(initSyncSignals));
@@ -573,7 +574,7 @@ struct AST_INTERNAL::ProcessGenerator
 			if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
 				rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
 			remove_unwanted_lvalue_bits(lhs, rhs);
-			actions.push_back(RTLIL::SigSig(lhs, rhs));
+			actions.push_back({lhs, rhs, ast ? ast->loc_string() : ""});
 			offset += lhs.size();
 		}
 	}
@@ -613,7 +614,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 				removeSignalFromCaseTree(lvalue, current_case);
 				remove_unwanted_lvalue_bits(lvalue, rvalue);
-				current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
+				current_case->actions.push_back({lvalue, rvalue, ast->loc_string()});
 			}
 			break;
 
@@ -657,18 +658,25 @@ struct AST_INTERNAL::ProcessGenerator
 						subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
 
 					RTLIL::CaseRule *backup_case = current_case;
+					// here
 					current_case = new RTLIL::CaseRule;
-					set_src_attr(current_case, child.get());
+					current_case->compare_src = child->loc_string();
 					last_generated_case = current_case;
-					addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
+					std::optional<AstNode*> block;
 					for (auto& node : child->children) {
-						if (node->type == AST_DEFAULT)
+						if (node->type == AST_DEFAULT) {
 							default_case = current_case;
-						else if (node->type == AST_BLOCK)
-							processAst(node.get());
-						else
+						} else if (node->type == AST_BLOCK) {
+							log_assert(!block.has_value());
+							block = node.get();
+						} else {
 							current_case->compare.push_back(node->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap()));
+						}
 					}
+					log_assert(block.has_value());
+					set_src_attr(current_case, *block);
+					addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue, *block);
+					processAst(*block);
 					if (default_case != current_case)
 						sw->cases.push_back(current_case);
 					else
@@ -687,13 +695,13 @@ struct AST_INTERNAL::ProcessGenerator
 					last_generated_case->compare.clear();
 			#else
 					default_case = new RTLIL::CaseRule;
-					addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)));
+					addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)), ast);
 					sw->cases.push_back(default_case);
 			#endif
 				} else {
 					if (default_case == nullptr) {
 						default_case = new RTLIL::CaseRule;
-						addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
+						addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue, ast);
 					}
 					sw->cases.push_back(default_case);
 				}
@@ -703,7 +711,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 				this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
 				removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
-				addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
+				addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp, ast);
 			}
 			break;
 
@@ -728,8 +736,8 @@ struct AST_INTERNAL::ProcessGenerator
 
 				Wire *en = current_module->addWire(sstr.str() + "_EN", 1);
 				set_src_attr(en, ast);
-				proc->root_case.actions.push_back(SigSig(en, false));
-				current_case->actions.push_back(SigSig(en, true));
+				proc->root_case.actions.push_back({en, SigSpec(false), ast->loc_string()});
+				current_case->actions.push_back({en, SigSpec(true), ast->loc_string()});
 
 				RTLIL::SigSpec triggers;
 				RTLIL::Const::Builder polarity_builder;
@@ -826,8 +834,8 @@ struct AST_INTERNAL::ProcessGenerator
 
 				Wire *en = current_module->addWire(cellname.str() + "_EN", 1);
 				set_src_attr(en, ast);
-				proc->root_case.actions.push_back(SigSig(en, false));
-				current_case->actions.push_back(SigSig(en, true));
+				proc->root_case.actions.push_back({en, SigSpec(false), ast->loc_string()});
+				current_case->actions.push_back({en, SigSpec(true), ast->loc_string()});
 
 				RTLIL::SigSpec triggers;
 				RTLIL::Const::Builder polarity_builder;

frontends/rtlil/rtlil_frontend.cc

@@ -23,6 +23,7 @@
 
 #include "kernel/register.h"
 #include "kernel/log.h"
+#include "kernel/rtlil.h"
 #include "kernel/utils.h"
 #include <charconv>
 #include <deque>
@@ -628,7 +629,7 @@ struct RTLILFrontendWorker {
 						"The assign statement is reordered to come before all switch statements.");
 				RTLIL::SigSpec s1 = parse_sigspec();
 				RTLIL::SigSpec s2 = parse_sigspec();
-				current_case->actions.push_back(RTLIL::SigSig(std::move(s1), std::move(s2)));
+				current_case->actions.push_back({std::move(s1), std::move(s2), Const("")});
 				expect_eol();
 			} else
 				return;
@@ -719,7 +720,7 @@ struct RTLILFrontendWorker {
 				if (try_parse_keyword("update")) {
 					RTLIL::SigSpec s1 = parse_sigspec();
 					RTLIL::SigSpec s2 = parse_sigspec();
-					rule->actions.push_back(RTLIL::SigSig(std::move(s1), std::move(s2)));
+					rule->actions.push_back({std::move(s1), std::move(s2), Const("")});
 					expect_eol();
 					continue;
 				}

frontends/verific/verific.cc

@@ -1271,7 +1271,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 
 		for (unsigned i = 0 ; i < selector->GetNumBranches() ; ++i) {
 
-			SigSig action(sig_out_val, sig_data_values.extract(offset_data, data_width));
+			RTLIL::SyncAction action{sig_out_val, sig_data_values.extract(offset_data, data_width), {}};
 			offset_data += data_width;
 
 			for (unsigned j = 0 ; j < selector->GetNumConditions(i) ; ++j) {
@@ -1307,7 +1307,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 			}
 		}
 		RTLIL::CaseRule *cs_default = new RTLIL::CaseRule;
-		cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default));
+		cs_default->actions.push_back({sig_out_val, sig_data_default, {}});
 		sw->cases.push_back(cs_default);
 
 		return true;

frontends/verilog/verilog_parser.y

@@ -3046,6 +3046,7 @@ case_item:
 		extra->case_type_stack.pop_back();
 		SET_AST_NODE_LOC(extra->ast_stack.back(), @4, @4);
 		extra->ast_stack.pop_back();
+		SET_AST_NODE_LOC(extra->ast_stack.back(), @2, @2);
 		extra->ast_stack.pop_back();
 	};