Vorago VA416x0 port improvements for flash layout and preparing for boot defaults#679
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…tore more hardware settings
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Pull request overview
This PR tightens the VA416x0 port by fixing the debug FRAM/flash layout and ensuring hal_prepare_boot() leaves the application in a cleaner reset-like hardware state.
Changes:
- Removed an unused variable in
test_ext_flash()and enhancedhal_prepare_boot()on VA416x0 to flush and fully disable the debug UART, stop SysTick, clear its pending interrupt, and disable EDAC-related NVIC IRQs and SYSCONFIG IRQ enables. - Adjusted the example VA416x0 FRAM layout options (ML-DSA and Debug profiles) so boot/update/swap regions no longer overrun the 256KB FRAM and better align with documented sizes.
- Changed the example config default to
WOLFBOOT_RESTORE_CLOCK?=1and added optional debug flags for external flash testing.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
hal/va416x0.c |
Cleans up unused variable and extends hal_prepare_boot() to restore more hardware state (UART, SysTick, EDAC IRQs, SYSCONFIG IRQs) before jumping to the application. |
config/examples/vorago_va416x0.config |
Corrects commented ML-DSA and Debug partition layouts to fit within 256KB FRAM and updates the default to restore the clock on boot; also adds commented debug flags for FRAM/ext flash testing. |
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Pull request overview
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3 participants
Fix issue with debug flash layout and improve hal_prepare_boot to restore more hardware settings
ZD 21128