verilog_parser: add port renaming tests

Author: xiota

tests/verilog/port_rename_equivalence.ys

@@ -0,0 +1,22 @@
+# Equivalence
+read_verilog << EOF
+module gold(input a, input b, output c);
+    assign c = a + b;
+endmodule
+
+module gate_header (
+    .a(x),
+    .b(y),
+    .c(z)
+);
+    input x;
+    input y;
+    output z;
+
+    assign z = x + y;
+endmodule
+EOF
+
+equiv_make gold gate_header equiv_header
+equiv_simple
+equiv_status -assert

tests/verilog/port_rename_error_1.ys

@@ -0,0 +1,12 @@
+# Multiple names for the same inout port
+logger -expect error "Missing details for module port" 1
+read_verilog << EOF
+module gate_multi_inout (
+    .i(a),
+    .o(a)
+);
+    inout a;
+endmodule
+EOF
+logger -check-expected
+design -reset

tests/verilog/port_rename_error_2.ys

@@ -0,0 +1,12 @@
+# Multiple names for the same input port
+logger -expect error "Missing details for module port" 1
+read_verilog << EOF
+module gate_multi_inout (
+    .i(a),
+    .j(a)
+);
+    input a;
+endmodule
+EOF
+logger -check-expected
+design -reset

tests/verilog/port_rename_error_3.ys

@@ -0,0 +1,15 @@
+# Multiple names for an output port
+logger -expect error "Missing details for module port" 1
+read_verilog << EOF
+module gate_multi_output (
+    a,
+    .c(b),
+    .b(b)
+);
+    input a;
+    output b;
+    assign b = a;
+endmodule
+EOF
+logger -check-expected
+design -reset

tests/verilog/port_rename_error_4.ys

@@ -0,0 +1,16 @@
+# Swapping names for two ports
+logger -expect error "not declared in module header" 1
+read_verilog << EOF
+module gate_swap (
+    .a(b),
+    .b(a),
+    c
+);
+    input a;
+    input b;
+    output c;
+    assign c = a & !b;
+endmodule
+EOF
+logger -check-expected
+design -reset

tests/verilog/port_rename_error_5.ys

@@ -0,0 +1,14 @@
+# ANSI-style renaming
+logger -expect error "syntax error" 1
+read_verilog << EOF
+module gate_ansi (
+    input  .alias_a(a),
+    output .alias_b(b)
+);
+    wire a;
+    wire b;
+    assign b = a;
+endmodule
+EOF
+logger -check-expected
+design -reset

tests/verilog/port_rename_pass_1.ys

@@ -0,0 +1,14 @@
+# Partial aliasing
+read_verilog << EOF
+module gate_swap (
+    .a(a),
+    .b(b),
+    c
+);
+    input a;
+    input b;
+    output c;
+    assign c = a & !b;
+endmodule
+EOF
+design -reset