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[ExportVerilog] Move declarations to the top of blocks when disallowDeclAssignments is set. #25783

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[ExportVerilog] Move declarations to the top of blocks when disallowDeclAssignments is set.

[ExportVerilog] Move declarations to the top of blocks when disallowDeclAssignments is set. #25783

Triggered via pull request December 6, 2025 03:41
@uenokuuenoku
opened #9309
uenoku:dev/hidetou/improve-disallow-decl
Status Success
Total duration 8m 33s
Artifacts –

shortIntegrationTests.yml

on: pull_request
Matrix: Build and Test
cleanup-cache  /  Cleanup Cache
8s
cleanup-cache / Cleanup Cache
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