Support for T-Head RISC-V instruction sets

[luojia65]

Currently both Robustone and Capstone do not have support for T-Head instruction set extensions. When we analyze hex code dedicated for practical T-Head chips, we see Robustone does not have support for it.

Example (using cstool v6.0.0 and robustone-cli v0.0.0):

$ cstool riscv64 "8b 12 73 02 0b 95 c5 06 8b 10 31 04 0b 94 a4 00"
ERROR: invalid assembly code
$ robustone riscv64 "8b 12 73 02 0b 95 c5 06 8b 10 31 04 0b 94 a4 00"
 0  8b 12 73 02  unknown        0x0273128b
 4  0b 95 c5 06  unknown        0x06c5950b
 8  8b 10 31 04  unknown        0x0431108b
 c  0b 94 a4 00  unknown        0x00a4940b

Those instructions are actual T-Head instructions as listed (expected output):

 0  8b 12 73 02  th.addsl x5, x6, x7, 1
 4  0b 95 c5 06  th.addsl x10, x11, x12, 3
 8  8b 10 31 04  th.addsl x1, x2, x3, 2
 c  0b 94 a4 00  th.addsl x8, x9, x10, 0

Due to that RISC-V vendors may define different subsets with conflicting binary representation (e.g. custom0 may have different meanings in T-Head or other vendors), we should implement xthead* instruction sets as 'Arch specific options'.

Capstone have provided those architecture specific options for instruction sets as listed:

$ cstool
......
Arch specific options:
......
        +msync           Has only the msync instruction instead of sync. Implies BookE. (only: PowerPC)
        +qpx             Enables QPX extension (only: PowerPC)
        +ps              Enables PS extension (only: PowerPC)
        +spe             Enables SPE extension (only: PowerPC)
        +apple           Enables Apple's proprietary AArch64 instructions (AMX, MUL53, and others). (only: Arm64)
        +v9              Enables Sparc v9 instruction set. (only: Sparc)

We can add a new 'Arch specific option' for Robustone:

        +thead           Enables T-Head instruction sets. (only: RISC-V)

Sub-tasks of T-Head RISC-V ISA

We follow the T-Head ISA extension specification (Xthead*), Version 2.3.0, 2023-11-10 (here).

This issue can be split into individual T-Head instruction sets:

• Chapter 3. Cache Management Operations (XTheadCmo, 21 instructions)
• Chapter 4. Multi-core synchronization instructions (XTheadSync, 5 instructions)
• Chapter 5. Address calculation instructions (XTheadBa, 1 instruction)
• Chapter 6. Basic bit-manipulation (XTheadBb, 9 instructions)
• Chapter 7. Single-bit instructions (XTheadBs, 1 instruction)
• Chapter 8. Conditional move (XTheadCondMov, 2 instructions)
• Chapter 9. Indexed memory operations (XTheadMemIdx, 44 instructions)
• Chapter 10. Two-GPR memory operations (XTheadMemPair, 5 instructions)
• Chapter 11. Indexed memory operations for floating-point registers (XTheadFMemIdx, 8 instructions)
• Chapter 12. Multiply-accumulate instructions (XTheadMac, 6 instructions)
• Chapter 13. Double-precision floating-point high-bit data transmission instructions (2 instructions)
• Chapter 14. Acceleration interruption instructions (2 instructions)
• Chapter 15. Vector four 8-bit multiply and add with 32-bit instructions (7 instructions)

[ChenMiaoi]

well, I think I can take it, please assign it to me.

[Plucky923]

With various instruction sets that capstone does not support added to the project, I think we need more comprehensive testing. Relying solely on the existing unit tests is probably unable to guarantee the stability of the project.

Reference: #39

[ChenMiaoi]

With various instruction sets that capstone does not support added to the project, I think we need more comprehensive testing. Relying solely on the existing unit tests is probably unable to guarantee the stability of the project.

Reference: #39

I think we should refactor the current architecture of Robustone. Of course, issue #31 (test framework) should be done after this.