From 515843786cc7831d2a969a646ae10923fb8550fb Mon Sep 17 00:00:00 2001 From: Eric Chan <55314107+LinuxMint-User@users.noreply.github.com> Date: Thu, 11 Dec 2025 22:39:43 +0800 Subject: [PATCH 01/20] fix: resolve QSPI compilation error and add CI guard for stm32l475-atk-pandora - Fix function pointer type mismatch between drv_qspi.h and rt_qspi_device - Add qspi-flash.attach file for CI compilation guard - Optimize code with macros and inline adapter - Include all related bug fixes and configuration updates Fixes: #11036 --- .../libraries/HAL_Drivers/drivers/drv_qspi.c | 34 ++++++++++++++++--- .../.ci/attachconfig/qspi-flash.attach | 31 +++++++++++++++++ .../board/ports/drv_qspi_flash.c | 17 +++++++--- 3 files changed, 72 insertions(+), 10 deletions(-) create mode 100644 bsp/stm32/stm32l475-atk-pandora/.ci/attachconfig/qspi-flash.attach diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c index 893cf559170..5be0be89c53 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2018-11-27 zylx first version + * Date Author Notes + * 2018-11-27 zylx first version + * 2025-12-14 LinuxMint-User resolve QSPI interface type mismatch */ #include "board.h" @@ -146,6 +147,7 @@ static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_messag { Cmdhandler.InstructionMode = QSPI_INSTRUCTION_4_LINES; } + if (message->address.qspi_lines == 0) { Cmdhandler.AddressMode = QSPI_ADDRESS_NONE; @@ -162,6 +164,7 @@ static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_messag { Cmdhandler.AddressMode = QSPI_ADDRESS_4_LINES; } + if (message->address.size == 24) { Cmdhandler.AddressSize = QSPI_ADDRESS_24_BITS; @@ -170,6 +173,7 @@ static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_messag { Cmdhandler.AddressSize = QSPI_ADDRESS_32_BITS; } + if (message->qspi_data_lines == 0) { Cmdhandler.DataMode = QSPI_DATA_NONE; @@ -323,8 +327,27 @@ rt_err_t rt_hw_qspi_device_attach(const char *bus_name, const char *device_name, goto __exit; } - qspi_device->enter_qspi_mode = enter_qspi_mode; - qspi_device->exit_qspi_mode = exit_qspi_mode; + /* Safe type conversion to resolve interface contract mismatch. + * Caller ensures the function pointer is compatible via adapter pattern. + */ + if (enter_qspi_mode != RT_NULL) + { + qspi_device->enter_qspi_mode = (void (*)(struct rt_qspi_device *))enter_qspi_mode; + } + else + { + qspi_device->enter_qspi_mode = RT_NULL; + } + + if (exit_qspi_mode != RT_NULL) + { + qspi_device->exit_qspi_mode = (void (*)(struct rt_qspi_device *))exit_qspi_mode; + } + else + { + qspi_device->exit_qspi_mode = RT_NULL; + } + qspi_device->config.qspi_dl_width = data_line_width; #ifdef BSP_QSPI_USING_SOFTCS @@ -377,3 +400,4 @@ INIT_BOARD_EXPORT(rt_hw_qspi_bus_init); #endif /* BSP_USING_QSPI */ #endif /* RT_USING_QSPI */ + diff --git a/bsp/stm32/stm32l475-atk-pandora/.ci/attachconfig/qspi-flash.attach b/bsp/stm32/stm32l475-atk-pandora/.ci/attachconfig/qspi-flash.attach new file mode 100644 index 00000000000..d1f367a7fec --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/.ci/attachconfig/qspi-flash.attach @@ -0,0 +1,31 @@ +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y + +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +CONFIG_RT_USING_QSPI=y +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +CONFIG_RT_SFUD_USING_QSPI=y +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +CONFIG_BSP_USING_QSPI_FLASH=y +CONFIG_BSP_USING_QSPI=y diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c index 6dac69cce75..91034998ab7 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2018-11-27 zylx first version + * Date Author Notes + * 2018-11-27 zylx first version + * 2025-12-14 LinuxMint-User resolve QSPI compilation error */ #include @@ -19,6 +20,9 @@ #include "dev_spi_flash.h" #include "dev_spi_flash_sfud.h" +#define QSPI_BUS_NAME "qspi1" +#define QSPI_DEVICE_NAME "qspi10" + char w25qxx_read_status_register2(struct rt_qspi_device *device) { /* 0x35 read status register2 */ @@ -62,16 +66,18 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { - rt_hw_qspi_device_attach("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); + rt_hw_qspi_device_attach(QSPI_BUS_NAME, QSPI_DEVICE_NAME, RT_NULL, 4, + (void (*)(void))w25qxx_enter_qspi_mode, RT_NULL); /* init w25q128 */ - if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) + if (RT_NULL == rt_sfud_flash_probe("W25Q128", QSPI_DEVICE_NAME)) { return -RT_ERROR; } return RT_EOK; } + INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); #if defined(RT_USING_DFS_ELMFAT) && !defined(BSP_USING_SDCARD_FATFS) @@ -108,3 +114,4 @@ INIT_ENV_EXPORT(mnt_init); #endif /* defined(RT_USING_DFS_ELMFAT) && !defined(BSP_USING_SDCARD_FATFS) */ #endif /* BSP_USING_QSPI_FLASH */ + From ccfc038f5f0d3c664ef6d91f98065c640119b3ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=E2=80=86b=E2=80=86b666?= <64397326+Rbb666@users.noreply.github.com> Date: Fri, 12 Dec 2025 10:34:53 +0800 Subject: [PATCH 02/20] Update RT_VER_NUM to 5.3.0 (#11039) --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index ea50610b1f9..efb21f27528 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -434,7 +434,7 @@ endif config RT_VER_NUM hex - default 0x50201 + default 0x50300 help RT-Thread version number From df404ee182d57d65f241059ac7a350d988e8e03b Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Tue, 9 Dec 2025 17:32:26 +0800 Subject: [PATCH 03/20] [dm][clk] refactoring the CLK framework The old CLK is can't link all hardware clock cell in system that the API of layout such as 'set_parent' can't work as expected. Some hareware clock cell need some flags to prevent some dangerous behaviors, eg: When a clock cell is link to the PMU, the SoC will power-down if the cell is disable. The new CLK can do it, and make the CLK drivers implemented easier from TRM/DataSheet. Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/clk/SConscript | 10 +- components/drivers/clk/clk-fixed-rate.c | 80 +- components/drivers/clk/clk.c | 2143 ++++++++++++++++------ components/drivers/include/drivers/clk.h | 205 ++- 4 files changed, 1805 insertions(+), 633 deletions(-) diff --git a/components/drivers/clk/SConscript b/components/drivers/clk/SConscript index af6ed4dbeb2..928697863d3 100644 --- a/components/drivers/clk/SConscript +++ b/components/drivers/clk/SConscript @@ -1,7 +1,6 @@ from building import * group = [] -objs = [] if not GetDepend(['RT_USING_CLK']): Return('group') @@ -15,12 +14,7 @@ src = ['clk.c'] if GetDepend(['RT_USING_OFW']): src += ['clk-fixed-rate.c'] -group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) -objs = objs + group +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) -Return('objs') +Return('group') diff --git a/components/drivers/clk/clk-fixed-rate.c b/components/drivers/clk/clk-fixed-rate.c index 0912e86dd6b..944269c257b 100644 --- a/components/drivers/clk/clk-fixed-rate.c +++ b/components/drivers/clk/clk-fixed-rate.c @@ -6,66 +6,72 @@ * Change Logs: * Date Author Notes * 2022-11-26 GuEe-GUI first version + * 2024-05-01 GuEe-GUI update for new clk */ #include #include -#include - -static rt_err_t fixed_clk_ofw_init(struct rt_platform_device *pdev, struct rt_clk_fixed_rate *clk_fixed) +struct clk_fixed { - rt_err_t err = RT_EOK; - rt_uint32_t rate, accuracy; - struct rt_ofw_node *np = pdev->parent.ofw_node; - const char *clk_name = np->name; - - if (!rt_ofw_prop_read_u32(np, "clock-frequency", &rate)) - { - rt_ofw_prop_read_u32(np, "clock-accuracy", &accuracy); - rt_ofw_prop_read_string(np, "clock-output-names", &clk_name); + struct rt_clk_node parent; - clk_fixed->clk.name = clk_name; - clk_fixed->clk.rate = rate; - clk_fixed->clk.min_rate = rate; - clk_fixed->clk.max_rate = rate; - clk_fixed->fixed_rate = rate; - clk_fixed->fixed_accuracy = accuracy; + struct rt_clk_fixed_rate fcell; + struct rt_clk_cell *cells[1]; +}; - rt_ofw_data(np) = &clk_fixed->clk; - } - else - { - err = -RT_EIO; - } +static rt_ubase_t fixed_clk_recalc_rate(struct rt_clk_cell *cell, rt_ubase_t parent_rate) +{ + struct rt_clk_fixed_rate *fr = rt_container_of(cell, struct rt_clk_fixed_rate, cell); - return err; + return fr->fixed_rate; } +static struct rt_clk_ops fixed_clk_ops = +{ + .recalc_rate = fixed_clk_recalc_rate, +}; + static rt_err_t fixed_clk_probe(struct rt_platform_device *pdev) { - rt_err_t err = RT_EOK; - struct rt_clk_fixed_rate *clk_fixed = rt_calloc(1, sizeof(*clk_fixed)); + rt_err_t err; + rt_uint32_t val; + struct rt_device *dev = &pdev->parent; + struct clk_fixed *cf = rt_calloc(1, sizeof(*cf)); - if (clk_fixed) + if (!cf) { - err = fixed_clk_ofw_init(pdev, clk_fixed); - } - else - { - err = -RT_ENOMEM; + return -RT_ENOMEM; } - if (!err) + if ((err = rt_dm_dev_prop_read_u32(dev, "clock-frequency", &val))) { - err = rt_clk_register(&clk_fixed->clk, RT_NULL); + goto _fail; } + cf->fcell.fixed_rate = val; + + val = 0; + rt_dm_dev_prop_read_u32(dev, "clock-accuracy", &val); + cf->fcell.fixed_accuracy = val; - if (err && clk_fixed) + rt_dm_dev_prop_read_string(dev, "clock-output-names", &cf->fcell.cell.name); + + cf->parent.dev = dev; + cf->parent.cells_nr = 1; + cf->parent.cells = cf->cells; + cf->cells[0] = &cf->fcell.cell; + cf->fcell.cell.ops = &fixed_clk_ops; + + if ((err = rt_clk_register(&cf->parent))) { - rt_free(clk_fixed); + goto _fail; } + return RT_EOK; + +_fail: + rt_free(cf); + return err; } diff --git a/components/drivers/clk/clk.c b/components/drivers/clk/clk.c index 2c2cc2fb42d..4d8a9c48eaa 100644 --- a/components/drivers/clk/clk.c +++ b/components/drivers/clk/clk.c @@ -7,6 +7,7 @@ * Date Author Notes * 2022-11-26 GuEe-GUI first version * 2025-01-24 wumingzi add doxygen comment + * 2024-05-01 GuEe-GUI make cell for hareware clock */ #include @@ -22,290 +23,265 @@ #define DBG_LVL DBG_INFO #include -static RT_DEFINE_SPINLOCK(_clk_lock); -static rt_list_t _clk_nodes = RT_LIST_OBJECT_INIT(_clk_nodes); +static rt_bool_t clk_ignore_unused = RT_FALSE; + +static struct rt_mutex _clk_lock; +static rt_list_t _clk_node_nodes = RT_LIST_OBJECT_INIT(_clk_node_nodes); static rt_list_t _clk_notifier_nodes = RT_LIST_OBJECT_INIT(_clk_notifier_nodes); -/** - * @brief Release clock node - * - * @param r point to reference count of clock node - * @warning The function only can print log and MORE DETAILS SHOULD BE IMPLEMENTED. - */ -static void clk_release(struct rt_ref *r) +static int clk_init(void) { - struct rt_clk_node *clk_np = rt_container_of(r, struct rt_clk_node, ref); - - LOG_E("%s is release", clk_np->name); - (void)clk_np; +#ifdef RT_USING_OFW + clk_ignore_unused = !!rt_ofw_bootargs_select("clk_ignore_unused", 0); +#endif + rt_mutex_init(&_clk_lock, "CLK", RT_IPC_FLAG_PRIO); - RT_ASSERT(0); + return 0; } +INIT_CORE_EXPORT(clk_init); /** - * @brief Increase reference count for clock node - * - * @param clk_np point to clock node + * @brief Acquire global clock framework lock. * - * @return struct rt_clk_node * point to clock node whose reference count has increased */ -rt_inline struct rt_clk_node *clk_get(struct rt_clk_node *clk_np) +static void clk_lock(void) { - rt_ref_get(&clk_np->ref); - - return clk_np; + if (rt_thread_self()) + { + rt_mutex_take(&_clk_lock, RT_WAITING_FOREVER); + } } /** - * @brief Decrease reference count for clock node - * - * @param clk_np point to clock node + * @brief Release global clock framework lock. * */ -rt_inline void clk_put(struct rt_clk_node *clk_np) +static void clk_unlock(void) { - rt_ref_put(&clk_np->ref, &clk_release); + if (rt_thread_self()) + { + rt_mutex_release(&_clk_lock); + } } /** * @brief Allocate memory space for struct clock and return it * - * @param clk_np point to clock node + * @param cell point to clock cell * @param dev_id device identifier for the clock * @param con_id connection identifier for the clock - * @param fw_node point to the firmware node associated with the clock * * @return struct rt_clk* point to clock */ -static struct rt_clk *clk_alloc(struct rt_clk_node *clk_np, const char *dev_id, - const char *con_id, void *fw_node) +static struct rt_clk *clk_alloc(struct rt_clk_cell *cell, const char *dev_id, const char *con_id) { struct rt_clk *clk = rt_calloc(1, sizeof(*clk)); - if (clk) + if (!clk) { - clk->clk_np = clk_np; - clk->dev_id = dev_id; - clk->con_id = con_id; + LOG_E("%s not memory to create CLK for dev_id = %s con_id = %s", + cell->name, dev_id, con_id); + return RT_NULL; + } + + clk->cell = cell; - clk->fw_node = fw_node; + clk->dev_id = dev_id; + clk->con_id = con_id; + + if (cell->clk) + { + clk->min_rate = cell->clk->min_rate; + clk->max_rate = cell->clk->max_rate; } else { - clk = rt_err_ptr(-RT_ENOMEM); + clk->min_rate = 0; + clk->max_rate = ~0UL; } return clk; } /** - * @brief Free memory space of clock object + * @brief Update clk cell hardware information * - * @param clk point to clock + * @param cell point to clock cell + * @param clk bind clk * */ -static void clk_free(struct rt_clk *clk) +static void clk_cell_bind(struct rt_clk_cell *cell, struct rt_clk *clk) { - struct rt_clk_node *clk_np = clk->clk_np; - - if (clk_np && clk_np->ops->finit) + if (!cell->clk) { - clk_np->ops->finit(clk); + cell->clk = clk; } - - rt_free(clk); -} - -/** - * @brief Allocate memory space and creat clock object - * - * @param clk_np point to clock node - * @param dev_id device identifier for the clock - * @param con_id connection identifier for the clock - * @param fw_data point to the firmware data associated with the clock - * @param fw_node point to the firmware node associated with the clock - * - * @return struct rt_clk* point to clock - */ -static struct rt_clk *clk_create(struct rt_clk_node *clk_np, const char *dev_id, - const char *con_id, void *fw_data, void *fw_node) -{ - struct rt_clk *clk = clk_alloc(clk_np, dev_id, con_id, fw_node); - - if (!rt_is_err(clk)) + else { - clk_get(clk_np); - - if (clk_np->ops->init && clk_np->ops->init(clk, fw_data)) + if (!cell->clk->dev_id) { - LOG_E("Dev[%s] Con[%s] init fail", dev_id, con_id); + cell->clk->dev_id = clk->dev_id; + } - clk_free(clk); - clk = RT_NULL; + if (!cell->clk->con_id) + { + cell->clk->con_id = clk->con_id; } } - - return clk; } /** - * @brief Notify corresponding clock from all + * @brief Register a clock node into the global clock framework. * - * @param clk_np point to clock node - * @param msg message identifier for the event - * @param old_rate old rate of the clock before the event - * @param new_rate new rate of the clock after the event + * This function initializes an @ref rt_clk_node structure and inserts it + * into the global clock node list. Each node may contain multiple + * @ref rt_clk_cell instances, which represent the individual output clocks + * provided by the node. * - * @return rt_err_t RT_EOK on notify clock sucessfully, and other value is failed. + * If the node is associated with a device (clk_np->dev is not NULL), + * the framework will automatically try to obtain its parent clocks by calling + * rt_clk_get_array(clk_np->dev). Otherwise, the node will be treated as a + * root-level provider (e.g., fixed clock). + * + * The caller must ensure that all @ref rt_clk_cell entries are allocated + * and linked to the node before calling this function. + * + * @param clk_np Pointer to the clock node to be registered. + * + * @retval RT_EOK Successfully registered. + * @retval -RT_EINVAL Invalid argument or missing cell list. + * @retval -RT_ENOMEM Failed to allocate parent clock array. */ -static rt_err_t clk_notify(struct rt_clk_node *clk_np, rt_ubase_t msg, rt_ubase_t old_rate, rt_ubase_t new_rate) +rt_err_t rt_clk_register(struct rt_clk_node *clk_np) { rt_err_t err = RT_EOK; - struct rt_clk_notifier *notifier; + struct rt_clk_cell *cell; - rt_list_for_each_entry(notifier, &_clk_notifier_nodes, list) + if (!clk_np || !clk_np->cells_nr || !clk_np->cells) { - if (notifier->clk->clk_np == clk_np) - { - err = notifier->callback(notifier, msg, old_rate, new_rate); + return -RT_EINVAL; + } - /* Only check hareware's error */ - if (err == -RT_EIO) - { - break; - } + if (clk_np->dev && !rt_is_err(clk_np->parents_clk)) + { + clk_np->parents_clk = rt_clk_get_array(clk_np->dev); + + if (rt_is_err(clk_np->parents_clk)) + { + return rt_ptr_err(clk_np->parents_clk); } } - return err; -} +#if RT_NAME_MAX > 0 + rt_strncpy(clk_np->parent.name, RT_CLK_NODE_OBJ_NAME, RT_NAME_MAX); +#else + clk_np->parent.name = RT_CLK_NODE_OBJ_NAME; +#endif -/** - * @brief Set parent clock - * - * @param clk_np point to clock node - * @param parent_np point to parent rt_clk - * - */ -static void clk_set_parent(struct rt_clk_node *clk_np, struct rt_clk_node *parent_np) -{ - rt_hw_spin_lock(&_clk_lock.lock); + rt_list_init(&clk_np->parent.list); - clk_np->parent = parent_np; + for (int i = 0; i < clk_np->cells_nr; ++i) + { + cell = clk_np->cells[i]; - rt_list_insert_after(&parent_np->children_nodes, &clk_np->list); + if (!cell) + { + continue; + } - rt_hw_spin_unlock(&_clk_lock.lock); -} + cell->clk_np = clk_np; -static const struct rt_clk_ops unused_clk_ops = -{ -}; + cell->rate = 0; + cell->prepare_count = 0; + cell->enable_count = 0; + } -/** - * @brief Register clock node into clock list - * - * @param clk_np point to child node that will be registered node. - * @param parent_np point to parent rt_clk. If it is RT_NULL, clock node will be linked to init node. - * - * @retval RT_EOK - * @retval -RT_ENOMEM - */ -rt_err_t rt_clk_register(struct rt_clk_node *clk_np, struct rt_clk_node *parent_np) -{ - rt_err_t err = RT_EOK; - struct rt_clk *clk = RT_NULL; + clk_lock(); + rt_list_insert_after(&_clk_node_nodes, &clk_np->parent.list); + clk_unlock(); - if (clk_np) +#ifdef RT_USING_OFW + if (clk_np->dev && clk_np->dev->ofw_node) { - clk_np->clk = clk; + rt_bool_t set_ofw_data = RT_FALSE; + struct rt_ofw_node *np = clk_np->dev->ofw_node; - if (!clk_np->ops) + if (!rt_ofw_data(np)) { - clk_np->ops = &unused_clk_ops; + set_ofw_data = RT_TRUE; + rt_ofw_data(np) = &clk_np->parent; } - #if RT_NAME_MAX > 0 - rt_strncpy(clk_np->rt_parent.name, RT_CLK_NODE_OBJ_NAME, RT_NAME_MAX); - #else - clk_np->rt_parent.name = RT_CLK_NODE_OBJ_NAME; - #endif - - rt_ref_init(&clk_np->ref); - rt_list_init(&clk_np->list); - rt_list_init(&clk_np->children_nodes); - clk_np->multi_clk = 0; - - if (parent_np) + if ((err = rt_ofw_clk_set_defaults(np))) { - clk_np->clk = clk_alloc(clk_np, RT_NULL, RT_NULL, RT_NULL); - - if (clk_np->clk) - { - clk_set_parent(clk_np, parent_np); - } - else + if (set_ofw_data) { - err = -RT_ENOMEM; + rt_ofw_data(np) = RT_NULL; } } - else - { - clk_np->parent = RT_NULL; - - rt_hw_spin_lock(&_clk_lock.lock); - - rt_list_insert_after(&_clk_nodes, &clk_np->list); - - rt_hw_spin_unlock(&_clk_lock.lock); - } } - else +#endif /* RT_USING_OFW */ + + if (err) { - err = -RT_ENOMEM; + if (!rt_is_err(clk_np->parents_clk)) + { + rt_clk_array_put(clk_np->parents_clk); + } } return err; } /** - * @brief Unregister clock node from clock list + * @brief Unregister a clock node from global clock list * - * @param clk_np point to child node that will be Unregistered node. + * This API is intended for rollback use only, typically called + * when a clock provider fails after registration but before any + * consumer starts using its clocks. * - * @retval RT_EOK - * @retval -RT_EBUSY - * @retval -RT_EINVAL + * It removes the specified clock node from the global list and + * releases its parent clock array if present. The function does + * not free memory of @ref rt_clk_cell instances or the node itself. + * + * @param clk_np Pointer to the clock node to be unregistered. + * + * @retval RT_EOK Successfully unregistered. + * @retval -RT_EINVAL Invalid parameter. + * @retval -RT_EBUSY One or more cells are active and cannot be removed. */ rt_err_t rt_clk_unregister(struct rt_clk_node *clk_np) { - rt_err_t err = RT_EOK; + struct rt_clk_cell *cell; - if (clk_np) + if (!clk_np) { - err = -RT_EBUSY; - - rt_hw_spin_lock(&_clk_lock.lock); + return -RT_EINVAL; + } - if (rt_list_isempty(&clk_np->children_nodes)) + if (clk_np->cells && clk_np->cells_nr) + { + for (int i = 0; i < clk_np->cells_nr; ++i) { - if (rt_ref_read(&clk_np->ref) <= 1) - { - rt_list_remove(&clk_np->list); - clk_free(clk_np->clk); + cell = clk_np->cells[i]; - err = RT_EOK; + if (cell && cell->enable_count > 0) + { + return -RT_EBUSY; } } - - rt_hw_spin_unlock(&_clk_lock.lock); } - else + + clk_lock(); + rt_list_remove(&clk_np->parent.list); + clk_unlock(); + + if (!rt_is_err(clk_np->parents_clk)) { - err = -RT_EINVAL; + rt_clk_array_put(clk_np->parents_clk); } - return err; + return RT_EOK; } /** @@ -319,18 +295,17 @@ rt_err_t rt_clk_unregister(struct rt_clk_node *clk_np) */ rt_err_t rt_clk_notifier_register(struct rt_clk *clk, struct rt_clk_notifier *notifier) { - if (!clk || !clk->clk_np || !notifier) + if (!clk || !notifier) { return -RT_EINVAL; } - rt_hw_spin_lock(&_clk_lock.lock); - - ++clk->clk_np->notifier_count; + notifier->clk = clk; rt_list_init(¬ifier->list); - rt_list_insert_after(&_clk_notifier_nodes, ¬ifier->list); - rt_hw_spin_unlock(&_clk_lock.lock); + clk_lock(); + rt_list_insert_after(&_clk_notifier_nodes, ¬ifier->list); + clk_unlock(); return RT_EOK; } @@ -353,51 +328,112 @@ rt_err_t rt_clk_notifier_unregister(struct rt_clk *clk, struct rt_clk_notifier * return -RT_EINVAL; } - rt_hw_spin_lock(&_clk_lock.lock); - + clk_lock(); rt_list_for_each_entry(notifier_find, &_clk_notifier_nodes, list) { - if (notifier_find->clk->clk_np == notifier->clk->clk_np) + if (notifier_find == notifier) { - --clk->clk_np->notifier_count; rt_list_remove(¬ifier->list); break; } } - - rt_hw_spin_unlock(&_clk_lock.lock); + clk_unlock(); return RT_EOK; } +/** + * @brief Notify corresponding clock from all + * + * @param clk_np point to clock node + * @param msg message identifier for the event + * @param old_rate old rate of the clock before the event + * @param new_rate new rate of the clock after the event + * + * @return rt_err_t RT_EOK on notify clock sucessfully, and other value is failed. + */ +static rt_err_t clk_notify(struct rt_clk_node *clk_np, rt_ubase_t msg, + rt_ubase_t old_rate, rt_ubase_t new_rate) +{ + rt_err_t err = RT_EOK; + struct rt_clk_notifier *notifier; + + rt_list_for_each_entry(notifier, &_clk_notifier_nodes, list) + { + if (notifier->clk->cell->clk_np == clk_np) + { + err = notifier->callback(notifier, msg, old_rate, new_rate); + + /* Only check hareware's error */ + if (err == -RT_EIO) + { + break; + } + } + } + + return err; +} + +static void clk_unprepare(struct rt_clk *clk); +static void clk_disable(struct rt_clk *clk); +static rt_ubase_t clk_round_rate(struct rt_clk *clk, rt_ubase_t rate); +static rt_err_t clk_set_rate(struct rt_clk *clk, rt_ubase_t rate); +static rt_err_t clk_set_parent(struct rt_clk *clk, struct rt_clk *parent); +static struct rt_clk *clk_get_parent(struct rt_clk *clk); +static rt_ubase_t clk_get_rate(struct rt_clk *clk); + +static struct rt_clk *clk_cell_get_clk(struct rt_clk_cell *cell); + /** * @brief Recursively prepare clock * * @param clk Ponit to clock that will be prepared - * @param clk_np Ponit to clock node that will be prepared * * @return rt_err_t RT_EOK on prepare clock sucessfully, and other value is failed. */ -static rt_err_t clk_prepare(struct rt_clk *clk, struct rt_clk_node *clk_np) +static rt_err_t clk_prepare(struct rt_clk *clk) { - rt_err_t err = RT_EOK; + rt_err_t err; + struct rt_clk *parent; + struct rt_clk_cell *cell; + + cell = clk->cell; - if (clk_np->parent) + /* Already prepared */ + if (cell->prepare_count++ > 0) { - clk_prepare(clk_np->clk, clk_np->parent); + return RT_EOK; } - if (clk->prepare_count == 0 && clk_np->ops->prepare) + parent = clk_get_parent(clk); + + if (parent) { - err = clk_np->ops->prepare(clk); + if ((err = clk_prepare(parent))) + { + goto _fail; + } } - if (!err) + if (cell->ops->prepare) { - ++clk->prepare_count; + if ((err = cell->ops->prepare(cell))) + { + if (parent) + { + clk_unprepare(parent); + } + + goto _fail; + } } + return RT_EOK; + +_fail: + --cell->prepare_count; return err; } @@ -410,17 +446,19 @@ static rt_err_t clk_prepare(struct rt_clk *clk, struct rt_clk_node *clk_np) */ rt_err_t rt_clk_prepare(struct rt_clk *clk) { - rt_err_t err = RT_EOK; + rt_err_t err; RT_DEBUG_NOT_IN_INTERRUPT; - if (clk && clk->clk_np) + if (clk) { - rt_hw_spin_lock(&_clk_lock.lock); - - err = clk_prepare(clk, clk->clk_np); - - rt_hw_spin_unlock(&_clk_lock.lock); + clk_lock(); + err = clk_prepare(clk); + clk_unlock(); + } + else + { + err = RT_EOK; } return err; @@ -430,42 +468,50 @@ rt_err_t rt_clk_prepare(struct rt_clk *clk) * @brief Recursively unprepare clock * * @param clk Ponit to clock that will be unprepared - * @param clk_np Ponit to clock node that will be unprepared * */ -static void clk_unprepare(struct rt_clk *clk, struct rt_clk_node *clk_np) +static void clk_unprepare(struct rt_clk *clk) { - if (clk_np->parent) + struct rt_clk *parent; + struct rt_clk_cell *cell; + + cell = clk->cell; + + /* Don't unprepare readly */ + if (cell->prepare_count-- > 1) { - clk_unprepare(clk_np->clk, clk_np->parent); + return; } - if (clk->prepare_count == 1 && clk_np->ops->unprepare) + if (cell->ops->unprepare) { - clk_np->ops->unprepare(clk); + cell->ops->unprepare(cell); } - if (clk->prepare_count) + + parent = clk_get_parent(clk); + + if (parent) { - --clk->prepare_count; + clk_unprepare(parent); } } -rt_err_t rt_clk_unprepare(struct rt_clk *clk) +/** + * @brief Unprepare clock + * + * @param clk Ponit to clock that will be unprepared + * + */ +void rt_clk_unprepare(struct rt_clk *clk) { - rt_err_t err = RT_EOK; - RT_DEBUG_NOT_IN_INTERRUPT; - if (clk && clk->clk_np) + if (clk) { - rt_hw_spin_lock(&_clk_lock.lock); - - clk_unprepare(clk, clk->clk_np); - - rt_hw_spin_unlock(&_clk_lock.lock); + clk_lock(); + clk_unprepare(clk); + clk_unlock(); } - - return err; } /** @@ -475,25 +521,47 @@ rt_err_t rt_clk_unprepare(struct rt_clk *clk) * * @return rt_err_t RT_EOK on enable clock FOREVER. */ -static rt_err_t clk_enable(struct rt_clk *clk, struct rt_clk_node *clk_np) +static rt_err_t clk_enable(struct rt_clk *clk) { - rt_err_t err = RT_EOK; + rt_err_t err; + struct rt_clk *parent; + struct rt_clk_cell *cell; - if (clk_np->parent) + cell = clk->cell; + + /* Already enabled */ + if (cell->enable_count++ > 0) { - clk_enable(clk_np->clk, clk_np->parent); + return RT_EOK; } - if (clk->enable_count == 0 && clk_np->ops->enable) + parent = clk_get_parent(clk); + + if (parent) { - err = clk_np->ops->enable(clk); + if ((err = clk_enable(parent))) + { + goto _fail; + } } - if (!err) + if (cell->ops->enable) { - ++clk->enable_count; + if ((err = cell->ops->enable(cell))) + { + if (parent) + { + clk_disable(parent); + } + + goto _fail; + } } + return RT_EOK; + +_fail: + --cell->enable_count; return err; } @@ -506,15 +574,17 @@ static rt_err_t clk_enable(struct rt_clk *clk, struct rt_clk_node *clk_np) */ rt_err_t rt_clk_enable(struct rt_clk *clk) { - rt_err_t err = RT_EOK; + rt_err_t err; - if (clk && clk->clk_np) + if (clk) { - rt_hw_spin_lock(&_clk_lock.lock); - - err = clk_enable(clk, clk->clk_np); - - rt_hw_spin_unlock(&_clk_lock.lock); + clk_lock(); + err = clk_enable(clk); + clk_unlock(); + } + else + { + err = RT_EOK; } return err; @@ -524,23 +594,46 @@ rt_err_t rt_clk_enable(struct rt_clk *clk) * @brief Recursively disable clock * * @param clk Ponit to clock that will be disabled - * @param clk_np Ponit to clock node that will be disabled * */ -static void clk_disable(struct rt_clk *clk, struct rt_clk_node *clk_np) +static void clk_disable(struct rt_clk *clk) { - if (clk_np->parent) + struct rt_clk *parent; + struct rt_clk_cell *cell; + + cell = clk->cell; + + if (cell->enable_count == 0) + { + LOG_W("%s: Disable called with count = 0", cell->name); + return; + } + + if (cell->enable_count-- > 1) + { + return; + } + + if (cell->flags & RT_CLK_F_IS_CRITICAL) + { + return; + } + + if (clk_ignore_unused && cell->flags & RT_CLK_F_IGNORE_UNUSED) { - clk_disable(clk_np->clk, clk_np->parent); + return; } - if (clk->enable_count == 1 && clk_np->ops->disable) + if (cell->ops->disable) { - clk_np->ops->disable(clk); + cell->ops->disable(cell); } - if (clk->enable_count) + + parent = clk_get_parent(clk); + + if (parent) { - --clk->enable_count; + clk_disable(parent); } } @@ -552,13 +645,11 @@ static void clk_disable(struct rt_clk *clk, struct rt_clk_node *clk_np) */ void rt_clk_disable(struct rt_clk *clk) { - if (clk && clk->clk_np) + if (clk) { - rt_hw_spin_lock(&_clk_lock.lock); - - clk_disable(clk, clk->clk_np); - - rt_hw_spin_unlock(&_clk_lock.lock); + clk_lock(); + clk_disable(clk); + clk_unlock(); } } @@ -571,23 +662,25 @@ void rt_clk_disable(struct rt_clk *clk) */ rt_err_t rt_clk_prepare_enable(struct rt_clk *clk) { - rt_err_t err = RT_EOK; + rt_err_t err; RT_DEBUG_NOT_IN_INTERRUPT; if (clk) { - err = rt_clk_prepare(clk); - - if (!err) + clk_lock(); + if (!(err = clk_prepare(clk))) { - err = rt_clk_enable(clk); - - if (err) + if ((err = clk_enable(clk))) { - rt_clk_unprepare(clk); + clk_unprepare(clk); } } + clk_unlock(); + } + else + { + err = RT_EOK; } return err; @@ -605,8 +698,10 @@ void rt_clk_disable_unprepare(struct rt_clk *clk) if (clk) { - rt_clk_disable(clk); - rt_clk_unprepare(clk); + clk_lock(); + clk_disable(clk); + clk_unprepare(clk); + clk_unlock(); } } @@ -619,7 +714,7 @@ void rt_clk_disable_unprepare(struct rt_clk *clk) */ rt_err_t rt_clk_array_prepare(struct rt_clk_array *clk_arr) { - rt_err_t err = RT_EOK; + rt_err_t err; if (clk_arr) { @@ -639,29 +734,29 @@ rt_err_t rt_clk_array_prepare(struct rt_clk_array *clk_arr) } } } + else + { + err = RT_EOK; + } return err; } -rt_err_t rt_clk_array_unprepare(struct rt_clk_array *clk_arr) +/** + * @brief Unprepare clock array for mutipule out clock + * + * @param clk_arr point to clock array + * + */ +void rt_clk_array_unprepare(struct rt_clk_array *clk_arr) { - rt_err_t err = RT_EOK; - if (clk_arr) { for (int i = 0; i < clk_arr->count; ++i) { - if ((err = rt_clk_unprepare(clk_arr->clks[i]))) - { - LOG_E("CLK Array[%d] %s failed error = %s", i, - "unprepare", rt_strerror(err)); - - break; - } + rt_clk_unprepare(clk_arr->clks[i]); } } - - return err; } /** @@ -673,7 +768,7 @@ rt_err_t rt_clk_array_unprepare(struct rt_clk_array *clk_arr) */ rt_err_t rt_clk_array_enable(struct rt_clk_array *clk_arr) { - rt_err_t err = RT_EOK; + rt_err_t err; if (clk_arr) { @@ -693,6 +788,10 @@ rt_err_t rt_clk_array_enable(struct rt_clk_array *clk_arr) } } } + else + { + err = RT_EOK; + } return err; } @@ -752,51 +851,85 @@ void rt_clk_array_disable_unprepare(struct rt_clk_array *clk_arr) } /** - * @brief Set clock rate range + * @brief Set and clamp clock rate within specified range. * - * @param clk point to clock - * @param min minimum clock rate - * @param max minimum clock rate + * @details This function updates the minimum and maximum allowed rate + * of a clock, clamps its current rate to the new range, and + * immediately applies the change via set_rate(). * - * @return rt_err_t RT_EOK on set clock rate range sucessfully, and other value is failed. + * @param clk Pointer to clock handle. + * @param min Minimum allowed rate (Hz). + * @param max Maximum allowed rate (Hz). + * + * @retval RT_EOK Successfully updated. + * @retval -RT_EINVAL Invalid parameter or range. + * @retval -RT_ENOSYS Clock driver does not support set_rate(). + * @retval other Hardware-specific error returned by set_rate(). */ -rt_err_t rt_clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t max) +static rt_err_t clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t max) { - rt_err_t err = RT_EOK; + rt_err_t err; + rt_ubase_t rate, old_min, old_max; + struct rt_clk_cell *cell; - if (clk && clk->clk_np) + if (min > max) { - struct rt_clk_node *clk_np = clk->clk_np; + return -RT_EINVAL; + } - rt_hw_spin_lock(&_clk_lock.lock); + cell = clk->cell; - if (clk_np->ops->set_rate) - { - rt_ubase_t rate = clk_np->rate; - rt_ubase_t old_min = clk_np->min_rate; - rt_ubase_t old_max = clk_np->max_rate; + old_min = clk->min_rate; + old_max = clk->max_rate; - clk_np->min_rate = min; - clk_np->max_rate = max; + clk->min_rate = min; + clk->max_rate = max; - rate = rt_clamp(rate, min, max); - err = clk_np->ops->set_rate(clk, rate, - rt_clk_get_rate(clk_np->parent ? clk_np->parent->clk : RT_NULL)); + if (cell->flags & RT_CLK_F_GET_RATE_NOCACHE) + { + rate = clk_get_rate(clk); + } + else + { + rate = cell->rate; + } - if (err) - { - clk_np->min_rate = old_min; - clk_np->max_rate = old_max; - } - } - else - { - err = -RT_ENOSYS; - } + if ((err = clk_set_rate(clk, rt_clamp(rate, min, max)))) + { + goto _fail; + } - rt_hw_spin_unlock(&_clk_lock.lock); + return RT_EOK; + +_fail: + clk->min_rate = old_min; + clk->max_rate = old_max; + + return err; +} + +/** + * @brief Set clock rate range + * + * @param clk point to clock + * @param min minimum clock rate + * @param max minimum clock rate + * + * @return rt_err_t RT_EOK on set clock rate range sucessfully, and other value is failed. + */ +rt_err_t rt_clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t max) +{ + rt_err_t err; + + if (!clk) + { + return RT_EOK; } + clk_lock(); + err = clk_set_rate_range(clk, min, max); + clk_unlock(); + return err; } @@ -810,16 +943,12 @@ rt_err_t rt_clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t ma */ rt_err_t rt_clk_set_min_rate(struct rt_clk *clk, rt_ubase_t rate) { - rt_err_t err = RT_EOK; - - if (clk && clk->clk_np) + if (clk) { - struct rt_clk_node *clk_np = clk->clk_np; - - err = rt_clk_set_rate_range(clk, rate, clk_np->max_rate); + return rt_clk_set_rate_range(clk, rate, clk->max_rate); } - return err; + return RT_EOK; } /** @@ -832,13 +961,158 @@ rt_err_t rt_clk_set_min_rate(struct rt_clk *clk, rt_ubase_t rate) */ rt_err_t rt_clk_set_max_rate(struct rt_clk *clk, rt_ubase_t rate) { - rt_err_t err = RT_EOK; + if (clk) + { + return rt_clk_set_rate_range(clk, clk->min_rate, rate); + } + + return RT_EOK; +} + +/** + * @brief Set clock rate. + * + * @details This function directly sets the frequency of the given clock. + * If the hardware driver supports set_rate(), the new rate will + * be applied immediately and the cached rate will be updated. + * + * @param clk Pointer to clock handle. + * @param rate Target frequency (Hz). + * + * @retval RT_EOK Successfully updated. + * @retval -RT_EINVAL Invalid parameter. + * @retval -RT_ENOSYS Clock driver does not support set_rate(). + * @retval other Hardware-specific error returned by set_rate(). + */ +static rt_err_t clk_set_rate(struct rt_clk *clk, rt_ubase_t rate) +{ + rt_err_t err; + rt_ubase_t old_rate, prate; + rt_bool_t was_enabled = RT_FALSE; + rt_bool_t was_disabled = RT_FALSE; + struct rt_clk *parent = RT_NULL; + struct rt_clk_node *clk_np; + struct rt_clk_cell *cell; + + cell = clk->cell; + + if (!cell->ops->set_rate) + { + return -RT_ENOSYS; + } + + clk_np = cell->clk_np; + + if (cell->flags & RT_CLK_F_GET_RATE_NOCACHE) + { + old_rate = clk_get_rate(clk); + } + else + { + old_rate = cell->rate; + } + rate = rt_clamp(rate, clk->min_rate, clk->max_rate); + + parent = clk_get_parent(clk); + + if (cell->parents_nr > 1) + { + rt_uint8_t best_idx = RT_UINT8_MAX; + rt_ubase_t best_rounded = 0, best_diff = ~0UL; + struct rt_clk_cell *parent_cell, *best_parent_cell = RT_NULL; + + for (rt_uint8_t idx = 0; idx < cell->parents_nr; ++idx) + { + rt_ubase_t rounded, diff; + + if (!(parent_cell = rt_clk_cell_get_parent_by_index(cell, idx))) + { + continue; + } + + if (!parent_cell->clk && !(parent_cell->clk = clk_cell_get_clk(parent_cell))) + { + return RT_NULL; + } + + prate = clk_get_rate(parent_cell->clk); + rounded = clk_round_rate(parent_cell->clk, rate); + rounded = (rounded > 0) ? rounded : rate; + + diff = rt_abs(rounded - rate); + + if (diff < best_diff) + { + best_idx = idx; + best_diff = diff; + best_rounded = rounded; + best_parent_cell = parent_cell; + } + } + + if (best_idx != RT_UINT8_MAX && parent->cell != best_parent_cell) + { + parent = best_parent_cell->clk; + + if ((err = clk_set_parent(clk, parent))) + { + return err; + } + + rate = best_rounded; + } + } + + if (parent) + { + if (cell->flags & RT_CLK_F_SET_RATE_PARENT) + { + if ((err = clk_set_rate(parent, rate))) + { + return err; + } + } + + prate = clk_get_rate(parent); + } + else + { + prate = 0; + } + + if ((cell->flags & RT_CLK_F_SET_RATE_GATE) && cell->enable_count > 0) + { + was_enabled = RT_TRUE; + clk_disable(clk); + } + else if ((cell->flags & RT_CLK_F_SET_RATE_UNGATE) && cell->enable_count == 0) + { + was_disabled = RT_TRUE; + clk_enable(clk); + } - if (clk && clk->clk_np) + clk_notify(clk_np, RT_CLK_MSG_PRE_RATE_CHANGE, old_rate, rate); + + if ((err = cell->ops->set_rate(cell, rate, prate))) { - struct rt_clk_node *clk_np = clk->clk_np; + clk_notify(clk_np, RT_CLK_MSG_ABORT_RATE_CHANGE, old_rate, rate); + + goto _end; + } + + /* Update cached rate */ + cell->rate = rate; - err = rt_clk_set_rate_range(clk, clk_np->min_rate, rate); + clk_notify(clk_np, RT_CLK_MSG_POST_RATE_CHANGE, old_rate, rate); + +_end: + if (was_enabled) + { + clk_enable(clk); + } + else if (was_disabled) + { + clk_disable(clk); } return err; @@ -854,76 +1128,361 @@ rt_err_t rt_clk_set_max_rate(struct rt_clk *clk, rt_ubase_t rate) */ rt_err_t rt_clk_set_rate(struct rt_clk *clk, rt_ubase_t rate) { - rt_err_t err = RT_EOK; + rt_err_t err; - rate = rt_clk_round_rate(clk, rate); + if (clk) + { + clk_lock(); + err = clk_set_rate(clk, rate); + clk_unlock(); + } + else + { + err = RT_EOK; + } + + return err; +} + +/** + * @brief Internal helper to get clock rate (no locking, no validation). + * + * @param clk Pointer to clock handle. + * + * @return Clock frequency in Hz, or 0 if invalid. + */ +static rt_ubase_t clk_get_rate(struct rt_clk *clk) +{ + rt_ubase_t prate; + struct rt_clk *parent; + struct rt_clk_cell *cell; + + cell = clk->cell; + parent = clk_get_parent(clk); + prate = parent ? clk_get_rate(parent) : 0; + + if (cell->ops->recalc_rate) + { + cell->rate = cell->ops->recalc_rate(cell, prate); + } + else + { + cell->rate = prate; + } + + return cell->rate; +} + +/** + * @brief Get clock rate + * + * @param clk point to clock + * + * @return rt_ubase_t clock rate or error code + */ +rt_ubase_t rt_clk_get_rate(struct rt_clk *clk) +{ + rt_ubase_t rate; - if (clk && clk->clk_np && rate > 0) + if (clk) + { + clk_lock(); + rate = clk_get_rate(clk); + clk_unlock(); + } + else { - struct rt_clk_node *clk_np = clk->clk_np; + rate = 0; + } + + return rate; +} + +/** + * @brief Internal helper to round clock rate (no locking). + * + * @param clk Pointer to clock handle. + * @param rate Desired frequency in Hz. + * + * @return Rounded frequency in Hz (may differ from requested value). + */ +static rt_ubase_t clk_round_rate(struct rt_clk *clk, rt_ubase_t rate) +{ + rt_ubase_t prate, rounded = rate; + struct rt_clk *parent; + struct rt_clk_cell *cell; + + cell = clk->cell; - rt_hw_spin_lock(&_clk_lock.lock); + parent = clk_get_parent(clk); + prate = parent ? clk_get_rate(parent) : 0; - if (clk_np->min_rate && rate < clk_np->min_rate) + /* If driver provides round_rate() callback, use it */ + if (cell->ops->round_rate) + { + rt_base_t res = cell->ops->round_rate(cell, rate, &prate); + + if (res > 0) { - err = -RT_EINVAL; + rounded = res; } + } + else if ((cell->flags & RT_CLK_F_SET_RATE_PARENT) && parent) + { + /* Delegate rounding to parent clock if supported */ + rounded = clk_round_rate(parent, rate); + } + + /* Clamp to valid range */ + return rt_clamp(rounded, clk->min_rate, clk->max_rate); +} - if (clk_np->max_rate && rate > clk_np->max_rate) +/** + * @brief Check if clock rate is in the minimum to maximun and get it + * + * @param clk point to clock + * @param rate rate will be checked + * + * @return rt_base_t get the correct rate + * @note if parameter rate less than the minimum or more than maximum, the + retrun rate will be set to minimum ormaximum value + */ +rt_base_t rt_clk_round_rate(struct rt_clk *clk, rt_ubase_t rate) +{ + rt_ubase_t rounded = 0; + + if (clk) + { + clk_lock(); + rounded = clk_round_rate(clk, rate); + clk_unlock(); + } + + return rounded; +} + +/** + * @brief Set parent clock + * + * @param clk_np point to clock node + * @param parent_np point to parent rt_clk + * + * @return rt_err_t RT_EOK on set clock parent sucessfully, and other value is failed. + */ +static rt_err_t clk_set_parent(struct rt_clk *clk, struct rt_clk *parent) +{ + rt_err_t err; + rt_uint8_t idx = RT_UINT8_MAX; + rt_bool_t was_enabled = RT_FALSE; + struct rt_clk_cell *cell; + + cell = clk->cell; + + /* Already same parent? */ + if (parent) + { + if (cell->parent == parent->cell->clk) { - err = -RT_EINVAL; + return RT_EOK; } + } + else if (!cell->parent) + { + return RT_EOK; + } - if (!err) + /* No multi-parent */ + if (cell->parents_nr <= 1) + { + return -RT_EINVAL; + } + + /* Multi-parent but driver lacks support */ + if (!cell->ops->set_parent) + { + return -RT_EINVAL; + } + + /* Find new parent index if provided */ + if (parent) + { + const char *pname = parent->cell->name; + + /* Temporarily gate if required */ + if ((cell->flags & RT_CLK_F_SET_PARENT_GATE) && cell->enable_count > 0) { - if (clk_np->ops->set_rate) + was_enabled = RT_TRUE; + clk_disable(clk); + } + + for (int i = 0; i < cell->parents_nr; ++i) + { + if (!rt_strcmp(cell->parent_names[i], pname)) { - rt_ubase_t old_rate = clk_np->rate; + idx = i; + break; + } + } - err = clk_np->ops->set_rate(clk, rate, - rt_clk_get_rate(clk_np->parent ? clk_np->parent->clk : RT_NULL)); + if (idx == RT_UINT8_MAX) + { + LOG_W("%s: Invalid parent %s", cell->name, pname); + err = -RT_EINVAL; + goto _end; + } - if (clk_np->rate != old_rate) - { - clk_notify(clk_np, RT_CLK_MSG_PRE_RATE_CHANGE, old_rate, clk_np->rate); - } - } - else + if (cell->ops->set_parent) + { + if (!(err = cell->ops->set_parent(cell, idx))) { - err = -RT_ENOSYS; + cell->parent = parent->cell->clk; } } + else + { + err = -RT_ENOSYS; + } - rt_hw_spin_unlock(&_clk_lock.lock); + _end: + if (was_enabled) + { + clk_enable(clk); + } + } + else + { + err = RT_EOK; } return err; } /** - * @brief Get clock rate + * @brief Set clock parent object * * @param clk point to clock + * @param clk_parent point to parent clock * - * @return rt_ubase_t clock rate or error code + * @return rt_err_t RT_EOK on set clock parent sucessfully, and other value is failed. */ -rt_ubase_t rt_clk_get_rate(struct rt_clk *clk) +rt_err_t rt_clk_set_parent(struct rt_clk *clk, struct rt_clk *clk_parent) { - rt_ubase_t rate = 0; + rt_err_t err; if (clk) { - if (clk->rate) + clk_lock(); + err = clk_set_parent(clk, clk_parent); + clk_unlock(); + } + else + { + err = RT_EOK; + } + + return err; +} + +/** + * @brief Resolve and return the parent clock of a given clock handle. + * + * @details This function determines the parent clock for the provided + * clock handle (`clk`). It first checks for an existing cached + * parent, and if none exists: + * 1. Calls the driver's `get_parent()` callback to retrieve + * the parent index. + * 2. Looks up the corresponding parent clock by name from: + * - The controller's `parents_clk` array, or + * - The controller's own `cells` array. + * 3. If a matching cell exists but no rt_clk handle yet, a new + * handle is allocated via `clk_alloc()`. + * 4. The resolved parent is cached in `cell->parent`. + * + * @param clk Pointer to the clock handle. + * + * @return Pointer to the parent clock handle, or NULL on failure. + */ +static struct rt_clk *clk_get_parent(struct rt_clk *clk) +{ + rt_uint8_t idx; + struct rt_clk *parent; + struct rt_clk_cell *cell, *parent_cell; + + cell = clk->cell; + + if (!cell->parent_names) + { + return RT_NULL; + } + + if (cell->parent) + { + return cell->parent; + } + + if (cell->parents_nr > 1) + { + if (!cell->ops->get_parent) { - rate = clk->rate; + LOG_E("%s: Missing get_parent() while having parent_names", cell->name); + return RT_NULL; } - else if (clk->clk_np) + + idx = cell->ops->get_parent(cell); + + if (idx >= cell->parents_nr) { - rate = clk->clk_np->rate; + LOG_E("%s: Get parent fail", cell->name); + return RT_NULL; } } + else + { + idx = 0; + } - return rate; + parent_cell = rt_clk_cell_get_parent_by_index(cell, idx); + + if (!parent_cell) + { + return RT_NULL; + } + + if (!parent_cell->clk && !(parent_cell->clk = clk_cell_get_clk(parent_cell))) + { + return RT_NULL; + } + + parent = parent_cell->clk; + cell->parent = parent; + + return parent; +} + +/** + * @brief Get parent clock pointer + * + * @param clk child clock + * + * @return struct rt_clk* parent clock object pointer will be return, unless child + clock node havn't parent node instead return RT_NULL + */ +struct rt_clk *rt_clk_get_parent(struct rt_clk *clk) +{ + struct rt_clk *parent; + + if (clk) + { + clk_lock(); + parent = clk_get_parent(clk); + clk_unlock(); + } + else + { + parent = RT_NULL; + } + + return parent; } /** @@ -936,15 +1495,32 @@ rt_ubase_t rt_clk_get_rate(struct rt_clk *clk) */ rt_err_t rt_clk_set_phase(struct rt_clk *clk, int degrees) { - rt_err_t err = RT_EOK; + rt_err_t err; - if (clk && clk->clk_np && clk->clk_np->ops->set_phase) + if (clk) { - rt_hw_spin_lock(&_clk_lock.lock); + struct rt_clk_cell *cell = clk->cell; - err = clk->clk_np->ops->set_phase(clk, degrees); + /* Sanity check degrees */ + degrees %= 360; - rt_hw_spin_unlock(&_clk_lock.lock); + if (degrees < 0) + { + degrees += 360; + } + + if (cell->ops->set_phase) + { + err = cell->ops->set_phase(cell, degrees); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = RT_EOK; } return err; @@ -959,122 +1535,310 @@ rt_err_t rt_clk_set_phase(struct rt_clk *clk, int degrees) */ rt_base_t rt_clk_get_phase(struct rt_clk *clk) { - rt_base_t res = RT_EOK; + rt_base_t res; - if (clk && clk->clk_np && clk->clk_np->ops->get_phase) + if (clk) { - rt_hw_spin_lock(&_clk_lock.lock); + struct rt_clk_cell *cell = clk->cell; - res = clk->clk_np->ops->get_phase(clk); - - rt_hw_spin_unlock(&_clk_lock.lock); + if (cell->ops->get_phase) + { + res = cell->ops->get_phase(cell); + } + else + { + res = 0; + } + } + else + { + res = 0; } return res; } /** - * @brief Check if clock rate is in the minimum to maximun and get it + * @brief Check if the clock cell is prepared * - * @param clk point to clock - * @param rate rate will be checked + * @param cell Pointer to clock cell * - * @return rt_base_t get the correct rate - * @note if parameter rate less than the minimum or more than maximum, the - retrun rate will be set to minimum ormaximum value + * @return RT_TRUE if prepared, otherwise RT_FALSE */ -rt_base_t rt_clk_round_rate(struct rt_clk *clk, rt_ubase_t rate) +rt_bool_t rt_clk_cell_is_prepared(const struct rt_clk_cell *cell) { - rt_base_t res = -RT_EINVAL; + RT_ASSERT(cell != RT_NULL); - if (clk && clk->clk_np) + if (cell->ops->is_prepared) { - struct rt_clk_node *clk_np = clk->clk_np; + return cell->ops->is_prepared((struct rt_clk_cell *)cell); + } - if (clk_np->ops->round_rate) - { - rt_ubase_t best_parent_rate; + return RT_TRUE; +} - rt_hw_spin_lock(&_clk_lock.lock); +/** + * @brief Get or create clock handle for a clock cell + * + * @param cell Pointer to clock cell + * + * @return Pointer to clock handle, or RT_NULL on failure + * + * @note If the clock handle does not exist, it will be created automatically. + */ +static struct rt_clk *clk_cell_get_clk(struct rt_clk_cell *cell) +{ + if (cell->clk) + { + return cell->clk; + } - if (clk_np->min_rate && clk_np->max_rate) - { - rate = rt_clamp(rate, clk_np->min_rate, clk_np->max_rate); - } + cell->clk = clk_alloc(cell, RT_NULL, RT_NULL); - res = clk_np->ops->round_rate(clk, rate, &best_parent_rate); - (void)best_parent_rate; + return cell->clk; +} - rt_hw_spin_unlock(&_clk_lock.lock); +/** + * @brief Get or create clock handle for a clock cell + * + * @param cell Pointer to clock cell + * @param con_id Connection identifier for the clock cell + * + * @return Pointer to clock handle, or RT_NULL on failure + * + * @note If the clock handle does not exist, it will be created automatically. + */ +struct rt_clk *rt_clk_cell_get_clk(const struct rt_clk_cell *cell, const char *con_id) +{ + struct rt_clk *clk; + + RT_ASSERT(cell != RT_NULL); + + if ((clk = clk_cell_get_clk((struct rt_clk_cell *)cell))) + { + if (!clk->con_id) + { + clk->con_id = con_id; } - else + } + + return clk; +} + +/** + * @brief Check if the clock cell is enabled + * + * @param cell Pointer to clock cell + * + * @return RT_TRUE if enabled, otherwise RT_FALSE + */ +rt_bool_t rt_clk_cell_is_enabled(const struct rt_clk_cell *cell) +{ + RT_ASSERT(cell != RT_NULL); + + if (cell->ops->is_enabled) + { + return cell->ops->is_enabled((struct rt_clk_cell *)cell); + } + + return RT_TRUE; +} + +/** + * @brief Get current rate of the clock cell + * + * @param cell Pointer to clock cell + * + * @return Current rate in Hz + */ +rt_ubase_t rt_clk_cell_get_rate(const struct rt_clk_cell *cell) +{ + struct rt_clk *clk; + + RT_ASSERT(cell != RT_NULL); + + clk = clk_cell_get_clk((struct rt_clk_cell *)cell); + + return clk_get_rate(clk); +} + +/** + * @brief Round a desired rate to the nearest supported rate + * + * @param cell Pointer to clock cell + * @param rate Desired frequency in Hz + * + * @return Closest supported frequency in Hz + */ +rt_ubase_t rt_clk_cell_round_rate(struct rt_clk_cell *cell, rt_ubase_t rate) +{ + struct rt_clk *clk; + + RT_ASSERT(cell != RT_NULL); + + clk = clk_cell_get_clk((struct rt_clk_cell *)cell); + + return clk_round_rate(clk, rate); +} + +/** + * @brief Get parent clock cell + * + * @param cell Pointer to clock cell + * + * @return Pointer to parent clock cell, or RT_NULL if none + */ +struct rt_clk_cell *rt_clk_cell_get_parent(const struct rt_clk_cell *cell) +{ + struct rt_clk *clk, *parent_clk; + + RT_ASSERT(cell != RT_NULL); + + clk = clk_cell_get_clk((struct rt_clk_cell *)cell); + + if ((parent_clk = clk_get_parent(clk))) + { + return parent_clk->cell; + } + + return RT_NULL; +} + +/** + * @brief Get parent clock cell by index + * + * @param cell Pointer to clock cell + * @param idx Parent index + * + * @return Pointer to parent clock cell, or RT_NULL if not found + */ +struct rt_clk_cell *rt_clk_cell_get_parent_by_index(const struct rt_clk_cell *cell, rt_uint8_t idx) +{ + const char *pname; + struct rt_clk_cell *parent_cell; + struct rt_clk_node *clk_np, *clk_np_raw; + + RT_ASSERT(cell != RT_NULL); + RT_ASSERT(idx != RT_UINT8_MAX); + + clk_np = cell->clk_np; + + if (cell->parents_nr > 1) + { + pname = cell->parent_names[idx]; + } + else if (idx == 0) + { + pname = cell->parent_name; + } + else + { + pname = RT_NULL; + goto _end; + } + + clk_np_raw = RT_NULL; + +_retry: + if (!rt_is_err_or_null(clk_np->parents_clk)) + { + struct rt_clk_array *parents_clk = clk_np->parents_clk; + + for (rt_uint8_t i = 0; i < parents_clk->count; ++i) { - if (rate < clk_np->min_rate) - { - res = clk_np->min_rate; - } - else if (rate > clk_np->max_rate) - { - res = clk_np->max_rate; - } - else + if (!rt_strcmp(pname, parents_clk->clks[i]->cell->name)) { - res = rate; + return parents_clk->clks[i]->cell; } } } - return res; + for (int i = 0; i < clk_np->cells_nr; ++i) + { + parent_cell = clk_np->cells[i]; + + if (!parent_cell) + { + continue; + } + + if (!rt_strcmp(parent_cell->name, pname)) + { + return (struct rt_clk_cell *)parent_cell; + } + } + + /* Find on the global list */ + if (clk_np_raw) + { + do { + clk_np = rt_list_entry(clk_np->parent.list.next, rt_typeof(*clk_np), parent.list); + } while (&clk_np->parent.list != &_clk_node_nodes && clk_np == clk_np_raw); + } + else + { + clk_np_raw = clk_np; + clk_np = rt_list_entry(_clk_node_nodes.next, rt_typeof(*clk_np), parent.list); + } + + if (&clk_np->parent.list != &_clk_node_nodes) + { + goto _retry; + } + +_end: + LOG_E("%s: Parent[%d] '%s' not found", cell->name, idx, pname); + + return RT_NULL; } /** - * @brief Set clock parent object + * @brief Get current parent index * - * @param clk point to clock - * @param clk_parent point to parent clock + * @param cell Pointer to clock cell * - * @return rt_err_t RT_EOK on set clock parent sucessfully, and other value is failed. + * @return Parent index on success, negative error code on failure */ -rt_err_t rt_clk_set_parent(struct rt_clk *clk, struct rt_clk *clk_parent) +rt_uint8_t rt_clk_cell_get_parent_index(struct rt_clk_cell *cell) { - rt_err_t err = RT_EOK; + RT_ASSERT(cell != RT_NULL); - if (clk && clk->clk_np && clk->clk_np->ops->set_parent) + if (cell->ops->get_parent) { - rt_hw_spin_lock(&_clk_lock.lock); - - err = clk->clk_np->ops->set_parent(clk, clk_parent); - - rt_hw_spin_unlock(&_clk_lock.lock); + return cell->ops->get_parent(cell); } - return err; + return RT_UINT8_MAX; } /** - * @brief Get parent clock pointer + * @brief Set new parent clock cell * - * @param clk child clock + * @param cell Pointer to clock cell + * @param parent Pointer to new parent clock cell * - * @return struct rt_clk* parent clock object pointer will be return, unless child - clock node havn't parent node instead return RT_NULL + * @return RT_EOK on success, or error code on failure */ -struct rt_clk *rt_clk_get_parent(struct rt_clk *clk) +rt_err_t rt_clk_cell_set_parent(struct rt_clk_cell *cell, struct rt_clk_cell *parent) { - struct rt_clk *parent = RT_NULL; + rt_err_t err; + struct rt_clk *clk, *parent_clk = RT_NULL; - if (clk) - { - struct rt_clk_node *clk_np = clk->clk_np; + RT_ASSERT(cell != RT_NULL); - rt_hw_spin_lock(&_clk_lock.lock); + clk = clk_cell_get_clk((struct rt_clk_cell *)cell); - parent = clk_np->parent ? clk_np->parent->clk : RT_NULL; + if (parent) + { + parent_clk = clk_cell_get_clk((struct rt_clk_cell *)parent); + } - rt_hw_spin_unlock(&_clk_lock.lock); + if ((err = clk_set_parent(clk, parent_clk))) + { + return err; } - return parent; + return RT_EOK; } /** @@ -1133,6 +1897,40 @@ struct rt_clk *rt_clk_get_by_name(struct rt_device *dev, const char *name) clk = rt_ofw_get_clk_by_name(dev->ofw_node, name); #endif + if (!clk && name) + { + struct rt_clk_node *clk_np; + struct rt_clk_cell *cell = RT_NULL; + + clk_lock(); + rt_list_for_each_entry(clk_np, &_clk_node_nodes, parent.list) + { + for (int i = 0; i < clk_np->cells_nr; ++i) + { + cell = clk_np->cells[i]; + + if (!cell) + { + continue; + } + + if (!rt_strcmp(cell->name, name)) + { + clk = clk_alloc(cell, rt_dm_dev_get_name(dev), RT_NULL); + + if (clk) + { + clk_cell_bind(cell, clk); + } + + goto _out_lock; + } + } + } + _out_lock: + clk_unlock(); + } + return clk; } @@ -1148,7 +1946,7 @@ void rt_clk_array_put(struct rt_clk_array *clk_arr) { for (int i = 0; i < clk_arr->count; ++i) { - if (clk_arr->clks[i]) + if (!rt_is_err_or_null(clk_arr->clks[i])) { rt_clk_put(clk_arr->clks[i]); } @@ -1170,100 +1968,122 @@ void rt_clk_array_put(struct rt_clk_array *clk_arr) */ void rt_clk_put(struct rt_clk *clk) { - if (clk) + if (clk && clk->cell->clk != clk) { - clk_put(clk->clk_np); - clk_free(clk); + rt_free(clk); } } #ifdef RT_USING_OFW +static struct rt_clk_array *ofw_get_clk_array(struct rt_ofw_node *np, + const char *basename, const char *propname); +static struct rt_clk *ofw_get_clk(struct rt_ofw_node *np, + const char *basename, int index, const char *name); + +/** + * @brief Retrieve a clock cell from a clock node using OFW (device tree) arguments. + * + * @details + * This helper function translates parsed device tree clock specifiers + * (from `clocks = <&phandle args...>;`) into an actual `rt_clk_cell` pointer + * belonging to the specified `clk_np` (clock node). + * + * Behavior: + * - If the clock node provides a custom parser (`clk_np->ofw_parse`), + * this function delegates the lookup to that callback. + * → This allows complex clock providers (e.g. multiplexers, dividers) + * to interpret multiple arguments or encoded indices. + * - Otherwise, it assumes the first argument (`args->args[0]`) + * is the cell index and directly returns `clk_np->cells[args->args[0]]`. + * + * This abstraction allows different clock providers to implement flexible + * device-tree bindings without changing the core clock framework. + * + * @param clk_np Pointer to the clock node containing clock cells. + * @param args Pointer to parsed OFW clock arguments (from device tree). + * + * @return Pointer to the resolved `rt_clk_cell` if found, or `RT_NULL` on failure. + * + * @note + * - The default indexing behavior assumes that the clock node’s `#clock-cells` + * property equals 1 (only one integer index). + * - Complex clock providers should implement their own `.ofw_parse()` callback + * to handle multiple argument cases. + * - This function is typically used during `rt_ofw_clk_get()` to + * resolve device clock references. + */ +static struct rt_clk_cell *ofw_get_cell(struct rt_clk_node *clk_np, struct rt_ofw_cell_args *args) +{ + if (clk_np->ofw_parse) + { + return clk_np->ofw_parse(clk_np, args); + } + + return clk_np->cells[args->args[0]]; +} + /** - * @brief Get a clock object from a device tree node without acquiring a lock + * @brief Get clock array from ofw by name * - * @param np point to ofw node - * @param index index of clock in ofw - * @param name connection identifier for the clock - * @param locked lock flag for indicating whether the caller holds the lock + * @param np point to ofw node + * @param basename name of clocks base name + * @param propname name of clocks prop name * - * @return struct rt_clk* point to the newly created clock object, or an error pointer + * @return struct rt_clk_array* point to the newly created clock array, or an error pointer */ -static struct rt_clk *ofw_get_clk_no_lock(struct rt_ofw_node *np, int index, const char *name, rt_bool_t locked) +static struct rt_clk_array *ofw_get_clk_array(struct rt_ofw_node *np, + const char *basename, const char *propname) { - struct rt_clk *clk = RT_NULL; - struct rt_ofw_cell_args clk_args; + int count; + rt_bool_t has_name; + struct rt_clk_array *clk_arr; - if (!rt_ofw_parse_phandle_cells(np, "clocks", "#clock-cells", index, &clk_args)) + if ((count = rt_ofw_count_phandle_cells(np, basename, "#clock-cells")) <= 0) { - int count; - struct rt_object *obj; - struct rt_clk_node *clk_np = RT_NULL; - struct rt_ofw_node *clk_ofw_np = clk_args.data; - - if (!rt_ofw_data(clk_ofw_np)) + if (count) { - if (locked) - { - rt_hw_spin_unlock(&_clk_lock.lock); - } - - rt_platform_ofw_request(clk_ofw_np); - - if (locked) - { - rt_hw_spin_lock(&_clk_lock.lock); - } + return rt_err_ptr(count); } - if (rt_ofw_data(clk_ofw_np) && (obj = rt_ofw_parse_object(clk_ofw_np, - RT_CLK_NODE_OBJ_NAME, "#clock-cells"))) - { - clk_np = rt_container_of(obj, struct rt_clk_node, rt_parent); + return RT_NULL; + } - count = rt_ofw_count_of_clk(clk_ofw_np); - } + clk_arr = rt_calloc(1, sizeof(*clk_arr) + sizeof(clk_arr->clks[0]) * count); + + if (!clk_arr) + { + return rt_err_ptr(-RT_ENOMEM); + } - rt_ofw_node_put(clk_ofw_np); + clk_arr->count = count; + has_name = rt_ofw_prop_read_bool(np, propname); - if (clk_np) - { - if (count > 1) - { - /* args[0] must be the index of CLK */ - clk_np = &clk_np[clk_args.args[0]]; - } + clk_lock(); + for (int i = 0; i < count; ++i) + { + const char *name = RT_NULL; - clk = clk_create(clk_np, np->full_name, name, &clk_args, np); - } - else + if (has_name) { - clk = rt_err_ptr(-RT_ERROR); + rt_ofw_prop_read_string_index(np, "clock-names", i, &name); } - } - return clk; -} + clk_arr->clks[i] = ofw_get_clk(np, basename, i, name); -/** - * @brief Get clock from ofw with acquiring a spin lock - * - * @param np point to ofw node - * @param index index of clock in ofw - * @param name connection identifier for the clock - * - * @return struct rt_clk* point to the newly created clock object, or an error pointer - */ -static struct rt_clk *ofw_get_clk(struct rt_ofw_node *np, int index, const char *name) -{ - struct rt_clk *clk; + if (rt_is_err(clk_arr->clks[i])) + { + rt_err_t err = rt_ptr_err(clk_arr->clks[i]); - rt_hw_spin_lock(&_clk_lock.lock); + clk_unlock(); - clk = ofw_get_clk_no_lock(np, index, name, RT_TRUE); + rt_clk_array_put(clk_arr); - rt_hw_spin_unlock(&_clk_lock.lock); + return rt_err_ptr(err); + } + } + clk_unlock(); - return clk; + return clk_arr; } /** @@ -1275,59 +2095,115 @@ static struct rt_clk *ofw_get_clk(struct rt_ofw_node *np, int index, const char */ struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np) { - int count; - struct rt_clk_array *clk_arr = RT_NULL; - if (!np) { return rt_err_ptr(-RT_EINVAL); } - if ((count = rt_ofw_count_phandle_cells(np, "clocks", "#clock-cells")) > 0) - { - clk_arr = rt_calloc(1, sizeof(*clk_arr) + sizeof(clk_arr->clks[0]) * count); + return ofw_get_clk_array(np, "clocks", "clock-names"); +} - if (clk_arr) - { - int i; - rt_err_t err = RT_EOK; - rt_bool_t has_name = rt_ofw_prop_read_bool(np, "clock-names"); +/** + * @brief Get clock from ofw + * + * @param np point to ofw node + * @param basename name of clocks base name + * @param index index of clock in ofw + * @param name connection identifier for the clock + * + * @return struct rt_clk* point to the newly created clock object, or an error pointer + */ +static struct rt_clk *ofw_get_clk(struct rt_ofw_node *np, + const char *basename, int index, const char *name) +{ + struct rt_object *obj; + struct rt_clk *clk; + struct rt_clk_cell *cell; + struct rt_clk_node *clk_np = RT_NULL; + struct rt_ofw_node *clk_ofw_np; + struct rt_ofw_cell_args clk_args; - clk_arr->count = count; + if (rt_ofw_parse_phandle_cells(np, basename, "#clock-cells", index, &clk_args)) + { + return RT_NULL; + } - rt_hw_spin_lock(&_clk_lock.lock); + clk_ofw_np = clk_args.data; - for (i = 0; i < count; ++i) - { - const char *name = RT_NULL; + if (!rt_ofw_data(clk_ofw_np)) + { + if (clk_ofw_np == np) + { + LOG_D("%s: No registration to the system yet", rt_ofw_node_full_name(clk_ofw_np)); + return RT_NULL; + } - if (has_name) - { - rt_ofw_prop_read_string_index(np, "clock-names", i, &name); - } + rt_platform_ofw_request(clk_ofw_np); + } - clk_arr->clks[i] = ofw_get_clk_no_lock(np, i, name, RT_FALSE); + if (rt_ofw_data(clk_ofw_np) && (obj = rt_ofw_parse_object(clk_ofw_np, + RT_CLK_NODE_OBJ_NAME, "#clock-cells"))) + { + clk_np = rt_container_of(obj, struct rt_clk_node, parent); + } - if (rt_is_err(clk_arr->clks[i])) - { - err = rt_ptr_err(clk_arr->clks[i]); + if (!clk_np) + { + clk = rt_err_ptr(-RT_EINVAL); + goto _end; + } - --i; - break; - } - } + if (!clk_args.args_count) + { + clk_args.args[0] = 0; + } + index = clk_args.args[0]; - rt_hw_spin_unlock(&_clk_lock.lock); + if (rt_ofw_prop_read_bool(clk_ofw_np, "clock-indices")) + { + const fdt32_t *val_raw; + rt_uint32_t val, indice = 0; + struct rt_ofw_prop *prop; - if (i > 0 && i < count) + rt_ofw_foreach_prop_u32(clk_ofw_np, "clock-indices", prop, val_raw, val) + { + if (index == val) { - rt_clk_array_put(clk_arr); - clk_arr = rt_err_ptr(err); + index = indice; + goto _goon; } + ++indice; } + + clk = rt_err_ptr(-RT_EINVAL); + goto _end; } +_goon: - return clk_arr; + rt_ofw_prop_read_string_index(clk_ofw_np, "clock-output-names", index, &name); + + if (!(cell = ofw_get_cell(clk_np, &clk_args))) + { + LOG_D("%s: CLK index = %d (%s) is not implemented", + rt_ofw_node_full_name(np), index, name); + return RT_NULL; + } + + clk = clk_alloc(cell, rt_ofw_node_full_name(np), name); + + if (clk) + { + clk_cell_bind(cell, clk); + } + else + { + clk = rt_err_ptr(-RT_ENOMEM); + } + +_end: + rt_ofw_node_put(clk_ofw_np); + + return clk; } /** @@ -1344,7 +2220,7 @@ struct rt_clk *rt_ofw_get_clk(struct rt_ofw_node *np, int index) if (np && index >= 0) { - clk = ofw_get_clk(np, index, RT_NULL); + clk = ofw_get_clk(np, "clocks", index, RT_NULL); } return clk; @@ -1368,7 +2244,7 @@ struct rt_clk *rt_ofw_get_clk_by_name(struct rt_ofw_node *np, const char *name) if (index >= 0) { - clk = ofw_get_clk(np, index, name); + clk = ofw_get_clk(np, "clocks", index, name); } } @@ -1431,6 +2307,10 @@ rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np) ++count; } } + if (!count) + { + count = 1; + } } else { @@ -1450,6 +2330,219 @@ rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np) return -RT_EINVAL; } +/** + * @brief Get parent clock name from device tree + * + * @param np Pointer to device tree node + * @param index Index within "clocks" property + * + * @return const char* Name of the parent clock, or NULL if not found + */ +const char *rt_ofw_clk_get_parent_name(struct rt_ofw_node *np, int index) +{ + const char *pname = RT_NULL; + struct rt_ofw_node *clk_ofw_np; + struct rt_ofw_cell_args clk_args; + + if (rt_ofw_parse_phandle_cells(np, "clocks", "#clock-cells", index, &clk_args)) + { + return RT_NULL; + } + + clk_ofw_np = clk_args.data; + + index = clk_args.args_count ? clk_args.args[0] : 0; + + if (rt_ofw_prop_read_bool(clk_ofw_np, "clock-indices")) + { + const fdt32_t *val_raw; + rt_uint32_t val, indice = 0; + struct rt_ofw_prop *prop; + + rt_ofw_foreach_prop_u32(clk_ofw_np, "clock-indices", prop, val_raw, val) + { + if (index == val) + { + index = indice; + goto _goon; + } + ++indice; + } + + goto _end; + } +_goon: + + if (rt_ofw_prop_read_string_index(clk_ofw_np, "clock-output-names", index, &pname)) + { + struct rt_clk *provider_clk = rt_ofw_get_clk(np, index); + + if (rt_is_err_or_null(provider_clk)) + { + pname = provider_clk->cell->name; + + rt_clk_put(provider_clk); + } + } + +_end: + rt_ofw_node_put(clk_ofw_np); + + return pname; +} + +/** + * @brief Initialize clock from device tree (OFW) defaults. + * + * @details + * This function applies the device tree–specified clock default. + * It processes the following standard DT bindings in order: + * + * - **assigned-clocks**: list of clock phandles that must be configured + * before the device is probed. + * - **assigned-clock-parents**: optional list of corresponding parent + * clock phandles for each entry in *assigned-clocks*. + * - **assigned-clock-rates**: optional list of target rates (in Hz) + * to set for each clock in *assigned-clocks*. + * + * For each assigned clock, the function will: + * 1. Retrieve the referenced clock handle. + * 2. Set its parent if a corresponding entry in + * *assigned-clock-parents* exists. + * 3. Set its rate if a corresponding entry in + * *assigned-clock-rates* exists. + * + * This ensures that all clocks required by a device are configured + * according to the hardware design before the device driver runs. + * + * @param np Point to ofw node + * + * @return + * - RT_EOK : Successfully applied assigned-clocks settings. + * - -RT_EINVAL : Invalid or inconsistent device tree entries. + * - -RT_ENOSYS : Clock driver does not support required operation. + * - Other negative values : Underlying driver or hardware error. + * + * @note + * - This function should be called **after all clocks in the system + * have been registered**, ensuring that referenced parents exist. + * - Clocks not listed in *assigned-clocks* are left unchanged. + * - The function is typically invoked at the end of + * `rt_clk_node_register()`. + */ +rt_err_t rt_ofw_clk_set_defaults(struct rt_ofw_node *np) +{ + struct rt_clk *clk; + struct rt_clk_array *clk_arr; + + if (!np) + { + return RT_EOK; + } + + clk_arr = ofw_get_clk_array(np, "assigned-clocks", RT_NULL); + + if (rt_is_err(clk_arr)) + { + return rt_ptr_err(clk_arr); + } + + if (clk_arr) + { + rt_uint32_t rate; + struct rt_clk_array *clk_parent_arr; + + clk_parent_arr = ofw_get_clk_array(np, "assigned-clock-parents", RT_NULL); + + if (rt_is_err(clk_parent_arr)) + { + rt_clk_array_put(clk_arr); + return rt_ptr_err(clk_parent_arr); + } + + for (int i = 0; i < clk_arr->count; ++i) + { + clk = clk_arr->clks[i]; + + if (clk_parent_arr && i < clk_parent_arr->count) + { + rt_clk_set_parent(clk, clk_parent_arr->clks[i]); + } + + if (!rt_ofw_prop_read_u32_index(np, "assigned-clock-rates", i, &rate)) + { + rt_clk_set_rate(clk, rate); + } + } + + rt_clk_array_put(clk_parent_arr); + rt_clk_array_put(clk_arr); + } + + return RT_EOK; +} #endif /* RT_USING_OFW */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_MSH) +static int list_clk(int argc, char**argv) +{ + struct rt_clk_node *clk_np; + struct rt_clk_cell *cell, *parent; + + rt_kprintf("%-*.s %-*.s %-*.s %-*.s %-*.s %-*.s Parent\n", + 32, "Name", + 12, "Enable Count", + 13, "Prepare Count", + 11, "Rate", + 32, "Device ID", + 32, "Connection ID"); + + clk_lock(); + rt_list_for_each_entry(clk_np, &_clk_node_nodes, parent.list) + { + for (int i = 0; i < clk_np->cells_nr; ++i) + { + rt_ubase_t rate; + const char *dev_id = "deviceless", *con_id = "no_connection_id"; + + cell = clk_np->cells[i]; + + if (!cell) + { + continue; + } + + rate = cell->rate ? : rt_clk_cell_get_rate(cell); + + if (cell->clk) + { + if (cell->clk->dev_id) + { + dev_id = cell->clk->dev_id; + } + if (cell->clk->con_id) + { + con_id = cell->clk->con_id; + } + } + + parent = rt_clk_cell_get_parent(cell); + + rt_kprintf("%-*.s %-12d %-13d %-11lu %-*.s %-*.s %s\n", + 32, cell->name, + cell->enable_count, + cell->prepare_count, + rate, + 32, dev_id, + 32, con_id, + parent ? parent->name : RT_NULL); + } + } + clk_unlock(); + + return 0; +} +MSH_CMD_EXPORT(list_clk, dump all of clk information); +#endif /* RT_USING_CONSOLE && RT_USING_MSH */ + /**@}*/ \ No newline at end of file diff --git a/components/drivers/include/drivers/clk.h b/components/drivers/include/drivers/clk.h index 26da4d87200..dd74fdc85bf 100644 --- a/components/drivers/include/drivers/clk.h +++ b/components/drivers/include/drivers/clk.h @@ -7,6 +7,7 @@ * Date Author Notes * 2022-11-26 GuEe-GUI first version * 2025-01-24 wumingzi add doxygen comment + * 2024-05-01 GuEe-GUI make cell for hareware clock */ #ifndef __CLK_H__ @@ -30,83 +31,131 @@ #define RT_CLK_NODE_OBJ_NAME "CLKNP" +struct rt_clk; struct rt_clk_ops; -struct rt_reset_control_node; +struct rt_clk_cell; /** - * @brief Clk node, it is a pat of clk source or controller - * @note Defined as the array like this if the CLK have multi out clocks: - * @code{.c} - * struct XYZ_single_clk - * { - * struct rt_clk_node parent; - * ... - * }; + * @brief Clock provider node - represents a hardware clock controller. * - * struct XYZ_multi_clk - * { - * struct rt_clk_node parent[N]; - * ... - * }; - * @endcode - * We assume the 'N' is the max value of element in 'clock-indices' if OFW. + * A @ref rt_clk_node corresponds to one hardware clock provider in the + * system, such as a PLL controller, a clock multiplexer, or a composite + * clock block defined in the device tree. + * + * Each clock node may contain multiple hardware clock outputs, described + * as @ref rt_clk_cell structures, which represent individual leaf clocks. + * + * Members: + * - `parent` — embedded @ref rt_object header for RT-Thread object system. + * - `dev` — back-reference to the hardware device providing this clock domain. + * - `parents_clk` — optional array of parent clock handles. + * - `multi_clk` — number of clock outputs exported by this provider. + * - `cells` — list of @ref rt_clk_cell pointers representing each output. + * - `ofw_parse` — callback used to parse clock arguments from device tree + * (`#clock-cells`) and select the corresponding @ref rt_clk_cell. + * - `priv` — implementation-specific private data. + * + * Typical usage: + * 1. Define a @ref rt_clk_node describing the hardware clock controller. + * 2. Implement `ofw_parse()` to resolve device tree `phandle` arguments. + * 3. Register the node using @ref rt_clk_register(). */ struct rt_clk_node { - struct rt_object rt_parent; + struct rt_object parent; - rt_list_t list; - rt_list_t children_nodes; + struct rt_device *dev; + struct rt_clk_array *parents_clk; + + rt_size_t multi_clk; + + rt_size_t cells_nr; + struct rt_clk_cell **cells; + + struct rt_clk_cell *(*ofw_parse)(struct rt_clk_node *clk_np, struct rt_ofw_cell_args *args); + + void *priv; +}; + +#define RT_CLK_F_SET_RATE_GATE RT_BIT(0) /**< Must be gated across rate change */ +#define RT_CLK_F_SET_PARENT_GATE RT_BIT(1) /**< Must be gated across re-parent */ +#define RT_CLK_F_SET_RATE_PARENT RT_BIT(2) /**< Propagate rate change up one level */ +#define RT_CLK_F_IGNORE_UNUSED RT_BIT(3) /**< Do not gate even if unused */ +#define RT_CLK_F_SET_RATE_UNGATE RT_BIT(4) /**< Clock needs to run to set rate */ +#define RT_CLK_F_IS_CRITICAL RT_BIT(5) /**< Do not gate, ever */ +#define RT_CLK_F_GET_RATE_NOCACHE RT_BIT(6) /**< Do not get rate by cache */ + +/** + * @brief Clock cell - represents a single hardware clock element. + * + * A clk_cell is the fundamental unit of a clock tree, such as a PLL, divider, + * mux, or gate. It maintains its relationship to parent clocks using pointers, + * not lists, for lightweight hierarchy management. + * + * The 'ops' field defines hardware-specific callbacks. The framework invokes + * these during enable, disable, and rate changes. + */ +struct rt_clk_cell +{ + struct rt_clk_node *clk_np; const char *name; const struct rt_clk_ops *ops; - struct rt_clk_node *parent; - struct rt_ref ref; + rt_uint8_t parents_nr; + union + { + const char *parent_name; /**< When parents_nr = 1 */ + const char *const *parent_names; + }; - rt_ubase_t rate; - rt_ubase_t min_rate; - rt_ubase_t max_rate; + rt_ubase_t rate; /**< Cached or fixed rate (not always accurate) */ + struct rt_clk *clk; + struct rt_clk *parent; - rt_size_t notifier_count; + int prepare_count; + int enable_count; - void *priv; + rt_uint32_t flags; - struct rt_clk *clk; - rt_size_t multi_clk; + void *priv; }; /** - * @brief Constant rate clk + * @brief Fixed-rate clock descriptor. + * + * Used for constant-frequency clocks without configurable parents or dividers. */ struct rt_clk_fixed_rate { - struct rt_clk_node clk; + struct rt_clk_cell cell; rt_ubase_t fixed_rate; rt_ubase_t fixed_accuracy; }; /** - * @brief Clk object, it can be clk source or controller + * @brief Clock handle - represents a consumer reference to a clock. + * + * Each consumer obtains an rt_clk instance bound to a specific clk_cell. + * The handle stores consumer-specific constraints such as min/max rate. */ struct rt_clk { - struct rt_clk_node *clk_np; + struct rt_clk_cell *cell; - const char *dev_id; - const char *con_id; + const char *dev_id; /**< Device identifier using this clock */ + const char *con_id; /**< Connection identifier (name) */ - rt_ubase_t rate; - int prepare_count; - int enable_count; - - void *fw_node; - void *priv; + rt_ubase_t min_rate; + rt_ubase_t max_rate; }; /** - * @brief Clk array + * @brief Clock array container. + * + * Represents a group of rt_clk handles, typically used for devices that + * require multiple clock inputs. */ struct rt_clk_array { @@ -116,20 +165,23 @@ struct rt_clk_array struct rt_clk_ops { - rt_err_t (*init)(struct rt_clk *, void *fw_data); - rt_err_t (*finit)(struct rt_clk *); - /* API */ - rt_err_t (*prepare)(struct rt_clk *); - void (*unprepare)(struct rt_clk *); - rt_bool_t (*is_prepared)(struct rt_clk *); - rt_err_t (*enable)(struct rt_clk *); - void (*disable)(struct rt_clk *); - rt_bool_t (*is_enabled)(struct rt_clk *); - rt_err_t (*set_rate)(struct rt_clk *, rt_ubase_t rate, rt_ubase_t parent_rate); - rt_err_t (*set_parent)(struct rt_clk *, struct rt_clk *parent); - rt_err_t (*set_phase)(struct rt_clk *, int degrees); - rt_base_t (*get_phase)(struct rt_clk *); - rt_base_t (*round_rate)(struct rt_clk *, rt_ubase_t drate, rt_ubase_t *prate); + rt_err_t (*prepare)(struct rt_clk_cell *cell); + void (*unprepare)(struct rt_clk_cell *cell); + rt_bool_t (*is_prepared)(struct rt_clk_cell *cell); + + rt_err_t (*enable)(struct rt_clk_cell *cell); + void (*disable)(struct rt_clk_cell *cell); + rt_bool_t (*is_enabled)(struct rt_clk_cell *cell); + + rt_ubase_t (*recalc_rate)(struct rt_clk_cell *cell, rt_ubase_t parent_rate); + rt_base_t (*round_rate)(struct rt_clk_cell *cell, rt_ubase_t drate, rt_ubase_t *prate); + rt_err_t (*set_rate)(struct rt_clk_cell *cell, rt_ubase_t rate, rt_ubase_t parent_rate); + + rt_err_t (*set_parent)(struct rt_clk_cell *cell, rt_uint8_t idx); + rt_uint8_t (*get_parent)(struct rt_clk_cell *cell); + + rt_err_t (*set_phase)(struct rt_clk_cell *cell, int degrees); + rt_base_t (*get_phase)(struct rt_clk_cell *cell); }; struct rt_clk_notifier; @@ -142,7 +194,10 @@ typedef rt_err_t (*rt_clk_notifier_callback)(struct rt_clk_notifier *notifier, rt_ubase_t msg, rt_ubase_t old_rate, rt_ubase_t new_rate); /** - * @brief Clock notifier, it containers of clock list and callback function + * @brief Clock notifier descriptor. + * + * Used to register callbacks for clock events (rate change, abort, etc). + * Each notifier is linked to a specific clock and triggered on rate changes. */ struct rt_clk_notifier { @@ -153,16 +208,14 @@ struct rt_clk_notifier void *priv; }; -rt_err_t rt_clk_register(struct rt_clk_node *clk_np, struct rt_clk_node *parent_np); +rt_err_t rt_clk_register(struct rt_clk_node *clk_np); rt_err_t rt_clk_unregister(struct rt_clk_node *clk_np); rt_err_t rt_clk_notifier_register(struct rt_clk *clk, struct rt_clk_notifier *notifier); rt_err_t rt_clk_notifier_unregister(struct rt_clk *clk, struct rt_clk_notifier *notifier); -rt_err_t rt_clk_set_parent(struct rt_clk *clk, struct rt_clk *clk_parent); - rt_err_t rt_clk_prepare(struct rt_clk *clk); -rt_err_t rt_clk_unprepare(struct rt_clk *clk); +void rt_clk_unprepare(struct rt_clk *clk); rt_err_t rt_clk_enable(struct rt_clk *clk); void rt_clk_disable(struct rt_clk *clk); @@ -171,7 +224,7 @@ rt_err_t rt_clk_prepare_enable(struct rt_clk *clk); void rt_clk_disable_unprepare(struct rt_clk *clk); rt_err_t rt_clk_array_prepare(struct rt_clk_array *clk_arr); -rt_err_t rt_clk_array_unprepare(struct rt_clk_array *clk_arr); +void rt_clk_array_unprepare(struct rt_clk_array *clk_arr); rt_err_t rt_clk_array_enable(struct rt_clk_array *clk_arr); void rt_clk_array_disable(struct rt_clk_array *clk_arr); @@ -185,12 +238,28 @@ rt_err_t rt_clk_set_max_rate(struct rt_clk *clk, rt_ubase_t rate); rt_err_t rt_clk_set_rate(struct rt_clk *clk, rt_ubase_t rate); rt_ubase_t rt_clk_get_rate(struct rt_clk *clk); +rt_base_t rt_clk_round_rate(struct rt_clk *clk, rt_ubase_t rate); + +rt_err_t rt_clk_set_parent(struct rt_clk *clk, struct rt_clk *clk_parent); +struct rt_clk *rt_clk_get_parent(struct rt_clk *clk); + rt_err_t rt_clk_set_phase(struct rt_clk *clk, int degrees); rt_base_t rt_clk_get_phase(struct rt_clk *clk); -rt_base_t rt_clk_round_rate(struct rt_clk *clk, rt_ubase_t rate); +struct rt_clk *rt_clk_cell_get_clk(const struct rt_clk_cell *cell, const char *con_id); -struct rt_clk *rt_clk_get_parent(struct rt_clk *clk); +rt_bool_t rt_clk_cell_is_prepared(const struct rt_clk_cell *cell); + +rt_bool_t rt_clk_cell_is_enabled(const struct rt_clk_cell *cell); + +rt_ubase_t rt_clk_cell_get_rate(const struct rt_clk_cell *cell); + +rt_ubase_t rt_clk_cell_round_rate(struct rt_clk_cell *cell, rt_ubase_t rate); + +struct rt_clk_cell *rt_clk_cell_get_parent(const struct rt_clk_cell *cell); +struct rt_clk_cell *rt_clk_cell_get_parent_by_index(const struct rt_clk_cell *cell, rt_uint8_t idx); +rt_uint8_t rt_clk_cell_get_parent_index(struct rt_clk_cell *cell); +rt_err_t rt_clk_cell_set_parent(struct rt_clk_cell *cell, struct rt_clk_cell *parent); struct rt_clk_array *rt_clk_get_array(struct rt_device *dev); struct rt_clk *rt_clk_get_by_index(struct rt_device *dev, int index); @@ -203,6 +272,8 @@ struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np); struct rt_clk *rt_ofw_get_clk(struct rt_ofw_node *np, int index); struct rt_clk *rt_ofw_get_clk_by_name(struct rt_ofw_node *np, const char *name); rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np); +const char *rt_ofw_clk_get_parent_name(struct rt_ofw_node *np, int index); +rt_err_t rt_ofw_clk_set_defaults(struct rt_ofw_node *np); #else rt_inline struct rt_clk *rt_ofw_get_clk(struct rt_ofw_node *np, int index) { @@ -216,6 +287,14 @@ rt_inline rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np) { return 0; } +rt_inline const char *rt_ofw_clk_get_parent_name(struct rt_ofw_node *np, int index) +{ + return RT_NULL; +} +rt_inline rt_err_t rt_ofw_clk_set_defaults(struct rt_ofw_node *np) +{ + return RT_EOK; +} #endif /* RT_USING_OFW */ /*! @}*/ From 77683e8c8c1e7d11c5b0d46a15a42683f8557bc3 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Tue, 9 Dec 2025 17:42:32 +0800 Subject: [PATCH 04/20] [dm][core] Set default CLK config for platform device probe Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/core/platform.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/components/drivers/core/platform.c b/components/drivers/core/platform.c index c3a141654a8..d308dd08065 100644 --- a/components/drivers/core/platform.c +++ b/components/drivers/core/platform.c @@ -15,6 +15,9 @@ #define DBG_LVL DBG_INFO #include +#ifdef RT_USING_CLK +#include +#endif #include #include #include @@ -119,6 +122,13 @@ static rt_err_t platform_probe(rt_device_t dev) struct rt_ofw_node *np = dev->ofw_node; #endif +#ifdef RT_USING_CLK + if ((err = rt_ofw_clk_set_defaults(dev->ofw_node))) + { + return err; + } +#endif + err = rt_dm_power_domain_attach(dev, RT_TRUE); if (err && err != -RT_EEMPTY) From daf063e452bb4a3d5423ed963556ab7b0db3ab5d Mon Sep 17 00:00:00 2001 From: Siwei Xu Date: Fri, 12 Dec 2025 13:42:35 +0800 Subject: [PATCH 05/20] [bsp][nxp][imx] Add FRDM-i.MX91 bsp #10570 --- .github/ALL_BSP_COMPILE.json | 3 +- bsp/Copyright_Notice.md | 11 + bsp/nxp/imx/imx91/.config | 1477 + bsp/nxp/imx/imx91/Kconfig | 29 + bsp/nxp/imx/imx91/Makefile | 10 + .../README.assets/GS-FRDM-IMX91-IMG1.webp | Bin 0 -> 74792 bytes .../README.assets/image-20251210021421740.png | Bin 0 -> 11017 bytes .../README.assets/image-20251210220620728.png | Bin 0 -> 18137 bytes bsp/nxp/imx/imx91/README.md | 233 + bsp/nxp/imx/imx91/SConscript | 14 + bsp/nxp/imx/imx91/SConstruct | 33 + bsp/nxp/imx/imx91/applications/SConscript | 9 + bsp/nxp/imx/imx91/applications/main.c | 18 + bsp/nxp/imx/imx91/drivers/Kconfig | 23 + bsp/nxp/imx/imx91/drivers/SConscript | 15 + bsp/nxp/imx/imx91/drivers/board.c | 83 + bsp/nxp/imx/imx91/drivers/board.h | 34 + bsp/nxp/imx/imx91/drivers/imx91.c | 30 + bsp/nxp/imx/imx91/drivers/imx91.h | 46 + .../Include/CMSIS_Include_core_ca.cmake | 12 + .../CMSIS/Core_AArch64/Include/cache_armv8a.h | 131 + .../Core_AArch64/Include/cmsis_compiler.h | 92 + .../CMSIS/Core_AArch64/Include/cmsis_gcc.h | 269 + .../CMSIS/Core_AArch64/Include/cmsis_iar.h | 30 + .../CMSIS/Core_AArch64/Include/core_ca53.h | 108 + .../CMSIS/Core_AArch64/Include/core_ca55.h | 109 + .../CMSIS/Core_AArch64/Include/core_common.h | 138 + .../sdk/CMSIS/Core_AArch64/Include/gic_v3.h | 949 + .../CMSIS/Core_AArch64/Include/mmu_armv8a.h | 248 + .../CMSIS/Core_AArch64/Include/timer_armv8a.h | 145 + .../drivers/sdk/CMSIS/Core_AArch64/SConscript | 19 + .../CMSIS/Core_AArch64/Source/cache_armv8a.c | 137 + .../CMSIS/Core_AArch64/Source/mmu_armv8a.c | 720 + .../imx/imx91/drivers/sdk/CMSIS/SConscript | 13 + bsp/nxp/imx/imx91/drivers/sdk/SConscript | 13 + .../drivers/sdk/devices/MIMX9131/MIMX9131.c | 24 + .../drivers/sdk/devices/MIMX9131/MIMX9131.h | 138365 +++++++++++++++ .../sdk/devices/MIMX9131/MIMX9131_features.h | 671 + .../drivers/sdk/devices/MIMX9131/SConscript | 19 + .../MIMX9131/all_lib_device_MIMX9131.cmake | 64 + .../sdk/devices/MIMX9131/device_CMSIS.cmake | 15 + .../sdk/devices/MIMX9131/device_system.cmake | 14 + .../MIMX9131/drivers/driver_clock.cmake | 15 + .../MIMX9131/drivers/driver_iomuxc.cmake | 10 + .../MIMX9131/drivers/driver_memory.cmake | 10 + .../MIMX9131/drivers/driver_reset.cmake | 10 + .../sdk/devices/MIMX9131/drivers/fsl_clock.c | 149 + .../sdk/devices/MIMX9131/drivers/fsl_clock.h | 1279 + .../sdk/devices/MIMX9131/drivers/fsl_iomuxc.h | 796 + .../devices/MIMX9131/fsl_device_registers.h | 33 + .../sdk/devices/MIMX9131/system_MIMX9131.c | 82 + .../sdk/devices/MIMX9131/system_MIMX9131.h | 101 + .../imx/imx91/drivers/sdk/devices/SConscript | 13 + .../imx/imx91/drivers/sdk/drivers/SConscript | 13 + .../drivers/sdk/drivers/cache/SConscript | 13 + .../sdk/drivers/cache/armv8-a/SConscript | 17 + .../sdk/drivers/cache/armv8-a/fsl_cache.c | 58 + .../sdk/drivers/cache/armv8-a/fsl_cache.h | 83 + .../drivers/sdk/drivers/common/SConscript | 17 + .../drivers/sdk/drivers/common/fsl_common.c | 90 + .../drivers/sdk/drivers/common/fsl_common.h | 355 + .../sdk/drivers/common/fsl_common_arm.c | 369 + .../sdk/drivers/common/fsl_common_arm.h | 1184 + .../sdk/drivers/common/fsl_common_dsc.c | 476 + .../sdk/drivers/common/fsl_common_dsc.h | 496 + .../sdk/drivers/common/fsl_common_dsp.c | 45 + .../sdk/drivers/common/fsl_common_dsp.h | 174 + .../sdk/drivers/common/fsl_common_riscv.c | 45 + .../sdk/drivers/common/fsl_common_riscv.h | 148 + .../drivers/sdk/drivers/lpuart/SConscript | 17 + .../drivers/sdk/drivers/lpuart/fsl_lpuart.c | 2786 + .../drivers/sdk/drivers/lpuart/fsl_lpuart.h | 1150 + .../sdk/drivers/lpuart/fsl_lpuart_dma.c | 434 + .../sdk/drivers/lpuart/fsl_lpuart_dma.h | 186 + .../sdk/drivers/lpuart/fsl_lpuart_edma.c | 469 + .../sdk/drivers/lpuart/fsl_lpuart_edma.h | 189 + .../drivers/sdk/drivers/rgpio/SConscript | 17 + .../drivers/sdk/drivers/rgpio/fsl_rgpio.c | 322 + .../drivers/sdk/drivers/rgpio/fsl_rgpio.h | 708 + bsp/nxp/imx/imx91/drivers/serial.c | 377 + bsp/nxp/imx/imx91/drivers/serial.h | 38 + bsp/nxp/imx/imx91/rtconfig.h | 468 + bsp/nxp/imx/imx91/rtconfig.py | 58 + 83 files changed, 157672 insertions(+), 1 deletion(-) create mode 100644 bsp/nxp/imx/imx91/.config create mode 100644 bsp/nxp/imx/imx91/Kconfig create mode 100644 bsp/nxp/imx/imx91/Makefile create mode 100644 bsp/nxp/imx/imx91/README.assets/GS-FRDM-IMX91-IMG1.webp create mode 100644 bsp/nxp/imx/imx91/README.assets/image-20251210021421740.png create mode 100644 bsp/nxp/imx/imx91/README.assets/image-20251210220620728.png create mode 100644 bsp/nxp/imx/imx91/README.md create mode 100644 bsp/nxp/imx/imx91/SConscript create mode 100644 bsp/nxp/imx/imx91/SConstruct create mode 100644 bsp/nxp/imx/imx91/applications/SConscript create mode 100644 bsp/nxp/imx/imx91/applications/main.c create mode 100644 bsp/nxp/imx/imx91/drivers/Kconfig create mode 100644 bsp/nxp/imx/imx91/drivers/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/board.c create mode 100644 bsp/nxp/imx/imx91/drivers/board.h create mode 100644 bsp/nxp/imx/imx91/drivers/imx91.c create mode 100644 bsp/nxp/imx/imx91/drivers/imx91.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/CMSIS_Include_core_ca.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cache_armv8a.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_compiler.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_gcc.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_iar.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca53.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca55.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_common.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/gic_v3.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/mmu_armv8a.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/timer_armv8a.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/cache_armv8a.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/mmu_armv8a.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/CMSIS/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131_features.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/all_lib_device_MIMX9131.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_CMSIS.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_system.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_clock.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_iomuxc.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_memory.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_reset.cmake create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_iomuxc.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/fsl_device_registers.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/devices/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.h create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/SConscript create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.c create mode 100644 bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.h create mode 100644 bsp/nxp/imx/imx91/drivers/serial.c create mode 100644 bsp/nxp/imx/imx91/drivers/serial.h create mode 100644 bsp/nxp/imx/imx91/rtconfig.h create mode 100644 bsp/nxp/imx/imx91/rtconfig.py diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 70f15a96ef0..f2703450484 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -387,7 +387,8 @@ "SUB_RTT_BSP": [ "qemu-virt64-aarch64", "raspberry-pi/raspi3-64", - "raspberry-pi/raspi4-64" + "raspberry-pi/raspi4-64", + "nxp/imx/imx91" ] }, { diff --git a/bsp/Copyright_Notice.md b/bsp/Copyright_Notice.md index 7a805d17719..59358aa5ffa 100644 --- a/bsp/Copyright_Notice.md +++ b/bsp/Copyright_Notice.md @@ -325,6 +325,17 @@ Path: - bsp/imx6ul/platform +### imx91 + +License: bsd-new + +Copyright: Copyright 2014-2016 Freescale Semiconductor, Inc. + Copyright 2016-2025 NXP + +Path: + +- bsp/nxp/imx/imx91/drivers/sdk + ### imxrt License: clear-bsd diff --git a/bsp/nxp/imx/imx91/.config b/bsp/nxp/imx/imx91/.config new file mode 100644 index 00000000000..b03e676ecf5 --- /dev/null +++ b/bsp/nxp/imx/imx91/.config @@ -0,0 +1,1477 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=16 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_THREADSAFE_PRINTF=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +# +# AArch64 Architecture Configuration +# +CONFIG_ARCH_TEXT_OFFSET=0x0 +CONFIG_ARCH_RAM_OFFSET=0x80000000 +CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 +CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USING_GENERIC_CPUID=y +CONFIG_ARCH_HEAP_SIZE=0x2000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x8000000 +# end of AArch64 Architecture Configuration + +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_RT_NO_USING_GIC=y +CONFIG_ARCH_ARM_CORTEX_A55=y +# CONFIG_ARCH_ARM_SECURE_MODE is not set +CONFIG_RT_BACKTRACE_FUNCTION_NAME=y +CONFIG_ARCH_ARMV8=y +CONFIG_ARCH_USING_ASID=y +CONFIG_ARCH_USING_HW_THREAD_SELF=y +CONFIG_ARCH_USING_IRQ_CTX_LIST=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=8092 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Memory management +# +# CONFIG_RT_PAGE_MPR_SIZE_DYNAMIC is not set +CONFIG_RT_PAGE_AFFINITY_BLOCK_SIZE=0x1000 +CONFIG_RT_PAGE_MAX_ORDER=11 +# CONFIG_RT_USING_MEMBLOCK is not set + +# +# Debugging +# +# CONFIG_RT_DEBUGGING_ALIASING is not set +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set +# CONFIG_RT_DEBUGGING_PAGE_POISON is not set +# end of Debugging +# end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_NCNN is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_BOARD_IMX91=y +CONFIG_SOC_MIMX91X1D=y + +# +# Hardware Drivers Config +# +CONFIG_BSP_USING_EARLY_CONSOLE=y +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GICV3=y +CONFIG_KERNEL_ASPACE_START=0x1000000 +# end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imx91/Kconfig b/bsp/nxp/imx/imx91/Kconfig new file mode 100644 index 00000000000..38ff35d75da --- /dev/null +++ b/bsp/nxp/imx/imx91/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Project Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" + +config BOARD_IMX91 + bool + select ARCH_ARM_CORTEX_A55 + select BSP_USING_GICV3 + select BSP_USING_GIC + default y + +config SOC_MIMX91X1D + bool + select ARCH_ARMV8 + select ARCH_CPU_64BIT + select RT_USING_CACHE + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select ARCH_ARM_BOOTWITH_FLUSH_CACHE + default y + +source "$(BSP_DIR)/drivers/Kconfig" diff --git a/bsp/nxp/imx/imx91/Makefile b/bsp/nxp/imx/imx91/Makefile new file mode 100644 index 00000000000..f9b884d9d3b --- /dev/null +++ b/bsp/nxp/imx/imx91/Makefile @@ -0,0 +1,10 @@ +scons:=python ${SCONS}\scons.py + +all: + @$(scons) + +clean: + @$(scons) -c + +copy: + @$(scons) --copy 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zskCRvyRvxL!>5M{)x;-j#V~{F*$gj?oyGyrqxe5~OPJ-;hMK9WK~~EIkj&}+m$dW9 z4rhumbcbj;rV$ex?h|I0+kOFw)YwzrG!@nZqahfJS!%FdZc25eSP2mDiOyV*VB|NH z*=(HLjr<%i8+b3bK)X+Z57yOpy%uDPaQCD zW=h^P0VzcZD`eb-!G)150$T}x`FYWDKyR4`{;k6x)~x+aJ92AYTYL9Ua9ey+)_$qYX>KfsW2UAqiKqKYu%%Oe+%K)9-OK7568tyR?>coLz0 zs-m{m*J#N6#mUJ7^w%0d0hzsJFk8$>eiHo&*mxTxV{jOr1fjY#y=lpSDg=^#qcTPm zn2fUeFa>OZ^vkg}|E=SH@<^>G)+**520hGir?xFxrpYgbLV*hdgpTLeh#UXg#FX$d z@tRpG3vcSXKLSh^tya(B;c)a~{r}ky(BUf^TsF(@xBnDW98vjkD{$n^<)DduD`*AN zC!5;=z@4$%*+Sly@QLjN4$v^jSg!w=e&o8|gzK{;K+A9rEIe5Y9Nz(s@afLDV4t88 zdn&fJM|0Lq{^qnO-NgTe~DWM4fa;%Zh literal 0 HcmV?d00001 diff --git a/bsp/nxp/imx/imx91/README.md b/bsp/nxp/imx/imx91/README.md new file mode 100644 index 00000000000..7a89cc674e6 --- /dev/null +++ b/bsp/nxp/imx/imx91/README.md @@ -0,0 +1,233 @@ +# FRDM-IMX91 板级支持包 使用说明 + +本目录包含NXP FRDM-IMX91 开发板的板级支持包代码。 + +## 1. 简介 + +### 1.1 i.MX91系列处理器简介 + +i.MX 91系列采用了可扩展的Arm® Cortex®-A55内核，其主频高达1.4GHz，支持新一代LPDDR4内存以延长平台寿命，支持双千兆以太网和双USB端口，以及面向医疗、工业和消费物联网市场细分领域的丰富外设。 + + + +### 1.2 FRDM-i.MX91开发板简介 + +FRDM i.MX 91开发板是一款低成本、紧凑型开发板，采用i.MX 91应用处理器。该板配备板载IW610模块，集成了恩智浦的三频解决方案，支持Wi-Fi 6、BLE 5.4和802.15.4，适用于开发现代工业和物联网应用。该开发板包含LPDDR4、用于快速启动的eMMC存储、PMIC以及扩展功能。 + +FRDM i.MX 91开发板是一款入门级紧凑型开发板，采用i.MX 91应用处理器。 + +![GS-FRDM-IMX91-IMG1](README.assets/GS-FRDM-IMX91-IMG1.webp) + +开发板主要硬件资源： + +| 资源 | 简介 | +| ------------------ | ------------------------------------------------------------ | +| 处理器 | ◆ i.MX 91应用处理器
◆ Cortex-A55@1.4G
◆ EdgeLock®安全区域 | +| 存储器 | ◆ 1GB LPDDR4
◆ 8GB eMMC5.1
◆ MicroSD插槽
◆ EEPROM | +| 显示器和摄像头接口 | ◆ 并行RGB LCD接口(40引脚扩展接口)
◆ 并行摄像头接口(40引脚扩展接口) | +| 无线 | ◆ u-blox MAYA-W476-00B三频Wi-Fi 6/BLE 5.4/802.15.4模块 | +| 音频 | ◆ 3.5mm耳机插孔 | +| 连接 | ◆ USB2.0 Type-C连接器
◆ USB2.0 type A连接器
◆ 两个GbE RJ45
◆ CAN(HDR)
◆ 40引脚(2x20)
◆ 扩展接口
◆ I²C HDR
◆ ADC HDR | +| 调试 | ◆ SWD连接器
◆ 通过USB Type C的UART | + + + +### 1.3 开发板和PC之间的连接 + +在FRDM i.MX 91开发板上调测RT-Thread的过程中，需要使用到的接口有： + +1. POWER（P1），USB供电接口，用于向开发板供电； +2. DEBUG（P16），带有USB转串口芯片，用于U-Boot和RT-Thread日志输出、命令行交互； +3. ENET1（P4）或者ENET2（P3），以太网口，用于网络下载编译生成的RT-Thread固件； + + + +## 2. 编译 + +### 2.1 下载AArch64工具链 + +从ARM开发者网站下载AArch64裸机工具链， + +下载页面： [Arm GNU Toolchain Downloads – Arm Developer](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads) + +例如，64位Windows主机上下载： https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-mingw-w64-x86_64-aarch64-none-elf.zip + +例如，下载后解压到本地路径：`D:\ARM\arm-gnu-toolchain-14.3.rel1-mingw-w64-x86_64-aarch64-none-elf` + + + +### 2.2 下载RT-Thread Env工具 + +下载页面：[rt-thread.org/download.html#download-rt-thread-env-tool](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) + + + +### 2.3 下载RT-Thread源代码 + +在Env环境中，使用git命令下载RT-Thread源代码，例如： + +```sh +git clone https://github.com/RT-Thread/rt-thread.git +``` + + + +### 2.4 编译FRDM-i.MX 91目标 + +在Env环境中，转到`i.MX 91`的BSP目录： + +```sh +cd bsp/nxp/imx/imx91/ +``` + +然后，设置工具链路径（Windows Env环境）： + +```bat +set RTT_EXEC_PATH=D:\ARM\arm-gnu-toolchain-14.3.rel1-mingw-w64-x86_64-aarch64-none-elf\bin +``` + +或者（bash）： + +```sh'' +export RTT_EXEC_PATH=/path/to/aarch64-none-elf/bin +``` + +接着，执行`scons`命令开始编译： + +```sh +scons -j 8 +``` + + + +## 3.下载 + +开发板默认固件带有U-Boot启动加载器，开机3秒内通过串口发送换行符，可以进入U-Boot命令行界面。 + +### 3.1 准备U-Boot网络环境 + +将开发板和PC连接到同一个路由器。 + +例如，PC的IP地址为：`192.168.0.101` + +在开发板的U-Boot命令行界面内，设置FRDM-i.MX为静态IP： + +```sh +setenv ipaddr 192.168.0.120 +``` + +或者从路由器动态获取IP： + +```sh +dhcp +``` + +成功后，可以使用ping命令测试是否可以访问PC： + +```sh +ping 192.168.0.101 +``` + +成功则表示网络环境正常，可以执行后续步骤。 + + + +### 3.2 安装TFTP服务 + +Windows系统可以使用Tftpd，下载链接： [Releases · PJO2/tftpd64](https://github.com/PJO2/tftpd64/releases/) + +例如，下载portable免安装版本： https://github.com/PJO2/tftpd64/releases/download/v4.74/tftpd64_portable_v4.74.zip + +启动后，设置TFTP工作目录： + +![image-20251210021421740](README.assets/image-20251210021421740.png) + + + +### 3.3 拷贝rtthread.bin到TFTP工作目录 + +在PC的Env环境中，将 `rtthread.bin` 拷贝到TFTP工作目录： +```bat +copy /Y rtthread.bin D:\PortableSoftwareApps\tftpd64_portable_v4.74\work\ +``` + +或者： + +```sh +cp rtthread.bin /path/to/tftp_work_dir/ +``` + + + +### 3.4 下载rtthread.bin到开发板内存中 + +在开发板的U-Boot命令行界面中，首先执行如下命令，设置TFTP服务地址（PC的IP地址）： + +```sh +setenv serverip 192.168.0.101 +``` + +然后，继续在开发板的U-Boot命令行界面中，执行如下命令，将`rtthread.bin`下载到内存中： + +```sh +tftp 0x80000000 rtthread.bin +``` + +下载的目标内存地址为：`0x80000000`； + + + +## 4. 运行 + +### 4.1 通过U-Boot的tftp命令下载、运行rtthread.bin + +完成前述步骤后，在开发板的 U-Boot 命令行界面中，继续执行以下命令，以跳转至 `0x80000000` 地址并执行代码： + +```sh +dcache flush +icache flush +go 0x80000000 +``` + +每次开发板上电启动后，均需执行上述 U-Boot 命令，RT-Thread 方可正常运行。这在需要反复调试时显得不够便捷。 + +为此，可将以上命令写入 U-Boot 的环境变量 `bootcmd` 中，从而实现开机自动执行，便于后续调试。具体操作命令如下： + +```sh +setenv ipaddr 192.168.0.120 +setenv serverip 192.168.0.101 +setenv bootcmd "tftp 0x80000000 rtthread.bin; dcache flush; icache flush; go 0x80000000" +saveenv +reset +``` + +其中，`saveenv` 命令用于保存环境变量的值，确保重启后依然生效；最后的 `reset` 为重启命令。 + +执行效果如下图所示： + +![image-20251210220620728](README.assets/image-20251210220620728.png) + +### 4.2 通过U-Boot的fatload命令下载、运行rtthread.bin + +另外，也可以先将PC上编译生产的`rtthread.bin`文件拷贝到MicroSD卡中，再将MicroSD弹出后插到开发板上，然后通过U-Boot的`fatload`命令将MicroSD卡中的文件加载内存，再执行跳转： + +```sh +fatload mmc 1:1 0x80000000 rtthread.bin; dcache flush ; icache flush; go 0x80000000 +``` + +相应的也可以保存到`bootcmd`变量中： + +```sh +setenv bootcmd "fatload mmc 1:1 0x80000000 rtthread.bin; dcache flush ; icache flush; go 0x80000000" +``` + + + +## 5. 参考链接 + +1. 维护人: [xusiwei](https://github.com/xusiwei) +2. AArch64工具链下载页面： [Arm GNU Toolchain Downloads – Arm Developer](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads) +3. Tftp64下载页面：https://github.com/PJO2/tftpd64/releases +4. FRDM-i.MX91开发板介绍：[FRDM i.MX 91 Development Board | NXP 半导体](https://www.nxp.com.cn/design/design-center/development-boards-and-designs/FRDM-IMX91) +5. i.MX91处理器介绍： [i.MX 91 Applications Processors Family | NXP 半导体](https://www.nxp.com.cn/products/i.MX91) + diff --git a/bsp/nxp/imx/imx91/SConscript b/bsp/nxp/imx/imx91/SConscript new file mode 100644 index 00000000000..744d8d78214 --- /dev/null +++ b/bsp/nxp/imx/imx91/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/SConstruct b/bsp/nxp/imx/imx91/SConstruct new file mode 100644 index 00000000000..456429c826a --- /dev/null +++ b/bsp/nxp/imx/imx91/SConstruct @@ -0,0 +1,33 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/imx/imx91/applications/SConscript b/bsp/nxp/imx/imx91/applications/SConscript new file mode 100644 index 00000000000..c583d3016e0 --- /dev/null +++ b/bsp/nxp/imx/imx91/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nxp/imx/imx91/applications/main.c b/bsp/nxp/imx/imx91/applications/main.c new file mode 100644 index 00000000000..780e49d0918 --- /dev/null +++ b/bsp/nxp/imx/imx91/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + */ + +#include + +int main(int argc, char** argv) +{ + rt_kprintf("Hi, this is RT-Thread!!\n"); + + return 0; +} diff --git a/bsp/nxp/imx/imx91/drivers/Kconfig b/bsp/nxp/imx/imx91/drivers/Kconfig new file mode 100644 index 00000000000..3ca01326427 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/Kconfig @@ -0,0 +1,23 @@ +menu "Hardware Drivers Config" + +config BSP_USING_EARLY_CONSOLE + bool "Enable early console" + default n + +config BSP_USING_UART1 + bool "Enable UART1" + default y + +config BSP_USING_GIC + bool "Enalbe GIC" + default y + +config BSP_USING_GICV3 + bool "Enable GICv3" + default y + +config KERNEL_ASPACE_START + hex "Kernel aspace start address" + default 0x1000000 + +endmenu \ No newline at end of file diff --git a/bsp/nxp/imx/imx91/drivers/SConscript b/bsp/nxp/imx/imx91/drivers/SConscript new file mode 100644 index 00000000000..356b6faf24d --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/SConscript @@ -0,0 +1,15 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +CPPPATH = [cwd] + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/board.c b/bsp/nxp/imx/imx91/drivers/board.c new file mode 100644 index 00000000000..0fcea165f62 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/board.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + * 2025-10-08 Siwei Xu Fix MMU Enable issues + */ +#include "board.h" + +#include "serial.h" +#include "MIMX9131.h" + +#include +#include +#include +#include +#include + +#include + +#define DRAM_MAP_START KERNEL_BOOT_ADDR +#define DRAM_MAP_SIZE MB_SIZE(256) + +#define MEM_DESC(vaddr_start, size, paddr_start, attr) \ + vaddr_start, (vaddr_start + size - 1uL), paddr_start, attr + +extern volatile unsigned long MMUTable[]; + +static struct mem_desc platform_mem_desc[] = { + { MEM_DESC(DRAM_MAP_START, DRAM_MAP_SIZE, DRAM_MAP_START, NORMAL_MEM) }, // 0x8000_0000 + { MEM_DESC(LPUART1_BASE, LPUART1_SIZE, LPUART1_BASE, DEVICE_MEM) }, // 0x4438_0000 + { MEM_DESC(CCM_CTRL_BASE, CCM_CTRL_SIZE, CCM_CTRL_BASE, DEVICE_MEM) }, // 0x4445_8000 + { MEM_DESC(GIC_DISTRIBUTOR_BASE, GIC_DISTRIBUTOR_SIZE, GIC_DISTRIBUTOR_BASE, DEVICE_MEM) }, // 0x4800_0000 + { MEM_DESC(GIC_REDISTRIBUTOR_BASE, GIC_REDISTRIBUTOR_SIZE, GIC_REDISTRIBUTOR_BASE, DEVICE_MEM) }, // 0x4804_0000 +}; + +static const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); + +static rt_region_t init_page_region; + +static rt_base_t get_sctlr_el1() +{ + rt_base_t sctlr = 0; + __asm__ volatile("mrs %0, sctlr_el1" : "=r"(sctlr)); + return sctlr; +} + +/** + * This function will initialize hardware board + */ +void rt_hw_board_init(void) +{ + rt_hw_earlycon_ioremap(); + rt_hw_earlycon_print_hex("sctlr_el1: ", get_sctlr_el1()); + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x080000000000, 0x10000000, (size_t *)MMUTable, 0); + + init_page_region.start = BOARD_PAGE_START; + init_page_region.end = BOARD_PAGE_END; + rt_page_init(init_page_region); + + rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size); + +#ifdef RT_USING_HEAP + /* initialize system heap */ + rt_system_heap_init((void *)BOARD_HEAP_BEGIN, (void *)BOARD_HEAP_END); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize uart */ + rt_hw_uart_init(); + + /* initialize timer for os tick */ + rt_hw_gtimer_init(); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} diff --git a/bsp/nxp/imx/imx91/drivers/board.h b/bsp/nxp/imx/imx91/drivers/board.h new file mode 100644 index 00000000000..de5153f9234 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/board.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + * 2025-12-10 Siwei Xu Fix ioremap issues + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "imx91.h" +#include "rtconfig.h" + +#ifndef KERNEL_BOOT_ADDR +#define KERNEL_BOOT_ADDR (ARCH_RAM_OFFSET + ARCH_TEXT_OFFSET) +#endif + +/* defined in linker script */ +extern unsigned char __bss_end; + +#define BOARD_PAGE_START RT_ALIGN((rt_base_t) & __bss_end, KB_SIZE(4)) +#define BOARD_PAGE_END (BOARD_PAGE_START + MB_SIZE(1)) + +#define BOARD_HEAP_BEGIN (BOARD_PAGE_END) +#define BOARD_HEAP_END (BOARD_HEAP_BEGIN + MB_SIZE(32)) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/nxp/imx/imx91/drivers/imx91.c b/bsp/nxp/imx/imx91/drivers/imx91.c new file mode 100644 index 00000000000..64380f07a19 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/imx91.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + */ +#include "imx91.h" + +#include "MIMX9131.h" + +#include +#include + +rt_base_t platform_get_gic_dist_base(void) +{ + return (rt_base_t)rt_ioremap((void *)GIC_DISTRIBUTOR_BASE, GIC_DISTRIBUTOR_SIZE); +} + +rt_base_t platform_get_gic_redist_base(void) +{ + return (rt_base_t)rt_ioremap((void *)GIC_REDISTRIBUTOR_BASE, GIC_REDISTRIBUTOR_SIZE); +} + +rt_base_t platform_get_gic_cpu_base(void) +{ + return (rt_base_t)rt_ioremap((void *)GIC_REDISTRIBUTOR_BASE, GIC_REDISTRIBUTOR_SIZE); +} diff --git a/bsp/nxp/imx/imx91/drivers/imx91.h b/bsp/nxp/imx/imx91/drivers/imx91.h new file mode 100644 index 00000000000..fd8452c10d5 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/imx91.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + */ + +#ifndef __IMX91_H__ +#define __IMX91_H__ + +#include + +/* 'ARM_GIC_MAX_NR' is the number of cores, gicv3.c required */ +#define ARM_GIC_MAX_NR 1 + +/* The platform maximum interrupts, interrupt.c required */ +#define ARM_GIC_NR_IRQS 256 + +/* Number of interrupts in the Vector table, interrupt.c required */ +#define MAX_HANDLERS 256 + +/* interrupt.c required. */ +rt_base_t platform_get_gic_dist_base(void); +rt_base_t platform_get_gic_redist_base(void); +rt_base_t platform_get_gic_cpu_base(void); + +/* interrupt.c required */ +#define GIC_IRQ_START 0 + +/* gic.c required */ +#define __REG32(x) (*((volatile unsigned int *)(x))) + +#define KB_SIZE(x) ((x) * 1024) +#define MB_SIZE(x) ((x) * 1024 * 1024) + +#define GIC_DISTRIBUTOR_SIZE KB_SIZE(64) +#define GIC_REDISTRIBUTOR_SIZE KB_SIZE(768) + +#define LPUART1_SIZE KB_SIZE(64) +#define CCM_CTRL_SIZE KB_SIZE(64) + +#endif /* __IMX91_H__ */ + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/CMSIS_Include_core_ca.cmake b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/CMSIS_Include_core_ca.cmake new file mode 100644 index 00000000000..5b5997984ec --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/CMSIS_Include_core_ca.cmake @@ -0,0 +1,12 @@ +#Description: CMSIS Include For Cortex-A; user_visible: True +include_guard(GLOBAL) +message("CMSIS_Include_core_ca component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../Source/cache_armv8a.c + ${CMAKE_CURRENT_LIST_DIR}/../Source/mmu_armv8a.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cache_armv8a.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cache_armv8a.h new file mode 100644 index 00000000000..f7d52f74269 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cache_armv8a.h @@ -0,0 +1,131 @@ +/**************************************************************************//** + * @file cache_armv8a.h + * @brief CMSIS AARCH64 Cache API header file + * @version V1.0.0 + * @date 21. January 2022 + ******************************************************************************/ + +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CACHE_ARMV8A_H +#define __CACHE_ARMV8A_H + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#define dcache_ops(op, operand) \ +({ \ + __asm__ volatile ("dc " __STRINGIFY(op) ", %0" \ + ::"r" (operand): "memory"); \ +}) + + +/* Invalidate instruction cache by virtual address to PoU */ +static inline void icache_invalidate_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end_addr = cur + size; + + /* Align address to line size */ + cur &= ~(ICACHE_LINE_SIZE - 1); + + do { + __asm__ volatile ("ic ivau, %0" ::"r" (cur): "memory"); + cur += ICACHE_LINE_SIZE; + } while (cur < end_addr); + + __DSB(); + __ISB(); +} + +/* Invalidate all instruction cache to PoU */ +static inline void icache_invalidate_all(void) +{ + __asm__ volatile ("ic iallu" ::: "memory"); + __DSB(); + __ISB(); +} + +/* Clean data cache by virtual address to PoC */ +static inline void dcache_clean_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end = addr + size; + + /* Align address to line size */ + cur &= ~(DCACHE_LINE_SIZE - 1); + + while (cur < end) { + dcache_ops(cvac, cur); + cur += DCACHE_LINE_SIZE; + } + + __DSB(); +} + +/* Invalidate data cache by virtual address to PoC */ +static inline void dcache_invalidate_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end = addr + size; + + if (end & (DCACHE_LINE_SIZE - 1)) { + end &= ~(DCACHE_LINE_SIZE - 1); + dcache_ops(civac, end); + } + + if (cur & (DCACHE_LINE_SIZE - 1)) { + cur &= ~(DCACHE_LINE_SIZE - 1); + if (cur != end) + dcache_ops(civac, cur); + cur += DCACHE_LINE_SIZE; + } + + while (cur < end) { + dcache_ops(ivac, cur); + cur += DCACHE_LINE_SIZE; + } + + __DSB(); +} + +/* Clean and invalidate data cache by virtual address to PoC */ +static inline void dcache_clean_invalidate_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end = addr + size; + + /* Align address to line size */ + cur &= ~(DCACHE_LINE_SIZE - 1); + + while (cur < end) { + dcache_ops(civac, cur); + cur += DCACHE_LINE_SIZE; + } + + __DSB(); +} + +void dcache_clean_all(void); +void dcache_invalidate_all(void); +void dcache_clean_invalidate_all(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CACHE_ARMV8A_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_compiler.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_compiler.h new file mode 100644 index 00000000000..3b8d8ca33ee --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_compiler.h @@ -0,0 +1,92 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler generic header file + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* Define compiler macros for CPU architecture, if not yet defined by the + * compiler default macros + */ +#if __ARM_ARCH_8A__ +/* Macro already defined */ +#else + #if defined(__ARM_ARCH_8A) && __ARM_ARCH_8A == 1 + #define __ARM_ARCH_8A__ 1 + #endif /* __ARM_ARCH_8A == 1 */ +#endif + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +#elif defined ( __ICCARM__ ) + #include "cmsis_iar.h" + +#else + #error Unknown compiler +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_COMPILER_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_gcc.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_gcc.h new file mode 100644 index 00000000000..50b706a6ed2 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_gcc.h @@ -0,0 +1,269 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif + +#ifndef __STRINGIFY + #define __STRINGIFY(x) #x +#endif + +#ifndef __MSR + #define __MSR(sysreg, val) \ + __asm volatile ("msr "__STRINGIFY(sysreg)", %0\n" : : "r"((uint64_t)(val))) +#endif + +#ifndef __MRS +#define __MRS(sysreg, pVal) \ + __asm volatile ("mrs %0, "__STRINGIFY(sysreg)"\n" : "=r"((*pVal))) +#endif + +#ifndef __WFI +#define __WFI() \ + __asm volatile ("wfi") +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Interrupt Mask Bits + \details Returns the current state of the interrupt mask bits from the DAIF register. + \return Interrupt Mask value + */ +__STATIC_FORCEINLINE uint64_t __get_DAIF(void) +{ + uint64_t result; + __MRS(DAIF, &result); + return result; +} + + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the DAIF. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("msr daifclr, #2" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the DAIF. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("msr daifset, #2" : : : "memory"); +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief Hypervisor call with 2 arguments + \details Makes an hypervisor call with two arguments stored in x0 and x1. + */ +#define HVC_2(imm, x0, x1) __asm volatile ( \ + "mov x0, %0 \n\t" \ + "mov x1, %1 \n\t" \ + "hvc #" __STRINGIFY(imm) "\n\t" \ + : : "r" (x0), "r" (x1) : "x0", "x1", "memory") + +/** + \brief Multiprocessor Affinity + \details Indicates the core number in the Cortex-Axx processor. + */ +__STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void) +{ + uint64_t result; + __MRS(MPIDR_EL1, &result); + return result; +} + +#define MPIDR_GetCoreID() \ + ({ uint64_t mpidr = __get_MPIDR_EL1(); \ + (mpidr >> (8 * MPIDR_SUPPORT_MT(mpidr))) & MPIDR_AFFLVL_MASK; }) + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#ifndef __ISB +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb":::"memory"); +} +#endif + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#ifndef __DSB +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb sy":::"memory"); +} +#endif + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#ifndef __DMB +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb sy":::"memory"); +} +#endif + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + return __builtin_bswap16(value); +} + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("brk "#value) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ + +__STATIC_FORCEINLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief likely/unlikely() branch prediction + \details Gives hints to the compiler to favor either side of a jump instruction + \param [in] expr Boolean expression under evaluation + \return The same boolean value + */ +#ifndef unlikely +__STATIC_FORCEINLINE long unlikely(long expr) +{ + return __builtin_expect(expr, 0L); +} +#endif + +#ifndef likely +__STATIC_FORCEINLINE long likely(long expr) +{ + return __builtin_expect(expr, 1L); +} +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_iar.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_iar.h new file mode 100644 index 00000000000..1011994e119 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_iar.h @@ -0,0 +1,30 @@ +/**************************************************************************//** + * @file cmsis_iar.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CMSIS_IAR_H +#define __CMSIS_IAR_H + +#error Unsupported compiler + +#endif /* __CMSIS_IAR_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca53.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca53.h new file mode 100644 index 00000000000..f8e58439d0a --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca53.h @@ -0,0 +1,108 @@ +/**************************************************************************//** + * @file core_ca53.h + * @brief CMSIS Cortex-A53 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021,2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA53_H_GENERIC +#define __CORE_CA53_H_GENERIC + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +#define __CORTEX_Axx (53U) /*!< Cortex-Axx Core */ + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA53_REV + #define __CA53_REV 0x0000U + #warning "__CA53_REV not defined in device header file; using default!" + #endif + + #ifndef __CACHE_PRESENT + #define __CACHE_PRESENT 1U + #warning "__CACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1U + #define __FPU_USED 1U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MMU_PRESENT + #define __MMU_PRESENT 1U + #warning "__MMU_PRESENT not defined in device header file; using default!" + #endif +#endif + +#include "cmsis_compiler.h" /* Core Instruction and Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA53_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA53_H_DEPENDANT +#define __CORE_CA53_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Cache Functions + ******************************************************************************/ +#define ICACHE_LINE_SIZE (64) +#define DCACHE_LINE_SIZE (64) + +#include "core_common.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA53_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca55.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca55.h new file mode 100644 index 00000000000..573a6e90704 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca55.h @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file core_ca55.h + * @brief CMSIS Cortex-A55 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date Nov. 2022 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021,2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA55_H_GENERIC +#define __CORE_CA55_H_GENERIC + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +#define __CORTEX_Axx (55U) /*!< Cortex-Axx Core */ + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA55_REV + #define __CA55_REV 0x0000U + #warning "__CA55_REV not defined in device header file; using default!" + #endif + + #ifndef __CACHE_PRESENT + #define __CACHE_PRESENT 1U + #warning "__CACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1U + #define __FPU_USED 1U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MMU_PRESENT + #define __MMU_PRESENT 1U + #warning "__MMU_PRESENT not defined in device header file; using default!" + #endif +#endif + +#include "cmsis_compiler.h" /* Core Instruction and Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA55_H_DEPENDANT +#define __CORE_CA55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Cache Functions + ******************************************************************************/ + +#define ICACHE_LINE_SIZE (64) +#define DCACHE_LINE_SIZE (64) + +#include "core_common.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_common.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_common.h new file mode 100644 index 00000000000..e197390722a --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_common.h @@ -0,0 +1,138 @@ +/**************************************************************************//** + * @file core_common.h + * @brief CMSIS Cortex-A AArch64 Core Common Header File + * @version V1.0.0 + * @date 06. Feb 2023 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_COMMON_H +#define __CORE_COMMON_H + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Register Definitions + ******************************************************************************/ + +#ifndef BIT +#define BIT(n) (1 << (n)) +#endif + +/* DAIF Register */ +#define DAIF_F_BIT BIT(6) +#define DAIF_I_BIT BIT(7) +#define DAIF_A_BIT BIT(8) +#define DAIF_D_BIT BIT(9) + +/* System Control Register */ +#define SCTLR_M_BIT BIT(0) +#define SCTLR_A_BIT BIT(1) +#define SCTLR_C_BIT BIT(2) +#define SCTLR_SA_BIT BIT(3) +#define SCTLR_I_BIT BIT(12) + +/* Exception levels EL0-EL3 */ +#define MODE_EL_SHIFT (0x2) +#define MODE_EL_MASK (0x3) + +#define MODE_EL3 (0x3) +#define MODE_EL2 (0x2) +#define MODE_EL1 (0x1) +#define MODE_EL0 (0x0) + +#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) + +/* MPIDR */ +#define MPIDR_AFFLVL_MASK (0xffULL) +#define MPIDR_AFF0_SHIFT (0) +#define MPIDR_AFF1_SHIFT (8) +#define MPIDR_AFF2_SHIFT (16) +#define MPIDR_AFF3_SHIFT (32) +#define MPIDR_MT_MASK (0x1) +#define MPIDR_MT_SHIFT (24) + +#define MPIDR_SUPPORT_MT(mpidr) ((mpidr >> MPIDR_MT_SHIFT) & MPIDR_MT_MASK) + + +#define MPIDR_TO_AFF_LEVEL(mpidr, aff_level) \ + (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK) + +#define MPIDR_AFFINITY_MASK \ + ((MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) + +/******************************************************************************* + * Cache Functions + ******************************************************************************/ + +#if defined (__CACHE_PRESENT) && (__CACHE_PRESENT == 1U) + + #include "cache_armv8a.h" + +#endif + + +/******************************************************************************* + * GIC Functions + ******************************************************************************/ + +#if defined (__GIC_PRESENT) && (__GIC_PRESENT == 1U) + + #include "gic_v3.h" + +#endif + + +/******************************************************************************* + * MMU Functions + ******************************************************************************/ + +#if defined (__MMU_PRESENT) && (__MMU_PRESENT == 1U) + + #include "mmu_armv8a.h" + +#endif + + +/******************************************************************************* + * Timer Functions + ******************************************************************************/ + +#if defined (__TIM_PRESENT) && (__TIM_PRESENT == 1U) + #include "timer_armv8a.h" +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_COMMON_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/gic_v3.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/gic_v3.h new file mode 100644 index 00000000000..b3a229a8a82 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/gic_v3.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file gic_v3.h + * @brief CMSIS Cortex-A53 Generic Interrupt Controller API header file + * @version V1.0.1 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __GIC_V3_H +#define __GIC_V3_H + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * GIC Data Types + ******************************************************************************/ + +/** \brief AArch64 System registers to access the Generic Interrupt Controller CPU interface +*/ +#if defined(__GNUC__) + #define ICC_BPR0_EL1 S3_0_C12_C8_3 + #define ICC_BPR1_EL1 S3_0_C12_C12_3 + #define ICC_CTLR_EL1 S3_0_C12_C12_4 + #define ICC_CTLR_EL3 S3_6_C12_C12_4 + #define ICC_EOIR0_EL1 S3_0_C12_C8_1 + #define ICC_EOIR1_EL1 S3_0_C12_C12_1 + #define ICC_HPPIR0_EL1 S3_0_C12_C8_2 + #define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + #define ICC_IAR0_EL1 S3_0_C12_C8_0 + #define ICC_IAR1_EL1 S3_0_C12_C12_0 + #define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 + #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 + #define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + #define ICC_PMR_EL1 S3_0_C4_C6_0 + #define ICC_RPR_EL1 S3_0_C12_C11_3 + #define ICC_SGI0R_EL1 S3_0_C12_C11_7 + #define ICC_SGI1R_EL1 S3_0_C12_C11_5 + #define ICC_SRE_EL1 S3_0_C12_C12_5 + #define ICC_SRE_EL2 S3_4_C12_C9_5 + #define ICC_SRE_EL3 S3_6_C12_C12_5 +#endif /* __GNUC__ */ + +/* ICC_SGIR */ +#define ICC_SGIR_TARGETLIST_SHIFT (0) +#define ICC_SGIR_TARGETLIST_MASK (0xffff) +#define ICC_SGIR_AFF_MASK (0xff) +#define ICC_SGIR_AFF1_SHIFT (16) +#define ICC_SGIR_INTID_SHIFT (24) +#define ICC_SGIR_INTID_MASK (0xf) +#define ICC_SGIR_AFF2_SHIFT (32) +#define ICC_SGIR_IRM_SHIFT (40) +#define ICC_SGIR_IRM_MASK (0x1) +#define ICC_SGIR_RS_SHIFT (44) +#define ICC_SGIR_RS_MASK (0xf) +#define ICC_SGIR_AFF3_SHIFT (48) + +#define MPIDR_TO_RS(mpidr) (MPIDR_TO_AFF_LEVEL(mpidr, 0) >> 4) + +#define COMPOSE_ICC_SGIR_VALUE(aff3, aff2, aff1, intid, irm, rs, tlist) \ + ((((uint64_t)(aff3) & ICC_SGIR_AFF_MASK) << ICC_SGIR_AFF3_SHIFT) | \ + (((uint64_t)(rs) & ICC_SGIR_RS_MASK) << ICC_SGIR_RS_SHIFT) | \ + (((uint64_t)(irm) & ICC_SGIR_IRM_MASK) << ICC_SGIR_IRM_SHIFT) | \ + (((uint64_t)(aff2) & ICC_SGIR_AFF_MASK) << ICC_SGIR_AFF2_SHIFT) | \ + (((intid) & ICC_SGIR_INTID_MASK) << ICC_SGIR_INTID_SHIFT) | \ + (((aff1) & ICC_SGIR_AFF_MASK) << ICC_SGIR_AFF1_SHIFT) | \ + (((tlist) & ICC_SGIR_TARGETLIST_MASK) << ICC_SGIR_TARGETLIST_SHIFT)) + +#define GIC_REDISTRIBUTOR_STRIDE (0x20000) +#define GICR_SGI_BASE_OFF (0x10000) + +#define GICR_TYPER_LAST_SHIFT (4) +#define GICR_TYPER_LAST_MASK (1 << GICR_TYPER_LAST_SHIFT) +#define GICR_TYPER_AFF_SHIFT (32) + +#define GICR_WAKER_PS_SHIFT (1) +#define GICR_WAKER_CA_SHIFT (2) + + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5172], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6000(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Redistributor (GICR) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Redistributor Control Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x004 (R/ ) Implementer Identification Register */ + __IM uint64_t TYPER; /*!< \brief Offset: 0x008 (R/ ) Redistributor Type Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + __IOM uint32_t WAKER; /*!< \brief Offset: 0x014 (R/W) Redistributor Wake Register */ + __IM uint32_t MPAMIDR; /*!< \brief Offset: 0x018 (R/ ) Report maximum PARTID and PMG Register */ + __IOM uint32_t PARTIDR; /*!< \brief Offset: 0x01C (R/W) Set PARTID and PMG Register */ + RESERVED(1[8], uint32_t) + __OM uint32_t SETLPIR; /*!< \brief Offset: 0x040 ( /W) Set LPI Pending Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRLPIR; /*!< \brief Offset: 0x048 ( /W) Clear LPI Pending Register */ + RESERVED(3[9], uint32_t) + __IOM uint32_t PROPBASER; /*!< \brief Offset: 0x070 (R/W) Redistributor Properties Base Address Register */ + RESERVED(4, uint32_t) + __IOM uint32_t PENDBASER; /*!< \brief Offset: 0x078 (R/W) Redistributor LPI Pending Table Base Address Register */ + RESERVED(5[9], uint32_t) + __OM uint32_t INVLPIR; /*!< \brief Offset: 0x0A0 ( /W) Redistributor Invalidate LPI Register */ + RESERVED(6[3], uint32_t) + __OM uint32_t INVALLR; /*!< \brief Offset: 0x0B0 ( /W) Redistributor Invalidate All Register */ + RESERVED(7[3], uint32_t) + __IM uint32_t SYNCR; /*!< \brief Offset: 0x0C0 (R/ ) Redistributor Synchronize Register */ +} GICRedistributor_Type; + +/* Memory mapped GIC interface may be disabled when ICC_SRE_ELx.SRE set 1 by hypervisor. + In this case we will be using MSR/MRS system registers. */ +#ifdef GIC_INTERFACE_BASE + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif /* GIC_INTERFACE_BASE */ + +/* ctrl register access in non-secure */ +#define GICD_CTLR_RWP 31 +#define GICD_CTLR_ARE_NS 4 +#define GICD_CTLR_ENGRP1A 1 +#define GICD_CTLR_ENGRP1 0 + +#define GICR_CTLR_RWP 3 + +enum gic_rwp { + GICD_RWP, + GICR_RWP, +}; + +/******************************************************************************* + * GIC Functions + ******************************************************************************/ + +/* ########################## GIC functions ###################################### */ + +/** \brief Get the recomposed MPIDR_EL1 Affinity fields. +* the recomposed Affinity value format is (aff3:aff2:aff1:aff0) +*/ +__STATIC_INLINE uint32_t GIC_MPIDRtoAffinity(void) +{ + uint32_t aff3, aff2, aff1, aff0, aff; + uint64_t mpidr = __get_MPIDR_EL1(); + + aff0 = MPIDR_TO_AFF_LEVEL(mpidr, 0); + aff1 = MPIDR_TO_AFF_LEVEL(mpidr, 1); + aff2 = MPIDR_TO_AFF_LEVEL(mpidr, 2); + aff3 = MPIDR_TO_AFF_LEVEL(mpidr, 3); + + aff = (aff0 & MPIDR_AFFLVL_MASK) << 0 | + (aff1 & MPIDR_AFFLVL_MASK) << 8 | + (aff2 & MPIDR_AFFLVL_MASK) << 16 | + (aff3 & MPIDR_AFFLVL_MASK) << 24; + + return aff; +} + +/** \brief Get the Redistributor base. +*/ +__STATIC_INLINE GICRedistributor_Type *GIC_GetRdist(void) +{ + uintptr_t rd_addr = GIC_REDISTRIBUTOR_BASE; + uint32_t rd_aff, aff = GIC_MPIDRtoAffinity(); + uint64_t rd_typer; + + do { + rd_typer = ((GICRedistributor_Type *)rd_addr)->TYPER; + rd_aff = rd_typer >> GICR_TYPER_AFF_SHIFT; + + if (rd_aff == aff) + return (GICRedistributor_Type *)rd_addr; + + rd_addr += GIC_REDISTRIBUTOR_STRIDE; + } while (!(rd_typer & GICR_TYPER_LAST_MASK)); + + return NULL; +} + +/** \brief Get the Redistributor SGI_base. +*/ +__STATIC_INLINE void *GIC_GetRdistSGIBase(void *rd_base) +{ + return (void *)((uintptr_t)rd_base + GICR_SGI_BASE_OFF); +} + +/** \brief Wait for register write pending. +*/ +__STATIC_INLINE void GIC_WaitRWP(enum gic_rwp rwp) +{ + uint32_t rwp_mask; + uint32_t __IM *base; + + if (rwp == GICR_RWP) { + base = &GIC_GetRdist()->CTLR; + if (!base) + return; + rwp_mask = BIT(GICR_CTLR_RWP); + } else if (rwp == GICD_RWP) { + base = &GICDistributor->CTLR; + rwp_mask = BIT(GICD_CTLR_RWP); + } else { + return; + } + + while (*base & rwp_mask) + ; +} + +/** \brief Get the Affinity Routing status. +*/ +__STATIC_INLINE bool GIC_GetARE(void) +{ + return !!(GICDistributor->CTLR & 0x30); +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; + GIC_WaitRWP(GICD_RWP); +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint64_t cpu_target) +{ + if (IRQn >= 32) + { + if (GIC_GetARE()) + { + /* affinity routing */ + GICDistributor->IROUTER[IRQn] = cpu_target; + } + else + { + /* legacy */ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); + } + } +} + +/** \brief Get the target core of the interrupt. +* \param [in] IRQn Interrupt to acquire the configuration for. +* +* \return: +* For SPI: GICDistributor_Type::ITARGETSR when Affinity Routing isn't enabled, +* or GICDistributor_Type::IROUTER when Affinity Routing is enabled +* For SGI/PPI: The Affinity fields of the MPIDR_EL1. +*/ +__STATIC_INLINE uint64_t GIC_GetTarget(IRQn_Type IRQn) +{ + uint64_t cpu_target = 0; + + if (IRQn >= 32) + { + if (GIC_GetARE()) + { + /* affinity routing */ + cpu_target = GICDistributor->IROUTER[IRQn]; + } + else + { + /* legacy */ + cpu_target = (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + } + } + else + { + /* local */ + cpu_target = __get_MPIDR_EL1() & MPIDR_AFFINITY_MASK; + } + + return cpu_target; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + uint64_t mpidr = __get_MPIDR_EL1(); + GICDistributor_Type *s_RedistPPIBaseAddrs; + + GIC_SetTarget(IRQn, mpidr & MPIDR_AFFINITY_MASK); + + if (IRQn < 32) { + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + s_RedistPPIBaseAddrs->ISENABLER[0] = 1U << IRQn; + } else { + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); + } +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs; + + if (IRQn < 32) { + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + s_RedistPPIBaseAddrs->ICENABLER[0] = 1U << IRQn; + GIC_WaitRWP(GICR_RWP); + } else { + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); + GIC_WaitRWP(GICD_RWP); + } +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +__STATIC_INLINE void GIC_SetRedistPriority(IRQn_Type IRQn, uint32_t priority) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + uint32_t mask = s_RedistPPIBaseAddrs->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + + s_RedistPPIBaseAddrs->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Set the priority for the given interrupt. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask; + + if ((IRQn < 32) && (GIC_GetARE())) { + GIC_SetRedistPriority(IRQn, priority); + } else { + mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); + } +} + +__STATIC_INLINE void GIC_RedistWakeUp(void) +{ + GICRedistributor_Type *const s_RedistBaseAddrs = GIC_GetRdist(); + + if (!s_RedistBaseAddrs) + return; + + if (!(s_RedistBaseAddrs->WAKER & (1 << GICR_WAKER_CA_SHIFT))) + return; + + s_RedistBaseAddrs->WAKER &= ~ (1 << GICR_WAKER_PS_SHIFT); + while (s_RedistBaseAddrs->WAKER & (1 << GICR_WAKER_CA_SHIFT)) + ; +} + +__STATIC_INLINE uint32_t GIC_GetRedistPriority(IRQn_Type IRQn) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs; + + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + return (s_RedistPPIBaseAddrs->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + if ((IRQn < 32) && (GIC_GetARE())) { + return GIC_GetRedistPriority(IRQn); + } else { + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + } +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt (Affinity Routing version). +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_aff Target affinity in MPIDR form. +* \param [in] tlist List of CPUs the software interrupt should be forwarded to. +*/ +__STATIC_INLINE void GIC_SendSGI_ARE(IRQn_Type IRQn, uint64_t target_aff, uint16_t tlist) +{ + uint32_t aff3, aff2, aff1, rs; + uint64_t val; + + if (IRQn >= 16) + return; + + aff1 = MPIDR_TO_AFF_LEVEL(target_aff, 1); + aff2 = MPIDR_TO_AFF_LEVEL(target_aff, 2); + aff3 = MPIDR_TO_AFF_LEVEL(target_aff, 3); + rs = MPIDR_TO_RS(target_aff); + val = COMPOSE_ICC_SGIR_VALUE(aff3, aff2, aff1, IRQn, 0, rs, tlist); + + __DSB(); + __MSR(ICC_SGI1R_EL1, val); + __ISB(); +} + +/** \brief Generate a software interrupt. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_aff Target affinity in MPIDR form. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint64_t target_aff, uint16_t target_list) +{ + if (IRQn >= 16) + return; + + if (GIC_GetARE()) { + /* affinity routing */ + GIC_SendSGI_ARE(IRQn, target_aff, target_list); + } else { + GICDistributor->SGIR = ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); + } +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +__STATIC_INLINE void GIC_SetRedistGroup(IRQn_Type IRQn, uint32_t group) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs; + uint32_t shift = (IRQn % 32U); + uint32_t igroupr; + + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + igroupr = s_RedistPPIBaseAddrs->IGROUPR[IRQn / 32U]; + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + s_RedistPPIBaseAddrs->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + uint32_t ppi_priority; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored. + Use PPI, as it is always accessible, even for a Guest OS using a hypervisor. + Then restore the initial state.*/ + ppi_priority = GIC_GetPriority((IRQn_Type)31U); + GIC_SetPriority((IRQn_Type)31U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)31U); + GIC_SetPriority((IRQn_Type)31U, ppi_priority); + + for (i = 32U; i < num_irq; i++) + { + /* Use non secure group1 for all SPI */ + GIC_SetGroup(i, 1); + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field*2U/3U); + } + + /* Enable distributor with ARE_NS and NS_Group1 */ + GICDistributor->CTLR = ((1U << GICD_CTLR_ARE_NS) | (1U << GICD_CTLR_ENGRP1A)); + GIC_WaitRWP(GICD_RWP); +} + +/** \brief Initialize the interrupt redistributor. +*/ +__STATIC_INLINE void GIC_RedistInit(void) +{ + uint32_t i; + uint32_t priority_field; + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetRedistPriority((IRQn_Type)31U, 0xFFU); + priority_field = GIC_GetRedistPriority((IRQn_Type)31U); + + /* Wakeup the GIC */ + GIC_RedistWakeUp(); + + for (i = 0; i < 32; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetRedistPriority((IRQn_Type)i, priority_field*2U/3U); + } +} + +#ifdef GICInterface + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +#else /* GICInterface */ + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + __MSR(ICC_IGRPEN1_EL1, 1); +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + __MSR(ICC_IGRPEN1_EL1, 0); +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + uint32_t result; + __MRS(ICC_IAR1_EL1, &result); + return (IRQn_Type)(result); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + __MSR(ICC_EOIR1_EL1, (uint32_t)IRQn); +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + __MSR(ICC_PMR_EL1, priority & 0xFFUL); +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + uint32_t result; + __MRS(ICC_PMR_EL1, &result); + return result; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + __MSR(ICC_BPR1_EL1, binary_point & 7U); +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + uint32_t result; + __MRS(ICC_BPR1_EL1, &result); + return result; +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + uint32_t result; + __MRS(ICC_HPPIR1_EL1, &result); + return result; +} + +#endif + +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if (i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field*2U/3U); + } + + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); + //Enable interface + GIC_EnableInterface(); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(int init_dist) +{ + /* Only one core should be responsible for the GIC distributor setup */ + if (init_dist) + GIC_DistInit(); + + GIC_RedistInit(); + GIC_CPUInterfaceInit(); //per CPU +} + +#ifdef __cplusplus +} +#endif + +#endif /* __GIC_V3_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/mmu_armv8a.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/mmu_armv8a.h new file mode 100644 index 00000000000..b081c922c15 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/mmu_armv8a.h @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file mmu_armv8a.h + * @brief CMSIS Cortex-Axx MMU API header file + * @version V1.0.0 + * @date 20. october 2021 + ******************************************************************************/ +/* + * Copyright 2019 Broadcom + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __MMU_ARMV8A_H +#define __MMU_ARMV8A_H + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************/ + +/* Following Memory types supported through MAIR encodings can be passed + * by user through "attrs"(attributes) field of specified memory region. + * As MAIR supports such 8 encodings, we will reserve attrs[2:0]; + * so that we can provide encodings upto 7 if needed in future. + */ +#define MT_TYPE_MASK 0x7U +#define MT_TYPE(attr) (attr & MT_TYPE_MASK) +#define MT_DEVICE_nGnRnE 0U +#define MT_DEVICE_nGnRE 1U +#define MT_DEVICE_GRE 2U +#define MT_NORMAL_NC 3U +#define MT_NORMAL 4U +#define MT_NORMAL_WT 5U + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \ + (0x04 << (MT_DEVICE_nGnRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (0xffUL << (MT_NORMAL * 8)) | \ + (0xbbUL << (MT_NORMAL_WT * 8))) + +/* More flags from user's perpective are supported using remaining bits + * of "attrs" field, i.e. attrs[31:3], underlying code will take care + * of setting PTE fields correctly. + * + * current usage of attrs[31:3] is: + * attrs[3] : Access Permissions + * attrs[4] : Memory access from secure/ns state + * attrs[5] : Execute Permissions privileged mode (PXN) + * attrs[6] : Execute Permissions unprivileged mode (UXN) + * attrs[7] : Mirror RO/RW permissions to EL0 + * attrs[8] : Overwrite existing mapping if any + * + */ +#define MT_PERM_SHIFT 3U +#define MT_SEC_SHIFT 4U +#define MT_P_EXECUTE_SHIFT 5U +#define MT_U_EXECUTE_SHIFT 6U +#define MT_RW_AP_SHIFT 7U +#define MT_NO_OVERWRITE_SHIFT 8U + +#define MT_RO (0U << MT_PERM_SHIFT) +#define MT_RW (1U << MT_PERM_SHIFT) + +#define MT_RW_AP_ELx (1U << MT_RW_AP_SHIFT) +#define MT_RW_AP_EL_HIGHER (0U << MT_RW_AP_SHIFT) + +#define MT_SECURE (0U << MT_SEC_SHIFT) +#define MT_NS (1U << MT_SEC_SHIFT) + +#define MT_P_EXECUTE (0U << MT_P_EXECUTE_SHIFT) +#define MT_P_EXECUTE_NEVER (1U << MT_P_EXECUTE_SHIFT) + +#define MT_U_EXECUTE (0U << MT_U_EXECUTE_SHIFT) +#define MT_U_EXECUTE_NEVER (1U << MT_U_EXECUTE_SHIFT) + +#define MT_NO_OVERWRITE (1U << MT_NO_OVERWRITE_SHIFT) + +#define MT_P_RW_U_RW (MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RW_U_NA (MT_RW | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RO_U_RO (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RO_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RO_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE) +#define MT_P_RX_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE | MT_U_EXECUTE) +#define MT_P_RX_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE | MT_U_EXECUTE_NEVER) + +#ifdef CONFIG_ARMV8_A_NS +#define MT_DEFAULT_SECURE_STATE MT_NS +#else +#define MT_DEFAULT_SECURE_STATE MT_SECURE +#endif +#ifndef CONFIG_ARM64_PA_BITS +#define CONFIG_ARM64_PA_BITS 48 +#endif +#ifndef CONFIG_ARM64_VA_BITS +#define CONFIG_ARM64_VA_BITS 48 +#endif + +/* + * PTE descriptor can be Block descriptor or Table descriptor + * or Page descriptor. + */ +#define PTE_DESC_TYPE_MASK 3U +#define PTE_BLOCK_DESC 1U +#define PTE_TABLE_DESC 3U +#define PTE_PAGE_DESC 3U +#define PTE_INVALID_DESC 0U + +/* + * Block and Page descriptor attributes fields + */ +#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) +#define PTE_BLOCK_DESC_NS (1ULL << 5) +#define PTE_BLOCK_DESC_AP_ELx (1ULL << 6) +#define PTE_BLOCK_DESC_AP_EL_HIGHER (0ULL << 6) +#define PTE_BLOCK_DESC_AP_RO (1ULL << 7) +#define PTE_BLOCK_DESC_AP_RW (0ULL << 7) +#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) +#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) +#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) +#define PTE_BLOCK_DESC_AF (1ULL << 10) +#define PTE_BLOCK_DESC_NG (1ULL << 11) +#define PTE_BLOCK_DESC_PXN (1ULL << 53) +#define PTE_BLOCK_DESC_UXN (1ULL << 54) + +/* + * TCR definitions. + */ +#define TCR_EL1_IPS_SHIFT 32U +#define TCR_EL2_PS_SHIFT 16U +#define TCR_EL3_PS_SHIFT 16U + +#define TCR_T0SZ_SHIFT 0U +#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) + +#define TCR_IRGN_NC (0ULL << 8) +#define TCR_IRGN_WBWA (1ULL << 8) +#define TCR_IRGN_WT (2ULL << 8) +#define TCR_IRGN_WBNWA (3ULL << 8) +#define TCR_IRGN_MASK (3ULL << 8) +#define TCR_ORGN_NC (0ULL << 10) +#define TCR_ORGN_WBWA (1ULL << 10) +#define TCR_ORGN_WT (2ULL << 10) +#define TCR_ORGN_WBNWA (3ULL << 10) +#define TCR_ORGN_MASK (3ULL << 10) +#define TCR_SHARED_NON (0ULL << 12) +#define TCR_SHARED_OUTER (2ULL << 12) +#define TCR_SHARED_INNER (3ULL << 12) +#define TCR_TG0_4K (0ULL << 14) +#define TCR_TG0_64K (1ULL << 14) +#define TCR_TG0_16K (2ULL << 14) +#define TCR_EPD1_DISABLE (1ULL << 23) + +#define TCR_PS_BITS_4GB 0x0ULL +#define TCR_PS_BITS_64GB 0x1ULL +#define TCR_PS_BITS_1TB 0x2ULL +#define TCR_PS_BITS_4TB 0x3ULL +#define TCR_PS_BITS_16TB 0x4ULL +#define TCR_PS_BITS_256TB 0x5ULL + +/* Region definition data structure */ +struct ARM_MMU_region { + /* Region BasePhysical Address */ + uintptr_t base_pa; + /* Region Base Virtual Address */ + uintptr_t base_va; + /* Region size */ + size_t size; + /* Region Name */ + const char *name; + /* Region Attributes */ + uint32_t attrs; +}; + +/* MMU configuration data structure */ +struct ARM_MMU_config { + /* Number of regions */ + unsigned int num_regions; + /* Regions */ + const struct ARM_MMU_region *mmu_regions; + /* Number of OS memory regions */ + unsigned int num_os_ranges; + /* OS memory regions */ + const struct ARM_MMU_flat_range *mmu_os_ranges; +}; + +struct ARM_MMU_flat_range { + char *name; + void *start; + void *end; + uint32_t attrs; +}; + +struct ARM_MMU_ptables { + uint64_t *base_xlat_table; +}; + +/* Convenience macros to represent the ARMv8-A-specific + * configuration for memory access permission and + * cache-ability attribution. + */ + +#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \ + {\ + .name = _name, \ + .base_pa = _base_pa, \ + .base_va = _base_va, \ + .size = _size, \ + .attrs = _attrs, \ + } + +#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \ + MMU_REGION_ENTRY(name, adr, adr, sz, attrs) + +void ARM_MMU_Initialize(const struct ARM_MMU_config *MMU_config, bool is_primary_core); +int ARM_MMU_AddMap(const char *name, uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs); +void ARM_MMU_InvalidateTLB(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MMU_ARMV8A_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/timer_armv8a.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/timer_armv8a.h new file mode 100644 index 00000000000..4ea2ef53942 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/timer_armv8a.h @@ -0,0 +1,145 @@ +/**************************************************************************//** + * @file timer_armv8a.h + * @brief CMSIS Cortex-Axx Generic Timer API header file + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __TIMER_ARMV8A_H +#define __TIMER_ARMV8A_H + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Timer Data Types + ******************************************************************************/ + +/** \brief ARMv8-A Generic Timer types */ +typedef enum _ARM_TIMER_TYPE { + ARM_TIMER_PHYSICAL, /** Physical Timer */ + ARM_TIMER_VIRTUAL, /** Virtual Timer */ + ARM_TIMER_HYPERVISOR_PHYSICAL, /** Hypervisor Physical Timer */ + ARM_TIMER_PHYSICAL_SECURE, /** Physical Secure Timer */ +} ARM_TIMER_type_t; + + +/******************************************************************************* + * Timer Functions + ******************************************************************************/ + +__STATIC_INLINE void ARM_TIMER_Initialize(ARM_TIMER_type_t timer) +{ +} + +__STATIC_INLINE void ARM_TIMER_GetFreq(uint32_t *pVal) +{ + __MRS(CNTFRQ_EL0, pVal); +} + +__STATIC_INLINE void ARM_TIMER_SetInterval(ARM_TIMER_type_t timer, uint32_t val) +{ + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MSR(CNTP_TVAL_EL0, val); + break; + case ARM_TIMER_VIRTUAL: + __MSR(CNTV_TVAL_EL0, val); + break; + case ARM_TIMER_HYPERVISOR_PHYSICAL: + __MSR(CNTHP_TVAL_EL2, val); + break; + case ARM_TIMER_PHYSICAL_SECURE: + __MSR(CNTPS_TVAL_EL1, val); + break; + default: + break; + } + + __DSB(); + __ISB(); +} + +__STATIC_INLINE void ARM_TIMER_GetCount(ARM_TIMER_type_t timer, uint32_t *val) +{ + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MRS(CNTP_TVAL_EL0, val); + break; + case ARM_TIMER_VIRTUAL: + __MRS(CNTV_TVAL_EL0, val); + break; + case ARM_TIMER_HYPERVISOR_PHYSICAL: + __MRS(CNTHP_TVAL_EL2, val); + break; + case ARM_TIMER_PHYSICAL_SECURE: + __MRS(CNTPS_TVAL_EL1, val); + break; + default: + break; + } +} + +__STATIC_INLINE void ARM_TIMER_Start(ARM_TIMER_type_t timer, bool irq_enable) +{ + uint64_t ctl = 1UL << 0; + + if (!irq_enable) + ctl |= 1UL << 1; + + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MSR(CNTP_CTL_EL0, ctl); + break; + case ARM_TIMER_VIRTUAL: + __MSR(CNTV_CTL_EL0, ctl); + break; + case ARM_TIMER_HYPERVISOR_PHYSICAL: + __MSR(CNTHP_CTL_EL2, ctl); + break; + case ARM_TIMER_PHYSICAL_SECURE: + __MSR(CNTPS_CTL_EL1, ctl); + break; + default: + break; + } +} + +__STATIC_FORCEINLINE void ARM_TIMER_GetCounterCount(ARM_TIMER_type_t timer, uint64_t *val) +{ + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MRS(cntpct_el0, val); + break; + case ARM_TIMER_VIRTUAL: + __MRS(cntvct_el0, val); + break; + default: + break; + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_ARMV8A_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/SConscript new file mode 100644 index 00000000000..f1ba1757af9 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('Source/*.c') + +CPPPATH = [cwd + '/Include'] +CPPDEFINES = [ + {'CPU_MIMX9131DVVXJ': 1} +] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/cache_armv8a.c b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/cache_armv8a.c new file mode 100644 index 00000000000..06cedd94521 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/cache_armv8a.c @@ -0,0 +1,137 @@ +/**************************************************************************//** + * @file cache_armv8a.c + * @brief CMSIS AARCH64 Cache Source file + * @version V1.0.0 + * @date 21. January 2022 + ******************************************************************************/ + +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "core_ca53.h" +#include "cache_armv8a.h" + +#ifndef BIT_MASK +#define BIT_MASK(n) ((1UL << n) - 1UL) +#endif + +/* CLIDR_EL1 */ +#define CLIDR_EL1_LOC_SHIFT 24 +#define CLIDR_EL1_LOC_MASK BIT_MASK(3) +#define CLIDR_EL1_CTYPE_SHIFT(l) ((l) * 3) +#define CLIDR_EL1_CTYPE_MASK BIT_MASK(3) + +/* CCSIDR_EL1 */ +#define CCSIDR_EL1_LN_SZ_SHIFT 0 +#define CCSIDR_EL1_LN_SZ_MASK BIT_MASK(3) +#define CCSIDR_EL1_WAYS_SHIFT 3 +#define CCSIDR_EL1_WAYS_MASK BIT_MASK(10) +#define CCSIDR_EL1_SETS_SHIFT 13 +#define CCSIDR_EL1_SETS_MASK BIT_MASK(15) + +/* CSSELR_EL1 */ +#define CSSELR_EL1_LEVEL_SHIFT 1 +#define CSSELR_EL1_LEVEL_MASK BIT_MASK(3) + +enum cache_ops { + CACHE_OP_C, /* Clean */ + CACHE_OP_I, /* Invalidate */ + CACHE_OP_CI /* Clean and Invalidate */ +}; + +/* + * Operation for all data cache to PoC + * op: CACHE_OP_C: clean + * CACHE_OP_I: invalidate + * CACHE_OP_CI: clean and invalidate + */ +int dcache_all(enum cache_ops op) +{ + uint32_t clidr_el1, csselr_el1, ccsidr_el1; + uint32_t num_ways, num_sets, set, way, operand; + uint8_t loc, cache_type, cache_level, set_shift, way_shift; + + __DSB(); + + __MRS(CLIDR_EL1, &clidr_el1); + + loc = (clidr_el1 >> CLIDR_EL1_LOC_SHIFT) & CLIDR_EL1_LOC_MASK; + if (!loc) + return 0; + + for (cache_level = 0; cache_level < loc; cache_level++) { + cache_type = (clidr_el1 >> CLIDR_EL1_CTYPE_SHIFT(cache_level)) & + CLIDR_EL1_CTYPE_MASK; + /* No Data or Unified cache at this level */ + if (cache_type < 2) + continue; + + /* Select cache level and Data/Unified cache */ + csselr_el1 = (cache_level & CSSELR_EL1_LEVEL_MASK) << + CSSELR_EL1_LEVEL_SHIFT; + __MSR(CSSELR_EL1, csselr_el1); + __ISB(); + + __MRS(CCSIDR_EL1, &ccsidr_el1); + set_shift = ((ccsidr_el1 >> CCSIDR_EL1_LN_SZ_SHIFT) & + CCSIDR_EL1_LN_SZ_MASK) + 4; + num_ways = ((ccsidr_el1 >> CCSIDR_EL1_WAYS_SHIFT) & + CCSIDR_EL1_WAYS_MASK) + 1; + num_sets = ((ccsidr_el1 >> CCSIDR_EL1_SETS_SHIFT) & + CCSIDR_EL1_SETS_MASK) + 1; + /* 32-log2(ways), bit position of way in DC operand */ + way_shift = __CLZ(num_ways - 1); + + for (set = 0; set < num_sets; set++) { + for (way = 0; way < num_ways; way++) { + /* cache level, aligned to pos in DC operand */ + operand = (cache_level << 1); + /* set number, aligned to pos in DC operand */ + operand |= set << set_shift; + /* way number, aligned to pos in DC operand */ + /* No way number field for direct-mapped cache */ + if (way_shift < 32) + operand |= way << way_shift; + + switch (op) { + case CACHE_OP_C: + dcache_ops(csw, operand); + break; + case CACHE_OP_I: + dcache_ops(isw, operand); + break; + case CACHE_OP_CI: + dcache_ops(cisw, operand); + break; + default: + return -1; + } + } + } + } + + __DSB(); + + /* Restore csselr_el1 to level 0 */ + __MSR(CSSELR_EL1, 0); + __ISB(); + + return 0; +} + +void dcache_clean_all(void) +{ + dcache_all(CACHE_OP_C); +} + +void dcache_invalidate_all(void) +{ + dcache_all(CACHE_OP_I); +} +void dcache_clean_invalidate_all(void) +{ + dcache_all(CACHE_OP_CI); +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/mmu_armv8a.c b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/mmu_armv8a.c new file mode 100644 index 00000000000..fe75a4f2672 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/mmu_armv8a.c @@ -0,0 +1,720 @@ +/**************************************************************************//** + * @file mmu_armv8a.c + * @brief CMSIS Cortex-Axx MMU Source file + * @version V1.0.0 + * @date 20. october 2021 + ******************************************************************************/ +/* + * Copyright 2019 Broadcom + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "core_ca53.h" +#include "mmu_armv8a.h" + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define __ASSERT(op, fmt, ...) \ + do { \ + if (!(op)) { \ + while(1) \ + /* wait here */; \ + } \ + } while (0) + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef KB +#define KB(x) ((x) << 10) +#endif + +#ifndef CONFIG_MMU_PAGE_SIZE +#define CONFIG_MMU_PAGE_SIZE 4096 +#endif +#ifndef CONFIG_MAX_XLAT_TABLES +#define CONFIG_MAX_XLAT_TABLES 32 +#endif +#ifndef CONFIG_ARM64_PA_BITS +#define CONFIG_ARM64_PA_BITS 48 +#endif +#ifndef CONFIG_ARM64_VA_BITS +#define CONFIG_ARM64_VA_BITS 48 +#endif + +#define LOG_ERR(fmt, ...) (void)(fmt) +#define ARG_UNUSED(x) (void)(x) + +#define BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +/******************************************************************************* + * from zephyr:/arch/arm/core/aarch64/mmu/arm_mmu.h: + ******************************************************************************/ + +/* Set below flag to get debug prints */ +//#define MMU_DEBUG_PRINTS 0 + +#if defined (MMU_DEBUG_PRINTS) && (MMU_DEBUG_PRINTS == 1) +/* To dump page table entries while filling them, set DUMP_PTE macro */ +#define DUMP_PTE 0 + #define MMU_DEBUG(fmt, ...) PRINTF(fmt, ##__VA_ARGS__) +#else + #define MMU_DEBUG(...) +#endif + +/* + * 48-bit address with 4KB granule size: + * + * +------------+------------+------------+------------+-----------+ + * | VA [47:39] | VA [38:30] | VA [29:21] | VA [20:12] | VA [11:0] | + * +---------------------------------------------------------------+ + * | L0 | L1 | L2 | L3 | block off | + * +------------+------------+------------+------------+-----------+ + */ + +/* Only 4K granule is supported */ +#define PAGE_SIZE_SHIFT 12U + +/* 48-bit VA address */ +#define VA_SIZE_SHIFT_MAX 48U + +/* Maximum 4 XLAT table levels (L0 - L3) */ +#define XLAT_LAST_LEVEL 3U + +/* The VA shift of L3 depends on the granule size */ +#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT + +/* Number of VA bits to assign to each table (9 bits) */ +#define Ln_XLAT_VA_SIZE_SHIFT (PAGE_SIZE_SHIFT - 3) + +/* Starting bit in the VA address for each level */ +#define L2_XLAT_VA_SIZE_SHIFT (L3_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) +#define L1_XLAT_VA_SIZE_SHIFT (L2_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) +#define L0_XLAT_VA_SIZE_SHIFT (L1_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) + +#define LEVEL_TO_VA_SIZE_SHIFT(level) \ + (PAGE_SIZE_SHIFT + (Ln_XLAT_VA_SIZE_SHIFT * \ + (XLAT_LAST_LEVEL - (level)))) + +/* Number of entries for each table (512) */ +#define Ln_XLAT_NUM_ENTRIES ((1U << PAGE_SIZE_SHIFT) / 8U) + +/* Virtual Address Index within a given translation table level */ +#define XLAT_TABLE_VA_IDX(va_addr, level) \ + ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (Ln_XLAT_NUM_ENTRIES - 1)) + +/* + * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS + * For a 4 KB page size: + * + * (va_bits <= 20) - base level 3 + * (21 <= va_bits <= 29) - base level 2 + * (30 <= va_bits <= 38) - base level 1 + * (39 <= va_bits <= 47) - base level 0 + */ +#define GET_BASE_XLAT_LEVEL(va_bits) \ + ((va_bits > L0_XLAT_VA_SIZE_SHIFT) ? 0U \ + : (va_bits > L1_XLAT_VA_SIZE_SHIFT) ? 1U \ + : (va_bits > L2_XLAT_VA_SIZE_SHIFT) ? 2U : 3U) + +/* Level for the base XLAT */ +#define BASE_XLAT_LEVEL GET_BASE_XLAT_LEVEL(CONFIG_ARM64_VA_BITS) + +#if (CONFIG_ARM64_PA_BITS == 48) +#define TCR_PS_BITS TCR_PS_BITS_256TB +#elif (CONFIG_ARM64_PA_BITS == 44) +#define TCR_PS_BITS TCR_PS_BITS_16TB +#elif (CONFIG_ARM64_PA_BITS == 42) +#define TCR_PS_BITS TCR_PS_BITS_4TB +#elif (CONFIG_ARM64_PA_BITS == 40) +#define TCR_PS_BITS TCR_PS_BITS_1TB +#elif (CONFIG_ARM64_PA_BITS == 36) +#define TCR_PS_BITS TCR_PS_BITS_64GB +#else +#define TCR_PS_BITS TCR_PS_BITS_4GB +#endif + +/* Upper and lower attributes mask for page/block descriptor */ +#define DESC_ATTRS_UPPER_MASK GENMASK(63, 51) +#define DESC_ATTRS_LOWER_MASK GENMASK(11, 2) + +#define DESC_ATTRS_MASK (DESC_ATTRS_UPPER_MASK | DESC_ATTRS_LOWER_MASK) + +/******************************************************************************/ + +static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES * Ln_XLAT_NUM_ENTRIES] + __aligned(Ln_XLAT_NUM_ENTRIES * sizeof(uint64_t)); +static uint16_t xlat_use_count[CONFIG_MAX_XLAT_TABLES]; + +/* Returns a reference to a free table */ +static uint64_t *new_table(void) +{ + unsigned int i; + + /* Look for a free table. */ + for (i = 0; i < CONFIG_MAX_XLAT_TABLES; i++) { + if (xlat_use_count[i] == 0) { + xlat_use_count[i] = 1; + return &xlat_tables[i * Ln_XLAT_NUM_ENTRIES]; + } + } + + LOG_ERR("CONFIG_MAX_XLAT_TABLES, too small"); + return NULL; +} + +static inline unsigned int table_index(uint64_t *pte) +{ + unsigned int i = (pte - xlat_tables) / Ln_XLAT_NUM_ENTRIES; + + __ASSERT(i < CONFIG_MAX_XLAT_TABLES, "table %p out of range", pte); + return i; +} + +/* Makes a table free for reuse. */ +static void free_table(uint64_t *table) +{ + unsigned int i = table_index(table); + + MMU_DEBUG("freeing table [%d]%p\r\n", i, table); + __ASSERT(xlat_use_count[i] == 1, "table still in use"); + xlat_use_count[i] = 0; +} + +/* Adjusts usage count and returns current count. */ +static int table_usage(uint64_t *table, int adjustment) +{ + unsigned int i = table_index(table); + + xlat_use_count[i] += adjustment; + __ASSERT(xlat_use_count[i] > 0, "usage count underflow"); + return xlat_use_count[i]; +} + +static inline bool is_table_unused(uint64_t *table) +{ + return table_usage(table, 0) == 1; +} + +static inline bool is_free_desc(uint64_t desc) +{ + return (desc & PTE_DESC_TYPE_MASK) == PTE_INVALID_DESC; +} + +static inline bool is_table_desc(uint64_t desc, unsigned int level) +{ + return level != XLAT_LAST_LEVEL && + (desc & PTE_DESC_TYPE_MASK) == PTE_TABLE_DESC; +} + +static inline bool is_block_desc(uint64_t desc) +{ + return (desc & PTE_DESC_TYPE_MASK) == PTE_BLOCK_DESC; +} + +static inline uint64_t *pte_desc_table(uint64_t desc) +{ + uint64_t address = desc & GENMASK(47, PAGE_SIZE_SHIFT); + + return (uint64_t *)address; +} + +static inline bool is_desc_superset(uint64_t desc1, uint64_t desc2, + unsigned int level) +{ + uint64_t mask = DESC_ATTRS_MASK | GENMASK(47, LEVEL_TO_VA_SIZE_SHIFT(level)); + + return (desc1 & mask) == (desc2 & mask); +} + +#if DUMP_PTE +static void debug_show_pte(uint64_t *pte, unsigned int level) +{ + MMU_DEBUG("%.*s", level * 2, ". . . "); + MMU_DEBUG("[%d]%p: ", table_index(pte), pte); + + if (is_free_desc(*pte)) { + MMU_DEBUG("---\r\n"); + return; + } + + if (is_table_desc(*pte, level)) { + uint64_t *table = pte_desc_table(*pte); + + MMU_DEBUG("[Table] [%d]%p\r\n", table_index(table), table); + return; + } + + if (is_block_desc(*pte)) { + MMU_DEBUG("[Block] "); + } else { + MMU_DEBUG("[Page] "); + } + + uint8_t mem_type = (*pte >> 2) & MT_TYPE_MASK; + + MMU_DEBUG((mem_type == MT_NORMAL) ? "MEM" : + ((mem_type == MT_NORMAL_NC) ? "NC" : "DEV")); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_AP_RO) ? "-RO" : "-RW"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_NS) ? "-NS" : "-S"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_AP_ELx) ? "-ELx" : "-ELh"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_PXN) ? "-PXN" : "-PX"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_UXN) ? "-UXN" : "-UX"); + MMU_DEBUG("\r\n"); +} +#else +static inline void debug_show_pte(uint64_t *pte, unsigned int level) { } +#endif + +static void set_pte_table_desc(uint64_t *pte, uint64_t *table, unsigned int level) +{ + /* Point pte to new table */ + *pte = PTE_TABLE_DESC | (uint64_t)table; + debug_show_pte(pte, level); +} + +static void set_pte_block_desc(uint64_t *pte, uint64_t desc, unsigned int level) +{ + if (desc) { + desc |= (level == XLAT_LAST_LEVEL) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; + } + *pte = desc; + debug_show_pte(pte, level); +} + +static uint64_t *expand_to_table(uint64_t *pte, unsigned int level) +{ + uint64_t *table; + + __ASSERT(level < XLAT_LAST_LEVEL, "can't expand last level"); + + table = new_table(); + if (!table) { + return NULL; + } + + if (!is_free_desc(*pte)) { + /* + * If entry at current level was already populated + * then we need to reflect that in the new table. + */ + uint64_t desc = *pte; + unsigned int i, stride_shift; + + MMU_DEBUG("expanding PTE 0x%016llx into table [%d]%p\r\n", + desc, table_index(table), table); + __ASSERT(is_block_desc(desc), ""); + + if (level + 1 == XLAT_LAST_LEVEL) { + desc |= PTE_PAGE_DESC; + } + + stride_shift = LEVEL_TO_VA_SIZE_SHIFT(level + 1); + for (i = 0; i < Ln_XLAT_NUM_ENTRIES; i++) { + table[i] = desc | (i << stride_shift); + } + table_usage(table, Ln_XLAT_NUM_ENTRIES); + } else { + /* + * Adjust usage count for parent table's entry + * that will no longer be free. + */ + table_usage(pte, 1); + } + + /* Link the new table in place of the pte it replaces */ + set_pte_table_desc(pte, table, level); + table_usage(table, 1); + + return table; +} + +static int set_mapping(struct ARM_MMU_ptables *ptables, + uintptr_t virt, size_t size, + uint64_t desc, bool may_overwrite) +{ + uint64_t *pte, *ptes[XLAT_LAST_LEVEL + 1]; + uint64_t level_size; + uint64_t *table = ptables->base_xlat_table; + unsigned int level = BASE_XLAT_LEVEL; + int ret = 0; + + while (size) { + __ASSERT(level <= XLAT_LAST_LEVEL, + "max translation table level exceeded\r\n"); + + /* Locate PTE for given virtual address and page table level */ + pte = &table[XLAT_TABLE_VA_IDX(virt, level)]; + ptes[level] = pte; + + if (is_table_desc(*pte, level)) { + /* Move to the next translation table level */ + level++; + table = pte_desc_table(*pte); + continue; + } + + if (!may_overwrite && !is_free_desc(*pte)) { + /* the entry is already allocated */ + LOG_ERR("entry already in use: " + "level %d pte %p *pte 0x%016llx", + level, pte, *pte); + ret = -1; + break; + } + + level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); + + if (is_desc_superset(*pte, desc, level)) { + /* This block already covers our range */ + level_size -= (virt & (level_size - 1)); + if (level_size > size) { + level_size = size; + } + goto move_on; + } + + if ((size < level_size) || (virt & (level_size - 1))) { + /* Range doesn't fit, create subtable */ + table = expand_to_table(pte, level); + if (!table) { + ret = -1; + break; + } + level++; + continue; + } + + /* Adjust usage count for corresponding table */ + if (is_free_desc(*pte)) { + table_usage(pte, 1); + } + if (!desc) { + table_usage(pte, -1); + } + /* Create (or erase) block/page descriptor */ + set_pte_block_desc(pte, desc, level); + + /* recursively free unused tables if any */ + while (level != BASE_XLAT_LEVEL && + is_table_unused(pte)) { + free_table(pte); + pte = ptes[--level]; + set_pte_block_desc(pte, 0, level); + table_usage(pte, -1); + } + +move_on: + virt += level_size; + desc += desc ? level_size : 0; + size -= level_size; + + /* Range is mapped, start again for next range */ + table = ptables->base_xlat_table; + level = BASE_XLAT_LEVEL; + } + + return ret; +} + +static uint64_t get_region_desc(uint32_t attrs) +{ + unsigned int mem_type; + uint64_t desc = 0; + + /* NS bit for security memory access from secure state */ + desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0; + + /* + * AP bits for EL0 / ELh Data access permission + * + * AP[2:1] ELh EL0 + * +--------------------+ + * 00 RW NA + * 01 RW RW + * 10 RO NA + * 11 RO RO + */ + + /* AP bits for Data access permission */ + desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; + + /* Mirror permissions to EL0 */ + desc |= (attrs & MT_RW_AP_ELx) ? + PTE_BLOCK_DESC_AP_ELx : PTE_BLOCK_DESC_AP_EL_HIGHER; + + /* the access flag */ + desc |= PTE_BLOCK_DESC_AF; + + /* memory attribute index field */ + mem_type = MT_TYPE(attrs); + desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type); + + switch (mem_type) { + case MT_DEVICE_nGnRnE: + case MT_DEVICE_nGnRE: + case MT_DEVICE_GRE: + /* Access to Device memory and non-cacheable memory are coherent + * for all observers in the system and are treated as + * Outer shareable, so, for these 2 types of memory, + * it is not strictly needed to set shareability field + */ + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + /* Map device memory as execute-never */ + desc |= PTE_BLOCK_DESC_PXN; + desc |= PTE_BLOCK_DESC_UXN; + break; + case MT_NORMAL_NC: + case MT_NORMAL: + /* Make Normal RW memory as execute never */ + if ((attrs & MT_RW) || (attrs & MT_P_EXECUTE_NEVER)) + desc |= PTE_BLOCK_DESC_PXN; + + if (((attrs & MT_RW) && (attrs & MT_RW_AP_ELx)) || + (attrs & MT_U_EXECUTE_NEVER)) + desc |= PTE_BLOCK_DESC_UXN; + + if (mem_type == MT_NORMAL) + desc |= PTE_BLOCK_DESC_INNER_SHARE; + else + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + break; + default: + break; + } + + return desc; +} + +static int add_map(struct ARM_MMU_ptables *ptables, const char *name, + uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs) +{ + uint64_t desc = get_region_desc(attrs); + bool may_overwrite = !(attrs & MT_NO_OVERWRITE); + + MMU_DEBUG("mmap [%s]: virt %lx phys %lx size %lx attr %llx\r\n", + name, virt, phys, size, desc); + __ASSERT(((virt | phys | size) & (CONFIG_MMU_PAGE_SIZE - 1)) == 0, + "address/size are not page aligned\r\n"); + desc |= phys; + return set_mapping(ptables, virt, size, desc, may_overwrite); +} + +/* OS execution regions with appropriate attributes */ + +static inline void add_ARM_MMU_flat_range(struct ARM_MMU_ptables *ptables, + const struct ARM_MMU_flat_range *range, + uint32_t extra_flags) +{ + uintptr_t address = (uintptr_t)range->start; + size_t size = (uintptr_t)range->end - address; + + if (size) { + add_map(ptables, range->name, address, address, + size, range->attrs | extra_flags); + } +} + +static inline void add_ARM_MMU_region(struct ARM_MMU_ptables *ptables, + const struct ARM_MMU_region *region, + uint32_t extra_flags) +{ + if (region->size || region->attrs) { + add_map(ptables, region->name, region->base_pa, region->base_va, + region->size, region->attrs | extra_flags); + } +} + +static void setup_page_tables(const struct ARM_MMU_config *MMU_config, + struct ARM_MMU_ptables *ptables) +{ + unsigned int index; + const struct ARM_MMU_flat_range *range; + const struct ARM_MMU_region *region; + uintptr_t max_va = 0, max_pa = 0; + + MMU_DEBUG("xlat tables:\r\n"); + for (index = 0; index < CONFIG_MAX_XLAT_TABLES; index++) + MMU_DEBUG("%d: %p\r\n", index, xlat_tables + index * Ln_XLAT_NUM_ENTRIES); + + for (index = 0; index < MMU_config->num_regions; index++) { + region = &MMU_config->mmu_regions[index]; + max_va = MAX(max_va, region->base_va + region->size); + max_pa = MAX(max_pa, region->base_pa + region->size); + } + + __ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS), + "Maximum VA not supported\r\n"); + __ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS), + "Maximum PA not supported\r\n"); + + /* setup translation table for OS execution regions */ + for (index = 0; index < MMU_config->num_os_ranges; index++) { + range = &MMU_config->mmu_os_ranges[index]; + add_ARM_MMU_flat_range(ptables, range, 0); + } + + /* + * Create translation tables for user provided platform regions. + * Those must not conflict with our default mapping. + */ + for (index = 0; index < MMU_config->num_regions; index++) { + region = &MMU_config->mmu_regions[index]; + add_ARM_MMU_region(ptables, region, MT_NO_OVERWRITE); + } + + ARM_MMU_InvalidateTLB(); +} + +/* Translation table control register settings */ +static uint64_t get_tcr(int el) +{ + uint64_t tcr; + uint64_t va_bits = CONFIG_ARM64_VA_BITS; + uint64_t tcr_ps_bits; + + tcr_ps_bits = TCR_PS_BITS; + + if (el == 1) { + tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT); + /* + * TCR_EL1.EPD1: Disable translation table walk for addresses + * that are translated using TTBR1_EL1. + */ + tcr |= TCR_EPD1_DISABLE; + } else + tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT); + + tcr |= TCR_T0SZ(va_bits); + /* + * Translation table walk is cacheable, inner/outer WBWA + */ + tcr |= TCR_TG0_4K | TCR_ORGN_WBWA | TCR_IRGN_WBWA; + + return tcr; +} + +static void enable_mmu_el1(struct ARM_MMU_ptables *ptables, unsigned int flags) +{ + ARG_UNUSED(flags); + uint64_t val; + + /* Set MAIR, TCR and TBBR registers */ + __MSR(MAIR_EL1, MEMORY_ATTRIBUTES); + __MSR(TCR_EL1, get_tcr(1)); + __MSR(TTBR0_EL1, (uint64_t)ptables->base_xlat_table); + + /* Ensure these changes are seen before MMU is enabled */ + __ISB(); + + /* Enable the MMU and caches */ + __MRS(SCTLR_EL1, &val); + __MSR(SCTLR_EL1, val | SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT); + + /* Ensure the MMU enable takes effect immediately */ + __ISB(); + + MMU_DEBUG("MMU enabled with caches\r\n"); +} + +/* ARM MMU Driver Initial Setup */ + +static struct ARM_MMU_ptables kernel_ptables; + +/* + * @brief MMU default configuration + * + * This function provides the default configuration mechanism for the Memory + * Management Unit (MMU). + */ +void ARM_MMU_Initialize(const struct ARM_MMU_config *MMU_config, + bool is_primary_core) +{ + unsigned int flags = 0; + uint64_t val; + + __ASSERT(CONFIG_MMU_PAGE_SIZE == KB(4), + "Only 4K page size is supported\r\n"); + + __MRS(CURRENTEL, &val); + __ASSERT(GET_EL(val) == MODE_EL1, + "Exception level not EL1, MMU not enabled!\r\n"); + + /* Ensure that MMU is already not enabled */ + __MRS(SCTLR_EL1, &val); + __ASSERT((val & SCTLR_M_BIT) == 0, "MMU is already enabled\r\n"); + + /* + * Only booting core setup up the page tables. + */ + if (is_primary_core) { + kernel_ptables.base_xlat_table = new_table(); + setup_page_tables(MMU_config, &kernel_ptables); + } + + /* currently only EL1 is supported */ + enable_mmu_el1(&kernel_ptables, flags); +} + +/* + * @brief MMU mapping setup + * + * This function sets a new MMU region mapping + */ +int ARM_MMU_AddMap(const char *name, uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs) +{ + int ret = -1; + + if ((virt + size) > (1ULL << CONFIG_ARM64_VA_BITS)) + goto exit; + + if ((phys + size) > (1ULL << CONFIG_ARM64_PA_BITS)) + goto exit; + + if (size) { + ret = add_map(&kernel_ptables, name, phys, virt, size, attrs); + + ARM_MMU_InvalidateTLB(); + } + +exit: + return ret; +} + +/* + * @brief MMU TLB invalidation + * + * This function invalidates the entire unified TLB + */ +void ARM_MMU_InvalidateTLB(void) +{ + __DSB(); + __ASM volatile("tlbi vmalle1"); + __DSB(); + __ISB(); +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.c b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.c new file mode 100644 index 00000000000..3e8ee8ce918 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + * 2025-10-08 Siwei Xu Fix MMU Enable issues + */ + +#include "MIMX9131.h" + +CCM_Type* CCM_CTRL = (CCM_Type *)CCM_CTRL_BASE; + +LPUART_Type* LPUART1 = (LPUART_Type *)LPUART1_BASE; +LPUART_Type* LPUART2 = (LPUART_Type *)LPUART2_BASE; +LPUART_Type* LPUART3 = (LPUART_Type *)LPUART3_BASE; +LPUART_Type* LPUART4 = (LPUART_Type *)LPUART4_BASE; +LPUART_Type* LPUART5 = (LPUART_Type *)LPUART5_BASE; +LPUART_Type* LPUART6 = (LPUART_Type *)LPUART6_BASE; +LPUART_Type* LPUART7 = (LPUART_Type *)LPUART7_BASE; +LPUART_Type* LPUART8 = (LPUART_Type *)LPUART8_BASE; diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.h new file mode 100644 index 00000000000..d9632dd7f53 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.h @@ -0,0 +1,138365 @@ +/* +** ################################################################### +** Processors: MIMX9131CVVXJ +** MIMX9131DVVXJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** +** Reference manual: IMX91RM Rev.1 +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** CMSIS Peripheral Access Layer for MIMX9131 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMX9131.h + * @version 1.0 + * @date 2024-11-15 + * @brief CMSIS Peripheral Access Layer for MIMX9131 + * + * CMSIS Peripheral Access Layer for MIMX9131 + */ + +#if !defined(MIMX9131_H_) +#define MIMX9131_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 300 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + Software0_IRQn = 0, /**< Cortex-A55 Software Generated Interrupt 0 */ + Software1_IRQn = 1, /**< Cortex-A55 Software Generated Interrupt 1 */ + Software2_IRQn = 2, /**< Cortex-A55 Software Generated Interrupt 2 */ + Software3_IRQn = 3, /**< Cortex-A55 Software Generated Interrupt 3 */ + Software4_IRQn = 4, /**< Cortex-A55 Software Generated Interrupt 4 */ + Software5_IRQn = 5, /**< Cortex-A55 Software Generated Interrupt 5 */ + Software6_IRQn = 6, /**< Cortex-A55 Software Generated Interrupt 6 */ + Software7_IRQn = 7, /**< Cortex-A55 Software Generated Interrupt 7 */ + Software8_IRQn = 8, /**< Cortex-A55 Software Generated Interrupt 8 */ + Software9_IRQn = 9, /**< Cortex-A55 Software Generated Interrupt 9 */ + Software10_IRQn = 10, /**< Cortex-A55 Software Generated Interrupt 10 */ + Software11_IRQn = 11, /**< Cortex-A55 Software Generated Interrupt 11 */ + Software12_IRQn = 12, /**< Cortex-A55 Software Generated Interrupt 12 */ + Software13_IRQn = 13, /**< Cortex-A55 Software Generated Interrupt 13 */ + Software14_IRQn = 14, /**< Cortex-A55 Software Generated Interrupt 14 */ + Software15_IRQn = 15, /**< Cortex-A55 Software Generated Interrupt 15 */ + VirtualMaintenance_IRQn = 25, /**< Cortex-A55 Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /**< Cortex-A55 Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /**< Cortex-A55 Virtual Timer Interrupt */ + LegacyFastInt_IRQn = 28, /**< Cortex-A55 Legacy nFIQ signal Interrupt */ + SecurePhyTimer_IRQn = 29, /**< Cortex-A55 Secure Physical Timer Interrupt */ + NonSecurePhyTimer_IRQn = 30, /**< Cortex-A55 Non-secure Physical Timer Interrupt */ + LegacyIRQ_IRQn = 31, /**< Cortex-A55 Legacy nIRQ Interrupt */ + + /* Device specific interrupts */ + Reserved32_IRQn = 32, /**< Reserved interrupt */ + DAP_IRQn = 33, /**< DAP interrupt */ + Reserved34_IRQn = 34, /**< Reserved interrupt */ + Reserved35_IRQn = 35, /**< Reserved interrupt */ + CTI_CA55_IRQn = 36, /**< CTI trigger outputs from CA55 platform */ + PMU_IRQn = 37, /**< Performance Unit Interrupts from CA55 platform */ + CACHE_ECC_ERR_IRQn = 38, /**< ECC error from CA55 platform cache */ + CACHE_ECC_PARITY_ERR_IRQn = 39, /**< 1-bit or 2-bit ECC or Parity error from CA55 platform cache */ + CAN1_IRQn = 40, /**< CAN1 interrupt */ + CAN1_ERROR_IRQn = 41, /**< CAN1 error interrupt */ + GPIO1_0_IRQn = 42, /**< General Purpose Input/Output 1 interrupt 0 */ + GPIO1_1_IRQn = 43, /**< General Purpose Input/Output 1 interrupt 1 */ + I3C1_IRQn = 44, /**< Improved Inter-Integrated Circuit 1 interrupt */ + LPI2C1_IRQn = 45, /**< Low Power Inter-Integrated Circuit module 1 */ + LPI2C2_IRQn = 46, /**< Low Power Inter-Integrated Circuit module 2 */ + LPIT1_IRQn = 47, /**< Low Power Periodic Interrupt Timer 1 */ + LPSPI1_IRQn = 48, /**< Low Power Serial Peripheral Interface 1 */ + LPSPI2_IRQn = 49, /**< Low Power Serial Peripheral Interface 2 */ + LPTMR1_IRQn = 50, /**< Low Power Timer 1 */ + LPUART1_IRQn = 51, /**< Low Power UART 1 */ + LPUART2_IRQn = 52, /**< Low Power UART 2 */ + Reserved53_IRQn = 53, /**< Reserved interrupt */ + Reserved54_IRQn = 54, /**< Reserved interrupt */ + Reserved55_IRQn = 55, /**< Reserved interrupt */ + Reserved56_IRQn = 56, /**< Reserved interrupt */ + Reserved57_IRQn = 57, /**< Reserved interrupt */ + Reserved58_IRQn = 58, /**< Reserved interrupt */ + Reserved59_IRQn = 59, /**< Reserved interrupt */ + EDGELOCK_TRUST_MUA_RX_IRQn = 60, /**< Edgelock Trust MUA RX full interrupt */ + EDGELOCK_TRUST_MUA_TX_IRQn = 61, /**< Edgelock Trust MUA TX empty interrupt */ + EDGELOCK_APP_MUA_RX_IRQn = 62, /**< Edgelock Apps Core MUA RX full interrupt */ + EDGELOCK_APP_MUA_TX_IRQn = 63, /**< Edgelock Apps Core MUA TX empty interrupt */ + EDGELOCK_RT_MUA_RX_IRQn = 64, /**< Edgelock Realtime Core MUA RX full interrupt */ + EDGELOCK_RT_MUA_TX_IRQn = 65, /**< Edgelock Realtime Core MUA TX empty interrupt */ + EDGELOCK_SECURE_IRQn = 66, /**< Edgelock secure interrupt */ + EDGELOCK_NONSECURE_IRQn = 67, /**< Edgelock non-secure interrupt */ + TPM1_IRQn = 68, /**< Timer PWM module 1 */ + TPM2_IRQn = 69, /**< Timer PWM module 2 */ + WDOG1_IRQn = 70, /**< Watchdog 1 Interrupt */ + WDOG2_IRQn = 71, /**< Watchdog 2 Interrupt */ + TRDC_IRQn = 72, /**< AONMIX TRDC transfer error interrupt */ + Reserved73_IRQn = 73, /**< Reserved interrupt */ + Reserved74_IRQn = 74, /**< Reserved interrupt */ + Reserved75_IRQn = 75, /**< Reserved interrupt */ + Reserved76_IRQn = 76, /**< Reserved interrupt */ + SAI1_IRQn = 77, /**< Serial Audio Interface 1 */ + Reserved78_IRQn = 78, /**< Reserved interrupt */ + Reserved79_IRQn = 79, /**< Reserved interrupt */ + Reserved80_IRQn = 80, /**< Reserved interrupt */ + Reserved81_IRQn = 81, /**< Reserved interrupt */ + Reserved82_IRQn = 82, /**< Reserved interrupt */ + CAN2_IRQn = 83, /**< CAN2 interrupt */ + CAN2_ERROR_IRQn = 84, /**< CAN2 error interrupt */ + Reserved85_IRQn = 85, /**< Reserved interrupt */ + Reserved86_IRQn = 86, /**< Reserved interrupt */ + FlexSPI1_IRQn = 87, /**< FlexSPI controller interface interrupt 1 */ + Reserved88_IRQn = 88, /**< Reserved interrupt */ + GPIO2_0_IRQn = 89, /**< General Purpose Input/Output 2 interrupt 0 */ + GPIO2_1_IRQn = 90, /**< General Purpose Input/Output 2 interrupt 1 */ + GPIO3_0_IRQn = 91, /**< General Purpose Input/Output 3 interrupt 0 */ + GPIO3_1_IRQn = 92, /**< General Purpose Input/Output 3 interrupt 1 */ + I3C2_IRQn = 93, /**< Improved Inter-Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 94, /**< Low Power Inter-Integrated Circuit module 3 */ + LPI2C4_IRQn = 95, /**< Low Power Inter-Integrated Circuit module 4 */ + LPIT2_IRQn = 96, /**< Low Power Periodic Interrupt Timer 2 */ + LPSPI3_IRQn = 97, /**< Low Power Serial Peripheral Interface 3 */ + LPSPI4_IRQn = 98, /**< Low Power Serial Peripheral Interface 4 */ + LPTMR2_IRQn = 99, /**< Low Power Timer 2 */ + LPUART3_IRQn = 100, /**< Low Power UART 3 */ + LPUART4_IRQn = 101, /**< Low Power UART 4 */ + LPUART5_IRQn = 102, /**< Low Power UART 5 */ + LPUART6_IRQn = 103, /**< Low Power UART 6 */ + MTR_MASTER_ERR_IRQn = 104, /**< MTR Master error interrupt */ + BBNSM_NONSECURE_IRQn = 105, /**< BBNSM Non-Secure interrupt */ + SYS_CTR_COMPARE_IRQn = 106, /**< System Counter compare interrupt */ + TPM3_IRQn = 107, /**< Timer PWM module 3 */ + TPM4_IRQn = 108, /**< Timer PWM module 4 */ + TPM5_IRQn = 109, /**< Timer PWM module 5 */ + TPM6_IRQn = 110, /**< Timer PWM module 6 */ + WDOG3_IRQn = 111, /**< Watchdog 3 Interrupt */ + WDOG4_IRQn = 112, /**< Watchdog 4 Interrupt */ + WDOG5_IRQn = 113, /**< Watchdog 5 Interrupt */ + TRDC_WAKEUPMIX_ERR_IRQn = 114, /**< WAKEUPMIX TRDC transfer error interrupt */ + TEMPMON_IRQn = 115, /**< TempSensor interrupt */ + Reserved116_IRQn = 116, /**< Reserved interrupt */ + Reserved117_IRQn = 117, /**< Reserved interrupt */ + uSDHC1_IRQn = 118, /**< ultra Secure Digital Host Controller interrupt 1 */ + uSDHC2_IRQn = 119, /**< ultra Secure Digital Host Controller interrupt 2 */ + TRDC_MEGAMIX_ERR_IRQn = 120, /**< MEGAMIX TRDC transfer error interrupt */ + TRDC_NIC_WRAPPER_ERR_IRQn = 121, /**< NIC_WRAPPER TRDC transfer error interrupt */ + DRAM_PERFMON_IRQn = 122, /**< DRAM controller Performance Monitor Interrupt */ + DRAM_CRITICAL_IRQn = 123, /**< DRAM controller Critical Interrupt */ + DRAM_PHY_CRITICAL_IRQn = 124, /**< DRAM Phy Critical Interrupt */ + Reserved125_IRQn = 125, /**< Reserved interrupt */ + DMA3_ERROR_IRQn = 126, /**< eDMA1 error interrupt */ + DMA3_0_IRQn = 127, /**< eDMA1 channel 0 interrupt */ + DMA3_1_IRQn = 128, /**< eDMA1 channel 1 interrupt */ + DMA3_2_IRQn = 129, /**< eDMA1 channel 2 interrupt */ + DMA3_3_IRQn = 130, /**< eDMA1 channel 3 interrupt */ + DMA3_4_IRQn = 131, /**< eDMA1 channel 4 interrupt */ + DMA3_5_IRQn = 132, /**< eDMA1 channel 5 interrupt */ + DMA3_6_IRQn = 133, /**< eDMA1 channel 6 interrupt */ + DMA3_7_IRQn = 134, /**< eDMA1 channel 7 interrupt */ + DMA3_8_IRQn = 135, /**< eDMA1 channel 8 interrupt */ + DMA3_9_IRQn = 136, /**< eDMA1 channel 9 interrupt */ + DMA3_10_IRQn = 137, /**< eDMA1 channel 10 interrupt */ + DMA3_11_IRQn = 138, /**< eDMA1 channel 11 interrupt */ + DMA3_12_IRQn = 139, /**< eDMA1 channel 12 interrupt */ + DMA3_13_IRQn = 140, /**< eDMA1 channel 13 interrupt */ + DMA3_14_IRQn = 141, /**< eDMA1 channel 14 interrupt */ + DMA3_15_IRQn = 142, /**< eDMA1 channel 15 interrupt */ + DMA3_16_IRQn = 143, /**< eDMA1 channel 16 interrupt */ + DMA3_17_IRQn = 144, /**< eDMA1 channel 17 interrupt */ + DMA3_18_IRQn = 145, /**< eDMA1 channel 18 interrupt */ + DMA3_19_IRQn = 146, /**< eDMA1 channel 19 interrupt */ + DMA3_20_IRQn = 147, /**< eDMA1 channel 20 interrupt */ + DMA3_21_IRQn = 148, /**< eDMA1 channel 21 interrupt */ + DMA3_22_IRQn = 149, /**< eDMA1 channel 22 interrupt */ + DMA3_23_IRQn = 150, /**< eDMA1 channel 23 interrupt */ + DMA3_24_IRQn = 151, /**< eDMA1 channel 24 interrupt */ + DMA3_25_IRQn = 152, /**< eDMA1 channel 25 interrupt */ + DMA3_26_IRQn = 153, /**< eDMA1 channel 26 interrupt */ + DMA3_27_IRQn = 154, /**< eDMA1 channel 27 interrupt */ + DMA3_28_IRQn = 155, /**< eDMA1 channel 28 interrupt */ + DMA3_29_IRQn = 156, /**< eDMA1 channel 29 interrupt */ + DMA3_30_IRQn = 157, /**< eDMA1 channel 30 interrupt */ + Reserved158_IRQn = 158, /**< Reserved interrupt */ + DMA4_ERROR_IRQn = 159, /**< eDMA2 error interrupt */ + DMA4_0_1_IRQn = 160, /**< eDMA2 channel 0/1 interrupt */ + DMA4_2_3_IRQn = 161, /**< eDMA2 channel 2/3 interrupt */ + DMA4_4_5_IRQn = 162, /**< eDMA2 channel 4/5 interrupt */ + DMA4_6_7_IRQn = 163, /**< eDMA2 channel 6/7 interrupt */ + DMA4_8_9_IRQn = 164, /**< eDMA2 channel 8/9 interrupt */ + DMA4_10_11_IRQn = 165, /**< eDMA2 channel 10/11 interrupt */ + DMA4_12_13_IRQn = 166, /**< eDMA2 channel 12/13 interrupt */ + DMA4_14_15_IRQn = 167, /**< eDMA2 channel 14/15 interrupt */ + DMA4_16_17_IRQn = 168, /**< eDMA2 channel 16/17 interrupt */ + DMA4_18_19_IRQn = 169, /**< eDMA2 channel 18/19 interrupt */ + DMA4_20_21_IRQn = 170, /**< eDMA2 channel 20/21 interrupt */ + DMA4_22_23_IRQn = 171, /**< eDMA2 channel 22/23 interrupt */ + DMA4_24_25_IRQn = 172, /**< eDMA2 channel 24/25 interrupt */ + DMA4_26_27_IRQn = 173, /**< eDMA2 channel 26/27 interrupt */ + DMA4_28_29_IRQn = 174, /**< eDMA2 channel 28/29 interrupt */ + DMA4_30_31_IRQn = 175, /**< eDMA2 channel 30/31 interrupt */ + DMA4_32_33_IRQn = 176, /**< eDMA2 channel 32/33 interrupt */ + DMA4_34_35_IRQn = 177, /**< eDMA2 channel 34/35 interrupt */ + DMA4_36_37_IRQn = 178, /**< eDMA2 channel 36/37 interrupt */ + DMA4_38_39_IRQn = 179, /**< eDMA2 channel 38/39 interrupt */ + DMA4_40_41_IRQn = 180, /**< eDMA2 channel 40/41 interrupt */ + DMA4_42_43_IRQn = 181, /**< eDMA2 channel 42/43 interrupt */ + DMA4_44_45_IRQn = 182, /**< eDMA2 channel 44/45 interrupt */ + DMA4_46_47_IRQn = 183, /**< eDMA2 channel 46/47 interrupt */ + DMA4_48_49_IRQn = 184, /**< eDMA2 channel 48/49 interrupt */ + DMA4_50_51_IRQn = 185, /**< eDMA2 channel 50/51 interrupt */ + DMA4_52_53_IRQn = 186, /**< eDMA2 channel 52/53 interrupt */ + DMA4_54_55_IRQn = 187, /**< eDMA2 channel 54/55 interrupt */ + DMA4_56_57_IRQn = 188, /**< eDMA2 channel 56/57 interrupt */ + DMA4_58_59_IRQn = 189, /**< eDMA2 channel 58/59 interrupt */ + DMA4_60_61_IRQn = 190, /**< eDMA2 channel 60/61 interrupt */ + DMA4_62_63_IRQn = 191, /**< eDMA2 channel 62/63 interrupt */ + DEBUG_WAKEUP_IRQn = 192, /**< Debug Wakeup Interrupt */ + EDGELOCK_GROUP1_RST_SRC_IRQn = 193, /**< Edgelock Group 1 reset source */ + EDGELOCK_GROUP2_RST_SRC_0_IRQn = 194, /**< Edgelock Group 2 reset source */ + EDGELOCK_GROUP2_RST_SRC_1_IRQn = 195, /**< Edgelock Group 2 reset source */ + DBG_TRACE_RST_SRC_IRQn = 196, /**< JTAGSW DAP MDM-AP SRC reset source */ + JTAGC_RST_SRC_IRQn = 197, /**< JTAGC SRC reset source */ + Reserved198_IRQn = 198, /**< Reserved interrupt */ + Reserved199_IRQn = 199, /**< Reserved interrupt */ + Reserved200_IRQn = 200, /**< Reserved interrupt */ + Reserved201_IRQn = 201, /**< Reserved interrupt */ + SAI2_IRQn = 202, /**< Serial Audio Interface 2 */ + SAI3_IRQn = 203, /**< Serial Audio Interface 3 */ + ISI_IRQn = 204, /**< ISI interrupt */ + Reserved205_IRQn = 205, /**< Reserved interrupt */ + Reserved206_IRQn = 206, /**< Reserved interrupt */ + Reserved207_IRQn = 207, /**< Reserved interrupt */ + LCDIFv3_IRQn = 208, /**< LCDIF Sync Interrupt */ + Reserved209_IRQn = 209, /**< Reserved interrupt */ + Reserved210_IRQn = 210, /**< Reserved interrupt */ + ENET_MAC0_Rx_Tx_Done1_IRQn = 211, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET_MAC0_Rx_Tx_Done2_IRQn = 212, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET_IRQn = 213, /**< MAC 0 IRQ */ + ENET_1588_IRQn = 214, /**< MAC 0 1588 Timer Interrupt - synchronous */ + ENET_QOS_PMT_IRQn = 215, /**< ENET QOS PMT interrupt */ + ENET_QOS_IRQn = 216, /**< ENET QOS interrupt */ + Reserved217_IRQn = 217, /**< Reserved interrupt */ + Reserved218_IRQn = 218, /**< Reserved interrupt */ + USB1_WAKEUP_IRQn = 219, /**< USB-1 Wake-up Interrupt */ + USB2_WAKEUP_IRQn = 220, /**< USB-2 Wake-up Interrupt */ + GPIO4_0_IRQn = 221, /**< General Purpose Input/Output 4 interrupt 0 */ + GPIO4_1_IRQn = 222, /**< General Purpose Input/Output 4 interrupt 1 */ + LPSPI5_IRQn = 223, /**< Low Power Serial Peripheral Interface 5 */ + LPSPI6_IRQn = 224, /**< Low Power Serial Peripheral Interface 6 */ + LPSPI7_IRQn = 225, /**< Low Power Serial Peripheral Interface 7 */ + LPSPI8_IRQn = 226, /**< Low Power Serial Peripheral Interface 8 */ + LPI2C5_IRQn = 227, /**< Low Power Inter-Integrated Circuit module 5 */ + LPI2C6_IRQn = 228, /**< Low Power Inter-Integrated Circuit module 6 */ + LPI2C7_IRQn = 229, /**< Low Power Inter-Integrated Circuit module 7 */ + LPI2C8_IRQn = 230, /**< Low Power Inter-Integrated Circuit module 8 */ + PDM_HWVAD_ERROR_IRQn = 231, /**< PDM interrupt */ + PDM_HWVAD_EVENT_IRQn = 232, /**< PDM interrupt */ + PDM_ERROR_IRQn = 233, /**< PDM interrupt */ + PDM_EVENT_IRQn = 234, /**< PDM interrupt */ + AUDIO_XCVR_0_IRQn = 235, /**< AUDIO XCVR interrupt */ + AUDIO_XCVR_1_IRQn = 236, /**< AUDIO XCVR interrupt */ + uSDHC3_IRQn = 237, /**< ultra Secure Digital Host Controller interrupt 3 */ + OCRAM_MECC_0_IRQn = 238, /**< OCRAM MECC interrupt */ + OCRAM_MECC_1_IRQn = 239, /**< OCRAM MECC interrupt */ + TRDC_HSIOMIX_ERR_IRQn = 240, /**< HSIOMIX TRDC transfer error interrupt */ + TRDC_MEDIAMIX_ERR_IRQn = 241, /**< MEDIAMIX TRDC transfer error interrupt */ + LPUART7_IRQn = 242, /**< Low Power UART 7 */ + LPUART8_IRQn = 243, /**< Low Power UART 8 */ + Reserved244_IRQn = 244, /**< Reserved interrupt */ + SFA_IRQn = 245, /**< SFA interrupt */ + GIC600_0_IRQn = 246, /**< GIC600 INTERRUPT */ + GIC600_1_IRQn = 247, /**< GIC600 INTERRUPT */ + GIC600_2_IRQn = 248, /**< GIC600 INTERRUPT */ + ADC_ER_IRQn = 249, /**< ADC interrupt */ + ADC_WD_IRQn = 250, /**< ADC interrupt */ + ADC_EOC_IRQn = 251, /**< ADC interrupt */ + Reserved252_IRQn = 252, /**< Reserved interrupt */ + I3C1_WAKEUP_IRQn = 253, /**< I3C1 wakeup irq after double sync */ + I3C2_WAKEUP_IRQn = 254, /**< I3C2 wakeup irq after double sync */ + Reserved255_IRQn = 255, /**< Reserved interrupt */ + Reserved256_IRQn = 256, /**< Reserved interrupt */ + Reserved257_IRQn = 257, /**< Reserved interrupt */ + Reserved258_IRQn = 258, /**< Reserved interrupt */ + Reserved259_IRQn = 259, /**< Reserved interrupt */ + Reserved260_IRQn = 260, /**< Reserved interrupt */ + Reserved261_IRQn = 261, /**< Reserved interrupt */ + Reserved262_IRQn = 262, /**< Reserved interrupt */ + Reserved263_IRQn = 263, /**< Reserved interrupt */ + Reserved264_IRQn = 264, /**< Reserved interrupt */ + Reserved265_IRQn = 265, /**< Reserved interrupt */ + Reserved266_IRQn = 266, /**< Reserved interrupt */ + Reserved267_IRQn = 267, /**< Reserved interrupt */ + Reserved268_IRQn = 268, /**< Reserved interrupt */ + Reserved269_IRQn = 269, /**< Reserved interrupt */ + Reserved270_IRQn = 270, /**< Reserved interrupt */ + Reserved271_IRQn = 271, /**< Reserved interrupt */ + Reserved272_IRQn = 272, /**< Reserved interrupt */ + Reserved273_IRQn = 273, /**< Reserved interrupt */ + Reserved274_IRQn = 274, /**< Reserved interrupt */ + Reserved275_IRQn = 275, /**< Reserved interrupt */ + Reserved276_IRQn = 276, /**< Reserved interrupt */ + Reserved277_IRQn = 277, /**< Reserved interrupt */ + Reserved278_IRQn = 278, /**< Reserved interrupt */ + Reserved279_IRQn = 279, /**< Reserved interrupt */ + Reserved280_IRQn = 280, /**< Reserved interrupt */ + Reserved281_IRQn = 281, /**< Reserved interrupt */ + Reserved282_IRQn = 282, /**< Reserved interrupt */ + Reserved283_IRQn = 283, /**< Reserved interrupt */ + Reserved284_IRQn = 284, /**< Reserved interrupt */ + Reserved285_IRQn = 285, /**< Reserved interrupt */ + Reserved286_IRQn = 286, /**< Reserved interrupt */ + Reserved287_IRQn = 287, /**< Reserved interrupt */ + Reserved288_IRQn = 288, /**< Reserved interrupt */ + Reserved289_IRQn = 289, /**< Reserved interrupt */ + Reserved290_IRQn = 290, /**< Reserved interrupt */ + Reserved291_IRQn = 291, /**< Reserved interrupt */ + Reserved292_IRQn = 292, /**< Reserved interrupt */ + Reserved293_IRQn = 293, /**< Reserved interrupt */ + Reserved294_IRQn = 294, /**< Reserved interrupt */ + Reserved295_IRQn = 295, /**< Reserved interrupt */ + Reserved296_IRQn = 296, /**< Reserved interrupt */ + Reserved297_IRQn = 297, /**< Reserved interrupt */ + Reserved298_IRQn = 298, /**< Reserved interrupt */ + Reserved299_IRQn = 299 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex A55 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex A55 Core Configuration + * @{ + */ + +#define __CA55_REV 0x0000 /**< Core revision r2p0 */ +#define __GIC_PRIO_BITS 4 /**< Number of priority bits implemented in the GIC */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __FPU_USED 1 /**< Indicates whether an FPU is used or not */ +#define __MMU_PRESENT 1 /**< MMU present or not */ +#define __TIM_PRESENT 1 /**< TIM present or not */ +#define __CACHE_PRESENT 1 /**< CACHE present or not */ +#define __GIC_PRESENT 1 /**< GIC present or not */ +#define GIC_DISTRIBUTOR_BASE 0x48000000 /**< GIC distributor base address */ +#define GIC_REDISTRIBUTOR_BASE 0x48040000 /**< GIC CPU redistributor base address */ + +#include "core_ca55.h" /* Core Peripheral Access Layer */ +#include "system_MIMX9131.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA3 hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma3_request_source +{ + kDma3RequestMuxCAN1 = 1U, /**< CAN1 */ + kDma3RequestMuxGPIO1Request0 = 3U, /**< GPIO1 channel 0 */ + kDma3RequestMuxGPIO1Request1 = 4U, /**< GPIO1 channel 1 */ + kDma3RequestMuxI3C1ToBusRequest = 5U, /**< I3C1 To-bus Request */ + kDma3RequestMuxI3C1FromBusRequest = 6U, /**< I3C1 From-bus Request */ + kDma3RequestMuxLPI2C1Tx = 7U, /**< LPI2C1 */ + kDma3RequestMuxLPI2C1Rx = 8U, /**< LPI2C1 */ + kDma3RequestMuxLPI2C2Tx = 9U, /**< LPI2C2 */ + kDma3RequestMuxLPI2C2Rx = 10U, /**< LPI2C2 */ + kDma3RequestMuxLPSPI1Tx = 11U, /**< LPSPI1 Transmit */ + kDma3RequestMuxLPSPI1Rx = 12U, /**< LPSPI1 Receive */ + kDma3RequestMuxLPSPI2Tx = 13U, /**< LPSPI2 Transmit */ + kDma3RequestMuxLPSPI2Rx = 14U, /**< LPSPI2 Receive */ + kDma3RequestMuxLPTMR1Request = 15U, /**< LPTMR1 Request */ + kDma3RequestMuxLPUART1Tx = 16U, /**< LPUART1 Transmit */ + kDma3RequestMuxLPUART1Rx = 17U, /**< LPUART1 Receive */ + kDma3RequestMuxLPUART2Tx = 18U, /**< LPUART2 Transmit */ + kDma3RequestMuxLPUART2Rx = 19U, /**< LPUART2 Receive */ + kDma3RequestMuxEdgelockRequest = 20U, /**< Edgelock enclave DMA Request */ + kDma3RequestMuxSai1Tx = 21U, /**< SAI1 Transmit */ + kDma3RequestMuxSai1Rx = 22U, /**< SAI1 Receive */ + kDma3RequestMuxTPM1Request0Request2 = 23U, /**< TPM1 request 0 and request 2 */ + kDma3RequestMuxTPM1Request1Request3 = 24U, /**< TPM1 request 1 and request 3 */ + kDma3RequestMuxTPM1OverflowRequest = 25U, /**< TPM1 Overflow request */ + kDma3RequestMuxTPM2Request0Request2 = 26U, /**< TPM2 request 0 and request 2 */ + kDma3RequestMuxTPM2Request1Request3 = 27U, /**< TPM2 request 1 and request 3 */ + kDma3RequestMuxTPM2OverflowRequest = 28U, /**< TPM2 Overflow request */ + kDma3RequestMuxPDMRequest = 29U, /**< PDM */ + kDma3RequestMuxADC1Request = 30U, /**< ADC1 */ +} dma3_request_source_t; + +/* @} */ + +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA4 hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma4_request_source +{ + kDma4RequestMuxCAN2 = 1U, /**< CAN2 */ + kDma4RequestMuxGPIO2Request0 = 2U, /**< GPIO2 channel 0 */ + kDma4RequestMuxGPIO2Request1 = 3U, /**< GPIO2 channel 1 */ + kDma4RequestMuxGPIO3Request0 = 4U, /**< GPIO3 channel 0 */ + kDma4RequestMuxGPIO3Request1 = 5U, /**< GPIO3 channel 1 */ + kDma4RequestMuxI3C2ToBusRequest = 6U, /**< I3C2 To-bus Request */ + kDma4RequestMuxI3C2FromBusRequest = 7U, /**< I3C2 From-bus Request */ + kDma4RequestMuxLPI2C3Tx = 8U, /**< LPI2C3 */ + kDma4RequestMuxLPI2C3Rx = 9U, /**< LPI2C3 */ + kDma4RequestMuxLPI2C4Tx = 10U, /**< LPI2C4 */ + kDma4RequestMuxLPI2C4Rx = 11U, /**< LPI2C4 */ + kDma4RequestMuxLPSPI3Tx = 12U, /**< LPSPI3 Transmit */ + kDma4RequestMuxLPSPI3Rx = 13U, /**< LPSPI3 Receive */ + kDma4RequestMuxLPSPI4Tx = 14U, /**< LPSPI4 Transmit */ + kDma4RequestMuxLPSPI4Rx = 15U, /**< LPSPI4 Receive */ + kDma4RequestMuxLPTMR2Request = 16U, /**< LPTMR2 Request */ + kDma4RequestMuxLPUART3Tx = 17U, /**< LPUART3 Transmit */ + kDma4RequestMuxLPUART3Rx = 18U, /**< LPUART3 Receive */ + kDma4RequestMuxLPUART4Tx = 19U, /**< LPUART4 Transmit */ + kDma4RequestMuxLPUART4Rx = 20U, /**< LPUART4 Receive */ + kDma4RequestMuxLPUART5Tx = 21U, /**< LPUART5 Transmit */ + kDma4RequestMuxLPUART5Rx = 22U, /**< LPUART5 Receive */ + kDma4RequestMuxLPUART6Tx = 23U, /**< LPUART6 Transmit */ + kDma4RequestMuxLPUART6Rx = 24U, /**< LPUART6 Receive */ + kDma4RequestMuxTPM3Request0Request2 = 25U, /**< TPM3 request 0 and request 2 */ + kDma4RequestMuxTPM3Request1Request3 = 26U, /**< TPM3 request 1 and request 3 */ + kDma4RequestMuxTPM3OverflowRequest = 27U, /**< TPM3 Overflow request */ + kDma4RequestMuxTPM4Request0Request2 = 28U, /**< TPM4 request 0 and request 2 */ + kDma4RequestMuxTPM4Request1Request3 = 29U, /**< TPM4 request 1 and request 3 */ + kDma4RequestMuxTPM4OverflowRequest = 30U, /**< TPM4 Overflow request */ + kDma4RequestMuxTPM5Request0Request2 = 31U, /**< TPM5 request 0 and request 2 */ + kDma4RequestMuxTPM5Request1Request3 = 32U, /**< TPM5 request 1 and request 3 */ + kDma4RequestMuxTPM5OverflowRequest = 33U, /**< TPM5 Overflow request */ + kDma4RequestMuxTPM6Request0Request2 = 34U, /**< TPM6 request 0 and request 2 */ + kDma4RequestMuxTPM6Request1Request3 = 35U, /**< TPM6 request 1 and request 3 */ + kDma4RequestMuxTPM6OverflowRequest = 36U, /**< TPM6 Overflow request */ + kDma4RequestMuxFlexIO1Request0 = 37U, /**< FlexIO1 Request0 */ + kDma4RequestMuxFlexIO1Request1 = 38U, /**< FlexIO1 Request1 */ + kDma4RequestMuxFlexIO1Request2 = 39U, /**< FlexIO1 Request2 */ + kDma4RequestMuxFlexIO1Request3 = 40U, /**< FlexIO1 Request3 */ + kDma4RequestMuxFlexIO1Request4 = 41U, /**< FlexIO1 Request4 */ + kDma4RequestMuxFlexIO1Request5 = 42U, /**< FlexIO1 Request5 */ + kDma4RequestMuxFlexIO1Request6 = 43U, /**< FlexIO1 Request6 */ + kDma4RequestMuxFlexIO1Request7 = 44U, /**< FlexIO1 Request7 */ + kDma4RequestMuxFlexIO2Request0 = 45U, /**< FlexIO2 Request0 */ + kDma4RequestMuxFlexIO2Request1 = 46U, /**< FlexIO2 Request1 */ + kDma4RequestMuxFlexIO2Request2 = 47U, /**< FlexIO2 Request2 */ + kDma4RequestMuxFlexIO2Request3 = 48U, /**< FlexIO2 Request3 */ + kDma4RequestMuxFlexIO2Request4 = 49U, /**< FlexIO2 Request4 */ + kDma4RequestMuxFlexIO2Request5 = 50U, /**< FlexIO2 Request5 */ + kDma4RequestMuxFlexIO2Request6 = 51U, /**< FlexIO2 Request6 */ + kDma4RequestMuxFlexIO2Request7 = 52U, /**< FlexIO2 Request7 */ + kDma4RequestMuxFlexSPI1Tx = 53U, /**< FlexSPI1 Transmit */ + kDma4RequestMuxFlexSPI1Rx = 54U, /**< FlexSPI1 Receive */ + kDma4RequestMuxSai2Tx = 58U, /**< SAI2 Transmit */ + kDma4RequestMuxSai2Rx = 59U, /**< SAI2 Receive */ + kDma4RequestMuxSai3Tx = 60U, /**< SAI3 Transmit */ + kDma4RequestMuxSai3Rx = 61U, /**< SAI3 Receive */ + kDma4RequestMuxGPIO4Request0 = 62U, /**< GPIO4 channel 0 */ + kDma4RequestMuxGPIO4Request1 = 63U, /**< GPIO4 channel 1 */ + kDma4RequestMuxSPDIFRequest = 65U, /**< SPDIF */ + kDma4RequestMuxSPDIFRequest1 = 66U, /**< SPDIF */ + kDma4RequestMuxENETRequest = 67U, /**< ENET */ + kDma4RequestMuxENETRequest1 = 68U, /**< ENET */ + kDma4RequestMuxENETRequest2 = 69U, /**< ENET */ + kDma4RequestMuxENETRequest3 = 70U, /**< ENET */ + kDma4RequestMuxLPI2C5Tx = 71U, /**< LPI2C5 */ + kDma4RequestMuxLPI2C5Rx = 72U, /**< LPI2C5 */ + kDma4RequestMuxLPI2C6Tx = 73U, /**< LPI2C6 */ + kDma4RequestMuxLPI2C6Rx = 74U, /**< LPI2C6 */ + kDma4RequestMuxLPI2C7Tx = 75U, /**< LPI2C7 */ + kDma4RequestMuxLPI2C7Rx = 76U, /**< LPI2C7 */ + kDma4RequestMuxLPI2C8Tx = 77U, /**< LPI2C8 */ + kDma4RequestMuxLPI2C8Rx = 78U, /**< LPI2C8 */ + kDma4RequestMuxLPSPI5Tx = 79U, /**< LPSPI5 Transmit */ + kDma4RequestMuxLPSPI5Rx = 80U, /**< LPSPI5 Receive */ + kDma4RequestMuxLPSPI6Tx = 81U, /**< LPSPI6 Transmit */ + kDma4RequestMuxLPSPI6Rx = 82U, /**< LPSPI6 Receive */ + kDma4RequestMuxLPSPI7Tx = 83U, /**< LPSPI7 Transmit */ + kDma4RequestMuxLPSPI7Rx = 84U, /**< LPSPI7 Receive */ + kDma4RequestMuxLPSPI8Tx = 85U, /**< LPSPI8 Transmit */ + kDma4RequestMuxLPSPI8Rx = 86U, /**< LPSPI8 Receive */ + kDma4RequestMuxLPUART7Tx = 87U, /**< LPUART7 Transmit */ + kDma4RequestMuxLPUART7Rx = 88U, /**< LPUART7 Receive */ + kDma4RequestMuxLPUART8Tx = 89U, /**< LPUART8 Transmit */ + kDma4RequestMuxLPUART8Rx = 90U, /**< LPUART8 Receive */ + kDma4RequestMuxENET_QOSRequest = 91U, /**< ENET_QOS */ + kDma4RequestMuxENET_QOSRequest1 = 92U, /**< ENET_QOS */ + kDma4RequestMuxENET_QOSRequest2 = 93U, /**< ENET_QOS */ + kDma4RequestMuxENET_QOSRequest3 = 94U, /**< ENET_QOS */ +} dma4_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Main Configuration, offset: 0x0 */ + __IO uint32_t MSR; /**< Main Status, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t ISR; /**< Interrupt Status, offset: 0x10 */ + __IO uint32_t CEOCFR0; /**< Channel Pending 0, offset: 0x14 */ + __IO uint32_t CEOCFR1; /**< Channel Pending 1, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x20 */ + __IO uint32_t CIMR0; /**< Channel Interrupt Mask 0, offset: 0x24 */ + __IO uint32_t CIMR1; /**< Channel Interrupt Mask 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t WTISR; /**< Watchdog Threshold Interrupt Status, offset: 0x30 */ + __IO uint32_t WTIMR; /**< Watchdog Threshold Interrupt Mask, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t DMAE; /**< DMAE, offset: 0x40 */ + __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ + __IO uint32_t DMAR1; /**< DMA 1, offset: 0x48 */ + uint8_t RESERVED_4[20]; + __IO uint32_t THRHLR0; /**< Analog Watchdog Threshold 0, offset: 0x60 */ + __IO uint32_t THRHLR1; /**< Analog Watchdog Threshold 1, offset: 0x64 */ + __IO uint32_t THRHLR2; /**< Analog Watchdog Threshold 2, offset: 0x68 */ + __IO uint32_t THRHLR3; /**< Analog Watchdog Threshold 3, offset: 0x6C */ + uint8_t RESERVED_5[16]; + __IO uint32_t PSCR; /**< Presampling Control, offset: 0x80 */ + __IO uint32_t PSR0; /**< Presampling 0, offset: 0x84 */ + __IO uint32_t PSR1; /**< Presampling 1, offset: 0x88 */ + uint8_t RESERVED_6[8]; + __IO uint32_t CTR0; /**< Conversion Timing 0, offset: 0x94 */ + __IO uint32_t CTR1; /**< Conversion Timing 1, offset: 0x98 */ + uint8_t RESERVED_7[8]; + __IO uint32_t NCMR0; /**< Normal Conversion Mask 0, offset: 0xA4 */ + __IO uint32_t NCMR1; /**< Normal Conversion Mask 1, offset: 0xA8 */ + uint8_t RESERVED_8[8]; + __IO uint32_t JCMR0; /**< Injected Conversion Mask 0, offset: 0xB4 */ + __IO uint32_t JCMR1; /**< Injected Conversion Mask 1, offset: 0xB8 */ + uint8_t RESERVED_9[4]; + __IO uint32_t USROFSGN; /**< User OFFSET and Gain, offset: 0xC0 */ + uint8_t RESERVED_10[4]; + __IO uint32_t PDEDR; /**< Power Down Exit Delay, offset: 0xC8 */ + uint8_t RESERVED_11[52]; + __I uint32_t PCDR[8]; /**< Precision Channel n Data, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_12[96]; + __I uint32_t ICDR[8]; /**< Internal Channel n Data, array offset: 0x180, array step: 0x4 */ + uint8_t RESERVED_13[224]; + __IO uint32_t THRHLR4; /**< Analog Watchdog Threshold 4, offset: 0x280 */ + __IO uint32_t THRHLR5; /**< Analog Watchdog Threshold 5, offset: 0x284 */ + __IO uint32_t THRHLR6; /**< Analog Watchdog Threshold 6, offset: 0x288 */ + __IO uint32_t THRHLR7; /**< Analog Watchdog Threshold 7, offset: 0x28C */ + uint8_t RESERVED_14[32]; + __IO uint32_t CWSELR0; /**< Channel Watchdog Select 0, offset: 0x2B0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CWSELR4; /**< Channel Watchdog Select 4, offset: 0x2C0 */ + uint8_t RESERVED_16[28]; + __IO uint32_t CWENR0; /**< Channel Watchdog Enable 0, offset: 0x2E0 */ + __IO uint32_t CWENR1; /**< Channel Watchdog Enable 1, offset: 0x2E4 */ + uint8_t RESERVED_17[8]; + __IO uint32_t AWORR0; /**< Analog Watchdog Out of Range 0, offset: 0x2F0 */ + __IO uint32_t AWORR1; /**< Analog Watchdog Out of Range 1, offset: 0x2F4 */ + uint8_t RESERVED_18[72]; + __IO uint32_t STCR1; /**< Self-Test Configuration 1, offset: 0x340 */ + __IO uint32_t STCR2; /**< Self-Test Configuration 2, offset: 0x344 */ + __IO uint32_t STCR3; /**< Self-Test Configuration 3, offset: 0x348 */ + __IO uint32_t STBRR; /**< Self-Test Baud Rate, offset: 0x34C */ + __IO uint32_t STSR1; /**< Self-Test Status 1, offset: 0x350 */ + __I uint32_t STSR2; /**< Self-Test Status 2, offset: 0x354 */ + __I uint32_t STSR3; /**< Self-Test Status 3, offset: 0x358 */ + __I uint32_t STSR4; /**< Self-Test Status 4, offset: 0x35C */ + uint8_t RESERVED_19[16]; + __I uint32_t STDR1; /**< Self-Test Data 1, offset: 0x370 */ + __I uint32_t STDR2; /**< Self-Test Data 2, offset: 0x374 */ + uint8_t RESERVED_20[8]; + __IO uint32_t STAW0R; /**< Self-Test Analog Watchdog 0, offset: 0x380 */ + __IO uint32_t STAW1AR; /**< Self-Test Analog Watchdog 1A, offset: 0x384 */ + __IO uint32_t STAW1BR; /**< Self-Test Analog Watchdog 1B, offset: 0x388 */ + __IO uint32_t STAW2R; /**< Self-Test Analog Watchdog 2, offset: 0x38C */ + uint32_t STAW3R; /**< Self-Test Analog Watchdog 3, offset: 0x390 */ + __IO uint32_t STAW4R; /**< Self-Test Analog Watchdog 4, offset: 0x394 */ + __IO uint32_t STAW5R; /**< Self-Test Analog Watchdog 5, offset: 0x398 */ + __I uint32_t CALSTAT; /**< Calibration Status, offset: 0x39C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name MCR - Main Configuration */ +/*! @{ */ + +#define ADC_MCR_PWDN_MASK (0x1U) +#define ADC_MCR_PWDN_SHIFT (0U) +/*! PWDN - Power-Down Enable + * 0b0..When ADC status is in Power-down mode (MSR[ADCSTATUS] = 001b), start ADC transition to IDLE mode + * 0b1..Request to enter Power-down mode + */ +#define ADC_MCR_PWDN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_PWDN_SHIFT)) & ADC_MCR_PWDN_MASK) + +#define ADC_MCR_ACKO_MASK (0x20U) +#define ADC_MCR_ACKO_SHIFT (5U) +/*! ACKO - Auto-Clock-Off Mode Enable + * 0b0..Auto-Clock-Off feature is disabled + * 0b1..Auto-Clock-Off feature is enabled + */ +#define ADC_MCR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ACKO_SHIFT)) & ADC_MCR_ACKO_MASK) + +#define ADC_MCR_ABORT_MASK (0x40U) +#define ADC_MCR_ABORT_SHIFT (6U) +/*! ABORT - Abort Conversion + * 0b0..Channel conversion has been aborted, or channel conversion is not currently running + * 0b1..Abort current channel conversion + */ +#define ADC_MCR_ABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORT_SHIFT)) & ADC_MCR_ABORT_MASK) + +#define ADC_MCR_ABORTCHAIN_MASK (0x80U) +#define ADC_MCR_ABORTCHAIN_SHIFT (7U) +/*! ABORTCHAIN - Abort Conversion Chain + * 0b0..Chain conversion aborted or is currently not running + * 0b1..Abort current chain conversion + */ +#define ADC_MCR_ABORTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORTCHAIN_SHIFT)) & ADC_MCR_ABORTCHAIN_MASK) + +#define ADC_MCR_ADCLKSE_MASK (0x100U) +#define ADC_MCR_ADCLKSE_SHIFT (8U) +/*! ADCLKSE - Analog Clock Frequency Select + * 0b0..AD_CLK frequency is half + * 0b1..AD_CLK frequency is equal to bus clock frequency + */ +#define ADC_MCR_ADCLKSE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ADCLKSE_SHIFT)) & ADC_MCR_ADCLKSE_MASK) + +#define ADC_MCR_TSAMP_MASK (0x600U) +#define ADC_MCR_TSAMP_SHIFT (9U) +/*! TSAMP - Sample Time for Calibration + * 0b00..22 cycles of AD_CLK (default) + * 0b01..8 cycles of AD_CLK + * 0b10..16 cycle of AD_CLK + * 0b11..32 cycle of AD_CLK + */ +#define ADC_MCR_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TSAMP_SHIFT)) & ADC_MCR_TSAMP_MASK) + +#define ADC_MCR_NRSMPL_MASK (0x1800U) +#define ADC_MCR_NRSMPL_SHIFT (11U) +/*! NRSMPL - Number of Averaging Samples + * 0b00..16 + * 0b01..32 + * 0b10..128 + * 0b11..512 + */ +#define ADC_MCR_NRSMPL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NRSMPL_SHIFT)) & ADC_MCR_NRSMPL_MASK) + +#define ADC_MCR_AVGEN_MASK (0x2000U) +#define ADC_MCR_AVGEN_SHIFT (13U) +/*! AVGEN - Average Enable + * 0b0..Disable + * 0b1..Enable (default) + */ +#define ADC_MCR_AVGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_AVGEN_SHIFT)) & ADC_MCR_AVGEN_MASK) + +#define ADC_MCR_CALSTART_MASK (0x4000U) +#define ADC_MCR_CALSTART_SHIFT (14U) +/*! CALSTART - Calibration Start + * 0b0..No effect + * 0b1..Start calibration + */ +#define ADC_MCR_CALSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_CALSTART_SHIFT)) & ADC_MCR_CALSTART_MASK) + +#define ADC_MCR_STCL_MASK (0x8000U) +#define ADC_MCR_STCL_SHIFT (15U) +/*! STCL - Self-Testing Configuration Lock + * 0b0..Not locked + * 0b1..Locked + */ +#define ADC_MCR_STCL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_STCL_SHIFT)) & ADC_MCR_STCL_MASK) + +#define ADC_MCR_JSTART_MASK (0x100000U) +#define ADC_MCR_JSTART_SHIFT (20U) +/*! JSTART - Start Injection Conversion */ +#define ADC_MCR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JSTART_SHIFT)) & ADC_MCR_JSTART_MASK) + +#define ADC_MCR_JEDGE_MASK (0x200000U) +#define ADC_MCR_JEDGE_SHIFT (21U) +/*! JEDGE - Injection Trigger Edge Selection + * 0b0..Falling edge is trigger + * 0b1..Rising edge is trigger + */ +#define ADC_MCR_JEDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JEDGE_SHIFT)) & ADC_MCR_JEDGE_MASK) + +#define ADC_MCR_JTRGEN_MASK (0x400000U) +#define ADC_MCR_JTRGEN_SHIFT (22U) +/*! JTRGEN - Injection External Trigger Enable + * 0b0..Injected conversion not started by external trigger + * 0b1..Injected conversion started by external trigger + */ +#define ADC_MCR_JTRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JTRGEN_SHIFT)) & ADC_MCR_JTRGEN_MASK) + +#define ADC_MCR_NSTART_MASK (0x1000000U) +#define ADC_MCR_NSTART_SHIFT (24U) +/*! NSTART - Normal Conversion Start */ +#define ADC_MCR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NSTART_SHIFT)) & ADC_MCR_NSTART_MASK) + +#define ADC_MCR_EDGE_MASK (0x4000000U) +#define ADC_MCR_EDGE_SHIFT (26U) +/*! EDGE - Trigger Edge Select + * 0b0..Falling edge is trigger + * 0b1..Rising edge is trigger + */ +#define ADC_MCR_EDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_EDGE_SHIFT)) & ADC_MCR_EDGE_MASK) + +#define ADC_MCR_TRGEN_MASK (0x8000000U) +#define ADC_MCR_TRGEN_SHIFT (27U) +/*! TRGEN - External Trigger Enable + * 0b0..External trigger is disabled + * 0b1..Enables the external trigger to start a conversion + */ +#define ADC_MCR_TRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TRGEN_SHIFT)) & ADC_MCR_TRGEN_MASK) + +#define ADC_MCR_MODE_MASK (0x20000000U) +#define ADC_MCR_MODE_SHIFT (29U) +/*! MODE - Normal Scan Mode Select + * 0b0..One-Shot Operation mode + * 0b1..Scan Operation mode + */ +#define ADC_MCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_MODE_SHIFT)) & ADC_MCR_MODE_MASK) + +#define ADC_MCR_WLSIDE_MASK (0x40000000U) +#define ADC_MCR_WLSIDE_SHIFT (30U) +/*! WLSIDE - Write Left Side + * 0b0..Write right-aligned conversion data (from 11 to 0) + * 0b1..Write left-aligned conversion data (from 15 to 4) + */ +#define ADC_MCR_WLSIDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_WLSIDE_SHIFT)) & ADC_MCR_WLSIDE_MASK) + +#define ADC_MCR_OWREN_MASK (0x80000000U) +#define ADC_MCR_OWREN_SHIFT (31U) +/*! OWREN - Overwrite Enable + * 0b0..Older valid conversion data is not overwritten by newer conversion data + * 0b1..Newer conversion result is always overwritten, irrespective of the validity of older conversion data + */ +#define ADC_MCR_OWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_OWREN_SHIFT)) & ADC_MCR_OWREN_MASK) +/*! @} */ + +/*! @name MSR - Main Status */ +/*! @{ */ + +#define ADC_MSR_ADCSTATUS_MASK (0x7U) +#define ADC_MSR_ADCSTATUS_SHIFT (0U) +/*! ADCSTATUS - ADC Status + * 0b000..Idle + * 0b001..Power-down + * 0b010..Wait state (waiting to start conversion after [external trigger]). + * 0b011..Busy in calibration + * 0b100..Sample + * 0b110..Conversion + */ +#define ADC_MSR_ADCSTATUS(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ADCSTATUS_SHIFT)) & ADC_MSR_ADCSTATUS_MASK) + +#define ADC_MSR_ACKO_MASK (0x20U) +#define ADC_MSR_ACKO_SHIFT (5U) +/*! ACKO - Auto-Clock-Off Enable + * 0b0..Auto-Clock-Off feature is not enabled + * 0b1..Auto-Clock-Off feature is enabled + */ +#define ADC_MSR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ACKO_SHIFT)) & ADC_MSR_ACKO_MASK) + +#define ADC_MSR_CHADDR_MASK (0xFE00U) +#define ADC_MSR_CHADDR_SHIFT (9U) +/*! CHADDR - Channel Address + * 0b0000000..Channel 0 selected + * 0b0000001..Channel 1 selected + * 0b0000010..Channel 2 selected + * 0b0000011..Channel 3 selected + * 0b0000100..Channel 4 selected + * 0b0000101..Channel 5 selected + * 0b0000110..Channel 6 selected + * 0b0000111..Channel 7 selected + * 0b0100000..Bandgap input selected + * 0b0100001..Pre-sample voltage - 1 : DVDD1P0/2 + * 0b0100010..Pre-sample voltage - 2 : AVDD1p8 + * 0b0100011..Pre-sample voltage - 3 : VREFL_1p8 + * 0b0100100..Pre-sample voltage - 4 : VREFH_1p8 + */ +#define ADC_MSR_CHADDR(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CHADDR_SHIFT)) & ADC_MSR_CHADDR_MASK) + +#define ADC_MSR_SELF_TEST_S_MASK (0x40000U) +#define ADC_MSR_SELF_TEST_S_SHIFT (18U) +/*! SELF_TEST_S - Self-Test Status + * 0b0..Self-test conversion is not in process + * 0b1..Self-test conversion is in process + */ +#define ADC_MSR_SELF_TEST_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_SELF_TEST_S_SHIFT)) & ADC_MSR_SELF_TEST_S_MASK) + +#define ADC_MSR_JSTART_MASK (0x100000U) +#define ADC_MSR_JSTART_SHIFT (20U) +/*! JSTART - Injected Conversion Status + * 0b0..Injected conversion is not in process + * 0b1..Injected conversion is in process + */ +#define ADC_MSR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JSTART_SHIFT)) & ADC_MSR_JSTART_MASK) + +#define ADC_MSR_JABORT_MASK (0x800000U) +#define ADC_MSR_JABORT_SHIFT (23U) +/*! JABORT - Injected Conversion Abort Status + * 0b0..Injected conversion has not been aborted + * 0b1..Injected conversion has been aborted + */ +#define ADC_MSR_JABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JABORT_SHIFT)) & ADC_MSR_JABORT_MASK) + +#define ADC_MSR_NSTART_MASK (0x1000000U) +#define ADC_MSR_NSTART_SHIFT (24U) +/*! NSTART - Normal Conversion Status + * 0b0..Normal conversion is not in process + * 0b1..Normal conversion is in process + */ +#define ADC_MSR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_NSTART_SHIFT)) & ADC_MSR_NSTART_MASK) + +#define ADC_MSR_CALBUSY_MASK (0x20000000U) +#define ADC_MSR_CALBUSY_SHIFT (29U) +/*! CALBUSY - Calibration Busy + * 0b0..ADC is ready for use + * 0b1..ADC is busy in a calibration process + */ +#define ADC_MSR_CALBUSY(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALBUSY_SHIFT)) & ADC_MSR_CALBUSY_MASK) + +#define ADC_MSR_CALFAIL_MASK (0x40000000U) +#define ADC_MSR_CALFAIL_SHIFT (30U) +/*! CALFAIL - Calibration Failed + * 0b0..Calibration passed (must be checked with CALBUSY = 0b) + * 0b0..No effect + * 0b1..Calibration failed + * 0b1..Clear the flag + */ +#define ADC_MSR_CALFAIL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALFAIL_SHIFT)) & ADC_MSR_CALFAIL_MASK) + +#define ADC_MSR_CALIBRTD_MASK (0x80000000U) +#define ADC_MSR_CALIBRTD_SHIFT (31U) +/*! CALIBRTD - Calibration Status + * 0b0..Uncalibrated or calibration unsuccessful + * 0b1..Calibrated or calibration successful + */ +#define ADC_MSR_CALIBRTD(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALIBRTD_SHIFT)) & ADC_MSR_CALIBRTD_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define ADC_ISR_ECH_MASK (0x1U) +#define ADC_ISR_ECH_SHIFT (0U) +/*! ECH - End of Conversion Chain + * 0b0..End of conversion chain has not occurred + * 0b0..No effect + * 0b1..End of conversion chain has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_ECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_ECH_SHIFT)) & ADC_ISR_ECH_MASK) + +#define ADC_ISR_EOC_MASK (0x2U) +#define ADC_ISR_EOC_SHIFT (1U) +/*! EOC - End of Channel Conversion + * 0b0..Channel end of conversion has not occurred + * 0b0..No effect + * 0b1..Channel end of conversion has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOC_SHIFT)) & ADC_ISR_EOC_MASK) + +#define ADC_ISR_JECH_MASK (0x4U) +#define ADC_ISR_JECH_SHIFT (2U) +/*! JECH - Injected End of Conversion Chain + * 0b0..Injected channel end of conversion chain has not occurred + * 0b0..No effect + * 0b1..Injected channel end of conversion chain has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_JECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JECH_SHIFT)) & ADC_ISR_JECH_MASK) + +#define ADC_ISR_JEOC_MASK (0x8U) +#define ADC_ISR_JEOC_SHIFT (3U) +/*! JEOC - Injected Channel End of Conversion + * 0b0..Injected channel end of conversion has not occurred + * 0b0..No effect + * 0b1..Injected channel end of conversion has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_JEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JEOC_SHIFT)) & ADC_ISR_JEOC_MASK) +/*! @} */ + +/*! @name CEOCFR0 - Channel Pending 0 */ +/*! @{ */ + +#define ADC_CEOCFR0_EOC_CH0_MASK (0x1U) +#define ADC_CEOCFR0_EOC_CH0_SHIFT (0U) +/*! EOC_CH0 - Channel 0 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH0_SHIFT)) & ADC_CEOCFR0_EOC_CH0_MASK) + +#define ADC_CEOCFR0_EOC_CH1_MASK (0x2U) +#define ADC_CEOCFR0_EOC_CH1_SHIFT (1U) +/*! EOC_CH1 - Channel 1 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH1_SHIFT)) & ADC_CEOCFR0_EOC_CH1_MASK) + +#define ADC_CEOCFR0_EOC_CH2_MASK (0x4U) +#define ADC_CEOCFR0_EOC_CH2_SHIFT (2U) +/*! EOC_CH2 - Channel 2 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH2_SHIFT)) & ADC_CEOCFR0_EOC_CH2_MASK) + +#define ADC_CEOCFR0_EOC_CH3_MASK (0x8U) +#define ADC_CEOCFR0_EOC_CH3_SHIFT (3U) +/*! EOC_CH3 - Channel 3 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH3_SHIFT)) & ADC_CEOCFR0_EOC_CH3_MASK) + +#define ADC_CEOCFR0_EOC_CH4_MASK (0x10U) +#define ADC_CEOCFR0_EOC_CH4_SHIFT (4U) +/*! EOC_CH4 - Channel 4 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH4_SHIFT)) & ADC_CEOCFR0_EOC_CH4_MASK) + +#define ADC_CEOCFR0_EOC_CH5_MASK (0x20U) +#define ADC_CEOCFR0_EOC_CH5_SHIFT (5U) +/*! EOC_CH5 - Channel 5 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH5_SHIFT)) & ADC_CEOCFR0_EOC_CH5_MASK) + +#define ADC_CEOCFR0_EOC_CH6_MASK (0x40U) +#define ADC_CEOCFR0_EOC_CH6_SHIFT (6U) +/*! EOC_CH6 - Channel 6 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH6_SHIFT)) & ADC_CEOCFR0_EOC_CH6_MASK) + +#define ADC_CEOCFR0_EOC_CH7_MASK (0x80U) +#define ADC_CEOCFR0_EOC_CH7_SHIFT (7U) +/*! EOC_CH7 - Channel 7 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH7_SHIFT)) & ADC_CEOCFR0_EOC_CH7_MASK) +/*! @} */ + +/*! @name CEOCFR1 - Channel Pending 1 */ +/*! @{ */ + +#define ADC_CEOCFR1_EOC_CH32_MASK (0x1U) +#define ADC_CEOCFR1_EOC_CH32_SHIFT (0U) +/*! EOC_CH32 - Channel 32 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH32_SHIFT)) & ADC_CEOCFR1_EOC_CH32_MASK) + +#define ADC_CEOCFR1_EOC_CH33_MASK (0x2U) +#define ADC_CEOCFR1_EOC_CH33_SHIFT (1U) +/*! EOC_CH33 - Channel 33 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH33_SHIFT)) & ADC_CEOCFR1_EOC_CH33_MASK) + +#define ADC_CEOCFR1_EOC_CH34_MASK (0x4U) +#define ADC_CEOCFR1_EOC_CH34_SHIFT (2U) +/*! EOC_CH34 - Channel 34 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH34_SHIFT)) & ADC_CEOCFR1_EOC_CH34_MASK) + +#define ADC_CEOCFR1_EOC_CH35_MASK (0x8U) +#define ADC_CEOCFR1_EOC_CH35_SHIFT (3U) +/*! EOC_CH35 - Channel 35 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH35_SHIFT)) & ADC_CEOCFR1_EOC_CH35_MASK) + +#define ADC_CEOCFR1_EOC_CH36_MASK (0x10U) +#define ADC_CEOCFR1_EOC_CH36_SHIFT (4U) +/*! EOC_CH36 - Channel 36 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH36_SHIFT)) & ADC_CEOCFR1_EOC_CH36_MASK) + +#define ADC_CEOCFR1_EOC_CH37_MASK (0x20U) +#define ADC_CEOCFR1_EOC_CH37_SHIFT (5U) +/*! EOC_CH37 - Channel 37 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH37_SHIFT)) & ADC_CEOCFR1_EOC_CH37_MASK) + +#define ADC_CEOCFR1_EOC_CH38_MASK (0x40U) +#define ADC_CEOCFR1_EOC_CH38_SHIFT (6U) +/*! EOC_CH38 - Channel 38 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH38_SHIFT)) & ADC_CEOCFR1_EOC_CH38_MASK) + +#define ADC_CEOCFR1_EOC_CH39_MASK (0x80U) +#define ADC_CEOCFR1_EOC_CH39_SHIFT (7U) +/*! EOC_CH39 - Channel 39 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH39_SHIFT)) & ADC_CEOCFR1_EOC_CH39_MASK) +/*! @} */ + +/*! @name IMR - Interrupt Mask */ +/*! @{ */ + +#define ADC_IMR_MSKECH_MASK (0x1U) +#define ADC_IMR_MSKECH_SHIFT (0U) +/*! MSKECH - End of Chain Conversion Interrupt Mask + * 0b0..End of chain conversion interrupt disabled + * 0b1..End of chain conversion interrupt enabled + */ +#define ADC_IMR_MSKECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKECH_SHIFT)) & ADC_IMR_MSKECH_MASK) + +#define ADC_IMR_MSKEOC_MASK (0x2U) +#define ADC_IMR_MSKEOC_SHIFT (1U) +/*! MSKEOC - End of Conversion Interrupt Mask + * 0b0..End of conversion interrupt disabled + * 0b1..End of conversion interrupt enabled + */ +#define ADC_IMR_MSKEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKEOC_SHIFT)) & ADC_IMR_MSKEOC_MASK) + +#define ADC_IMR_MSKJECH_MASK (0x4U) +#define ADC_IMR_MSKJECH_SHIFT (2U) +/*! MSKJECH - End of Injected Chain Conversion Interrupt Mask + * 0b0..End of injected chain conversion interrupt disabled + * 0b1..End of injected chain conversion interrupt enabled + */ +#define ADC_IMR_MSKJECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJECH_SHIFT)) & ADC_IMR_MSKJECH_MASK) + +#define ADC_IMR_MSKJEOC_MASK (0x8U) +#define ADC_IMR_MSKJEOC_SHIFT (3U) +/*! MSKJEOC - End of Injected Conversion Interrupt Mask + * 0b0..End of injected conversion interrupt disabled + * 0b1..End of injected conversion interrupt enabled + */ +#define ADC_IMR_MSKJEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJEOC_SHIFT)) & ADC_IMR_MSKJEOC_MASK) +/*! @} */ + +/*! @name CIMR0 - Channel Interrupt Mask 0 */ +/*! @{ */ + +#define ADC_CIMR0_CIM0_MASK (0x1U) +#define ADC_CIMR0_CIM0_SHIFT (0U) +/*! CIM0 - Channel 0 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM0_SHIFT)) & ADC_CIMR0_CIM0_MASK) + +#define ADC_CIMR0_CIM1_MASK (0x2U) +#define ADC_CIMR0_CIM1_SHIFT (1U) +/*! CIM1 - Channel 1 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM1_SHIFT)) & ADC_CIMR0_CIM1_MASK) + +#define ADC_CIMR0_CIM2_MASK (0x4U) +#define ADC_CIMR0_CIM2_SHIFT (2U) +/*! CIM2 - Channel 2 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM2_SHIFT)) & ADC_CIMR0_CIM2_MASK) + +#define ADC_CIMR0_CIM3_MASK (0x8U) +#define ADC_CIMR0_CIM3_SHIFT (3U) +/*! CIM3 - Channel 3 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM3_SHIFT)) & ADC_CIMR0_CIM3_MASK) + +#define ADC_CIMR0_CIM4_MASK (0x10U) +#define ADC_CIMR0_CIM4_SHIFT (4U) +/*! CIM4 - Channel 4 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM4_SHIFT)) & ADC_CIMR0_CIM4_MASK) + +#define ADC_CIMR0_CIM5_MASK (0x20U) +#define ADC_CIMR0_CIM5_SHIFT (5U) +/*! CIM5 - Channel 5 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM5_SHIFT)) & ADC_CIMR0_CIM5_MASK) + +#define ADC_CIMR0_CIM6_MASK (0x40U) +#define ADC_CIMR0_CIM6_SHIFT (6U) +/*! CIM6 - Channel 6 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM6_SHIFT)) & ADC_CIMR0_CIM6_MASK) + +#define ADC_CIMR0_CIM7_MASK (0x80U) +#define ADC_CIMR0_CIM7_SHIFT (7U) +/*! CIM7 - Channel 7 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM7_SHIFT)) & ADC_CIMR0_CIM7_MASK) +/*! @} */ + +/*! @name CIMR1 - Channel Interrupt Mask 1 */ +/*! @{ */ + +#define ADC_CIMR1_CIM32_MASK (0x1U) +#define ADC_CIMR1_CIM32_SHIFT (0U) +/*! CIM32 - Channel 32 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM32_SHIFT)) & ADC_CIMR1_CIM32_MASK) + +#define ADC_CIMR1_CIM33_MASK (0x2U) +#define ADC_CIMR1_CIM33_SHIFT (1U) +/*! CIM33 - Channel 33 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM33_SHIFT)) & ADC_CIMR1_CIM33_MASK) + +#define ADC_CIMR1_CIM34_MASK (0x4U) +#define ADC_CIMR1_CIM34_SHIFT (2U) +/*! CIM34 - Channel 34 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM34_SHIFT)) & ADC_CIMR1_CIM34_MASK) + +#define ADC_CIMR1_CIM35_MASK (0x8U) +#define ADC_CIMR1_CIM35_SHIFT (3U) +/*! CIM35 - Channel 35 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM35_SHIFT)) & ADC_CIMR1_CIM35_MASK) + +#define ADC_CIMR1_CIM36_MASK (0x10U) +#define ADC_CIMR1_CIM36_SHIFT (4U) +/*! CIM36 - Channel 36 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM36_SHIFT)) & ADC_CIMR1_CIM36_MASK) + +#define ADC_CIMR1_CIM37_MASK (0x20U) +#define ADC_CIMR1_CIM37_SHIFT (5U) +/*! CIM37 - Channel 37 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM37_SHIFT)) & ADC_CIMR1_CIM37_MASK) + +#define ADC_CIMR1_CIM38_MASK (0x40U) +#define ADC_CIMR1_CIM38_SHIFT (6U) +/*! CIM38 - Channel 38 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM38_SHIFT)) & ADC_CIMR1_CIM38_MASK) + +#define ADC_CIMR1_CIM39_MASK (0x80U) +#define ADC_CIMR1_CIM39_SHIFT (7U) +/*! CIM39 - Channel 39 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM39_SHIFT)) & ADC_CIMR1_CIM39_MASK) +/*! @} */ + +/*! @name WTISR - Watchdog Threshold Interrupt Status */ +/*! @{ */ + +#define ADC_WTISR_WDG0L_MASK (0x1U) +#define ADC_WTISR_WDG0L_SHIFT (0U) +/*! WDG0L - Channel 0 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG0L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0L_SHIFT)) & ADC_WTISR_WDG0L_MASK) + +#define ADC_WTISR_WDG0H_MASK (0x2U) +#define ADC_WTISR_WDG0H_SHIFT (1U) +/*! WDG0H - Channel 0 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG0H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0H_SHIFT)) & ADC_WTISR_WDG0H_MASK) + +#define ADC_WTISR_WDG1L_MASK (0x4U) +#define ADC_WTISR_WDG1L_SHIFT (2U) +/*! WDG1L - Channel 1 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG1L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1L_SHIFT)) & ADC_WTISR_WDG1L_MASK) + +#define ADC_WTISR_WDG1H_MASK (0x8U) +#define ADC_WTISR_WDG1H_SHIFT (3U) +/*! WDG1H - Channel 1 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG1H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1H_SHIFT)) & ADC_WTISR_WDG1H_MASK) + +#define ADC_WTISR_WDG2L_MASK (0x10U) +#define ADC_WTISR_WDG2L_SHIFT (4U) +/*! WDG2L - Channel 2 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG2L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2L_SHIFT)) & ADC_WTISR_WDG2L_MASK) + +#define ADC_WTISR_WDG2H_MASK (0x20U) +#define ADC_WTISR_WDG2H_SHIFT (5U) +/*! WDG2H - Channel 2 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG2H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2H_SHIFT)) & ADC_WTISR_WDG2H_MASK) + +#define ADC_WTISR_WDG3L_MASK (0x40U) +#define ADC_WTISR_WDG3L_SHIFT (6U) +/*! WDG3L - Channel 3 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG3L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3L_SHIFT)) & ADC_WTISR_WDG3L_MASK) + +#define ADC_WTISR_WDG3H_MASK (0x80U) +#define ADC_WTISR_WDG3H_SHIFT (7U) +/*! WDG3H - Channel 3 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG3H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3H_SHIFT)) & ADC_WTISR_WDG3H_MASK) + +#define ADC_WTISR_WDG4L_MASK (0x100U) +#define ADC_WTISR_WDG4L_SHIFT (8U) +/*! WDG4L - Channel 4 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG4L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4L_SHIFT)) & ADC_WTISR_WDG4L_MASK) + +#define ADC_WTISR_WDG4H_MASK (0x200U) +#define ADC_WTISR_WDG4H_SHIFT (9U) +/*! WDG4H - Channel 4 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG4H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4H_SHIFT)) & ADC_WTISR_WDG4H_MASK) + +#define ADC_WTISR_WDG5L_MASK (0x400U) +#define ADC_WTISR_WDG5L_SHIFT (10U) +/*! WDG5L - Channel 5 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG5L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5L_SHIFT)) & ADC_WTISR_WDG5L_MASK) + +#define ADC_WTISR_WDG5H_MASK (0x800U) +#define ADC_WTISR_WDG5H_SHIFT (11U) +/*! WDG5H - Channel 5 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG5H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5H_SHIFT)) & ADC_WTISR_WDG5H_MASK) + +#define ADC_WTISR_WDG6L_MASK (0x1000U) +#define ADC_WTISR_WDG6L_SHIFT (12U) +/*! WDG6L - Channel 6 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG6L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6L_SHIFT)) & ADC_WTISR_WDG6L_MASK) + +#define ADC_WTISR_WDG6H_MASK (0x2000U) +#define ADC_WTISR_WDG6H_SHIFT (13U) +/*! WDG6H - Channel 6 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG6H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6H_SHIFT)) & ADC_WTISR_WDG6H_MASK) + +#define ADC_WTISR_WDG7L_MASK (0x4000U) +#define ADC_WTISR_WDG7L_SHIFT (14U) +/*! WDG7L - Channel 7 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG7L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7L_SHIFT)) & ADC_WTISR_WDG7L_MASK) + +#define ADC_WTISR_WDG7H_MASK (0x8000U) +#define ADC_WTISR_WDG7H_SHIFT (15U) +/*! WDG7H - Channel 7 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG7H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7H_SHIFT)) & ADC_WTISR_WDG7H_MASK) +/*! @} */ + +/*! @name WTIMR - Watchdog Threshold Interrupt Mask */ +/*! @{ */ + +#define ADC_WTIMR_MSKWDG0L_MASK (0x1U) +#define ADC_WTIMR_MSKWDG0L_SHIFT (0U) +/*! MSKWDG0L - Channel 0 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG0L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0L_SHIFT)) & ADC_WTIMR_MSKWDG0L_MASK) + +#define ADC_WTIMR_MSKWDG0H_MASK (0x2U) +#define ADC_WTIMR_MSKWDG0H_SHIFT (1U) +/*! MSKWDG0H - Channel 0 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG0H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0H_SHIFT)) & ADC_WTIMR_MSKWDG0H_MASK) + +#define ADC_WTIMR_MSKWDG1L_MASK (0x4U) +#define ADC_WTIMR_MSKWDG1L_SHIFT (2U) +/*! MSKWDG1L - Channel 1 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG1L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1L_SHIFT)) & ADC_WTIMR_MSKWDG1L_MASK) + +#define ADC_WTIMR_MSKWDG1H_MASK (0x8U) +#define ADC_WTIMR_MSKWDG1H_SHIFT (3U) +/*! MSKWDG1H - Channel 1 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG1H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1H_SHIFT)) & ADC_WTIMR_MSKWDG1H_MASK) + +#define ADC_WTIMR_MSKWDG2L_MASK (0x10U) +#define ADC_WTIMR_MSKWDG2L_SHIFT (4U) +/*! MSKWDG2L - Channel 2 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG2L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2L_SHIFT)) & ADC_WTIMR_MSKWDG2L_MASK) + +#define ADC_WTIMR_MSKWDG2H_MASK (0x20U) +#define ADC_WTIMR_MSKWDG2H_SHIFT (5U) +/*! MSKWDG2H - Channel 2 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG2H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2H_SHIFT)) & ADC_WTIMR_MSKWDG2H_MASK) + +#define ADC_WTIMR_MSKWDG3L_MASK (0x40U) +#define ADC_WTIMR_MSKWDG3L_SHIFT (6U) +/*! MSKWDG3L - Channel 3 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG3L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3L_SHIFT)) & ADC_WTIMR_MSKWDG3L_MASK) + +#define ADC_WTIMR_MSKWDG3H_MASK (0x80U) +#define ADC_WTIMR_MSKWDG3H_SHIFT (7U) +/*! MSKWDG3H - Channel 3 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG3H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3H_SHIFT)) & ADC_WTIMR_MSKWDG3H_MASK) + +#define ADC_WTIMR_MSKWDG4L_MASK (0x100U) +#define ADC_WTIMR_MSKWDG4L_SHIFT (8U) +/*! MSKWDG4L - Channel 4 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG4L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4L_SHIFT)) & ADC_WTIMR_MSKWDG4L_MASK) + +#define ADC_WTIMR_MSKWDG4H_MASK (0x200U) +#define ADC_WTIMR_MSKWDG4H_SHIFT (9U) +/*! MSKWDG4H - Channel 4 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG4H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4H_SHIFT)) & ADC_WTIMR_MSKWDG4H_MASK) + +#define ADC_WTIMR_MSKWDG5L_MASK (0x400U) +#define ADC_WTIMR_MSKWDG5L_SHIFT (10U) +/*! MSKWDG5L - Channel 5 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG5L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5L_SHIFT)) & ADC_WTIMR_MSKWDG5L_MASK) + +#define ADC_WTIMR_MSKWDG5H_MASK (0x800U) +#define ADC_WTIMR_MSKWDG5H_SHIFT (11U) +/*! MSKWDG5H - Channel 5 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG5H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5H_SHIFT)) & ADC_WTIMR_MSKWDG5H_MASK) + +#define ADC_WTIMR_MSKWDG6L_MASK (0x1000U) +#define ADC_WTIMR_MSKWDG6L_SHIFT (12U) +/*! MSKWDG6L - Channel 6 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG6L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6L_SHIFT)) & ADC_WTIMR_MSKWDG6L_MASK) + +#define ADC_WTIMR_MSKWDG6H_MASK (0x2000U) +#define ADC_WTIMR_MSKWDG6H_SHIFT (13U) +/*! MSKWDG6H - Channel 6 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG6H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6H_SHIFT)) & ADC_WTIMR_MSKWDG6H_MASK) + +#define ADC_WTIMR_MSKWDG7L_MASK (0x4000U) +#define ADC_WTIMR_MSKWDG7L_SHIFT (14U) +/*! MSKWDG7L - Channel 7 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG7L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7L_SHIFT)) & ADC_WTIMR_MSKWDG7L_MASK) + +#define ADC_WTIMR_MSKWDG7H_MASK (0x8000U) +#define ADC_WTIMR_MSKWDG7H_SHIFT (15U) +/*! MSKWDG7H - Channel 7 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG7H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7H_SHIFT)) & ADC_WTIMR_MSKWDG7H_MASK) +/*! @} */ + +/*! @name DMAE - DMAE */ +/*! @{ */ + +#define ADC_DMAE_DMAEN_MASK (0x1U) +#define ADC_DMAE_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Global Enable + * 0b0..DMA feature is disabled + * 0b1..DMA feature is enabled + */ +#define ADC_DMAE_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DMAEN_SHIFT)) & ADC_DMAE_DMAEN_MASK) + +#define ADC_DMAE_DCLR_MASK (0x2U) +#define ADC_DMAE_DCLR_SHIFT (1U) +/*! DCLR - DMA Clear Sequence Enable + * 0b0..DMA request cleared by acknowledge from DMA controller + * 0b1..DMA request cleared on read of data registers + */ +#define ADC_DMAE_DCLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DCLR_SHIFT)) & ADC_DMAE_DCLR_MASK) +/*! @} */ + +/*! @name DMAR0 - DMA 0 */ +/*! @{ */ + +#define ADC_DMAR0_DMA0_MASK (0x1U) +#define ADC_DMAR0_DMA0_SHIFT (0U) +/*! DMA0 - Channel 0 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA0_SHIFT)) & ADC_DMAR0_DMA0_MASK) + +#define ADC_DMAR0_DMA1_MASK (0x2U) +#define ADC_DMAR0_DMA1_SHIFT (1U) +/*! DMA1 - Channel 1 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA1_SHIFT)) & ADC_DMAR0_DMA1_MASK) + +#define ADC_DMAR0_DMA2_MASK (0x4U) +#define ADC_DMAR0_DMA2_SHIFT (2U) +/*! DMA2 - Channel 2 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA2_SHIFT)) & ADC_DMAR0_DMA2_MASK) + +#define ADC_DMAR0_DMA3_MASK (0x8U) +#define ADC_DMAR0_DMA3_SHIFT (3U) +/*! DMA3 - Channel 3 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA3_SHIFT)) & ADC_DMAR0_DMA3_MASK) + +#define ADC_DMAR0_DMA4_MASK (0x10U) +#define ADC_DMAR0_DMA4_SHIFT (4U) +/*! DMA4 - Channel 4 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA4_SHIFT)) & ADC_DMAR0_DMA4_MASK) + +#define ADC_DMAR0_DMA5_MASK (0x20U) +#define ADC_DMAR0_DMA5_SHIFT (5U) +/*! DMA5 - Channel 5 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA5_SHIFT)) & ADC_DMAR0_DMA5_MASK) + +#define ADC_DMAR0_DMA6_MASK (0x40U) +#define ADC_DMAR0_DMA6_SHIFT (6U) +/*! DMA6 - Channel 6 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA6_SHIFT)) & ADC_DMAR0_DMA6_MASK) + +#define ADC_DMAR0_DMA7_MASK (0x80U) +#define ADC_DMAR0_DMA7_SHIFT (7U) +/*! DMA7 - Channel 7 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA7_SHIFT)) & ADC_DMAR0_DMA7_MASK) +/*! @} */ + +/*! @name DMAR1 - DMA 1 */ +/*! @{ */ + +#define ADC_DMAR1_DMA32_MASK (0x1U) +#define ADC_DMAR1_DMA32_SHIFT (0U) +/*! DMA32 - Channel 32 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA32(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA32_SHIFT)) & ADC_DMAR1_DMA32_MASK) + +#define ADC_DMAR1_DMA33_MASK (0x2U) +#define ADC_DMAR1_DMA33_SHIFT (1U) +/*! DMA33 - Channel 33 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA33(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA33_SHIFT)) & ADC_DMAR1_DMA33_MASK) + +#define ADC_DMAR1_DMA34_MASK (0x4U) +#define ADC_DMAR1_DMA34_SHIFT (2U) +/*! DMA34 - Channel 34 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA34(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA34_SHIFT)) & ADC_DMAR1_DMA34_MASK) + +#define ADC_DMAR1_DMA35_MASK (0x8U) +#define ADC_DMAR1_DMA35_SHIFT (3U) +/*! DMA35 - Channel 35 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA35(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA35_SHIFT)) & ADC_DMAR1_DMA35_MASK) + +#define ADC_DMAR1_DMA36_MASK (0x10U) +#define ADC_DMAR1_DMA36_SHIFT (4U) +/*! DMA36 - Channel 36 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA36(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA36_SHIFT)) & ADC_DMAR1_DMA36_MASK) + +#define ADC_DMAR1_DMA37_MASK (0x20U) +#define ADC_DMAR1_DMA37_SHIFT (5U) +/*! DMA37 - Channel 37 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA37(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA37_SHIFT)) & ADC_DMAR1_DMA37_MASK) + +#define ADC_DMAR1_DMA38_MASK (0x40U) +#define ADC_DMAR1_DMA38_SHIFT (6U) +/*! DMA38 - Channel 38 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA38(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA38_SHIFT)) & ADC_DMAR1_DMA38_MASK) + +#define ADC_DMAR1_DMA39_MASK (0x80U) +#define ADC_DMAR1_DMA39_SHIFT (7U) +/*! DMA39 - Channel 39 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA39(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA39_SHIFT)) & ADC_DMAR1_DMA39_MASK) +/*! @} */ + +/*! @name THRHLR0 - Analog Watchdog Threshold 0 */ +/*! @{ */ + +#define ADC_THRHLR0_THRL_MASK (0xFFFU) +#define ADC_THRHLR0_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR0_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRL_SHIFT)) & ADC_THRHLR0_THRL_MASK) + +#define ADC_THRHLR0_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR0_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR0_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRH_SHIFT)) & ADC_THRHLR0_THRH_MASK) +/*! @} */ + +/*! @name THRHLR1 - Analog Watchdog Threshold 1 */ +/*! @{ */ + +#define ADC_THRHLR1_THRL_MASK (0xFFFU) +#define ADC_THRHLR1_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR1_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRL_SHIFT)) & ADC_THRHLR1_THRL_MASK) + +#define ADC_THRHLR1_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR1_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR1_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRH_SHIFT)) & ADC_THRHLR1_THRH_MASK) +/*! @} */ + +/*! @name THRHLR2 - Analog Watchdog Threshold 2 */ +/*! @{ */ + +#define ADC_THRHLR2_THRL_MASK (0xFFFU) +#define ADC_THRHLR2_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR2_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRL_SHIFT)) & ADC_THRHLR2_THRL_MASK) + +#define ADC_THRHLR2_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR2_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR2_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRH_SHIFT)) & ADC_THRHLR2_THRH_MASK) +/*! @} */ + +/*! @name THRHLR3 - Analog Watchdog Threshold 3 */ +/*! @{ */ + +#define ADC_THRHLR3_THRL_MASK (0xFFFU) +#define ADC_THRHLR3_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR3_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRL_SHIFT)) & ADC_THRHLR3_THRL_MASK) + +#define ADC_THRHLR3_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR3_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR3_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRH_SHIFT)) & ADC_THRHLR3_THRH_MASK) +/*! @} */ + +/*! @name PSCR - Presampling Control */ +/*! @{ */ + +#define ADC_PSCR_PRECONV_MASK (0x1U) +#define ADC_PSCR_PRECONV_SHIFT (0U) +/*! PRECONV - Convert Presampled Value + * 0b0..Presampling is followed by sampling then conversion. + * 0b1..Presampling is followed by the conversion. + */ +#define ADC_PSCR_PRECONV(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PRECONV_SHIFT)) & ADC_PSCR_PRECONV_MASK) + +#define ADC_PSCR_PREVAL0_MASK (0x6U) +#define ADC_PSCR_PREVAL0_SHIFT (1U) +/*! PREVAL0 - Internal Presampling Voltage Selection */ +#define ADC_PSCR_PREVAL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL0_SHIFT)) & ADC_PSCR_PREVAL0_MASK) + +#define ADC_PSCR_PREVAL1_MASK (0x18U) +#define ADC_PSCR_PREVAL1_SHIFT (3U) +/*! PREVAL1 - Internal Presampling Voltage Selection. */ +#define ADC_PSCR_PREVAL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL1_SHIFT)) & ADC_PSCR_PREVAL1_MASK) +/*! @} */ + +/*! @name PSR0 - Presampling 0 */ +/*! @{ */ + +#define ADC_PSR0_PRES0_MASK (0x1U) +#define ADC_PSR0_PRES0_SHIFT (0U) +/*! PRES0 - Presampling Enable for Channel 0 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES0_SHIFT)) & ADC_PSR0_PRES0_MASK) + +#define ADC_PSR0_PRES1_MASK (0x2U) +#define ADC_PSR0_PRES1_SHIFT (1U) +/*! PRES1 - Presampling Enable for Channel 1 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES1_SHIFT)) & ADC_PSR0_PRES1_MASK) + +#define ADC_PSR0_PRES2_MASK (0x4U) +#define ADC_PSR0_PRES2_SHIFT (2U) +/*! PRES2 - Presampling Enable for Channel 2 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES2(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES2_SHIFT)) & ADC_PSR0_PRES2_MASK) + +#define ADC_PSR0_PRES3_MASK (0x8U) +#define ADC_PSR0_PRES3_SHIFT (3U) +/*! PRES3 - Presampling Enable for Channel 3 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES3(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES3_SHIFT)) & ADC_PSR0_PRES3_MASK) + +#define ADC_PSR0_PRES4_MASK (0x10U) +#define ADC_PSR0_PRES4_SHIFT (4U) +/*! PRES4 - Presampling Enable for Channel 4 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES4(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES4_SHIFT)) & ADC_PSR0_PRES4_MASK) + +#define ADC_PSR0_PRES5_MASK (0x20U) +#define ADC_PSR0_PRES5_SHIFT (5U) +/*! PRES5 - Presampling Enable for Channel 5 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES5(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES5_SHIFT)) & ADC_PSR0_PRES5_MASK) + +#define ADC_PSR0_PRES6_MASK (0x40U) +#define ADC_PSR0_PRES6_SHIFT (6U) +/*! PRES6 - Presampling Enable for Channel 6 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES6(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES6_SHIFT)) & ADC_PSR0_PRES6_MASK) + +#define ADC_PSR0_PRES7_MASK (0x80U) +#define ADC_PSR0_PRES7_SHIFT (7U) +/*! PRES7 - Presampling Enable for Channel 7 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES7(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES7_SHIFT)) & ADC_PSR0_PRES7_MASK) +/*! @} */ + +/*! @name PSR1 - Presampling 1 */ +/*! @{ */ + +#define ADC_PSR1_PRES32_MASK (0x1U) +#define ADC_PSR1_PRES32_SHIFT (0U) +/*! PRES32 - Presampling Enable for Channel 32 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES32(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES32_SHIFT)) & ADC_PSR1_PRES32_MASK) + +#define ADC_PSR1_PRES33_MASK (0x2U) +#define ADC_PSR1_PRES33_SHIFT (1U) +/*! PRES33 - Presampling Enable for Channel 33 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES33(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES33_SHIFT)) & ADC_PSR1_PRES33_MASK) + +#define ADC_PSR1_PRES34_MASK (0x4U) +#define ADC_PSR1_PRES34_SHIFT (2U) +/*! PRES34 - Presampling Enable for Channel 34 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES34(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES34_SHIFT)) & ADC_PSR1_PRES34_MASK) + +#define ADC_PSR1_PRES35_MASK (0x8U) +#define ADC_PSR1_PRES35_SHIFT (3U) +/*! PRES35 - Presampling Enable for Channel 35 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES35(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES35_SHIFT)) & ADC_PSR1_PRES35_MASK) + +#define ADC_PSR1_PRES36_MASK (0x10U) +#define ADC_PSR1_PRES36_SHIFT (4U) +/*! PRES36 - Presampling Enable for Channel 36 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES36(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES36_SHIFT)) & ADC_PSR1_PRES36_MASK) + +#define ADC_PSR1_PRES37_MASK (0x20U) +#define ADC_PSR1_PRES37_SHIFT (5U) +/*! PRES37 - Presampling Enable for Channel 37 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES37(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES37_SHIFT)) & ADC_PSR1_PRES37_MASK) + +#define ADC_PSR1_PRES38_MASK (0x40U) +#define ADC_PSR1_PRES38_SHIFT (6U) +/*! PRES38 - Presampling Enable for Channel 38 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES38(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES38_SHIFT)) & ADC_PSR1_PRES38_MASK) + +#define ADC_PSR1_PRES39_MASK (0x80U) +#define ADC_PSR1_PRES39_SHIFT (7U) +/*! PRES39 - Presampling Enable for Channel 39 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES39(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES39_SHIFT)) & ADC_PSR1_PRES39_MASK) +/*! @} */ + +/*! @name CTR0 - Conversion Timing 0 */ +/*! @{ */ + +#define ADC_CTR0_INPSAMP_MASK (0xFFU) +#define ADC_CTR0_INPSAMP_SHIFT (0U) +/*! INPSAMP - Sampling Phase Duration */ +#define ADC_CTR0_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR0_INPSAMP_SHIFT)) & ADC_CTR0_INPSAMP_MASK) +/*! @} */ + +/*! @name CTR1 - Conversion Timing 1 */ +/*! @{ */ + +#define ADC_CTR1_INPSAMP_MASK (0xFFU) +#define ADC_CTR1_INPSAMP_SHIFT (0U) +/*! INPSAMP - Sampling Phase Duration */ +#define ADC_CTR1_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR1_INPSAMP_SHIFT)) & ADC_CTR1_INPSAMP_MASK) +/*! @} */ + +/*! @name NCMR0 - Normal Conversion Mask 0 */ +/*! @{ */ + +#define ADC_NCMR0_CH0_MASK (0x1U) +#define ADC_NCMR0_CH0_SHIFT (0U) +/*! CH0 - Normal Conversion Mask for Channel 0 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH0_SHIFT)) & ADC_NCMR0_CH0_MASK) + +#define ADC_NCMR0_CH1_MASK (0x2U) +#define ADC_NCMR0_CH1_SHIFT (1U) +/*! CH1 - Normal Conversion Mask for Channel 1 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH1_SHIFT)) & ADC_NCMR0_CH1_MASK) + +#define ADC_NCMR0_CH2_MASK (0x4U) +#define ADC_NCMR0_CH2_SHIFT (2U) +/*! CH2 - Normal Conversion Mask for Channel 2 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH2_SHIFT)) & ADC_NCMR0_CH2_MASK) + +#define ADC_NCMR0_CH3_MASK (0x8U) +#define ADC_NCMR0_CH3_SHIFT (3U) +/*! CH3 - Normal Conversion Mask for Channel 3 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH3_SHIFT)) & ADC_NCMR0_CH3_MASK) + +#define ADC_NCMR0_CH4_MASK (0x10U) +#define ADC_NCMR0_CH4_SHIFT (4U) +/*! CH4 - Normal Conversion Mask for Channel 4 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH4_SHIFT)) & ADC_NCMR0_CH4_MASK) + +#define ADC_NCMR0_CH5_MASK (0x20U) +#define ADC_NCMR0_CH5_SHIFT (5U) +/*! CH5 - Normal Conversion Mask for Channel 5 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH5_SHIFT)) & ADC_NCMR0_CH5_MASK) + +#define ADC_NCMR0_CH6_MASK (0x40U) +#define ADC_NCMR0_CH6_SHIFT (6U) +/*! CH6 - Normal Conversion Mask for Channel 6 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH6_SHIFT)) & ADC_NCMR0_CH6_MASK) + +#define ADC_NCMR0_CH7_MASK (0x80U) +#define ADC_NCMR0_CH7_SHIFT (7U) +/*! CH7 - Normal Conversion Mask for Channel 7 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH7_SHIFT)) & ADC_NCMR0_CH7_MASK) +/*! @} */ + +/*! @name NCMR1 - Normal Conversion Mask 1 */ +/*! @{ */ + +#define ADC_NCMR1_CH32_MASK (0x1U) +#define ADC_NCMR1_CH32_SHIFT (0U) +/*! CH32 - Normal Conversion Mask for Channel 32 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH32_SHIFT)) & ADC_NCMR1_CH32_MASK) + +#define ADC_NCMR1_CH33_MASK (0x2U) +#define ADC_NCMR1_CH33_SHIFT (1U) +/*! CH33 - Normal Conversion Mask for Channel 33 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH33_SHIFT)) & ADC_NCMR1_CH33_MASK) + +#define ADC_NCMR1_CH34_MASK (0x4U) +#define ADC_NCMR1_CH34_SHIFT (2U) +/*! CH34 - Normal Conversion Mask for Channel 34 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH34_SHIFT)) & ADC_NCMR1_CH34_MASK) + +#define ADC_NCMR1_CH35_MASK (0x8U) +#define ADC_NCMR1_CH35_SHIFT (3U) +/*! CH35 - Normal Conversion Mask for Channel 35 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH35_SHIFT)) & ADC_NCMR1_CH35_MASK) + +#define ADC_NCMR1_CH36_MASK (0x10U) +#define ADC_NCMR1_CH36_SHIFT (4U) +/*! CH36 - Normal Conversion Mask for Channel 36 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH36_SHIFT)) & ADC_NCMR1_CH36_MASK) + +#define ADC_NCMR1_CH37_MASK (0x20U) +#define ADC_NCMR1_CH37_SHIFT (5U) +/*! CH37 - Normal Conversion Mask for Channel 37 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH37_SHIFT)) & ADC_NCMR1_CH37_MASK) + +#define ADC_NCMR1_CH38_MASK (0x40U) +#define ADC_NCMR1_CH38_SHIFT (6U) +/*! CH38 - Normal Conversion Mask for Channel 38 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH38_SHIFT)) & ADC_NCMR1_CH38_MASK) + +#define ADC_NCMR1_CH39_MASK (0x80U) +#define ADC_NCMR1_CH39_SHIFT (7U) +/*! CH39 - Normal Conversion Mask for Channel 39 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH39_SHIFT)) & ADC_NCMR1_CH39_MASK) +/*! @} */ + +/*! @name JCMR0 - Injected Conversion Mask 0 */ +/*! @{ */ + +#define ADC_JCMR0_CH0_MASK (0x1U) +#define ADC_JCMR0_CH0_SHIFT (0U) +/*! CH0 - Injected Conversion Mask for Channel 0 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH0_SHIFT)) & ADC_JCMR0_CH0_MASK) + +#define ADC_JCMR0_CH1_MASK (0x2U) +#define ADC_JCMR0_CH1_SHIFT (1U) +/*! CH1 - Injected Conversion Mask for Channel 1 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH1_SHIFT)) & ADC_JCMR0_CH1_MASK) + +#define ADC_JCMR0_CH2_MASK (0x4U) +#define ADC_JCMR0_CH2_SHIFT (2U) +/*! CH2 - Injected Conversion Mask for Channel 2 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH2_SHIFT)) & ADC_JCMR0_CH2_MASK) + +#define ADC_JCMR0_CH3_MASK (0x8U) +#define ADC_JCMR0_CH3_SHIFT (3U) +/*! CH3 - Injected Conversion Mask for Channel 3 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH3_SHIFT)) & ADC_JCMR0_CH3_MASK) + +#define ADC_JCMR0_CH4_MASK (0x10U) +#define ADC_JCMR0_CH4_SHIFT (4U) +/*! CH4 - Injected Conversion Mask for Channel 4 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH4_SHIFT)) & ADC_JCMR0_CH4_MASK) + +#define ADC_JCMR0_CH5_MASK (0x20U) +#define ADC_JCMR0_CH5_SHIFT (5U) +/*! CH5 - Injected Conversion Mask for Channel 5 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH5_SHIFT)) & ADC_JCMR0_CH5_MASK) + +#define ADC_JCMR0_CH6_MASK (0x40U) +#define ADC_JCMR0_CH6_SHIFT (6U) +/*! CH6 - Injected Conversion Mask for Channel 6 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH6_SHIFT)) & ADC_JCMR0_CH6_MASK) + +#define ADC_JCMR0_CH7_MASK (0x80U) +#define ADC_JCMR0_CH7_SHIFT (7U) +/*! CH7 - Injected Conversion Mask for Channel 7 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH7_SHIFT)) & ADC_JCMR0_CH7_MASK) +/*! @} */ + +/*! @name JCMR1 - Injected Conversion Mask 1 */ +/*! @{ */ + +#define ADC_JCMR1_CH32_MASK (0x1U) +#define ADC_JCMR1_CH32_SHIFT (0U) +/*! CH32 - Injected Conversion Mask for Channel 32 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH32_SHIFT)) & ADC_JCMR1_CH32_MASK) + +#define ADC_JCMR1_CH33_MASK (0x2U) +#define ADC_JCMR1_CH33_SHIFT (1U) +/*! CH33 - Injected Conversion Mask for Channel 33 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH33_SHIFT)) & ADC_JCMR1_CH33_MASK) + +#define ADC_JCMR1_CH34_MASK (0x4U) +#define ADC_JCMR1_CH34_SHIFT (2U) +/*! CH34 - Injected Conversion Mask for Channel 34 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH34_SHIFT)) & ADC_JCMR1_CH34_MASK) + +#define ADC_JCMR1_CH35_MASK (0x8U) +#define ADC_JCMR1_CH35_SHIFT (3U) +/*! CH35 - Injected Conversion Mask for Channel 35 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH35_SHIFT)) & ADC_JCMR1_CH35_MASK) + +#define ADC_JCMR1_CH36_MASK (0x10U) +#define ADC_JCMR1_CH36_SHIFT (4U) +/*! CH36 - Injected Conversion Mask for Channel 36 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH36_SHIFT)) & ADC_JCMR1_CH36_MASK) + +#define ADC_JCMR1_CH37_MASK (0x20U) +#define ADC_JCMR1_CH37_SHIFT (5U) +/*! CH37 - Injected Conversion Mask for Channel 37 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH37_SHIFT)) & ADC_JCMR1_CH37_MASK) + +#define ADC_JCMR1_CH38_MASK (0x40U) +#define ADC_JCMR1_CH38_SHIFT (6U) +/*! CH38 - Injected Conversion Mask for Channel 38 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH38_SHIFT)) & ADC_JCMR1_CH38_MASK) + +#define ADC_JCMR1_CH39_MASK (0x80U) +#define ADC_JCMR1_CH39_SHIFT (7U) +/*! CH39 - Injected Conversion Mask for Channel 39 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH39_SHIFT)) & ADC_JCMR1_CH39_MASK) +/*! @} */ + +/*! @name USROFSGN - User OFFSET and Gain */ +/*! @{ */ + +#define ADC_USROFSGN_OFFSUSER_MASK (0xFFU) +#define ADC_USROFSGN_OFFSUSER_SHIFT (0U) +/*! OFFSUSER - User Defined Offset */ +#define ADC_USROFSGN_OFFSUSER(x) (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_OFFSUSER_SHIFT)) & ADC_USROFSGN_OFFSUSER_MASK) + +#define ADC_USROFSGN_GAINUSER_MASK (0x3FF0000U) +#define ADC_USROFSGN_GAINUSER_SHIFT (16U) +/*! GAINUSER - User-Defined Gain Value */ +#define ADC_USROFSGN_GAINUSER(x) (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_GAINUSER_SHIFT)) & ADC_USROFSGN_GAINUSER_MASK) +/*! @} */ + +/*! @name PDEDR - Power Down Exit Delay */ +/*! @{ */ + +#define ADC_PDEDR_PDED_MASK (0xFFU) +#define ADC_PDEDR_PDED_SHIFT (0U) +/*! PDED - Power Down Exist Delay */ +#define ADC_PDEDR_PDED(x) (((uint32_t)(((uint32_t)(x)) << ADC_PDEDR_PDED_SHIFT)) & ADC_PDEDR_PDED_MASK) +/*! @} */ + +/*! @name PCDR - Precision Channel n Data */ +/*! @{ */ + +#define ADC_PCDR_CDATA_MASK (0xFFFU) +#define ADC_PCDR_CDATA_SHIFT (0U) +/*! CDATA - Channel Converted Data */ +#define ADC_PCDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_CDATA_SHIFT)) & ADC_PCDR_CDATA_MASK) + +#define ADC_PCDR_RESULT_MASK (0x30000U) +#define ADC_PCDR_RESULT_SHIFT (16U) +/*! RESULT - Mode of Conversion Status + * 0b00..Data is a result of Normal conversion mode + * 0b01..Data is a result of Injected conversion mode + * 0b10..Data is a result of CTU conversion mode + * 0b11..Reserved + */ +#define ADC_PCDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_RESULT_SHIFT)) & ADC_PCDR_RESULT_MASK) + +#define ADC_PCDR_OVERW_MASK (0x40000U) +#define ADC_PCDR_OVERW_SHIFT (18U) +/*! OVERW - Data Overwrite + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_PCDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_OVERW_SHIFT)) & ADC_PCDR_OVERW_MASK) + +#define ADC_PCDR_VALID_MASK (0x80000U) +#define ADC_PCDR_VALID_SHIFT (19U) +/*! VALID - Conversion Data Valid + * 0b0..Not valid data + * 0b1..Valid data + */ +#define ADC_PCDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_VALID_SHIFT)) & ADC_PCDR_VALID_MASK) +/*! @} */ + +/* The count of ADC_PCDR */ +#define ADC_PCDR_COUNT (8U) + +/*! @name ICDR - Internal Channel n Data */ +/*! @{ */ + +#define ADC_ICDR_CDATA_MASK (0xFFFU) +#define ADC_ICDR_CDATA_SHIFT (0U) +/*! CDATA - Channel Converted Data */ +#define ADC_ICDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_CDATA_SHIFT)) & ADC_ICDR_CDATA_MASK) + +#define ADC_ICDR_RESULT_MASK (0x30000U) +#define ADC_ICDR_RESULT_SHIFT (16U) +/*! RESULT - Mode of Conversion Status + * 0b00..Data is a result of Normal conversion mode + * 0b01..Data is a result of Injected conversion mode + * 0b10..Data is a result of CTU conversion mode + * 0b11..Reserved + */ +#define ADC_ICDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_RESULT_SHIFT)) & ADC_ICDR_RESULT_MASK) + +#define ADC_ICDR_OVERW_MASK (0x40000U) +#define ADC_ICDR_OVERW_SHIFT (18U) +/*! OVERW - Data Overwrite + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_ICDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_OVERW_SHIFT)) & ADC_ICDR_OVERW_MASK) + +#define ADC_ICDR_VALID_MASK (0x80000U) +#define ADC_ICDR_VALID_SHIFT (19U) +/*! VALID - Conversion Data Valid + * 0b0..Not valid data + * 0b1..Valid data + */ +#define ADC_ICDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_VALID_SHIFT)) & ADC_ICDR_VALID_MASK) +/*! @} */ + +/* The count of ADC_ICDR */ +#define ADC_ICDR_COUNT (8U) + +/*! @name THRHLR4 - Analog Watchdog Threshold 4 */ +/*! @{ */ + +#define ADC_THRHLR4_THRL_MASK (0xFFFU) +#define ADC_THRHLR4_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR4_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRL_SHIFT)) & ADC_THRHLR4_THRL_MASK) + +#define ADC_THRHLR4_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR4_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR4_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRH_SHIFT)) & ADC_THRHLR4_THRH_MASK) +/*! @} */ + +/*! @name THRHLR5 - Analog Watchdog Threshold 5 */ +/*! @{ */ + +#define ADC_THRHLR5_THRL_MASK (0xFFFU) +#define ADC_THRHLR5_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR5_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRL_SHIFT)) & ADC_THRHLR5_THRL_MASK) + +#define ADC_THRHLR5_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR5_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR5_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRH_SHIFT)) & ADC_THRHLR5_THRH_MASK) +/*! @} */ + +/*! @name THRHLR6 - Analog Watchdog Threshold 6 */ +/*! @{ */ + +#define ADC_THRHLR6_THRL_MASK (0xFFFU) +#define ADC_THRHLR6_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR6_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRL_SHIFT)) & ADC_THRHLR6_THRL_MASK) + +#define ADC_THRHLR6_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR6_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR6_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRH_SHIFT)) & ADC_THRHLR6_THRH_MASK) +/*! @} */ + +/*! @name THRHLR7 - Analog Watchdog Threshold 7 */ +/*! @{ */ + +#define ADC_THRHLR7_THRL_MASK (0xFFFU) +#define ADC_THRHLR7_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR7_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRL_SHIFT)) & ADC_THRHLR7_THRL_MASK) + +#define ADC_THRHLR7_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR7_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR7_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRH_SHIFT)) & ADC_THRHLR7_THRH_MASK) +/*! @} */ + +/*! @name CWSELR0 - Channel Watchdog Select 0 */ +/*! @{ */ + +#define ADC_CWSELR0_WSEL_CH0_MASK (0x7U) +#define ADC_CWSELR0_WSEL_CH0_SHIFT (0U) +/*! WSEL_CH0 - Channel Watchdog Select for Channel 0 */ +#define ADC_CWSELR0_WSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH0_SHIFT)) & ADC_CWSELR0_WSEL_CH0_MASK) + +#define ADC_CWSELR0_WSEL_CH1_MASK (0x70U) +#define ADC_CWSELR0_WSEL_CH1_SHIFT (4U) +/*! WSEL_CH1 - Channel Watchdog Select for Channel 1 */ +#define ADC_CWSELR0_WSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH1_SHIFT)) & ADC_CWSELR0_WSEL_CH1_MASK) + +#define ADC_CWSELR0_WSEL_CH2_MASK (0x700U) +#define ADC_CWSELR0_WSEL_CH2_SHIFT (8U) +/*! WSEL_CH2 - Channel Watchdog Select for Channel 2 */ +#define ADC_CWSELR0_WSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH2_SHIFT)) & ADC_CWSELR0_WSEL_CH2_MASK) + +#define ADC_CWSELR0_WSEL_CH3_MASK (0x7000U) +#define ADC_CWSELR0_WSEL_CH3_SHIFT (12U) +/*! WSEL_CH3 - Channel Watchdog Select for Channel 3 */ +#define ADC_CWSELR0_WSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH3_SHIFT)) & ADC_CWSELR0_WSEL_CH3_MASK) + +#define ADC_CWSELR0_WSEL_CH4_MASK (0x70000U) +#define ADC_CWSELR0_WSEL_CH4_SHIFT (16U) +/*! WSEL_CH4 - Channel Watchdog Select for Channel 4 */ +#define ADC_CWSELR0_WSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH4_SHIFT)) & ADC_CWSELR0_WSEL_CH4_MASK) + +#define ADC_CWSELR0_WSEL_CH5_MASK (0x700000U) +#define ADC_CWSELR0_WSEL_CH5_SHIFT (20U) +/*! WSEL_CH5 - Channel Watchdog Select for Channel 5 */ +#define ADC_CWSELR0_WSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH5_SHIFT)) & ADC_CWSELR0_WSEL_CH5_MASK) + +#define ADC_CWSELR0_WSEL_CH6_MASK (0x7000000U) +#define ADC_CWSELR0_WSEL_CH6_SHIFT (24U) +/*! WSEL_CH6 - Channel Watchdog Select for Channel 6 */ +#define ADC_CWSELR0_WSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH6_SHIFT)) & ADC_CWSELR0_WSEL_CH6_MASK) + +#define ADC_CWSELR0_WSEL_CH7_MASK (0x70000000U) +#define ADC_CWSELR0_WSEL_CH7_SHIFT (28U) +/*! WSEL_CH7 - Channel Watchdog Select for Channel 7 */ +#define ADC_CWSELR0_WSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH7_SHIFT)) & ADC_CWSELR0_WSEL_CH7_MASK) +/*! @} */ + +/*! @name CWSELR4 - Channel Watchdog Select 4 */ +/*! @{ */ + +#define ADC_CWSELR4_WSEL_CH32_MASK (0x7U) +#define ADC_CWSELR4_WSEL_CH32_SHIFT (0U) +/*! WSEL_CH32 - Channel Watchdog Select for Channel 32 */ +#define ADC_CWSELR4_WSEL_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH32_SHIFT)) & ADC_CWSELR4_WSEL_CH32_MASK) + +#define ADC_CWSELR4_WSEL_CH33_MASK (0x70U) +#define ADC_CWSELR4_WSEL_CH33_SHIFT (4U) +/*! WSEL_CH33 - Channel Watchdog Select for Channel 33 */ +#define ADC_CWSELR4_WSEL_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH33_SHIFT)) & ADC_CWSELR4_WSEL_CH33_MASK) + +#define ADC_CWSELR4_WSEL_CH34_MASK (0x700U) +#define ADC_CWSELR4_WSEL_CH34_SHIFT (8U) +/*! WSEL_CH34 - Channel Watchdog Select for Channel 34 */ +#define ADC_CWSELR4_WSEL_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH34_SHIFT)) & ADC_CWSELR4_WSEL_CH34_MASK) + +#define ADC_CWSELR4_WSEL_CH35_MASK (0x7000U) +#define ADC_CWSELR4_WSEL_CH35_SHIFT (12U) +/*! WSEL_CH35 - Channel Watchdog Select for Channel 35 */ +#define ADC_CWSELR4_WSEL_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH35_SHIFT)) & ADC_CWSELR4_WSEL_CH35_MASK) + +#define ADC_CWSELR4_WSEL_CH36_MASK (0x70000U) +#define ADC_CWSELR4_WSEL_CH36_SHIFT (16U) +/*! WSEL_CH36 - Channel Watchdog Select for Channel 36 */ +#define ADC_CWSELR4_WSEL_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH36_SHIFT)) & ADC_CWSELR4_WSEL_CH36_MASK) + +#define ADC_CWSELR4_WSEL_CH37_MASK (0x700000U) +#define ADC_CWSELR4_WSEL_CH37_SHIFT (20U) +/*! WSEL_CH37 - Channel Watchdog Select for Channel 37 */ +#define ADC_CWSELR4_WSEL_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH37_SHIFT)) & ADC_CWSELR4_WSEL_CH37_MASK) + +#define ADC_CWSELR4_WSEL_CH38_MASK (0x7000000U) +#define ADC_CWSELR4_WSEL_CH38_SHIFT (24U) +/*! WSEL_CH38 - Channel Watchdog Select for Channel 38 */ +#define ADC_CWSELR4_WSEL_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH38_SHIFT)) & ADC_CWSELR4_WSEL_CH38_MASK) + +#define ADC_CWSELR4_WSEL_CH39_MASK (0x70000000U) +#define ADC_CWSELR4_WSEL_CH39_SHIFT (28U) +/*! WSEL_CH39 - Channel Watchdog Select for Channel 39 */ +#define ADC_CWSELR4_WSEL_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH39_SHIFT)) & ADC_CWSELR4_WSEL_CH39_MASK) +/*! @} */ + +/*! @name CWENR0 - Channel Watchdog Enable 0 */ +/*! @{ */ + +#define ADC_CWENR0_CWEN0_MASK (0x1U) +#define ADC_CWENR0_CWEN0_SHIFT (0U) +/*! CWEN0 - Watchdog Enable for Channel 0 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN0_SHIFT)) & ADC_CWENR0_CWEN0_MASK) + +#define ADC_CWENR0_CWEN1_MASK (0x2U) +#define ADC_CWENR0_CWEN1_SHIFT (1U) +/*! CWEN1 - Watchdog Enable for Channel 1 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN1_SHIFT)) & ADC_CWENR0_CWEN1_MASK) + +#define ADC_CWENR0_CWEN2_MASK (0x4U) +#define ADC_CWENR0_CWEN2_SHIFT (2U) +/*! CWEN2 - Watchdog Enable for Channel 2 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN2_SHIFT)) & ADC_CWENR0_CWEN2_MASK) + +#define ADC_CWENR0_CWEN3_MASK (0x8U) +#define ADC_CWENR0_CWEN3_SHIFT (3U) +/*! CWEN3 - Watchdog Enable for Channel 3 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN3_SHIFT)) & ADC_CWENR0_CWEN3_MASK) + +#define ADC_CWENR0_CWEN4_MASK (0x10U) +#define ADC_CWENR0_CWEN4_SHIFT (4U) +/*! CWEN4 - Watchdog Enable for Channel 4 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN4_SHIFT)) & ADC_CWENR0_CWEN4_MASK) + +#define ADC_CWENR0_CWEN5_MASK (0x20U) +#define ADC_CWENR0_CWEN5_SHIFT (5U) +/*! CWEN5 - Watchdog Enable for Channel 5 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN5_SHIFT)) & ADC_CWENR0_CWEN5_MASK) + +#define ADC_CWENR0_CWEN6_MASK (0x40U) +#define ADC_CWENR0_CWEN6_SHIFT (6U) +/*! CWEN6 - Watchdog Enable for Channel 6 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN6_SHIFT)) & ADC_CWENR0_CWEN6_MASK) + +#define ADC_CWENR0_CWEN7_MASK (0x80U) +#define ADC_CWENR0_CWEN7_SHIFT (7U) +/*! CWEN7 - Watchdog Enable for Channel 7 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN7_SHIFT)) & ADC_CWENR0_CWEN7_MASK) +/*! @} */ + +/*! @name CWENR1 - Channel Watchdog Enable 1 */ +/*! @{ */ + +#define ADC_CWENR1_CWEN32_MASK (0x1U) +#define ADC_CWENR1_CWEN32_SHIFT (0U) +/*! CWEN32 - Watchdog Enable for Channel 32 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN32_SHIFT)) & ADC_CWENR1_CWEN32_MASK) + +#define ADC_CWENR1_CWEN33_MASK (0x2U) +#define ADC_CWENR1_CWEN33_SHIFT (1U) +/*! CWEN33 - Watchdog Enable for Channel 33 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN33_SHIFT)) & ADC_CWENR1_CWEN33_MASK) + +#define ADC_CWENR1_CWEN34_MASK (0x4U) +#define ADC_CWENR1_CWEN34_SHIFT (2U) +/*! CWEN34 - Watchdog Enable for Channel 34 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN34_SHIFT)) & ADC_CWENR1_CWEN34_MASK) + +#define ADC_CWENR1_CWEN35_MASK (0x8U) +#define ADC_CWENR1_CWEN35_SHIFT (3U) +/*! CWEN35 - Watchdog Enable for Channel 35 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN35_SHIFT)) & ADC_CWENR1_CWEN35_MASK) + +#define ADC_CWENR1_CWEN36_MASK (0x10U) +#define ADC_CWENR1_CWEN36_SHIFT (4U) +/*! CWEN36 - Watchdog Enable for Channel 36 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN36_SHIFT)) & ADC_CWENR1_CWEN36_MASK) + +#define ADC_CWENR1_CWEN37_MASK (0x20U) +#define ADC_CWENR1_CWEN37_SHIFT (5U) +/*! CWEN37 - Watchdog Enable for Channel 37 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN37_SHIFT)) & ADC_CWENR1_CWEN37_MASK) + +#define ADC_CWENR1_CWEN38_MASK (0x40U) +#define ADC_CWENR1_CWEN38_SHIFT (6U) +/*! CWEN38 - Watchdog Enable for Channel 38 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN38_SHIFT)) & ADC_CWENR1_CWEN38_MASK) + +#define ADC_CWENR1_CWEN39_MASK (0x80U) +#define ADC_CWENR1_CWEN39_SHIFT (7U) +/*! CWEN39 - Watchdog Enable for Channel 39 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN39_SHIFT)) & ADC_CWENR1_CWEN39_MASK) +/*! @} */ + +/*! @name AWORR0 - Analog Watchdog Out of Range 0 */ +/*! @{ */ + +#define ADC_AWORR0_AWOR_CH0_MASK (0x1U) +#define ADC_AWORR0_AWOR_CH0_SHIFT (0U) +/*! AWOR_CH0 - Analog Watchdog Out of Range for Channel 0 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH0_SHIFT)) & ADC_AWORR0_AWOR_CH0_MASK) + +#define ADC_AWORR0_AWOR_CH1_MASK (0x2U) +#define ADC_AWORR0_AWOR_CH1_SHIFT (1U) +/*! AWOR_CH1 - Analog Watchdog Out of Range for Channel 1 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH1_SHIFT)) & ADC_AWORR0_AWOR_CH1_MASK) + +#define ADC_AWORR0_AWOR_CH2_MASK (0x4U) +#define ADC_AWORR0_AWOR_CH2_SHIFT (2U) +/*! AWOR_CH2 - Analog Watchdog Out of Range for Channel 2 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH2_SHIFT)) & ADC_AWORR0_AWOR_CH2_MASK) + +#define ADC_AWORR0_AWOR_CH3_MASK (0x8U) +#define ADC_AWORR0_AWOR_CH3_SHIFT (3U) +/*! AWOR_CH3 - Analog Watchdog Out of Range for Channel 3 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH3_SHIFT)) & ADC_AWORR0_AWOR_CH3_MASK) + +#define ADC_AWORR0_AWOR_CH4_MASK (0x10U) +#define ADC_AWORR0_AWOR_CH4_SHIFT (4U) +/*! AWOR_CH4 - Analog Watchdog Out of Range for Channel 4 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH4_SHIFT)) & ADC_AWORR0_AWOR_CH4_MASK) + +#define ADC_AWORR0_AWOR_CH5_MASK (0x20U) +#define ADC_AWORR0_AWOR_CH5_SHIFT (5U) +/*! AWOR_CH5 - Analog Watchdog Out of Range for Channel 5 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH5_SHIFT)) & ADC_AWORR0_AWOR_CH5_MASK) + +#define ADC_AWORR0_AWOR_CH6_MASK (0x40U) +#define ADC_AWORR0_AWOR_CH6_SHIFT (6U) +/*! AWOR_CH6 - Analog Watchdog Out of Range for Channel 6 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH6_SHIFT)) & ADC_AWORR0_AWOR_CH6_MASK) + +#define ADC_AWORR0_AWOR_CH7_MASK (0x80U) +#define ADC_AWORR0_AWOR_CH7_SHIFT (7U) +/*! AWOR_CH7 - Analog Watchdog Out of Range for Channel 7 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH7_SHIFT)) & ADC_AWORR0_AWOR_CH7_MASK) +/*! @} */ + +/*! @name AWORR1 - Analog Watchdog Out of Range 1 */ +/*! @{ */ + +#define ADC_AWORR1_AWOR_CH32_MASK (0x1U) +#define ADC_AWORR1_AWOR_CH32_SHIFT (0U) +/*! AWOR_CH32 - Analog Watchdog Out of Range for Channel 32 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH32_SHIFT)) & ADC_AWORR1_AWOR_CH32_MASK) + +#define ADC_AWORR1_AWOR_CH33_MASK (0x2U) +#define ADC_AWORR1_AWOR_CH33_SHIFT (1U) +/*! AWOR_CH33 - Analog Watchdog Out of Range for Channel 33 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH33_SHIFT)) & ADC_AWORR1_AWOR_CH33_MASK) + +#define ADC_AWORR1_AWOR_CH34_MASK (0x4U) +#define ADC_AWORR1_AWOR_CH34_SHIFT (2U) +/*! AWOR_CH34 - Analog Watchdog Out of Range for Channel 34 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH34_SHIFT)) & ADC_AWORR1_AWOR_CH34_MASK) + +#define ADC_AWORR1_AWOR_CH35_MASK (0x8U) +#define ADC_AWORR1_AWOR_CH35_SHIFT (3U) +/*! AWOR_CH35 - Analog Watchdog Out of Range for Channel 35 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH35_SHIFT)) & ADC_AWORR1_AWOR_CH35_MASK) + +#define ADC_AWORR1_AWOR_CH36_MASK (0x10U) +#define ADC_AWORR1_AWOR_CH36_SHIFT (4U) +/*! AWOR_CH36 - Analog Watchdog Out of Range for Channel 36 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH36_SHIFT)) & ADC_AWORR1_AWOR_CH36_MASK) + +#define ADC_AWORR1_AWOR_CH37_MASK (0x20U) +#define ADC_AWORR1_AWOR_CH37_SHIFT (5U) +/*! AWOR_CH37 - Analog Watchdog Out of Range for Channel 37 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH37_SHIFT)) & ADC_AWORR1_AWOR_CH37_MASK) + +#define ADC_AWORR1_AWOR_CH38_MASK (0x40U) +#define ADC_AWORR1_AWOR_CH38_SHIFT (6U) +/*! AWOR_CH38 - Analog Watchdog Out of Range for Channel 38 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH38_SHIFT)) & ADC_AWORR1_AWOR_CH38_MASK) + +#define ADC_AWORR1_AWOR_CH39_MASK (0x80U) +#define ADC_AWORR1_AWOR_CH39_SHIFT (7U) +/*! AWOR_CH39 - Analog Watchdog Out of Range for Channel 39 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH39_SHIFT)) & ADC_AWORR1_AWOR_CH39_MASK) +/*! @} */ + +/*! @name STCR1 - Self-Test Configuration 1 */ +/*! @{ */ + +#define ADC_STCR1_INPSAMP_S_MASK (0xFF00U) +#define ADC_STCR1_INPSAMP_S_SHIFT (8U) +/*! INPSAMP_S - Sampling Configuration for Algorithm S */ +#define ADC_STCR1_INPSAMP_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_S_SHIFT)) & ADC_STCR1_INPSAMP_S_MASK) + +#define ADC_STCR1_INPSAMP_C_MASK (0xFF000000U) +#define ADC_STCR1_INPSAMP_C_SHIFT (24U) +/*! INPSAMP_C - Sampling Configuration for Algorithm C */ +#define ADC_STCR1_INPSAMP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_C_SHIFT)) & ADC_STCR1_INPSAMP_C_MASK) +/*! @} */ + +/*! @name STCR2 - Self-Test Configuration 2 */ +/*! @{ */ + +#define ADC_STCR2_FMA_S_MASK (0x1U) +#define ADC_STCR2_FMA_S_SHIFT (0U) +/*! FMA_S - Fault Mapping for BGAP Algorithm + * 0b0..NCF + * 0b1..CF + */ +#define ADC_STCR2_FMA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_S_SHIFT)) & ADC_STCR2_FMA_S_MASK) + +#define ADC_STCR2_FMA_C_MASK (0x4U) +#define ADC_STCR2_FMA_C_SHIFT (2U) +/*! FMA_C - Fault Mapping for Algorithm C + * 0b0..NCF + * 0b1..CF + */ +#define ADC_STCR2_FMA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_C_SHIFT)) & ADC_STCR2_FMA_C_MASK) + +#define ADC_STCR2_FMA_WDTERR_MASK (0x8U) +#define ADC_STCR2_FMA_WDTERR_SHIFT (3U) +/*! FMA_WDTERR - Fault Mapping for Watchdog Timer Error + * 0b0..NCF + * 0b1..CF + */ +#define ADC_STCR2_FMA_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDTERR_SHIFT)) & ADC_STCR2_FMA_WDTERR_MASK) + +#define ADC_STCR2_FMA_WDSERR_MASK (0x10U) +#define ADC_STCR2_FMA_WDSERR_SHIFT (4U) +/*! FMA_WDSERR - Fault Mapping for Watchdog Sequence Error + * 0b0..NCF mapping + * 0b1..CF mapping + */ +#define ADC_STCR2_FMA_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDSERR_SHIFT)) & ADC_STCR2_FMA_WDSERR_MASK) + +#define ADC_STCR2_EN_MASK (0x80U) +#define ADC_STCR2_EN_SHIFT (7U) +/*! EN - Self-Testing Channel Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ADC_STCR2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_EN_SHIFT)) & ADC_STCR2_EN_MASK) + +#define ADC_STCR2_MSKERR_S0_MASK (0x800U) +#define ADC_STCR2_MSKERR_S0_SHIFT (11U) +/*! MSKERR_S0 - Error on Algorithm S0 Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S0_SHIFT)) & ADC_STCR2_MSKERR_S0_MASK) + +#define ADC_STCR2_MSKERR_S1_MASK (0x1000U) +#define ADC_STCR2_MSKERR_S1_SHIFT (12U) +/*! MSKERR_S1 - Error on Algorithm S1 Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S1_SHIFT)) & ADC_STCR2_MSKERR_S1_MASK) + +#define ADC_STCR2_MSKERR_S2_MASK (0x2000U) +#define ADC_STCR2_MSKERR_S2_SHIFT (13U) +/*! MSKERR_S2 - Error on Algorithm S2 Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S2_SHIFT)) & ADC_STCR2_MSKERR_S2_MASK) + +#define ADC_STCR2_MSKERR_C_MASK (0x8000U) +#define ADC_STCR2_MSKERR_C_SHIFT (15U) +/*! MSKERR_C - Error on Algorithm C Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_C_SHIFT)) & ADC_STCR2_MSKERR_C_MASK) + +#define ADC_STCR2_MSKWDG_EOA_S_MASK (0x10000U) +#define ADC_STCR2_MSKWDG_EOA_S_SHIFT (16U) +/*! MSKWDG_EOA_S - End of Algorithm S Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_S_SHIFT)) & ADC_STCR2_MSKWDG_EOA_S_MASK) + +#define ADC_STCR2_MSKWDG_EOA_C_MASK (0x40000U) +#define ADC_STCR2_MSKWDG_EOA_C_SHIFT (18U) +/*! MSKWDG_EOA_C - End of Algorithm C Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_C_SHIFT)) & ADC_STCR2_MSKWDG_EOA_C_MASK) + +#define ADC_STCR2_MSKST_EOC_MASK (0x800000U) +#define ADC_STCR2_MSKST_EOC_SHIFT (23U) +/*! MSKST_EOC - Self-Test EOC Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKST_EOC_SHIFT)) & ADC_STCR2_MSKST_EOC_MASK) + +#define ADC_STCR2_MSKWDTERR_MASK (0x2000000U) +#define ADC_STCR2_MSKWDTERR_SHIFT (25U) +/*! MSKWDTERR - Watchdog Timer Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDTERR_SHIFT)) & ADC_STCR2_MSKWDTERR_MASK) + +#define ADC_STCR2_SERR_MASK (0x4000000U) +#define ADC_STCR2_SERR_SHIFT (26U) +/*! SERR - Error Fault Injection Field (write-only) */ +#define ADC_STCR2_SERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_SERR_SHIFT)) & ADC_STCR2_SERR_MASK) + +#define ADC_STCR2_MSKWDSERR_MASK (0x8000000U) +#define ADC_STCR2_MSKWDSERR_SHIFT (27U) +/*! MSKWDSERR - Watchdog Sequence Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDSERR_SHIFT)) & ADC_STCR2_MSKWDSERR_MASK) +/*! @} */ + +/*! @name STCR3 - Self-Test Configuration 3 */ +/*! @{ */ + +#define ADC_STCR3_MSTEP_MASK (0x1FU) +#define ADC_STCR3_MSTEP_SHIFT (0U) +/*! MSTEP - Self-Test Step Select */ +#define ADC_STCR3_MSTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_MSTEP_SHIFT)) & ADC_STCR3_MSTEP_MASK) + +#define ADC_STCR3_ALG_MASK (0x300U) +#define ADC_STCR3_ALG_SHIFT (8U) +/*! ALG - Self-Test Algorithm Select + * 0b00..Algorithm S + * 0b01..Reserved + * 0b10..Algorithm C + * 0b11..Algorithm S (for One-Shot Operation mode); Algorithm S + C (for Scan Operation mode) + */ +#define ADC_STCR3_ALG(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_ALG_SHIFT)) & ADC_STCR3_ALG_MASK) +/*! @} */ + +/*! @name STBRR - Self-Test Baud Rate */ +/*! @{ */ + +#define ADC_STBRR_BR_MASK (0xFFU) +#define ADC_STBRR_BR_SHIFT (0U) +/*! BR - Algorithm Baud Rate */ +#define ADC_STBRR_BR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_BR_SHIFT)) & ADC_STBRR_BR_MASK) + +#define ADC_STBRR_WDT_MASK (0x70000U) +#define ADC_STBRR_WDT_SHIFT (16U) +/*! WDT - Watchdog Timer Value + * 0b000..0.1 ms ((0008h * Prescaler) cycles at 80 MHz) + * 0b001..0.5 ms ((0027h * Prescaler) cycles at 80 MHz) + * 0b010..1 ms ((004Eh * Prescaler) cycles at 80 MHz) + * 0b011..2 ms ((009Ch * Prescaler) cycles at 80 MHz) + * 0b100..5 ms ((0187h * Prescaler) cycles at 80 MHz) + * 0b101..10 ms ((030Dh * Prescaler) cycles at 80 MHz) + * 0b110..20 ms (061Ah * Prescaler) cycles at 80 MHz) + * 0b111..50 ms (0F42h *Prescaler) cycles at 80 MHz) + */ +#define ADC_STBRR_WDT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_WDT_SHIFT)) & ADC_STBRR_WDT_MASK) +/*! @} */ + +/*! @name STSR1 - Self-Test Status 1 */ +/*! @{ */ + +#define ADC_STSR1_STEP_C_MASK (0x3E0U) +#define ADC_STSR1_STEP_C_SHIFT (5U) +/*! STEP_C - Algorithm C Step Number Error */ +#define ADC_STSR1_STEP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_STEP_C_SHIFT)) & ADC_STSR1_STEP_C_MASK) + +#define ADC_STSR1_ERR_S0_MASK (0x800U) +#define ADC_STSR1_ERR_S0_SHIFT (11U) +/*! ERR_S0 - Algorithm S0 Error + * 0b0..No VREF error + * 0b0..No effect + * 0b1..VREF error occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S0_SHIFT)) & ADC_STSR1_ERR_S0_MASK) + +#define ADC_STSR1_ERR_S1_MASK (0x1000U) +#define ADC_STSR1_ERR_S1_SHIFT (12U) +/*! ERR_S1 - Algorithm S1 Error + * 0b0..No VDD ERROR + * 0b0..No effect + * 0b1..VDD ERROR occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S1_SHIFT)) & ADC_STSR1_ERR_S1_MASK) + +#define ADC_STSR1_ERR_S2_MASK (0x2000U) +#define ADC_STSR1_ERR_S2_SHIFT (13U) +/*! ERR_S2 - Algorithm S2 Error + * 0b0..No error occurred on the sampled signal + * 0b0..No effect + * 0b1..Error occurred on the sampled signal + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S2_SHIFT)) & ADC_STSR1_ERR_S2_MASK) + +#define ADC_STSR1_ERR_C_MASK (0x8000U) +#define ADC_STSR1_ERR_C_SHIFT (15U) +/*! ERR_C - Algorithm C Error + * 0b0..No Algorithm C error + * 0b0..No effect + * 0b1..Algorithm C error occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_C_SHIFT)) & ADC_STSR1_ERR_C_MASK) + +#define ADC_STSR1_WDG_EOA_S_MASK (0x10000U) +#define ADC_STSR1_WDG_EOA_S_SHIFT (16U) +/*! WDG_EOA_S - Watchdog End of Algorithm S + * 0b0..Self-test end of Algorithm S conversion is not complete. + * 0b0..No effect + * 0b1..Self-test end of Algorithm S conversion is complete. + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_S_SHIFT)) & ADC_STSR1_WDG_EOA_S_MASK) + +#define ADC_STSR1_WDG_EOA_C_MASK (0x40000U) +#define ADC_STSR1_WDG_EOA_C_SHIFT (18U) +/*! WDG_EOA_C - Watchdog End of Algorithm C + * 0b0..Self-test end of Algorithm C conversion is not complete + * 0b0..No effect + * 0b1..Self-test end of Algorithm C conversion is complete + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_C_SHIFT)) & ADC_STSR1_WDG_EOA_C_MASK) + +#define ADC_STSR1_ST_EOC_MASK (0x800000U) +#define ADC_STSR1_ST_EOC_SHIFT (23U) +/*! ST_EOC - Self-Test EOC + * 0b0..Self-test end of conversion is not complete + * 0b0..No effect + * 0b1..Self-test end of conversion is complete + * 0b1..Clear the flag + */ +#define ADC_STSR1_ST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ST_EOC_SHIFT)) & ADC_STSR1_ST_EOC_MASK) + +#define ADC_STSR1_OVERWR_MASK (0x1000000U) +#define ADC_STSR1_OVERWR_SHIFT (24U) +/*! OVERWR - Overwrite Error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Overwrite error occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_OVERWR_SHIFT)) & ADC_STSR1_OVERWR_MASK) + +#define ADC_STSR1_WDTERR_MASK (0x2000000U) +#define ADC_STSR1_WDTERR_SHIFT (25U) +/*! WDTERR - Watchdog Timer Error + * 0b0..No failure + * 0b0..No effect + * 0b1..Failure occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDTERR_SHIFT)) & ADC_STSR1_WDTERR_MASK) + +#define ADC_STSR1_WDSERR_MASK (0x8000000U) +#define ADC_STSR1_WDSERR_SHIFT (27U) +/*! WDSERR - Watchdog Sequence Errors + * 0b0..No failure + * 0b0..No effect + * 0b1..Failure occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDSERR_SHIFT)) & ADC_STSR1_WDSERR_MASK) +/*! @} */ + +/*! @name STSR2 - Self-Test Status 2 */ +/*! @{ */ + +#define ADC_STSR2_DATA0_MASK (0xFFFU) +#define ADC_STSR2_DATA0_SHIFT (0U) +/*! DATA0 - Test Channel Converted Data when ERR_S1 Occurred */ +#define ADC_STSR2_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA0_SHIFT)) & ADC_STSR2_DATA0_MASK) + +#define ADC_STSR2_DATA1_MASK (0xFFF0000U) +#define ADC_STSR2_DATA1_SHIFT (16U) +/*! DATA1 - Test Channel Converted Data when ERR_S1 Occurred */ +#define ADC_STSR2_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA1_SHIFT)) & ADC_STSR2_DATA1_MASK) + +#define ADC_STSR2_OVFL_MASK (0x80000000U) +#define ADC_STSR2_OVFL_SHIFT (31U) +/*! OVFL - Overflow Bit + * 0b0..Not overflow + * 0b1..Overflow + */ +#define ADC_STSR2_OVFL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_OVFL_SHIFT)) & ADC_STSR2_OVFL_MASK) +/*! @} */ + +/*! @name STSR3 - Self-Test Status 3 */ +/*! @{ */ + +#define ADC_STSR3_DATA0_MASK (0xFFFU) +#define ADC_STSR3_DATA0_SHIFT (0U) +/*! DATA0 - Test Channel Converted Data when ERR_S0 Occurred */ +#define ADC_STSR3_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA0_SHIFT)) & ADC_STSR3_DATA0_MASK) + +#define ADC_STSR3_DATA1_MASK (0xFFF0000U) +#define ADC_STSR3_DATA1_SHIFT (16U) +/*! DATA1 - Test Channel Converted Data when ERR_C Occurred */ +#define ADC_STSR3_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA1_SHIFT)) & ADC_STSR3_DATA1_MASK) +/*! @} */ + +/*! @name STSR4 - Self-Test Status 4 */ +/*! @{ */ + +#define ADC_STSR4_DATA1_MASK (0xFFF0000U) +#define ADC_STSR4_DATA1_SHIFT (16U) +/*! DATA1 - Test Channel Converted Data When ERR_C Occurred */ +#define ADC_STSR4_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR4_DATA1_SHIFT)) & ADC_STSR4_DATA1_MASK) +/*! @} */ + +/*! @name STDR1 - Self-Test Data 1 */ +/*! @{ */ + +#define ADC_STDR1_TCDATA_MASK (0xFFFU) +#define ADC_STDR1_TCDATA_SHIFT (0U) +/*! TCDATA - Test Channel Converted Data */ +#define ADC_STDR1_TCDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_TCDATA_SHIFT)) & ADC_STDR1_TCDATA_MASK) + +#define ADC_STDR1_OWERWR_MASK (0x40000U) +#define ADC_STDR1_OWERWR_SHIFT (18U) +/*! OWERWR - Overwrite Data + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_STDR1_OWERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_OWERWR_SHIFT)) & ADC_STDR1_OWERWR_MASK) + +#define ADC_STDR1_VALID_MASK (0x80000U) +#define ADC_STDR1_VALID_SHIFT (19U) +/*! VALID - Valid Data + * 0b0..Data not valid + * 0b1..Data valid + */ +#define ADC_STDR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_VALID_SHIFT)) & ADC_STDR1_VALID_MASK) +/*! @} */ + +/*! @name STDR2 - Self-Test Data 2 */ +/*! @{ */ + +#define ADC_STDR2_IDATA_MASK (0xFFFU) +#define ADC_STDR2_IDATA_SHIFT (0U) +/*! IDATA - Integer Data */ +#define ADC_STDR2_IDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_IDATA_SHIFT)) & ADC_STDR2_IDATA_MASK) + +#define ADC_STDR2_OVERWR_MASK (0x40000U) +#define ADC_STDR2_OVERWR_SHIFT (18U) +/*! OVERWR - Overwrite Data + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_STDR2_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_OVERWR_SHIFT)) & ADC_STDR2_OVERWR_MASK) + +#define ADC_STDR2_VALID_MASK (0x80000U) +#define ADC_STDR2_VALID_SHIFT (19U) +/*! VALID - Valid Data + * 0b0..Data not valid + * 0b1..Data valid + */ +#define ADC_STDR2_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_VALID_SHIFT)) & ADC_STDR2_VALID_MASK) + +#define ADC_STDR2_FDATA_MASK (0xFFF00000U) +#define ADC_STDR2_FDATA_SHIFT (20U) +/*! FDATA - Fractional Data */ +#define ADC_STDR2_FDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_FDATA_SHIFT)) & ADC_STDR2_FDATA_MASK) +/*! @} */ + +/*! @name STAW0R - Self-Test Analog Watchdog 0 */ +/*! @{ */ + +#define ADC_STAW0R_THRL_MASK (0xFFFU) +#define ADC_STAW0R_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Algorithm S Step0 */ +#define ADC_STAW0R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRL_SHIFT)) & ADC_STAW0R_THRL_MASK) + +#define ADC_STAW0R_THRH_MASK (0xFFF0000U) +#define ADC_STAW0R_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Algorithm S Step0 */ +#define ADC_STAW0R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRH_SHIFT)) & ADC_STAW0R_THRH_MASK) + +#define ADC_STAW0R_WDTE_MASK (0x40000000U) +#define ADC_STAW0R_WDTE_SHIFT (30U) +/*! WDTE - Watchdog Timer Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW0R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_WDTE_SHIFT)) & ADC_STAW0R_WDTE_MASK) + +#define ADC_STAW0R_AWDE_MASK (0x80000000U) +#define ADC_STAW0R_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW0R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_AWDE_SHIFT)) & ADC_STAW0R_AWDE_MASK) +/*! @} */ + +/*! @name STAW1AR - Self-Test Analog Watchdog 1A */ +/*! @{ */ + +#define ADC_STAW1AR_THRL_MASK (0xFFFU) +#define ADC_STAW1AR_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1AR_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRL_SHIFT)) & ADC_STAW1AR_THRL_MASK) + +#define ADC_STAW1AR_THRH_MASK (0xFFF0000U) +#define ADC_STAW1AR_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1AR_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRH_SHIFT)) & ADC_STAW1AR_THRH_MASK) + +#define ADC_STAW1AR_AWDE_MASK (0x80000000U) +#define ADC_STAW1AR_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW1AR_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_AWDE_SHIFT)) & ADC_STAW1AR_AWDE_MASK) +/*! @} */ + +/*! @name STAW1BR - Self-Test Analog Watchdog 1B */ +/*! @{ */ + +#define ADC_STAW1BR_THRL_MASK (0xFFFU) +#define ADC_STAW1BR_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1BR_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRL_SHIFT)) & ADC_STAW1BR_THRL_MASK) + +#define ADC_STAW1BR_THRH_MASK (0xFFF0000U) +#define ADC_STAW1BR_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1BR_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRH_SHIFT)) & ADC_STAW1BR_THRH_MASK) +/*! @} */ + +/*! @name STAW2R - Self-Test Analog Watchdog 2 */ +/*! @{ */ + +#define ADC_STAW2R_THRL_MASK (0xFFFU) +#define ADC_STAW2R_THRL_SHIFT (0U) +/*! THRL - Threshold level low */ +#define ADC_STAW2R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_THRL_SHIFT)) & ADC_STAW2R_THRL_MASK) + +#define ADC_STAW2R_AWDE_MASK (0x80000000U) +#define ADC_STAW2R_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW2R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_AWDE_SHIFT)) & ADC_STAW2R_AWDE_MASK) +/*! @} */ + +/*! @name STAW4R - Self-Test Analog Watchdog 4 */ +/*! @{ */ + +#define ADC_STAW4R_THRL_MASK (0xFFFU) +#define ADC_STAW4R_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Step0 of Algorithm C */ +#define ADC_STAW4R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRL_SHIFT)) & ADC_STAW4R_THRL_MASK) + +#define ADC_STAW4R_THRH_MASK (0xFFF0000U) +#define ADC_STAW4R_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Step0 of Algorithm C */ +#define ADC_STAW4R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRH_SHIFT)) & ADC_STAW4R_THRH_MASK) + +#define ADC_STAW4R_WDTE_MASK (0x40000000U) +#define ADC_STAW4R_WDTE_SHIFT (30U) +/*! WDTE - Watchdog Timer Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW4R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_WDTE_SHIFT)) & ADC_STAW4R_WDTE_MASK) + +#define ADC_STAW4R_AWDE_MASK (0x80000000U) +#define ADC_STAW4R_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW4R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_AWDE_SHIFT)) & ADC_STAW4R_AWDE_MASK) +/*! @} */ + +/*! @name STAW5R - Self-Test Analog Watchdog 5 */ +/*! @{ */ + +#define ADC_STAW5R_THRL_MASK (0xFFFU) +#define ADC_STAW5R_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Step0 of Algorithm C */ +#define ADC_STAW5R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRL_SHIFT)) & ADC_STAW5R_THRL_MASK) + +#define ADC_STAW5R_THRH_MASK (0xFFF0000U) +#define ADC_STAW5R_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Step N of Algorithm C */ +#define ADC_STAW5R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRH_SHIFT)) & ADC_STAW5R_THRH_MASK) +/*! @} */ + +/*! @name CALSTAT - Calibration Status */ +/*! @{ */ + +#define ADC_CALSTAT_STAT_1_MASK (0x1U) +#define ADC_CALSTAT_STAT_1_SHIFT (0U) +/*! STAT_1 - Status of Calibration Step 1 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_1_SHIFT)) & ADC_CALSTAT_STAT_1_MASK) + +#define ADC_CALSTAT_STAT_2_MASK (0x2U) +#define ADC_CALSTAT_STAT_2_SHIFT (1U) +/*! STAT_2 - Status of Calibration Step 2 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_2_SHIFT)) & ADC_CALSTAT_STAT_2_MASK) + +#define ADC_CALSTAT_STAT_3_MASK (0x4U) +#define ADC_CALSTAT_STAT_3_SHIFT (2U) +/*! STAT_3 - Status of Calibration Step 3 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_3_SHIFT)) & ADC_CALSTAT_STAT_3_MASK) + +#define ADC_CALSTAT_STAT_4_MASK (0x8U) +#define ADC_CALSTAT_STAT_4_SHIFT (3U) +/*! STAT_4 - Status of calibration step 4 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_4_SHIFT)) & ADC_CALSTAT_STAT_4_MASK) + +#define ADC_CALSTAT_STAT_5_MASK (0x10U) +#define ADC_CALSTAT_STAT_5_SHIFT (4U) +/*! STAT_5 - Status of Calibration Step 5 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_5_SHIFT)) & ADC_CALSTAT_STAT_5_MASK) + +#define ADC_CALSTAT_STAT_6_MASK (0x20U) +#define ADC_CALSTAT_STAT_6_SHIFT (5U) +/*! STAT_6 - Status of Calibration Step 6 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_6_SHIFT)) & ADC_CALSTAT_STAT_6_MASK) + +#define ADC_CALSTAT_STAT_7_MASK (0x40U) +#define ADC_CALSTAT_STAT_7_SHIFT (6U) +/*! STAT_7 - Status of Calibration Step 7 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_7_SHIFT)) & ADC_CALSTAT_STAT_7_MASK) + +#define ADC_CALSTAT_STAT_8_MASK (0x80U) +#define ADC_CALSTAT_STAT_8_SHIFT (7U) +/*! STAT_8 - Status of Calibration Step 8 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_8_SHIFT)) & ADC_CALSTAT_STAT_8_MASK) + +#define ADC_CALSTAT_STAT_9_MASK (0x100U) +#define ADC_CALSTAT_STAT_9_SHIFT (8U) +/*! STAT_9 - Status of Calibration Step 9 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_9_SHIFT)) & ADC_CALSTAT_STAT_9_MASK) + +#define ADC_CALSTAT_STAT_10_MASK (0x200U) +#define ADC_CALSTAT_STAT_10_SHIFT (9U) +/*! STAT_10 - Status of Calibration Step 10 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_10_SHIFT)) & ADC_CALSTAT_STAT_10_MASK) + +#define ADC_CALSTAT_STAT_11_MASK (0x400U) +#define ADC_CALSTAT_STAT_11_SHIFT (10U) +/*! STAT_11 - Status of Calibration Step 11 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_11_SHIFT)) & ADC_CALSTAT_STAT_11_MASK) + +#define ADC_CALSTAT_STAT_12_MASK (0x800U) +#define ADC_CALSTAT_STAT_12_SHIFT (11U) +/*! STAT_12 - Status of Calibration Step 12 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_12_SHIFT)) & ADC_CALSTAT_STAT_12_MASK) + +#define ADC_CALSTAT_TEST_RESULT_MASK (0xFFFF0000U) +#define ADC_CALSTAT_TEST_RESULT_SHIFT (16U) +/*! TEST_RESULT - TEST_RESULT */ +#define ADC_CALSTAT_TEST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_TEST_RESULT_SHIFT)) & ADC_CALSTAT_TEST_RESULT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x44530000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC1 } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANA_OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANA_OSC_Peripheral_Access_Layer ANA_OSC Peripheral Access Layer + * @{ + */ + +/** ANA_OSC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __I uint32_t DIGPROG_DEVICE_ID; /**< Device ID, offset: 0x800 */ +} ANA_OSC_Type; + +/* ---------------------------------------------------------------------------- + -- ANA_OSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANA_OSC_Register_Masks ANA_OSC Register Masks + * @{ + */ + +/*! @name DIGPROG_DEVICE_ID - Device ID */ +/*! @{ */ + +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_MASK (0xFFU) +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_SHIFT (0U) +/*! DIGPROG_MINOR - Bit[3:0] is the metal layer revision. Bit[7:4] is the base layer revision. */ +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_SHIFT)) & ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_MASK) + +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_SHIFT (8U) +/*! DIGPROG_MAJOR_LOWER - DIGPROG_MAJOR_LOWER */ +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_SHIFT)) & ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_MASK) + +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_SHIFT (16U) +/*! DIGPROG_MAJOR_UPPER - DIGPROG_MAJOR_UPPER */ +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_SHIFT)) & ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANA_OSC_Register_Masks */ + + +/* ANA_OSC - Peripheral instance base addresses */ +/** Peripheral ANA_OSC base address */ +#define ANA_OSC_BASE (0x44480000u) +/** Peripheral ANA_OSC base pointer */ +#define ANA_OSC ((ANA_OSC_Type *)ANA_OSC_BASE) +/** Array initializer of ANA_OSC peripheral base addresses */ +#define ANA_OSC_BASE_ADDRS { ANA_OSC_BASE } +/** Array initializer of ANA_OSC peripheral base pointers */ +#define ANA_OSC_BASE_PTRS { ANA_OSC } + +/*! + * @} + */ /* end of group ANA_OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer + * @{ + */ + +/** AXBS - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRS0; /**< Priority Slave Registers, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CRS0; /**< Control Register, offset: 0x10 */ + uint8_t RESERVED_1[236]; + __IO uint32_t PRS1; /**< Priority Slave Registers, offset: 0x100 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CRS1; /**< Control Register, offset: 0x110 */ + uint8_t RESERVED_3[236]; + __IO uint32_t PRS2; /**< Priority Slave Registers, offset: 0x200 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CRS2; /**< Control Register, offset: 0x210 */ + uint8_t RESERVED_5[236]; + __IO uint32_t PRS3; /**< Priority Slave Registers, offset: 0x300 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CRS3; /**< Control Register, offset: 0x310 */ + uint8_t RESERVED_7[236]; + __IO uint32_t PRS4; /**< Priority Slave Registers, offset: 0x400 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CRS4; /**< Control Register, offset: 0x410 */ + uint8_t RESERVED_9[236]; + __IO uint32_t PRS5; /**< Priority Slave Registers, offset: 0x500 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CRS5; /**< Control Register, offset: 0x510 */ + uint8_t RESERVED_11[236]; + __IO uint32_t PRS6; /**< Priority Slave Registers, offset: 0x600 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CRS6; /**< Control Register, offset: 0x610 */ + uint8_t RESERVED_13[236]; + __IO uint32_t PRS7; /**< Priority Slave Registers, offset: 0x700 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CRS7; /**< Control Register, offset: 0x710 */ + uint8_t RESERVED_15[236]; + __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + uint8_t RESERVED_16[252]; + __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + uint8_t RESERVED_17[252]; + __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + uint8_t RESERVED_18[252]; + __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ + uint8_t RESERVED_19[252]; + __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + uint8_t RESERVED_20[252]; + __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ + uint8_t RESERVED_21[252]; + __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */ + uint8_t RESERVED_22[252]; + __IO uint32_t MGPCR7; /**< Master General Purpose Control Register, offset: 0xF00 */ +} AXBS_Type; + +/* ---------------------------------------------------------------------------- + -- AXBS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Register_Masks AXBS Register Masks + * @{ + */ + +/*! @name PRS0 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS0_M0_MASK (0x7U) +#define AXBS_PRS0_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M0_SHIFT)) & AXBS_PRS0_M0_MASK) + +#define AXBS_PRS0_M1_MASK (0x70U) +#define AXBS_PRS0_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M1_SHIFT)) & AXBS_PRS0_M1_MASK) + +#define AXBS_PRS0_M2_MASK (0x700U) +#define AXBS_PRS0_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M2_SHIFT)) & AXBS_PRS0_M2_MASK) + +#define AXBS_PRS0_M3_MASK (0x7000U) +#define AXBS_PRS0_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M3_SHIFT)) & AXBS_PRS0_M3_MASK) + +#define AXBS_PRS0_M4_MASK (0x70000U) +#define AXBS_PRS0_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M4_SHIFT)) & AXBS_PRS0_M4_MASK) + +#define AXBS_PRS0_M5_MASK (0x700000U) +#define AXBS_PRS0_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M5_SHIFT)) & AXBS_PRS0_M5_MASK) + +#define AXBS_PRS0_M6_MASK (0x7000000U) +#define AXBS_PRS0_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M6_SHIFT)) & AXBS_PRS0_M6_MASK) + +#define AXBS_PRS0_M7_MASK (0x70000000U) +#define AXBS_PRS0_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M7_SHIFT)) & AXBS_PRS0_M7_MASK) +/*! @} */ + +/*! @name CRS0 - Control Register */ +/*! @{ */ + +#define AXBS_CRS0_PARK_MASK (0x7U) +#define AXBS_CRS0_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS0_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PARK_SHIFT)) & AXBS_CRS0_PARK_MASK) + +#define AXBS_CRS0_PCTL_MASK (0x30U) +#define AXBS_CRS0_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS0_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PCTL_SHIFT)) & AXBS_CRS0_PCTL_MASK) + +#define AXBS_CRS0_ARB_MASK (0x300U) +#define AXBS_CRS0_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS0_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_ARB_SHIFT)) & AXBS_CRS0_ARB_MASK) + +#define AXBS_CRS0_HPE0_MASK (0x10000U) +#define AXBS_CRS0_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE0_SHIFT)) & AXBS_CRS0_HPE0_MASK) + +#define AXBS_CRS0_HPE1_MASK (0x20000U) +#define AXBS_CRS0_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE1_SHIFT)) & AXBS_CRS0_HPE1_MASK) + +#define AXBS_CRS0_HPE2_MASK (0x40000U) +#define AXBS_CRS0_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE2_SHIFT)) & AXBS_CRS0_HPE2_MASK) + +#define AXBS_CRS0_HPE3_MASK (0x80000U) +#define AXBS_CRS0_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE3_SHIFT)) & AXBS_CRS0_HPE3_MASK) + +#define AXBS_CRS0_HPE4_MASK (0x100000U) +#define AXBS_CRS0_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE4_SHIFT)) & AXBS_CRS0_HPE4_MASK) + +#define AXBS_CRS0_HPE5_MASK (0x200000U) +#define AXBS_CRS0_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE5_SHIFT)) & AXBS_CRS0_HPE5_MASK) + +#define AXBS_CRS0_HPE6_MASK (0x400000U) +#define AXBS_CRS0_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE6_SHIFT)) & AXBS_CRS0_HPE6_MASK) + +#define AXBS_CRS0_HPE7_MASK (0x800000U) +#define AXBS_CRS0_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE7_SHIFT)) & AXBS_CRS0_HPE7_MASK) + +#define AXBS_CRS0_RO_MASK (0x80000000U) +#define AXBS_CRS0_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS0_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_RO_SHIFT)) & AXBS_CRS0_RO_MASK) +/*! @} */ + +/*! @name PRS1 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS1_M0_MASK (0x7U) +#define AXBS_PRS1_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M0_SHIFT)) & AXBS_PRS1_M0_MASK) + +#define AXBS_PRS1_M1_MASK (0x70U) +#define AXBS_PRS1_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M1_SHIFT)) & AXBS_PRS1_M1_MASK) + +#define AXBS_PRS1_M2_MASK (0x700U) +#define AXBS_PRS1_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M2_SHIFT)) & AXBS_PRS1_M2_MASK) + +#define AXBS_PRS1_M3_MASK (0x7000U) +#define AXBS_PRS1_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M3_SHIFT)) & AXBS_PRS1_M3_MASK) + +#define AXBS_PRS1_M4_MASK (0x70000U) +#define AXBS_PRS1_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M4_SHIFT)) & AXBS_PRS1_M4_MASK) + +#define AXBS_PRS1_M5_MASK (0x700000U) +#define AXBS_PRS1_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M5_SHIFT)) & AXBS_PRS1_M5_MASK) + +#define AXBS_PRS1_M6_MASK (0x7000000U) +#define AXBS_PRS1_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M6_SHIFT)) & AXBS_PRS1_M6_MASK) + +#define AXBS_PRS1_M7_MASK (0x70000000U) +#define AXBS_PRS1_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M7_SHIFT)) & AXBS_PRS1_M7_MASK) +/*! @} */ + +/*! @name CRS1 - Control Register */ +/*! @{ */ + +#define AXBS_CRS1_PARK_MASK (0x7U) +#define AXBS_CRS1_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS1_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PARK_SHIFT)) & AXBS_CRS1_PARK_MASK) + +#define AXBS_CRS1_PCTL_MASK (0x30U) +#define AXBS_CRS1_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS1_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PCTL_SHIFT)) & AXBS_CRS1_PCTL_MASK) + +#define AXBS_CRS1_ARB_MASK (0x300U) +#define AXBS_CRS1_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS1_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_ARB_SHIFT)) & AXBS_CRS1_ARB_MASK) + +#define AXBS_CRS1_HPE0_MASK (0x10000U) +#define AXBS_CRS1_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE0_SHIFT)) & AXBS_CRS1_HPE0_MASK) + +#define AXBS_CRS1_HPE1_MASK (0x20000U) +#define AXBS_CRS1_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE1_SHIFT)) & AXBS_CRS1_HPE1_MASK) + +#define AXBS_CRS1_HPE2_MASK (0x40000U) +#define AXBS_CRS1_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE2_SHIFT)) & AXBS_CRS1_HPE2_MASK) + +#define AXBS_CRS1_HPE3_MASK (0x80000U) +#define AXBS_CRS1_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE3_SHIFT)) & AXBS_CRS1_HPE3_MASK) + +#define AXBS_CRS1_HPE4_MASK (0x100000U) +#define AXBS_CRS1_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE4_SHIFT)) & AXBS_CRS1_HPE4_MASK) + +#define AXBS_CRS1_HPE5_MASK (0x200000U) +#define AXBS_CRS1_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE5_SHIFT)) & AXBS_CRS1_HPE5_MASK) + +#define AXBS_CRS1_HPE6_MASK (0x400000U) +#define AXBS_CRS1_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE6_SHIFT)) & AXBS_CRS1_HPE6_MASK) + +#define AXBS_CRS1_HPE7_MASK (0x800000U) +#define AXBS_CRS1_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE7_SHIFT)) & AXBS_CRS1_HPE7_MASK) + +#define AXBS_CRS1_RO_MASK (0x80000000U) +#define AXBS_CRS1_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS1_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_RO_SHIFT)) & AXBS_CRS1_RO_MASK) +/*! @} */ + +/*! @name PRS2 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS2_M0_MASK (0x7U) +#define AXBS_PRS2_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M0_SHIFT)) & AXBS_PRS2_M0_MASK) + +#define AXBS_PRS2_M1_MASK (0x70U) +#define AXBS_PRS2_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M1_SHIFT)) & AXBS_PRS2_M1_MASK) + +#define AXBS_PRS2_M2_MASK (0x700U) +#define AXBS_PRS2_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M2_SHIFT)) & AXBS_PRS2_M2_MASK) + +#define AXBS_PRS2_M3_MASK (0x7000U) +#define AXBS_PRS2_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M3_SHIFT)) & AXBS_PRS2_M3_MASK) + +#define AXBS_PRS2_M4_MASK (0x70000U) +#define AXBS_PRS2_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M4_SHIFT)) & AXBS_PRS2_M4_MASK) + +#define AXBS_PRS2_M5_MASK (0x700000U) +#define AXBS_PRS2_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M5_SHIFT)) & AXBS_PRS2_M5_MASK) + +#define AXBS_PRS2_M6_MASK (0x7000000U) +#define AXBS_PRS2_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M6_SHIFT)) & AXBS_PRS2_M6_MASK) + +#define AXBS_PRS2_M7_MASK (0x70000000U) +#define AXBS_PRS2_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M7_SHIFT)) & AXBS_PRS2_M7_MASK) +/*! @} */ + +/*! @name CRS2 - Control Register */ +/*! @{ */ + +#define AXBS_CRS2_PARK_MASK (0x7U) +#define AXBS_CRS2_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS2_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PARK_SHIFT)) & AXBS_CRS2_PARK_MASK) + +#define AXBS_CRS2_PCTL_MASK (0x30U) +#define AXBS_CRS2_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS2_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PCTL_SHIFT)) & AXBS_CRS2_PCTL_MASK) + +#define AXBS_CRS2_ARB_MASK (0x300U) +#define AXBS_CRS2_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS2_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_ARB_SHIFT)) & AXBS_CRS2_ARB_MASK) + +#define AXBS_CRS2_HPE0_MASK (0x10000U) +#define AXBS_CRS2_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE0_SHIFT)) & AXBS_CRS2_HPE0_MASK) + +#define AXBS_CRS2_HPE1_MASK (0x20000U) +#define AXBS_CRS2_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE1_SHIFT)) & AXBS_CRS2_HPE1_MASK) + +#define AXBS_CRS2_HPE2_MASK (0x40000U) +#define AXBS_CRS2_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE2_SHIFT)) & AXBS_CRS2_HPE2_MASK) + +#define AXBS_CRS2_HPE3_MASK (0x80000U) +#define AXBS_CRS2_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE3_SHIFT)) & AXBS_CRS2_HPE3_MASK) + +#define AXBS_CRS2_HPE4_MASK (0x100000U) +#define AXBS_CRS2_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE4_SHIFT)) & AXBS_CRS2_HPE4_MASK) + +#define AXBS_CRS2_HPE5_MASK (0x200000U) +#define AXBS_CRS2_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE5_SHIFT)) & AXBS_CRS2_HPE5_MASK) + +#define AXBS_CRS2_HPE6_MASK (0x400000U) +#define AXBS_CRS2_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE6_SHIFT)) & AXBS_CRS2_HPE6_MASK) + +#define AXBS_CRS2_HPE7_MASK (0x800000U) +#define AXBS_CRS2_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE7_SHIFT)) & AXBS_CRS2_HPE7_MASK) + +#define AXBS_CRS2_RO_MASK (0x80000000U) +#define AXBS_CRS2_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS2_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_RO_SHIFT)) & AXBS_CRS2_RO_MASK) +/*! @} */ + +/*! @name PRS3 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS3_M0_MASK (0x7U) +#define AXBS_PRS3_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M0_SHIFT)) & AXBS_PRS3_M0_MASK) + +#define AXBS_PRS3_M1_MASK (0x70U) +#define AXBS_PRS3_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M1_SHIFT)) & AXBS_PRS3_M1_MASK) + +#define AXBS_PRS3_M2_MASK (0x700U) +#define AXBS_PRS3_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M2_SHIFT)) & AXBS_PRS3_M2_MASK) + +#define AXBS_PRS3_M3_MASK (0x7000U) +#define AXBS_PRS3_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M3_SHIFT)) & AXBS_PRS3_M3_MASK) + +#define AXBS_PRS3_M4_MASK (0x70000U) +#define AXBS_PRS3_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M4_SHIFT)) & AXBS_PRS3_M4_MASK) + +#define AXBS_PRS3_M5_MASK (0x700000U) +#define AXBS_PRS3_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M5_SHIFT)) & AXBS_PRS3_M5_MASK) + +#define AXBS_PRS3_M6_MASK (0x7000000U) +#define AXBS_PRS3_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M6_SHIFT)) & AXBS_PRS3_M6_MASK) + +#define AXBS_PRS3_M7_MASK (0x70000000U) +#define AXBS_PRS3_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M7_SHIFT)) & AXBS_PRS3_M7_MASK) +/*! @} */ + +/*! @name CRS3 - Control Register */ +/*! @{ */ + +#define AXBS_CRS3_PARK_MASK (0x7U) +#define AXBS_CRS3_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS3_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PARK_SHIFT)) & AXBS_CRS3_PARK_MASK) + +#define AXBS_CRS3_PCTL_MASK (0x30U) +#define AXBS_CRS3_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS3_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PCTL_SHIFT)) & AXBS_CRS3_PCTL_MASK) + +#define AXBS_CRS3_ARB_MASK (0x300U) +#define AXBS_CRS3_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS3_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_ARB_SHIFT)) & AXBS_CRS3_ARB_MASK) + +#define AXBS_CRS3_HPE0_MASK (0x10000U) +#define AXBS_CRS3_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE0_SHIFT)) & AXBS_CRS3_HPE0_MASK) + +#define AXBS_CRS3_HPE1_MASK (0x20000U) +#define AXBS_CRS3_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE1_SHIFT)) & AXBS_CRS3_HPE1_MASK) + +#define AXBS_CRS3_HPE2_MASK (0x40000U) +#define AXBS_CRS3_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE2_SHIFT)) & AXBS_CRS3_HPE2_MASK) + +#define AXBS_CRS3_HPE3_MASK (0x80000U) +#define AXBS_CRS3_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE3_SHIFT)) & AXBS_CRS3_HPE3_MASK) + +#define AXBS_CRS3_HPE4_MASK (0x100000U) +#define AXBS_CRS3_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE4_SHIFT)) & AXBS_CRS3_HPE4_MASK) + +#define AXBS_CRS3_HPE5_MASK (0x200000U) +#define AXBS_CRS3_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE5_SHIFT)) & AXBS_CRS3_HPE5_MASK) + +#define AXBS_CRS3_HPE6_MASK (0x400000U) +#define AXBS_CRS3_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE6_SHIFT)) & AXBS_CRS3_HPE6_MASK) + +#define AXBS_CRS3_HPE7_MASK (0x800000U) +#define AXBS_CRS3_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE7_SHIFT)) & AXBS_CRS3_HPE7_MASK) + +#define AXBS_CRS3_RO_MASK (0x80000000U) +#define AXBS_CRS3_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS3_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_RO_SHIFT)) & AXBS_CRS3_RO_MASK) +/*! @} */ + +/*! @name PRS4 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS4_M0_MASK (0x7U) +#define AXBS_PRS4_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M0_SHIFT)) & AXBS_PRS4_M0_MASK) + +#define AXBS_PRS4_M1_MASK (0x70U) +#define AXBS_PRS4_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M1_SHIFT)) & AXBS_PRS4_M1_MASK) + +#define AXBS_PRS4_M2_MASK (0x700U) +#define AXBS_PRS4_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M2_SHIFT)) & AXBS_PRS4_M2_MASK) + +#define AXBS_PRS4_M3_MASK (0x7000U) +#define AXBS_PRS4_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M3_SHIFT)) & AXBS_PRS4_M3_MASK) + +#define AXBS_PRS4_M4_MASK (0x70000U) +#define AXBS_PRS4_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M4_SHIFT)) & AXBS_PRS4_M4_MASK) + +#define AXBS_PRS4_M5_MASK (0x700000U) +#define AXBS_PRS4_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M5_SHIFT)) & AXBS_PRS4_M5_MASK) + +#define AXBS_PRS4_M6_MASK (0x7000000U) +#define AXBS_PRS4_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M6_SHIFT)) & AXBS_PRS4_M6_MASK) + +#define AXBS_PRS4_M7_MASK (0x70000000U) +#define AXBS_PRS4_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M7_SHIFT)) & AXBS_PRS4_M7_MASK) +/*! @} */ + +/*! @name CRS4 - Control Register */ +/*! @{ */ + +#define AXBS_CRS4_PARK_MASK (0x7U) +#define AXBS_CRS4_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS4_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PARK_SHIFT)) & AXBS_CRS4_PARK_MASK) + +#define AXBS_CRS4_PCTL_MASK (0x30U) +#define AXBS_CRS4_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS4_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PCTL_SHIFT)) & AXBS_CRS4_PCTL_MASK) + +#define AXBS_CRS4_ARB_MASK (0x300U) +#define AXBS_CRS4_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS4_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_ARB_SHIFT)) & AXBS_CRS4_ARB_MASK) + +#define AXBS_CRS4_HPE0_MASK (0x10000U) +#define AXBS_CRS4_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE0_SHIFT)) & AXBS_CRS4_HPE0_MASK) + +#define AXBS_CRS4_HPE1_MASK (0x20000U) +#define AXBS_CRS4_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE1_SHIFT)) & AXBS_CRS4_HPE1_MASK) + +#define AXBS_CRS4_HPE2_MASK (0x40000U) +#define AXBS_CRS4_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE2_SHIFT)) & AXBS_CRS4_HPE2_MASK) + +#define AXBS_CRS4_HPE3_MASK (0x80000U) +#define AXBS_CRS4_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE3_SHIFT)) & AXBS_CRS4_HPE3_MASK) + +#define AXBS_CRS4_HPE4_MASK (0x100000U) +#define AXBS_CRS4_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE4_SHIFT)) & AXBS_CRS4_HPE4_MASK) + +#define AXBS_CRS4_HPE5_MASK (0x200000U) +#define AXBS_CRS4_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE5_SHIFT)) & AXBS_CRS4_HPE5_MASK) + +#define AXBS_CRS4_HPE6_MASK (0x400000U) +#define AXBS_CRS4_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE6_SHIFT)) & AXBS_CRS4_HPE6_MASK) + +#define AXBS_CRS4_HPE7_MASK (0x800000U) +#define AXBS_CRS4_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE7_SHIFT)) & AXBS_CRS4_HPE7_MASK) + +#define AXBS_CRS4_RO_MASK (0x80000000U) +#define AXBS_CRS4_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS4_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_RO_SHIFT)) & AXBS_CRS4_RO_MASK) +/*! @} */ + +/*! @name PRS5 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS5_M0_MASK (0x7U) +#define AXBS_PRS5_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M0_SHIFT)) & AXBS_PRS5_M0_MASK) + +#define AXBS_PRS5_M1_MASK (0x70U) +#define AXBS_PRS5_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M1_SHIFT)) & AXBS_PRS5_M1_MASK) + +#define AXBS_PRS5_M2_MASK (0x700U) +#define AXBS_PRS5_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M2_SHIFT)) & AXBS_PRS5_M2_MASK) + +#define AXBS_PRS5_M3_MASK (0x7000U) +#define AXBS_PRS5_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M3_SHIFT)) & AXBS_PRS5_M3_MASK) + +#define AXBS_PRS5_M4_MASK (0x70000U) +#define AXBS_PRS5_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M4_SHIFT)) & AXBS_PRS5_M4_MASK) + +#define AXBS_PRS5_M5_MASK (0x700000U) +#define AXBS_PRS5_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M5_SHIFT)) & AXBS_PRS5_M5_MASK) + +#define AXBS_PRS5_M6_MASK (0x7000000U) +#define AXBS_PRS5_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M6_SHIFT)) & AXBS_PRS5_M6_MASK) + +#define AXBS_PRS5_M7_MASK (0x70000000U) +#define AXBS_PRS5_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M7_SHIFT)) & AXBS_PRS5_M7_MASK) +/*! @} */ + +/*! @name CRS5 - Control Register */ +/*! @{ */ + +#define AXBS_CRS5_PARK_MASK (0x7U) +#define AXBS_CRS5_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS5_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PARK_SHIFT)) & AXBS_CRS5_PARK_MASK) + +#define AXBS_CRS5_PCTL_MASK (0x30U) +#define AXBS_CRS5_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS5_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PCTL_SHIFT)) & AXBS_CRS5_PCTL_MASK) + +#define AXBS_CRS5_ARB_MASK (0x300U) +#define AXBS_CRS5_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS5_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_ARB_SHIFT)) & AXBS_CRS5_ARB_MASK) + +#define AXBS_CRS5_HPE0_MASK (0x10000U) +#define AXBS_CRS5_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE0_SHIFT)) & AXBS_CRS5_HPE0_MASK) + +#define AXBS_CRS5_HPE1_MASK (0x20000U) +#define AXBS_CRS5_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE1_SHIFT)) & AXBS_CRS5_HPE1_MASK) + +#define AXBS_CRS5_HPE2_MASK (0x40000U) +#define AXBS_CRS5_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE2_SHIFT)) & AXBS_CRS5_HPE2_MASK) + +#define AXBS_CRS5_HPE3_MASK (0x80000U) +#define AXBS_CRS5_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE3_SHIFT)) & AXBS_CRS5_HPE3_MASK) + +#define AXBS_CRS5_HPE4_MASK (0x100000U) +#define AXBS_CRS5_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE4_SHIFT)) & AXBS_CRS5_HPE4_MASK) + +#define AXBS_CRS5_HPE5_MASK (0x200000U) +#define AXBS_CRS5_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE5_SHIFT)) & AXBS_CRS5_HPE5_MASK) + +#define AXBS_CRS5_HPE6_MASK (0x400000U) +#define AXBS_CRS5_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE6_SHIFT)) & AXBS_CRS5_HPE6_MASK) + +#define AXBS_CRS5_HPE7_MASK (0x800000U) +#define AXBS_CRS5_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE7_SHIFT)) & AXBS_CRS5_HPE7_MASK) + +#define AXBS_CRS5_RO_MASK (0x80000000U) +#define AXBS_CRS5_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS5_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_RO_SHIFT)) & AXBS_CRS5_RO_MASK) +/*! @} */ + +/*! @name PRS6 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS6_M0_MASK (0x7U) +#define AXBS_PRS6_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M0_SHIFT)) & AXBS_PRS6_M0_MASK) + +#define AXBS_PRS6_M1_MASK (0x70U) +#define AXBS_PRS6_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M1_SHIFT)) & AXBS_PRS6_M1_MASK) + +#define AXBS_PRS6_M2_MASK (0x700U) +#define AXBS_PRS6_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M2_SHIFT)) & AXBS_PRS6_M2_MASK) + +#define AXBS_PRS6_M3_MASK (0x7000U) +#define AXBS_PRS6_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M3_SHIFT)) & AXBS_PRS6_M3_MASK) + +#define AXBS_PRS6_M4_MASK (0x70000U) +#define AXBS_PRS6_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M4_SHIFT)) & AXBS_PRS6_M4_MASK) + +#define AXBS_PRS6_M5_MASK (0x700000U) +#define AXBS_PRS6_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M5_SHIFT)) & AXBS_PRS6_M5_MASK) + +#define AXBS_PRS6_M6_MASK (0x7000000U) +#define AXBS_PRS6_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M6_SHIFT)) & AXBS_PRS6_M6_MASK) + +#define AXBS_PRS6_M7_MASK (0x70000000U) +#define AXBS_PRS6_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M7_SHIFT)) & AXBS_PRS6_M7_MASK) +/*! @} */ + +/*! @name CRS6 - Control Register */ +/*! @{ */ + +#define AXBS_CRS6_PARK_MASK (0x7U) +#define AXBS_CRS6_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS6_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PARK_SHIFT)) & AXBS_CRS6_PARK_MASK) + +#define AXBS_CRS6_PCTL_MASK (0x30U) +#define AXBS_CRS6_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS6_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PCTL_SHIFT)) & AXBS_CRS6_PCTL_MASK) + +#define AXBS_CRS6_ARB_MASK (0x300U) +#define AXBS_CRS6_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS6_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_ARB_SHIFT)) & AXBS_CRS6_ARB_MASK) + +#define AXBS_CRS6_HPE0_MASK (0x10000U) +#define AXBS_CRS6_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE0_SHIFT)) & AXBS_CRS6_HPE0_MASK) + +#define AXBS_CRS6_HPE1_MASK (0x20000U) +#define AXBS_CRS6_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE1_SHIFT)) & AXBS_CRS6_HPE1_MASK) + +#define AXBS_CRS6_HPE2_MASK (0x40000U) +#define AXBS_CRS6_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE2_SHIFT)) & AXBS_CRS6_HPE2_MASK) + +#define AXBS_CRS6_HPE3_MASK (0x80000U) +#define AXBS_CRS6_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE3_SHIFT)) & AXBS_CRS6_HPE3_MASK) + +#define AXBS_CRS6_HPE4_MASK (0x100000U) +#define AXBS_CRS6_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE4_SHIFT)) & AXBS_CRS6_HPE4_MASK) + +#define AXBS_CRS6_HPE5_MASK (0x200000U) +#define AXBS_CRS6_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE5_SHIFT)) & AXBS_CRS6_HPE5_MASK) + +#define AXBS_CRS6_HPE6_MASK (0x400000U) +#define AXBS_CRS6_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE6_SHIFT)) & AXBS_CRS6_HPE6_MASK) + +#define AXBS_CRS6_HPE7_MASK (0x800000U) +#define AXBS_CRS6_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE7_SHIFT)) & AXBS_CRS6_HPE7_MASK) + +#define AXBS_CRS6_RO_MASK (0x80000000U) +#define AXBS_CRS6_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS6_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_RO_SHIFT)) & AXBS_CRS6_RO_MASK) +/*! @} */ + +/*! @name PRS7 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS7_M0_MASK (0x7U) +#define AXBS_PRS7_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M0_SHIFT)) & AXBS_PRS7_M0_MASK) + +#define AXBS_PRS7_M1_MASK (0x70U) +#define AXBS_PRS7_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M1_SHIFT)) & AXBS_PRS7_M1_MASK) + +#define AXBS_PRS7_M2_MASK (0x700U) +#define AXBS_PRS7_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M2_SHIFT)) & AXBS_PRS7_M2_MASK) + +#define AXBS_PRS7_M3_MASK (0x7000U) +#define AXBS_PRS7_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M3_SHIFT)) & AXBS_PRS7_M3_MASK) + +#define AXBS_PRS7_M4_MASK (0x70000U) +#define AXBS_PRS7_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M4_SHIFT)) & AXBS_PRS7_M4_MASK) + +#define AXBS_PRS7_M5_MASK (0x700000U) +#define AXBS_PRS7_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M5_SHIFT)) & AXBS_PRS7_M5_MASK) + +#define AXBS_PRS7_M6_MASK (0x7000000U) +#define AXBS_PRS7_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M6_SHIFT)) & AXBS_PRS7_M6_MASK) + +#define AXBS_PRS7_M7_MASK (0x70000000U) +#define AXBS_PRS7_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M7_SHIFT)) & AXBS_PRS7_M7_MASK) +/*! @} */ + +/*! @name CRS7 - Control Register */ +/*! @{ */ + +#define AXBS_CRS7_PARK_MASK (0x7U) +#define AXBS_CRS7_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS7_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PARK_SHIFT)) & AXBS_CRS7_PARK_MASK) + +#define AXBS_CRS7_PCTL_MASK (0x30U) +#define AXBS_CRS7_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS7_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PCTL_SHIFT)) & AXBS_CRS7_PCTL_MASK) + +#define AXBS_CRS7_ARB_MASK (0x300U) +#define AXBS_CRS7_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS7_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_ARB_SHIFT)) & AXBS_CRS7_ARB_MASK) + +#define AXBS_CRS7_HPE0_MASK (0x10000U) +#define AXBS_CRS7_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE0_SHIFT)) & AXBS_CRS7_HPE0_MASK) + +#define AXBS_CRS7_HPE1_MASK (0x20000U) +#define AXBS_CRS7_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE1_SHIFT)) & AXBS_CRS7_HPE1_MASK) + +#define AXBS_CRS7_HPE2_MASK (0x40000U) +#define AXBS_CRS7_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE2_SHIFT)) & AXBS_CRS7_HPE2_MASK) + +#define AXBS_CRS7_HPE3_MASK (0x80000U) +#define AXBS_CRS7_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE3_SHIFT)) & AXBS_CRS7_HPE3_MASK) + +#define AXBS_CRS7_HPE4_MASK (0x100000U) +#define AXBS_CRS7_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE4_SHIFT)) & AXBS_CRS7_HPE4_MASK) + +#define AXBS_CRS7_HPE5_MASK (0x200000U) +#define AXBS_CRS7_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE5_SHIFT)) & AXBS_CRS7_HPE5_MASK) + +#define AXBS_CRS7_HPE6_MASK (0x400000U) +#define AXBS_CRS7_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE6_SHIFT)) & AXBS_CRS7_HPE6_MASK) + +#define AXBS_CRS7_HPE7_MASK (0x800000U) +#define AXBS_CRS7_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE7_SHIFT)) & AXBS_CRS7_HPE7_MASK) + +#define AXBS_CRS7_RO_MASK (0x80000000U) +#define AXBS_CRS7_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS7_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_RO_SHIFT)) & AXBS_CRS7_RO_MASK) +/*! @} */ + +/*! @name MGPCR0 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR0_AULB_MASK (0x7U) +#define AXBS_MGPCR0_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) +/*! @} */ + +/*! @name MGPCR1 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR1_AULB_MASK (0x7U) +#define AXBS_MGPCR1_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) +/*! @} */ + +/*! @name MGPCR2 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR2_AULB_MASK (0x7U) +#define AXBS_MGPCR2_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) +/*! @} */ + +/*! @name MGPCR3 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR3_AULB_MASK (0x7U) +#define AXBS_MGPCR3_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) +/*! @} */ + +/*! @name MGPCR4 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR4_AULB_MASK (0x7U) +#define AXBS_MGPCR4_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) +/*! @} */ + +/*! @name MGPCR5 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR5_AULB_MASK (0x7U) +#define AXBS_MGPCR5_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) +/*! @} */ + +/*! @name MGPCR6 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR6_AULB_MASK (0x7U) +#define AXBS_MGPCR6_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK) +/*! @} */ + +/*! @name MGPCR7 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR7_AULB_MASK (0x7U) +#define AXBS_MGPCR7_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR7_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR7_AULB_SHIFT)) & AXBS_MGPCR7_AULB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AXBS_Register_Masks */ + + +/* AXBS - Peripheral instance base addresses */ +/** Peripheral AXBS base address */ +#define AXBS_BASE (0x44510000u) +/** Peripheral AXBS base pointer */ +#define AXBS ((AXBS_Type *)AXBS_BASE) +/** Array initializer of AXBS peripheral base addresses */ +#define AXBS_BASE_ADDRS { AXBS_BASE } +/** Array initializer of AXBS peripheral base pointers */ +#define AXBS_BASE_PTRS { AXBS } + +/*! + * @} + */ /* end of group AXBS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BBNSM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BBNSM_Peripheral_Access_Layer BBNSM Peripheral Access Layer + * @{ + */ + +/** BBNSM - Register Layout Typedef */ +typedef struct { + __I uint32_t BBNSM_VID; /**< BBNSM Version ID Register, offset: 0x0 */ + __I uint32_t BBNSM_FEATURES; /**< BBNSM Features Register, offset: 0x4 */ + __IO uint32_t BBNSM_CTRL; /**< BBNSM Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t BBNSM_INT_EN; /**< BBNSM Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t BBNSM_EVENTS; /**< BBNSM Events Register, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BBNSM_PAD_CTRL; /**< BBNSM External Pad Control Register, offset: 0x24 */ + uint8_t RESERVED_2[24]; + __IO uint32_t BBNSM_RTC_LS; /**< BBNSM Real-Time Counter LS Register, offset: 0x40 */ + __IO uint32_t BBNSM_RTC_MS; /**< BBNSM Real-Time Counter MS Register, offset: 0x44 */ + uint8_t RESERVED_3[8]; + __IO uint32_t BBNSM_TA; /**< BBNSM Time Alarm Register, offset: 0x50 */ + uint8_t RESERVED_4[684]; + __IO uint32_t GPR[8]; /**< General Purpose Register Word 0..General Purpose Register Word 7, array offset: 0x300, array step: 0x4 */ +} BBNSM_Type; + +/* ---------------------------------------------------------------------------- + -- BBNSM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BBNSM_Register_Masks BBNSM Register Masks + * @{ + */ + +/*! @name BBNSM_VID - BBNSM Version ID Register */ +/*! @{ */ + +#define BBNSM_BBNSM_VID_BBNSM_IPID_MASK (0xFFU) +#define BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT (0U) +/*! BBNSM_IPID - BBNSM IP ID */ +#define BBNSM_BBNSM_VID_BBNSM_IPID(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_IPID_MASK) + +#define BBNSM_BBNSM_VID_BBNSM_REV_MASK (0xFF00U) +#define BBNSM_BBNSM_VID_BBNSM_REV_SHIFT (8U) +/*! BBNSM_REV - BBNSM Revision */ +#define BBNSM_BBNSM_VID_BBNSM_REV(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_REV_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_REV_MASK) + +#define BBNSM_BBNSM_VID_BBNSM_VID_MASK (0xFF0000U) +#define BBNSM_BBNSM_VID_BBNSM_VID_SHIFT (16U) +/*! BBNSM_VID - BBNSM Version ID */ +#define BBNSM_BBNSM_VID_BBNSM_VID(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_VID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_VID_MASK) +/*! @} */ + +/*! @name BBNSM_FEATURES - BBNSM Features Register */ +/*! @{ */ + +#define BBNSM_BBNSM_FEATURES_GPR_SZ_MASK (0xFCU) +#define BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT (2U) +/*! GPR_SZ - GPR Register Array Size + * 0b000000..This version of BBNSM does not implement a general-purpose register array. + * *..The number of 32-bit words implemented in the general-purpose register array. + */ +#define BBNSM_BBNSM_FEATURES_GPR_SZ(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT)) & BBNSM_BBNSM_FEATURES_GPR_SZ_MASK) +/*! @} */ + +/*! @name BBNSM_CTRL - BBNSM Control Register */ +/*! @{ */ + +#define BBNSM_BBNSM_CTRL_RTC_EN_MASK (0x3U) +#define BBNSM_BBNSM_CTRL_RTC_EN_SHIFT (0U) +/*! RTC_EN - Real-Time Counter Enable + * 0b01..Disable the real-time counter. + * 0b10..Enable the real-time counter. + */ +#define BBNSM_BBNSM_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_RTC_EN_SHIFT)) & BBNSM_BBNSM_CTRL_RTC_EN_MASK) + +#define BBNSM_BBNSM_CTRL_TA_EN_MASK (0xCU) +#define BBNSM_BBNSM_CTRL_TA_EN_SHIFT (2U) +/*! TA_EN - Time Alarm Enable + * 0b01..Disable the time alarm. + * 0b10..Enable the time alarm. A time alarm event occurs if the value in the real-time counter register is equal + * to the value in the time alarm register. + */ +#define BBNSM_BBNSM_CTRL_TA_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TA_EN_SHIFT)) & BBNSM_BBNSM_CTRL_TA_EN_MASK) + +#define BBNSM_BBNSM_CTRL_CAL_EN_MASK (0x10U) +#define BBNSM_BBNSM_CTRL_CAL_EN_SHIFT (4U) +/*! CAL_EN - Calibration Enable + * 0b0..RTC Time calibration is disabled. + * 0b1..RTC Time calibration is enabled. + */ +#define BBNSM_BBNSM_CTRL_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_EN_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_EN_MASK) + +#define BBNSM_BBNSM_CTRL_CAL_VAL_MASK (0x1F00U) +#define BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT (8U) +/*! CAL_VAL - Calibration Value + * 0b00000..+0 counts per each 32768 ticks of the counter clock. + * 0b00001..+1 counts per each 32768 ticks of the counter clock. + * 0b00010..+2 counts per each 32768 ticks of the counter clock. + * 0b01111..+15 counts per each 32768 ticks of the counter clock. + * 0b10000..-16 counts per each 32768 ticks of the counter clock. + * 0b10001..-15 counts per each 32768 ticks of the counter clock. + * 0b11110..-2 counts per each 32768 ticks of the counter clock. + * 0b11111..-1 counts per each 32768 ticks of the counter clock. + */ +#define BBNSM_BBNSM_CTRL_CAL_VAL(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_VAL_MASK) + +#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK (0x30000U) +#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT (16U) +/*! BTN_TIMEOUT - Button Press Timeout + * 0b00..5 seconds. + * 0b01..10 seconds. + * 0b10..15 seconds. + * 0b11..Timeout disabled. Long button presses will not request a power down. + */ +#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT)) & BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK) + +#define BBNSM_BBNSM_CTRL_DEBOUNCE_MASK (0xC0000U) +#define BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT (18U) +/*! DEBOUNCE - Debounce Time + * 0b00..50 milliseconds. + * 0b01..100 milliseconds. + * 0b10..500 milliseconds. + * 0b11..0 milliseconds. + */ +#define BBNSM_BBNSM_CTRL_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT)) & BBNSM_BBNSM_CTRL_DEBOUNCE_MASK) + +#define BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK (0x300000U) +#define BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT (20U) +/*! TURN_ON_TIME - Turn-On Time + * 0b00..500 milliseconds. + * 0b01..50 milliseconds. + * 0b10..100 milliseconds. + * 0b11..0 milliseconds. + */ +#define BBNSM_BBNSM_CTRL_TURN_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT)) & BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK) + +#define BBNSM_BBNSM_CTRL_PK_EN_MASK (0x400000U) +#define BBNSM_BBNSM_CTRL_PK_EN_SHIFT (22U) +/*! PK_EN - PMIC On Request Enable + * 0b0..PMIC On Request is disabled. + * 0b1..PMIC On Request is enabled. + */ +#define BBNSM_BBNSM_CTRL_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_EN_SHIFT)) & BBNSM_BBNSM_CTRL_PK_EN_MASK) + +#define BBNSM_BBNSM_CTRL_PK_OVR_MASK (0x800000U) +#define BBNSM_BBNSM_CTRL_PK_OVR_SHIFT (23U) +/*! PK_OVR - PMIC On Request Override + * 0b0..PMIC On Request Override is disabled. + * 0b1..PMIC On Request Override is enabled. + */ +#define BBNSM_BBNSM_CTRL_PK_OVR(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_OVR_SHIFT)) & BBNSM_BBNSM_CTRL_PK_OVR_MASK) + +#define BBNSM_BBNSM_CTRL_DP_EN_MASK (0x1000000U) +#define BBNSM_BBNSM_CTRL_DP_EN_SHIFT (24U) +/*! DP_EN - Dumb PMIC Enable + * 0b0..Smart PMIC is enabled. + * 0b1..Dumb PMIC is enabled. + */ +#define BBNSM_BBNSM_CTRL_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DP_EN_SHIFT)) & BBNSM_BBNSM_CTRL_DP_EN_MASK) + +#define BBNSM_BBNSM_CTRL_TOSP_MASK (0x2000000U) +#define BBNSM_BBNSM_CTRL_TOSP_SHIFT (25U) +/*! TOSP - Turn Off System Power + * 0b0..Leave system power on. + * 0b1..Turn off system power when Dumb PMIC is enabled. + */ +#define BBNSM_BBNSM_CTRL_TOSP(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TOSP_SHIFT)) & BBNSM_BBNSM_CTRL_TOSP_MASK) +/*! @} */ + +/*! @name BBNSM_INT_EN - BBNSM Interrupt Enable Register */ +/*! @{ */ + +#define BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK (0x3U) +#define BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT (0U) +/*! RTC_INT_EN - Real-Time Counter Rollover Interrupt Enable + * 0b01..Do not issue an interrupt when RTC has rolled over. The interrupt is cleared when this value is written. + * 0b10..Issue an interrupt when RTC has rolled over. + */ +#define BBNSM_BBNSM_INT_EN_RTC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK) + +#define BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK (0xCU) +#define BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT (2U) +/*! TA_INT_EN - Time Alarm Interrupt Enable + * 0b01..Do not issue an interrupt when RTC has reached alarm time. The interrupt is cleared when this value is written. + * 0b10..Issue an interrupt when RTC has reached alarm time. + */ +#define BBNSM_BBNSM_INT_EN_TA_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK) +/*! @} */ + +/*! @name BBNSM_EVENTS - BBNSM Events Register */ +/*! @{ */ + +#define BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK (0x3U) +#define BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT (0U) +/*! RTC_ROLL - Real-Time Counter Rollover Event + * 0b01..The real-time counter has not rolled over. + * 0b10..The real-time counter has rolled over. + */ +#define BBNSM_BBNSM_EVENTS_RTC_ROLL(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT)) & BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK) + +#define BBNSM_BBNSM_EVENTS_TA_MASK (0xCU) +#define BBNSM_BBNSM_EVENTS_TA_SHIFT (2U) +/*! TA - Time Alarm Event + * 0b01..The real-time counter has not reached the alarm time. + * 0b10..The real-time counter has reached the alarm time. + */ +#define BBNSM_BBNSM_EVENTS_TA(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_TA_SHIFT)) & BBNSM_BBNSM_EVENTS_TA_MASK) + +#define BBNSM_BBNSM_EVENTS_EMG_OFF_MASK (0x10U) +#define BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT (4U) +/*! EMG_OFF - Emergency Off Event + * 0b0..An emergency power off has not been requested. + * 0b1..An emergency power off has been requested. + */ +#define BBNSM_BBNSM_EVENTS_EMG_OFF(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_EMG_OFF_MASK) + +#define BBNSM_BBNSM_EVENTS_PWR_OFF_MASK (0x20U) +#define BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT (5U) +/*! PWR_OFF - Set Power Off Event + * 0b0..The power off interrupt has not been requested. + * 0b1..The power off interrupt has been requested. + */ +#define BBNSM_BBNSM_EVENTS_PWR_OFF(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_OFF_MASK) + +#define BBNSM_BBNSM_EVENTS_PWR_ON_MASK (0x40U) +#define BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT (6U) +/*! PWR_ON - Set Power On Event + * 0b0..The power on interrupt has not been requested. + * 0b1..The power on interrupt has been requested. + */ +#define BBNSM_BBNSM_EVENTS_PWR_ON(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_ON_MASK) +/*! @} */ + +/*! @name BBNSM_PAD_CTRL - BBNSM External Pad Control Register */ +/*! @{ */ + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK (0x1U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT (0U) +/*! PAD_CTRL0 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK (0x2U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT (1U) +/*! PAD_CTRL1 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK (0x4U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT (2U) +/*! PAD_CTRL2 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK (0x8U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT (3U) +/*! PAD_CTRL3 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK (0x10U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT (4U) +/*! PAD_CTRL4 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK (0x20U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT (5U) +/*! PAD_CTRL5 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK (0x40U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT (6U) +/*! PAD_CTRL6 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK (0x80U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT (7U) +/*! PAD_CTRL7 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK (0x100U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT (8U) +/*! PAD_CTRL8 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK (0x200U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT (9U) +/*! PAD_CTRL9 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK (0x400U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT (10U) +/*! PAD_CTRL10 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK (0x800U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT (11U) +/*! PAD_CTRL11 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK (0x1000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT (12U) +/*! PAD_CTRL12 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK (0x2000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT (13U) +/*! PAD_CTRL13 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK (0x4000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT (14U) +/*! PAD_CTRL14 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK (0x8000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT (15U) +/*! PAD_CTRL15 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK) +/*! @} */ + +/*! @name BBNSM_RTC_LS - BBNSM Real-Time Counter LS Register */ +/*! @{ */ + +#define BBNSM_BBNSM_RTC_LS_RTC_MASK (0xFFFFFFFFU) +#define BBNSM_BBNSM_RTC_LS_RTC_SHIFT (0U) +/*! RTC - Real-time Counter */ +#define BBNSM_BBNSM_RTC_LS_RTC(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_LS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_LS_RTC_MASK) +/*! @} */ + +/*! @name BBNSM_RTC_MS - BBNSM Real-Time Counter MS Register */ +/*! @{ */ + +#define BBNSM_BBNSM_RTC_MS_RTC_MASK (0x7FFFU) +#define BBNSM_BBNSM_RTC_MS_RTC_SHIFT (0U) +/*! RTC - Real-Time Counter */ +#define BBNSM_BBNSM_RTC_MS_RTC(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_MS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_MS_RTC_MASK) +/*! @} */ + +/*! @name BBNSM_TA - BBNSM Time Alarm Register */ +/*! @{ */ + +#define BBNSM_BBNSM_TA_TA_MASK (0xFFFFFFFFU) +#define BBNSM_BBNSM_TA_TA_SHIFT (0U) +/*! TA - Time Alarm Value */ +#define BBNSM_BBNSM_TA_TA(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_TA_TA_SHIFT)) & BBNSM_BBNSM_TA_TA_MASK) +/*! @} */ + +/*! @name GPR - General Purpose Register Word 0..General Purpose Register Word 7 */ +/*! @{ */ + +#define BBNSM_GPR_GPR_MASK (0xFFFFFFFFU) +#define BBNSM_GPR_GPR_SHIFT (0U) +/*! GPR - 32 bits of the GPR. */ +#define BBNSM_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_GPR_GPR_SHIFT)) & BBNSM_GPR_GPR_MASK) +/*! @} */ + +/* The count of BBNSM_GPR */ +#define BBNSM_GPR_COUNT (8U) + + +/*! + * @} + */ /* end of group BBNSM_Register_Masks */ + + +/* BBNSM - Peripheral instance base addresses */ +/** Peripheral BBNSM base address */ +#define BBNSM_BASE (0x44440000u) +/** Peripheral BBNSM base pointer */ +#define BBNSM ((BBNSM_Type *)BBNSM_BASE) +/** Array initializer of BBNSM peripheral base addresses */ +#define BBNSM_BASE_ADDRS { BBNSM_BASE } +/** Array initializer of BBNSM peripheral base pointers */ +#define BBNSM_BASE_PTRS { BBNSM } + +/*! + * @} + */ /* end of group BBNSM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_DDRMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_DDRMIX_Peripheral_Access_Layer BLK_CTRL_DDRMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_DDRMIX - Register Layout Typedef */ +typedef struct { + __IO uint32_t HWFFC_CTRL; /**< DDRPHY DfiClk, DflCtlClk HWFFC Control, offset: 0x0 */ + __IO uint32_t CA55_SEL_CTRL; /**< CA55 Arm PLL, Anamix PLL Observe Select, offset: 0x4 */ + __IO uint32_t VREF_PSW_CTRL; /**< DRAM_VREF power switch, offset: 0x8 */ + __IO uint32_t DDRC_STOP_CTRL; /**< DDR Controller ipg_stop SW control, offset: 0xC */ + __IO uint32_t AUTO_CG_CTRL; /**< DDR Controller automatic clock gating, offset: 0x10 */ + __IO uint32_t SSI_LP_CTRL; /**< DDRMIX SSI Slave low power signal control, offset: 0x14 */ +} BLK_CTRL_DDRMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_DDRMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_DDRMIX_Register_Masks BLK_CTRL_DDRMIX Register Masks + * @{ + */ + +/*! @name HWFFC_CTRL - DDRPHY DfiClk, DflCtlClk HWFFC Control */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_MASK (0x1U) +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_SHIFT (0U) +/*! HWFFC_EN - DDRPHY DfiClk, DfiCtlClk HWFFC Enable + * 0b0..DDRPHY HWFFC is disabled + * 0b1..DDRPHY HWFFC is enabled + */ +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_SHIFT)) & BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_MASK) + +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_MASK (0x2U) +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_SHIFT (1U) +/*! HWFFC_SEL - DDRPHY DfiClk, DfiCtlClk HWFFC Select + * 0b0..Normal clock is selected + * 0b1..Div2 frequency clock is selected + */ +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_SHIFT)) & BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_MASK) +/*! @} */ + +/*! @name CA55_SEL_CTRL - CA55 Arm PLL, Anamix PLL Observe Select */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_MASK (0x3U) +#define BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_SHIFT (0U) +/*! CA55_SEL - CA55 Arm PLL/Anamix PLL output select into DDRPHY + * 0b00..Normal DfiClk from DRAM PLL is selected + * 0b01..Anamix PLL output is selected + * 0b10..Normal DfiClk from DRAM PLL is selected + * 0b11..CA55 mix Arm PLL is selected + */ +#define BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_SHIFT)) & BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_MASK) +/*! @} */ + +/*! @name VREF_PSW_CTRL - DRAM_VREF power switch */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_MASK (0x1U) +#define BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_SHIFT (0U) +/*! VREF_PSW - DDRPHY DRAM_VREF Power Switch + * 0b0..Power switch is closed to prevent leakage + * 0b1..Power switch is opened and is set together with DDRPHY[VrefInGlobal] + */ +#define BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_SHIFT)) & BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_MASK) +/*! @} */ + +/*! @name DDRC_STOP_CTRL - DDR Controller ipg_stop SW control */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_MASK (0x1U) +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_SHIFT (0U) +/*! DDRC_STOP - DDR Controller ipg_stop + * 0b0..Clear DDR Controller ipg_stop signal + * 0b1..Set DDR Controller ipg_stop signal + */ +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_SHIFT)) & BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_MASK) + +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_MASK (0x2U) +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_SHIFT (1U) +/*! DDRC_STOP_ACK - DDR Controller ipg_stop_ack + * 0b0..DDR Controller ipg_stop_ack is a 0 + * 0b1..DDR Controller ipg_stop_ack is a 1 + */ +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_SHIFT)) & BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_MASK) +/*! @} */ + +/*! @name AUTO_CG_CTRL - DDR Controller automatic clock gating */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_MASK (0xFFFFU) +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_SHIFT (0U) +/*! SSI_IDLE_STRAP - SSI Idle Strap */ +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_SHIFT)) & BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_MASK) + +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_MASK (0x10000U) +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_SHIFT (16U) +/*! AUTO_CG_ENA - DDR Controller automatic clock gating enable + * 0b0..DDR Controller automatic clock gating is disabled + * 0b1..DDR Controller automatic clock gating is enabled + */ +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_SHIFT)) & BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_MASK) + +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_MASK (0x20000U) +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_SHIFT (17U) +/*! HWFFC_ACG_FORCE_B - DDR Controller hwffc and auto CG send ipg_stop allow + * 0b0..DDR Controller hwffc and auto CG cannot send ipg_stop + * 0b1..DDR Controller hwffc and auto CG can send ipg_stop + */ +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_SHIFT)) & BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_MASK) +/*! @} */ + +/*! @name SSI_LP_CTRL - DDRMIX SSI Slave low power signal control */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_MASK (0x1U) +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_SHIFT (0U) +/*! SSI_ISO_CTRL - DDRMIX SSI isolation mode control + * 0b0..in normal mode + * 0b1..enter pause mode + */ +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_SHIFT)) & BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_MASK) + +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_MASK (0x2U) +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_SHIFT (1U) +/*! SSI_POW_CTRL - DDRMIX SSI power control + * 0b0..enter no power mode for SSI + * 0b1..power mode for SSI + */ +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_SHIFT)) & BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_MASK) + +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_MASK (0x4U) +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_SHIFT (2U) +/*! SSI_IDLE - DDRMIX SSI idle signal + * 0b0..means SSI is not idle + * 0b1..means SSI is idle + */ +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_SHIFT)) & BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_DDRMIX_Register_Masks */ + + +/* BLK_CTRL_DDRMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_DDRMIX1 base address */ +#define BLK_CTRL_DDRMIX1_BASE (0x4E010000u) +/** Peripheral BLK_CTRL_DDRMIX1 base pointer */ +#define BLK_CTRL_DDRMIX1 ((BLK_CTRL_DDRMIX_Type *)BLK_CTRL_DDRMIX1_BASE) +/** Array initializer of BLK_CTRL_DDRMIX peripheral base addresses */ +#define BLK_CTRL_DDRMIX_BASE_ADDRS { BLK_CTRL_DDRMIX1_BASE } +/** Array initializer of BLK_CTRL_DDRMIX peripheral base pointers */ +#define BLK_CTRL_DDRMIX_BASE_PTRS { BLK_CTRL_DDRMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_DDRMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_MEDIAMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_MEDIAMIX_Peripheral_Access_Layer BLK_CTRL_MEDIAMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_MEDIAMIX - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t LCDIFr; /**< QOS and cache of LCDIF, offset: 0xC, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LCDIF' */ + uint8_t RESERVED_1[4]; + __IO uint32_t ISI0; /**< Cache of ISI, offset: 0x14 */ + uint8_t RESERVED_2[4]; + __IO uint32_t ISI1; /**< QoS of ISI, offset: 0x1C */ + uint8_t RESERVED_3[28]; + __I uint32_t PIXEL_CTRL; /**< Read Pixel Control Register, offset: 0x3C */ + uint8_t RESERVED_4[32]; + __IO uint32_t DISPLAY_MUX; /**< Display Mux Control Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __IO uint32_t IF_CTRL_REG; /**< Parallel Camera Interface Register, offset: 0x70 */ + __I uint32_t INTERFACE_STATUS; /**< Interface Status Register, offset: 0x74 */ + __IO uint32_t INTERFACE_CTRL_REG; /**< Interface Control Register, offset: 0x78 */ + __IO uint32_t INTERFACE_CTRL_REG1; /**< Interface Control Register 1, offset: 0x7C */ + } BUS_CONTROL; + struct { /* offset: 0x0 */ + __IO uint32_t RESET; /**< RESET Control Register, offset: 0x0 */ + __IO uint32_t CLK; /**< CLK Control Register, offset: 0x4 */ + } CLK_RESETN; + }; +} BLK_CTRL_MEDIAMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_MEDIAMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_MEDIAMIX_Register_Masks BLK_CTRL_MEDIAMIX Register Masks + * @{ + */ + +/*! @name LCDIF - QOS and cache of LCDIF */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_MASK (0xFU) +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_SHIFT (0U) +/*! ARCACHE - ARCACHE value of LCDIF */ +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_MASK) + +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_SHIFT (4U) +/*! ARCACHE_EN - ARCACHE enable of LCDIF + * 0b0..Do not enable ARCACHE + * 0b1..Enable ARCACHE + */ +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_MASK (0xF00U) +#define BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_SHIFT (8U) +/*! CFG_QOS - cfg_qos value of LCDIF */ +#define BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_MASK) + +#define BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_MASK (0xF000U) +#define BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_SHIFT (12U) +/*! DEFAULT_QOS - Default QoS value of LCDIF */ +#define BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_MASK) +/*! @} */ + +/*! @name ISI0 - Cache of ISI */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_MASK (0xFU) +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_SHIFT (0U) +/*! ARCACHE_Y - ARCACHE_Y value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_MASK (0xF0U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_SHIFT (4U) +/*! AWCACHE_Y - AWCACHE_Y value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_MASK (0xF00U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_SHIFT (8U) +/*! AWCACHE_U - AWCACHE_U value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_MASK (0xF000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_SHIFT (12U) +/*! AWCACHE_V - AWCACHE_V value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_MASK (0x10000U) +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_SHIFT (16U) +/*! ARCACHE_Y_EN - ARCACHE_Y enable of ISI + * 0b0..Do not enable ARCACHE_Y + * 0b1..Enable ARCACHE_Y + */ +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_MASK (0x20000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_SHIFT (17U) +/*! AWCACHE_Y_EN - AWCACHE_Y enable of ISI + * 0b0..Do not enable AWCACHE_Y + * 0b1..Enable AWCACHE_Y + */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_MASK (0x40000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_SHIFT (18U) +/*! AWCACHE_U_EN - AWCACHE_U enable of ISI + * 0b0..Do not enable AWACHE_U + * 0b1..Enable AWCACHE_U + */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_MASK (0x80000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_SHIFT (19U) +/*! AWCACHE_V_EN - AWCACHE_V enable of ISI + * 0b0..Do not enable AWCACHE_V + * 0b1..Enable AWCACHE_V + */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_MASK) +/*! @} */ + +/*! @name ISI1 - QoS of ISI */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_MASK (0xFU) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_SHIFT (0U) +/*! CFG_QOS_Y_W - cfg_qos_y_w value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_MASK (0xF0U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_SHIFT (4U) +/*! DEFAULT_QOS_Y_W - Default QOS_Y_W value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_MASK (0xF00U) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_SHIFT (8U) +/*! CFG_QOS_Y_R - CFG_QOS_Y_R value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_MASK (0xF000U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_SHIFT (12U) +/*! DEFAULT_QOS_Y_R - Default QOS_Y_R value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_MASK (0xF0000U) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_SHIFT (16U) +/*! CFG_QOS_U - cfg_qos_u value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_MASK (0xF00000U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_SHIFT (20U) +/*! DEFAULT_QOS_U - Default QoS value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_MASK (0xF000000U) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_SHIFT (24U) +/*! CFG_QOS_V - CFG_QOS_V value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_MASK (0xF0000000U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_SHIFT (28U) +/*! DEFAULT_QOS_V - Default QOS_V value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_MASK) +/*! @} */ + +/*! @name PIXEL_CTRL - Read Pixel Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_MASK (0xFFFU) +#define BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_SHIFT (0U) +/*! PIXEL_CTRL - Read pixel control information status */ +#define BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_SHIFT)) & BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_MASK) +/*! @} */ + +/*! @name DISPLAY_MUX - Display Mux Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_MASK (0x700U) +#define BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_SHIFT (8U) +/*! PARALLEL_DISP_FORMAT - Parallel display format configuration + * 0b000..RGB888 -> RGB888 + * 0b001..RGB888 -> RGB666. Truncate the two least significant bits of each color component (pass through the 6 + * most significant bits of each color component.) + * 0b010..RGB565 -> RGB565 + * 0b011..RGB555 -> RGB555 + * 0b100..YUV -> YCbCr 24 bits + * 0b101..YUV -> YUV444 + */ +#define BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_SHIFT)) & BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_MASK) +/*! @} */ + +/*! @name IF_CTRL_REG - Parallel Camera Interface Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U) +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U) +/*! DATA_TYPE_SEL - Pixel link data type select + * 0b0..Reserved + * 0b1..Pixel Link data type comes from IF_CTRL_REG DATA_TYPE[4:0] + */ +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_MASK (0x3E00U) +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SHIFT (9U) +/*! DATA_TYPE - Date type to ISI control bus [11:7] + * 0b00000..Null data + * 0b00100..RGB format + * 0b01000..YUV444 format + * 0b10000..YYU420 type(a) odd line (not supported) + * 0b10010..YYU420 type(a) even line (not supported) + * 0b11000..YYU420 type(a) YYY odd line (not supported) + * 0b11010..YYU420 type(b) UYVY even line (not supported) + * 0b11100..RAW + */ +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SHIFT)) & BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_MASK) +/*! @} */ + +/*! @name INTERFACE_STATUS - Interface Status Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_MASK (0x1U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_SHIFT (0U) +/*! FIELD_TOGGLE_STATUS - Field toggle status + * 0b0..VSYNC field toggle mode disabled + * 0b1..VSYNC field toggle mode enabled + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_SHIFT (1U) +/*! ECC_ERROR_STATUS - ECC error status + * 0b0..No ECC error detected + * 0b1..ECC error detected + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_MASK) +/*! @} */ + +/*! @name INTERFACE_CTRL_REG - Interface Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U) +/*! PIXEL_CLK_POL - Pixel clock polarity control + * 0b0..Pixel clcok is not inverted. + * 0b1..Pixel clock input is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_MASK (0x4U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_SHIFT (2U) +/*! HSYNC_POL - HSYNC polarity control + * 0b0..HSYNC output to Pixel Link is not inverted. + * 0b1..HSYNC output to Pixel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_MASK (0x8U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_SHIFT (3U) +/*! VSYNC_POL - VSYNC polarity control + * 0b0..VSYNC output to Pixel Link is not inverted. + * 0b1..VSYNC output to Pixel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_SHIFT (4U) +/*! DE_POL - DE polarity control + * 0b0..DE output to Pixel Link is not inverted. + * 0b1..DE output to Pixcel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U) +/*! PIXEL_DATA_POL - PIXEL_DATA polarity control + * 0b0..PIXEL_DATA output to Pixel Link is not inverted. + * 0b1..PIXEL_DATA output to Pixel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U) +/*! CCIR_EXT_VSYNC_EN - External VSYNC enable */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_MASK (0x80U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_SHIFT (7U) +/*! CCIR_EN - CCIR mode enable + * 0b0..CCIR mode disable + * 0b1..CCIR mode enable + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U) +/*! CCIR_VIDEO_MODE - CCIR video mode + * 0b0..Progressive mode + * 0b1..Interlace + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U) +/*! CCIR_NTSC_EN - CCIR NTSC enable + * 0b0..PAL + * 0b1..NTSC + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_MASK (0x400U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_SHIFT (10U) +/*! CCIR_VSYNC_RST_EN - CCIR_VSYNC_RESET_EN */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_MASK (0x800U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_SHIFT (11U) +/*! CCIR_ECC_CORR_EN - CCIR error correction enable + * 0b0..ECC error correction is disabled. + * 0b1..ECC error correction is enabled. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U) +/*! HSYNC_FORCE_EN - HSYNC force enable + * 0b0..Do not override HSYNC. + * 0b1..Override HSYNC. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U) +/*! VSYNC_FORCE_EN - VSYNC force enable + * 0b0..Do not override VSYNC. + * 0b1..Override VSYNC. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_SHIFT (14U) +/*! GCLK_MODE_EN - Gate clock mode enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_MASK (0x8000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_SHIFT (15U) +/*! VALID_SEL - Data valid select + * 0b0..HSYNC data valid. + * 0b1..Data enable valid. Not supported. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_MASK (0x10000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_SHIFT (16U) +/*! RAW_OUT_SEL - RAW output select + * 0b0..Right justified output + * 0b1..Left justified to 14-bit output + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U) +/*! HSYNC_OUT_SEL - HSYNC output select + * 0b0..HYSNC output level + * 0b1..HYSNC output pulse + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_MASK (0x380000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_SHIFT (19U) +/*! HSYNC_PULSE - HSYNC_PULSE */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_MASK (0x400000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_SHIFT (22U) +/*! UV_SWAP_EN - UV swap enable + * 0b0..UV swap disable + * 0b1..UV swap enable + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_MASK) +/*! @} */ + +/*! @name INTERFACE_CTRL_REG1 - Interface Control Register 1 */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFFU) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_SHIFT (0U) +/*! VSYNC_PULSE - VSYNC pulse width */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_MASK) +/*! @} */ + +/*! @name RESET - RESET Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_MASK (0x1U) +#define BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_SHIFT (0U) +/*! bus_apb_en - Bus apb_clk reset + * 0b0..Reset bus apb_clk related logic + * 0b1..Do not reset bus apb_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_bus_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_SHIFT (1U) +/*! bus_blk_en - Bus axi_clk reset + * 0b0..Reset bus axi_clk related logic + * 0b1..Do not reset bus axi_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_bus_blk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_MASK (0x4U) +#define BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_SHIFT (2U) +/*! isi_apb_en - ISI apb_clk reset + * 0b0..Reset ISI apb_clk related logic + * 0b1..Do not reset ISI apb_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_isi_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_MASK (0x8U) +#define BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_SHIFT (3U) +/*! isi_proc_en - ISI axi_clk reset + * 0b0..Reset ISI axi_clk related logic + * 0b1..Do not reset ISI axi_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_isi_proc_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_SHIFT (4U) +/*! lcdif_apb_en - LCDIF apb_clk reset + * 0b0..Reset LCDIF apb_clk related logic + * 0b1..Do not reset LCDIF apb_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_MASK (0x20U) +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_SHIFT (5U) +/*! lcdif_axi_en - LCDIF axi_clk reset + * 0b0..Reset LCDIF axi_clk related logic + * 0b1..Do not reset LCDIF axi_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_MASK (0x40U) +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_SHIFT (6U) +/*! lcdif_pix_en - LCDIF pix_clk reset + * 0b0..Reset LCDIF pix_clk related logic + * 0b1..Do not reset LCDIF pix_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_MASK (0x400U) +#define BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_SHIFT (10U) +/*! cam_clk_en - Camera clock reset + * 0b0..Reset camera related logic + * 0b1..Do not reset camera clock related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_cam_clk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_MASK) +/*! @} */ + +/*! @name CLK - CLK Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_MASK (0x1U) +#define BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_SHIFT (0U) +/*! bus_apb_en - Bus apb_clk gate enable + * 0b0..Do not gate bus apb_clk root + * 0b1..Gate bus apb_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_bus_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_SHIFT (1U) +/*! bus_blk_en - Bus axi_clk gate enable + * 0b0..Do not gate bus axi_clk root + * 0b1..Gate bus axi_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_bus_blk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_MASK (0x4U) +#define BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_SHIFT (2U) +/*! isi_apb_en - ISI apb_clk gate enable + * 0b0..Do not gate ISI apb_clk root + * 0b1..Gate ISI apb_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_isi_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_MASK (0x8U) +#define BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_SHIFT (3U) +/*! isi_proc_en - ISI axi_clk gate enable + * 0b0..Do not gate ISI axi_clk root + * 0b1..Gate ISI axi_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_isi_proc_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_SHIFT (4U) +/*! lcdif_apb_en - LCDIF apb_clk gate enable + * 0b0..Do not gate LCDIF apb_clk root + * 0b1..Gate LCDIF apb_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_MASK (0x20U) +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_SHIFT (5U) +/*! lcdif_axi_en - LCDIF axi_clk gate enable + * 0b0..Do not gate LCDIF axi_clk root + * 0b1..Gate LCDIF axi_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_MASK (0x40U) +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_SHIFT (6U) +/*! lcdif_pix_en - LCDIF pix_clk gate enable + * 0b0..Do not gate LCDIF pix_clk root + * 0b1..Gate LCDIF pix_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_MASK (0x400U) +#define BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_SHIFT (10U) +/*! cam_clk_en - cam_clk gate enable + * 0b0..Do not gate cam_clk root + * 0b1..Gate cam_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_cam_clk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_MEDIAMIX_Register_Masks */ + + +/* BLK_CTRL_MEDIAMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_MEDIAMIX1 base address */ +#define BLK_CTRL_MEDIAMIX1_BASE (0x4AC10000u) +/** Peripheral BLK_CTRL_MEDIAMIX1 base pointer */ +#define BLK_CTRL_MEDIAMIX1 ((BLK_CTRL_MEDIAMIX_Type *)BLK_CTRL_MEDIAMIX1_BASE) +/** Array initializer of BLK_CTRL_MEDIAMIX peripheral base addresses */ +#define BLK_CTRL_MEDIAMIX_BASE_ADDRS { BLK_CTRL_MEDIAMIX1_BASE } +/** Array initializer of BLK_CTRL_MEDIAMIX peripheral base pointers */ +#define BLK_CTRL_MEDIAMIX_BASE_PTRS { BLK_CTRL_MEDIAMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_MEDIAMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NIC_WRAPPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NIC_WRAPPER_Peripheral_Access_Layer BLK_CTRL_NIC_WRAPPER Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_NIC_WRAPPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEXSC_ERR; /**< DEXSC error response configuration, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AXI_LIMIT_WAKEUPMIX; /**< Configuration register for axi_limit_wakeupmix, offset: 0x8 */ + __IO uint32_t CACHE_ATTR; /**< Configuration register for AxCACHE[1] override, offset: 0xC */ + __IO uint32_t WAKEUPMIX_QOS; /**< Configuration register for QoS value from wakeupmix, offset: 0x10 */ + __IO uint32_t CACHE_QOS; /**< Configuration register for QoS value from A55, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t HSIOMIX_QOS; /**< Configuration register for QoS value from hsiomix, offset: 0x20 */ + __IO uint32_t TIE_VALUE; /**< GPR for uncertain tie0 or tie1, offset: 0x24 */ + __IO uint32_t OCRAM_SGLECC_ERR_INT; /**< OCRAM single ECC error interrupt flag, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SSI_MST_DDRMIX; /**< low power control for SSI_MST_DDRMIX, offset: 0x30 */ + __IO uint32_t SSI_MST_GIC600; /**< low power control for SSI_MST_GIC600, offset: 0x34 */ + __IO uint32_t SSI_MST_WAKEUPMIX; /**< low power control for SSI_MST_WAKEUPMIX, offset: 0x38 */ + __IO uint32_t SSI_SLV_CACHE; /**< low power control for SSI_SLV_CACHE, offset: 0x3C */ + __IO uint32_t SSI_SLV_GIC600; /**< low power control for SSI_SLV_GIC600, offset: 0x40 */ + __IO uint32_t SSI_SLV_HSIOMIX; /**< low power control for SSI_SLV_HSIOMIX, offset: 0x44 */ + __IO uint32_t SSI_SLV_MEDIAMIX; /**< low power control for SSI_SLV_MEDIAMIX, offset: 0x48 */ + __IO uint32_t SSI_SLV_WAKEUPMIX; /**< low power control for SSI_SLV_WAKEUPMIX, offset: 0x4C */ + uint8_t RESERVED_3[16]; + __IO uint32_t REG_RW; /**< reserved, offset: 0x60 */ + __I uint32_t REG_RO; /**< reserved, offset: 0x64 */ +} BLK_CTRL_NIC_WRAPPER_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NIC_WRAPPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NIC_WRAPPER_Register_Masks BLK_CTRL_NIC_WRAPPER Register Masks + * @{ + */ + +/*! @name DEXSC_ERR - DEXSC error response configuration */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_SHIFT (0U) +/*! OCRAM_ERR_RESP_EN - OCRAM DEXSC error response enable + * 0b0..DEXSC will not respond error if there is read error on DEXSC + * 0b1..DEXSC will respond slave error if there is read error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_MASK (0x2U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_SHIFT (1U) +/*! OCRAM_EXC_ERR_RESP_EN - OCRAM DEXSC exclusive error response enable + * 0b0..DEXSC will not respond error if there is exclusive error on DEXSC + * 0b1..DEXSC will respond slave error if there is exclusive error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_SHIFT (2U) +/*! OCRAM_LOCK_ERR_RESP_EN - Lock bit of OCRAM_ERR_RESP_EN and OCRAM_EXC_ERR_RESP_EN */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_MASK (0x10000U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_SHIFT (16U) +/*! DRAM_ERR_RESP_EN - DRAM DEXSC error response enable + * 0b0..DEXSC will not respond error if there is read error on DEXSC + * 0b1..DEXSC will respond slave error if there is read error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_MASK (0x20000U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_SHIFT (17U) +/*! DRAM_EXC_ERR_RESP_EN - DRAM DEXSC exclusive error response enable + * 0b0..DEXSC will not respond error if there is exclusive error on DEXSC + * 0b1..DEXSC will respond slave error if there is exclusive error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_MASK (0x40000U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_SHIFT (18U) +/*! DRAM_LOCK_ERR_RESP_EN - Lock bit of DRAM_ERR_RESP_EN and DRAM_EXC_ERR_RESP_EN */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_MASK) +/*! @} */ + +/*! @name AXI_LIMIT_WAKEUPMIX - Configuration register for axi_limit_wakeupmix */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_SHIFT (0U) +/*! ENABLE - Enable the beat limit on the access from wakeupmix + * 0b0..Disable the beat limit + * 0b1..Enable the beat limit + */ +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_MASK (0xFFFF0000U) +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_SHIFT (16U) +/*! BEAT_LIMIT - Beat limit number */ +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_SHIFT)) & BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_MASK) +/*! @} */ + +/*! @name CACHE_ATTR - Configuration register for AxCACHE[1] override */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_SHIFT (0U) +/*! WAKEUPMIX_ARCACHE_EN - Enable ARCACHE[1] override + * 0b0..Disable override ARCACHE[1] from ssi_slv_wakeupmix + * 0b1..enable override ARCACHE[1] from ssi_slv_wakeupmix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_MASK (0x2U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_SHIFT (1U) +/*! WAKEUPMIX_AWCACHE_EN - Enable AWCACHE[1] override + * 0b0..Disable override AWCACHE[1] from ssi_slv_wakeupmix + * 0b1..enable override AWCACHE[1] from ssi_slv_wakeupmix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_SHIFT (2U) +/*! CACHE_ARCACHE_EN - Enable ARCACHE[1] override + * 0b0..Disable override ARCACHE[1] from ssi_slv_cache + * 0b1..enable override ARCACHE[1] from ssi_slv_cache + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_SHIFT (3U) +/*! CACHE_AWCACHE_EN - Enable AWCACHE[1] override + * 0b0..Disable override AWCACHE[1] from ssi_slv_cache + * 0b1..enable override AWCACHE[1] from ssi_slv_cache + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_SHIFT (4U) +/*! HSIOMIX_ARCACHE_EN - Enable ARCACHE[1] override + * 0b0..Disable override ARCACHE[1] from ssi_slv_hsiomix + * 0b1..enable override ARCACHE[1] from ssi_slv_hsiomix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_SHIFT (5U) +/*! HSIOMIX_AWCACHE_EN - Enable AWCACHE[1] override + * 0b0..Disable override AWCACHE[1] from ssi_slv_hsiomix + * 0b1..enable override AWCACHE[1] from ssi_slv_hsiomix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_MASK (0x10000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_SHIFT (16U) +/*! WAKEUPMIX_ARCACHE - Override value + * 0b0..Override ARCACHE[1] from ssi_slv_wakeupmix to 0 + * 0b1..Override ARCACHE[1] from ssi_slv_wakeupmix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_MASK (0x20000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_SHIFT (17U) +/*! WAKEUPMIX_AWCACHE - Override value + * 0b0..Override AWCACHE[1] from ssi_slv_wakeupmix to 0 + * 0b1..Override AWCACHE[1] from ssi_slv_wakeupmix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_MASK (0x40000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_SHIFT (18U) +/*! CACHE_ARCACHE - Override value + * 0b0..Override ARCACHE[1] from ssi_slv_cache to 0 + * 0b1..Override ARCACHE[1] from ssi_slv_cache to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_MASK (0x80000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_SHIFT (19U) +/*! CACHE_AWCACHE - Override value + * 0b0..Override AWCACHE[1] from ssi_slv_cache to 0 + * 0b1..Override AWCACHE[1] from ssi_slv_cache to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_MASK (0x100000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_SHIFT (20U) +/*! HSIOMIX_ARCACHE - Override value + * 0b0..Override ARCACHE[1] from ssi_slv_hsiomix to 0 + * 0b1..Override ARCACHE[1] from ssi_slv_hsiomix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_MASK (0x200000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_SHIFT (21U) +/*! HSIOMIX_AWCACHE - Override value + * 0b0..Override AWCACHE[1] from ssi_slv_hsiomix to 0 + * 0b1..Override AWCACHE[1] from ssi_slv_hsiomix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_MASK) +/*! @} */ + +/*! @name WAKEUPMIX_QOS - Configuration register for QoS value from wakeupmix */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_SHIFT (0U) +/*! PANIC_AW - Value of aw_qos_paNIC from wakeupmix */ +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_MASK (0xF0U) +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_SHIFT (4U) +/*! PANIC_AR - Value of ar_qos_paNIC from wakeupmix */ +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_MASK) +/*! @} */ + +/*! @name CACHE_QOS - Configuration register for QoS value from A55 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_SHIFT (0U) +/*! PANIC_AW - Value of aw_qos_paNIC from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_MASK (0xF0U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_SHIFT (4U) +/*! PANIC_AR - Value of ar_qos_paNIC from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_MASK (0xF0000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_SHIFT (16U) +/*! DEFAULT_AW - Value of aw_qos_default from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_MASK (0xF00000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_SHIFT (20U) +/*! DEFAULT_AR - Value of ar_qos_default from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_MASK) +/*! @} */ + +/*! @name HSIOMIX_QOS - Configuration register for QoS value from hsiomix */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_SHIFT (0U) +/*! PANIC_AW - Value of aw_qos_paNIC from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_MASK (0xF0U) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_SHIFT (4U) +/*! PANIC_AR - Value of ar_qos_paNIC from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_MASK) + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_MASK (0xF0000U) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_SHIFT (16U) +/*! DEFAULT_AW - Value of aw_qos_default from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_MASK (0xF00000U) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_SHIFT (20U) +/*! DEFAULT_AR - Value of ar_qos_default from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_MASK) +/*! @} */ + +/*! @name TIE_VALUE - GPR for uncertain tie0 or tie1 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_SHIFT (0U) +/*! AIPS4_HBSTRB - Value of aips4.hbstrb */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_MASK (0x30U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_SHIFT (4U) +/*! XCPT_RTN - Dac_cache_r.xcpt_rtn and dac_cache_w.xcpt_rtn */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_MASK (0x40U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_SHIFT (6U) +/*! GICT_ALLOW_NS - GIC600.gict_allow_ns */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_MASK (0x80U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_SHIFT (7U) +/*! GICP_ALLOW_NS - GIC600.gicp_allow_ns */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_MASK (0x300U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_SHIFT (8U) +/*! ARBAR_S - GIC600.ARBAR_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_MASK (0xC00U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_SHIFT (10U) +/*! AWBAR_S - GIC600.AWBAR_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_MASK (0x7000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_SHIFT (12U) +/*! ARUSER_S - GIC600.ARUSER_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_MASK (0x38000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_SHIFT (15U) +/*! AWUSER_S - GIC600.AWUSER_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_MASK (0x3C0000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_SHIFT (18U) +/*! ARSNOOP_S - GIC600.arsnoop_s */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_MASK (0x1C00000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_SHIFT (22U) +/*! AWSNOOP_S - GIC600.awsnoop_s */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_MASK (0x1E000000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_SHIFT (25U) +/*! HPROT_GPV_CENTRAL - NIC400_central.HPROT_gpv_central */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_MASK (0x20000000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_SHIFT (29U) +/*! DFTRAMHOLD - GIC600.dftramhold */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_MASK) +/*! @} */ + +/*! @name OCRAM_SGLECC_ERR_INT - OCRAM single ECC error interrupt flag */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_SHIFT (0U) +/*! SGL_ECC_ERR_IF - OCRAM single ECC error interrupt flag */ +#define BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_SHIFT)) & BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_MASK) +/*! @} */ + +/*! @name SSI_MST_DDRMIX - low power control for SSI_MST_DDRMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_MST_GIC600 - low power control for SSI_MST_GIC600 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_MASK) +/*! @} */ + +/*! @name SSI_MST_WAKEUPMIX - low power control for SSI_MST_WAKEUPMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_CACHE - low power control for SSI_SLV_CACHE */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_MASK (0x3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_GIC600 - low power control for SSI_SLV_GIC600 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_HSIOMIX - low power control for SSI_SLV_HSIOMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_MASK (0x3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_MEDIAMIX - low power control for SSI_SLV_MEDIAMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_MASK (0x3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_WAKEUPMIX - low power control for SSI_SLV_WAKEUPMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_MASK) +/*! @} */ + +/*! @name REG_RW - reserved */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_SHIFT)) & BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_MASK) +/*! @} */ + +/*! @name REG_RO - reserved */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_SHIFT)) & BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_NIC_WRAPPER_Register_Masks */ + + +/* BLK_CTRL_NIC_WRAPPER - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_NIC_WRAPPER1 base address */ +#define BLK_CTRL_NIC_WRAPPER1_BASE (0x49000000u) +/** Peripheral BLK_CTRL_NIC_WRAPPER1 base pointer */ +#define BLK_CTRL_NIC_WRAPPER1 ((BLK_CTRL_NIC_WRAPPER_Type *)BLK_CTRL_NIC_WRAPPER1_BASE) +/** Array initializer of BLK_CTRL_NIC_WRAPPER peripheral base addresses */ +#define BLK_CTRL_NIC_WRAPPER_BASE_ADDRS { BLK_CTRL_NIC_WRAPPER1_BASE } +/** Array initializer of BLK_CTRL_NIC_WRAPPER peripheral base pointers */ +#define BLK_CTRL_NIC_WRAPPER_BASE_PTRS { BLK_CTRL_NIC_WRAPPER1 } + +/*! + * @} + */ /* end of group BLK_CTRL_NIC_WRAPPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NS_AONMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer BLK_CTRL_NS_AONMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_NS_AONMIX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12]; + __IO uint32_t IPG_DEBUG_CA55C0; /**< IPG DEBUG MASK BIT CA55 CORE0, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t LP_HANDSHAKE; /**< LP HANDSHAKE, offset: 0x14 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MQS_SETTINGS; /**< MQS settings., offset: 0x20 */ + uint8_t RESERVED_3[4]; + __I uint32_t FUSE_ACC_DIS; /**< Read-only version of the OCOTP fuse-access-disable bit, offset: 0x28 */ + uint8_t RESERVED_4[4]; + __I uint32_t OCOTP_FUSE_DATA0; /**< Read-only version of OCOTP fusedata_mtr_cfg_0, offset: 0x30 */ + __I uint32_t OCOTP_FUSE_DATA1; /**< Read-only version of OCOTP fusedata_mtr_cfg_1, offset: 0x34 */ + __I uint32_t OCOTP_FUSE_DATA2; /**< Read-only version of OCOTP fusedata_mtr_cfg_2, offset: 0x38 */ + __I uint32_t OCOTP_FUSE_DATA3; /**< Read-only version of OCOTP fusedata_mtr_cfg_3, offset: 0x3C */ + __I uint32_t OCOTP_FUSE_DATA4; /**< Read-only version of OCOTP fusedata_mtr_cfg_4, offset: 0x40 */ + __I uint32_t OCOTP_FUSE_DATA5; /**< Read-only version of OCOTP fusedata_mtr_cfg_5, offset: 0x44 */ + __I uint32_t OCOTP_FUSE_DATA6; /**< Read-only version of OCOTP fusedata_mtr_cfg_6, offset: 0x48 */ + __I uint32_t OCOTP_FUSE_DATA7; /**< Read-only version of OCOTP fusedata_mtr_cfg_7, offset: 0x4C */ + __I uint32_t OCOTP_FUSE_DATA8; /**< Read-only version of OCOTP fusedata_mem_trim_cfg0, offset: 0x50 */ + __I uint32_t OCOTP_FUSE_DATA9; /**< Read-only version of OCOTP fusedata_mem_trim_cfg1, offset: 0x54 */ + __I uint32_t OCOTP_FUSE_DATA10; /**< Read-only version of OCOTP fusedata_mem_trim_cfg2, offset: 0x58 */ + __I uint32_t OCOTP_FUSE_DATA11; /**< Read-only version of OCOTP fusedata_mem_trim_cfg3, offset: 0x5C */ + __I uint32_t OCOTP_FUSE_DATA12; /**< Read-only version of OCOTP fusedata_mem_trim_cfg4, offset: 0x60 */ + __I uint32_t OCOTP_FUSE_DATA13; /**< Read-only version of OCOTP fusedata_mem_trim_cfg5, offset: 0x64 */ + __I uint32_t OCOTP_FUSE_DATA14; /**< Read-only version of OCOTP fusedata_mem_trim_cfg6, offset: 0x68 */ + __I uint32_t OCOTP_FUSE_DATA15; /**< Read-only version of OCOTP fusedata_mem_trim_cfg7, offset: 0x6C */ + __IO uint32_t I3C1_WAKEUP; /**< I3C1 WAKEUPX CLR, offset: 0x70 */ + __I uint32_t OCOTP_STATUS; /**< OCOTP status, offset: 0x74 */ + __IO uint32_t PDM_CLK_SEL; /**< PDM clock selection register, offset: 0x78 */ + __IO uint32_t I3C1_SDA_IRQ; /**< I3C1 SDA IRQ CONTROL, offset: 0x7C */ + __I uint32_t FASTBOOT_ENABLE; /**< Fastboot enable, offset: 0x80 */ + __I uint32_t EDGELOCK_FW_PRESENT; /**< Read only Edgelock fuse, offset: 0x84 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SSI_MASTER_AON2WKUP; /**< low power control for SSI_MASTER_AON2WKUP, offset: 0x90 */ + __IO uint32_t SSI_SLV_WKUP2AON; /**< low power control for SSI_SLV_WKUP2AON, offset: 0x94 */ +} BLK_CTRL_NS_AONMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NS_AONMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NS_AONMIX_Register_Masks BLK_CTRL_NS_AONMIX Register Masks + * @{ + */ + +/*! @name IPG_DEBUG_CA55C0 - IPG DEBUG MASK BIT CA55 CORE0 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_SHIFT (0U) +/*! CAN1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_MASK (0x2U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_SHIFT (1U) +/*! EDMA1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_MASK (0x4U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_SHIFT (2U) +/*! LPI2C1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_MASK (0x8U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_SHIFT (3U) +/*! LPI2C2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_MASK (0x10U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_SHIFT (4U) +/*! LPIT1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_MASK (0x20U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_SHIFT (5U) +/*! LPSPI1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_MASK (0x40U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_SHIFT (6U) +/*! LPSPI2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_MASK (0x80U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_SHIFT (7U) +/*! LPTMR1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_MASK (0x100U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_SHIFT (8U) +/*! SAI1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_MASK (0x200U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_SHIFT (9U) +/*! TPM1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_MASK (0x400U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_SHIFT (10U) +/*! TPM2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_MASK (0x800U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_SHIFT (11U) +/*! WDOG1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_MASK (0x1000U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_SHIFT (12U) +/*! WDOG2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_MASK (0x2000U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_SHIFT (13U) +/*! I3C1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_MASK (0x4000U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_SHIFT (14U) +/*! PDM - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_MASK) +/*! @} */ + +/*! @name LP_HANDSHAKE - LP HANDSHAKE */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_SHIFT (0U) +/*! CAN1_STOP - CAN1 STOP + * 0b0..QCHANNEL is enabled + * 0b1..QCHANNEL is disabled + */ +#define BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_SHIFT)) & BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_MASK) +/*! @} */ + +/*! @name MQS_SETTINGS - MQS settings. */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_MASK (0x2U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_SHIFT (1U) +/*! MQS_EN - MQS Enable */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_MASK) + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_MASK (0x4U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_SHIFT (2U) +/*! SOFT_RESET - Software Reset */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_MASK) + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_MASK (0x8U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_SHIFT (3U) +/*! OVERSAMPLE - Oversample enable */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_MASK) + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_MASK (0xFF00U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_SHIFT (8U) +/*! CLK_DIVIDE - Clock divide factor configuration */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_MASK) +/*! @} */ + +/*! @name FUSE_ACC_DIS - Read-only version of the OCOTP fuse-access-disable bit */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT (0U) +/*! OSCCA_FUSE_READ_DIS - OSCCA fuse read disable + * 0b0..The chip is allowed to access the OCOTP registers + * 0b1..The chip is not allowed to access the OCOTP registers + */ +#define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT)) & BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA0 - Read-only version of OCOTP fusedata_mtr_cfg_0 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_SHIFT (0U) +/*! OCOTP_FUSE_DATA0 - OCOTP_FUSE_DATA0 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA1 - Read-only version of OCOTP fusedata_mtr_cfg_1 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_SHIFT (0U) +/*! OCOTP_FUSE_DATA1 - OCOTP_FUSE_DATA1 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA2 - Read-only version of OCOTP fusedata_mtr_cfg_2 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_SHIFT (0U) +/*! OCOTP_FUSE_DATA2 - OCOTP_FUSE_DATA2 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA3 - Read-only version of OCOTP fusedata_mtr_cfg_3 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_SHIFT (0U) +/*! OCOTP_FUSE_DATA3 - OCOTP_FUSE_DATA3 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA4 - Read-only version of OCOTP fusedata_mtr_cfg_4 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_SHIFT (0U) +/*! OCOTP_FUSE_DATA4 - OCOTP_FUSE_DATA4 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA5 - Read-only version of OCOTP fusedata_mtr_cfg_5 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_SHIFT (0U) +/*! OCOTP_FUSE_DATA5 - OCOTP_FUSE_DATA5 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA6 - Read-only version of OCOTP fusedata_mtr_cfg_6 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_SHIFT (0U) +/*! OCOTP_FUSE_DATA6 - OCOTP_FUSE_DATA6 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA7 - Read-only version of OCOTP fusedata_mtr_cfg_7 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_SHIFT (0U) +/*! OCOTP_FUSE_DATA7 - OCOTP_FUSE_DATA7 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA8 - Read-only version of OCOTP fusedata_mem_trim_cfg0 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_SHIFT (0U) +/*! OCOTP_FUSE_DATA8 - OCOTP_FUSE_DATA8 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA9 - Read-only version of OCOTP fusedata_mem_trim_cfg1 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_SHIFT (0U) +/*! OCOTP_FUSE_DATA9 - OCOTP_FUSE_DATA9 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA10 - Read-only version of OCOTP fusedata_mem_trim_cfg2 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_SHIFT (0U) +/*! OCOTP_FUSE_DATA10 - OCOTP_FUSE_DATA10 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA11 - Read-only version of OCOTP fusedata_mem_trim_cfg3 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_SHIFT (0U) +/*! OCOTP_FUSE_DATA11 - OCOTP_FUSE_DATA12 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA12 - Read-only version of OCOTP fusedata_mem_trim_cfg4 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_SHIFT (0U) +/*! OCOTP_FUSE_DATA12 - OCOTP_FUSE_DATA13 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA13 - Read-only version of OCOTP fusedata_mem_trim_cfg5 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_SHIFT (0U) +/*! OCOTP_FUSE_DATA13 - OCOTP_FUSE_DATA13 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA14 - Read-only version of OCOTP fusedata_mem_trim_cfg6 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_SHIFT (0U) +/*! OCOTP_FUSE_DATA14 - OCOTP_FUSE_DATA14 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA15 - Read-only version of OCOTP fusedata_mem_trim_cfg7 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_SHIFT (0U) +/*! OCOTP_FUSE_DATA15 - OCOTP_FUSE_DATA15 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_MASK) +/*! @} */ + +/*! @name I3C1_WAKEUP - I3C1 WAKEUPX CLR */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_SHIFT (0U) +/*! IRQ_CLR - I3C1 Interrupt request clear */ +#define BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_SHIFT)) & BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_MASK) +/*! @} */ + +/*! @name OCOTP_STATUS - OCOTP status */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_SHIFT (0U) +/*! BUSY - OCOTP controller busy bit + * 0b0..Idle + * 0b1..OCOTP is Busy + */ +#define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name PDM_CLK_SEL - PDM clock selection register */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_SHIFT (0U) +/*! SEL - Select source for PDM clock + * 0b0..PDM root clock + * 0b1..SAI1_MCLK + */ +#define BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_SHIFT)) & BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_MASK) +/*! @} */ + +/*! @name I3C1_SDA_IRQ - I3C1 SDA IRQ CONTROL */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_SHIFT (0U) +/*! ENABLE - IRQ enable bit + * 0b0..I3C1 SDA IRQ disable + * 0b1..I3C1 SDA IRQ enable + */ +#define BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_SHIFT)) & BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_MASK) +/*! @} */ + +/*! @name FASTBOOT_ENABLE - Fastboot enable */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_MASK (0x3U) +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_SHIFT (0U) +/*! FASTBOOT_ENABLE - FASTBOOT_ENABLE bits */ +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_SHIFT)) & BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_MASK) + +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_MASK (0xCU) +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_SHIFT (2U) +/*! BP_FASTBOOT_ENABLE - BP_FASTBOOT_ENABLE */ +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_SHIFT)) & BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_MASK) +/*! @} */ + +/*! @name EDGELOCK_FW_PRESENT - Read only Edgelock fuse */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_SHIFT (0U) +/*! EDGELOCK_FW_PRESENT - Read only bit for Edgelock fuse */ +#define BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_SHIFT)) & BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_MASK) +/*! @} */ + +/*! @name SSI_MASTER_AON2WKUP - low power control for SSI_MASTER_AON2WKUP */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_SHIFT (0U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_MASK (0x4U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_SHIFT (2U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_MASK (0x10U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_SHIFT (4U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_MASK (0x20U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_SHIFT (5U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_WKUP2AON - low power control for SSI_SLV_WKUP2AON */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_SHIFT (0U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_MASK (0x10U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_SHIFT (4U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_MASK (0x20U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_SHIFT (5U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_NS_AONMIX_Register_Masks */ + + +/* BLK_CTRL_NS_AONMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_NS_AONMIX1 base address */ +#define BLK_CTRL_NS_AONMIX1_BASE (0x44210000u) +/** Peripheral BLK_CTRL_NS_AONMIX1 base pointer */ +#define BLK_CTRL_NS_AONMIX1 ((BLK_CTRL_NS_AONMIX_Type *)BLK_CTRL_NS_AONMIX1_BASE) +/** Array initializer of BLK_CTRL_NS_AONMIX peripheral base addresses */ +#define BLK_CTRL_NS_AONMIX_BASE_ADDRS { BLK_CTRL_NS_AONMIX1_BASE } +/** Array initializer of BLK_CTRL_NS_AONMIX peripheral base pointers */ +#define BLK_CTRL_NS_AONMIX_BASE_PTRS { BLK_CTRL_NS_AONMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_S_AONMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_S_AONMIX_Peripheral_Access_Layer BLK_CTRL_S_AONMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_S_AONMIX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[64]; + __IO uint32_t CA55_IRQ_MASK0; /**< CA55_IRQ_MASK0, offset: 0x40 */ + __IO uint32_t CA55_IRQ_MASK1; /**< CA55_IRQ_MASK1, offset: 0x44 */ + __IO uint32_t CA55_IRQ_MASK2; /**< CA55_IRQ_MASK2, offset: 0x48 */ + __IO uint32_t CA55_IRQ_MASK3; /**< CA55_IRQ_MASK3, offset: 0x4C */ + __IO uint32_t CA55_IRQ_MASK4; /**< CA55_IRQ_MASK4, offset: 0x50 */ + __IO uint32_t CA55_IRQ_MASK5; /**< CA55_IRQ_MASK5, offset: 0x54 */ + __IO uint32_t CA55_IRQ_MASK6; /**< CA55_IRQ_MASK6, offset: 0x58 */ + uint8_t RESERVED_1[164]; + __IO uint32_t DAP_ACCESS_STKYBIT; /**< Dap Access Sticky Bit, offset: 0x100 */ + uint8_t RESERVED_2[12]; + __IO uint32_t LP_HANDSHAKE; /**< Low power handshake enable, offset: 0x110 */ + __IO uint32_t LP_HANDSHAKE2; /**< Low power handshake enable, offset: 0x114 */ + __IO uint32_t CA55_CPUWAIT; /**< CPUWAIT settings for CA55 CPU, offset: 0x118 */ + __IO uint32_t CA55_RVBARADDR0_L; /**< CA55_RVBARADDR0_L, offset: 0x11C */ + __IO uint32_t CA55_RVBARADDR0_H; /**< CA55_RVBARADDR0_H, offset: 0x120 */ + uint8_t RESERVED_3[8]; + __IO uint32_t ELE_IRQ_MASK; /**< Mask bits of Edgelock interrupt, offset: 0x12C */ + __IO uint32_t ELE_RESET_REQ_MASK; /**< Mask bits of ELE reset, offset: 0x130 */ + __IO uint32_t ELE_HALT_ST; /**< ELE halt status, offset: 0x134 */ + __IO uint32_t CA55_MODE; /**< Control the boot mode of two ca55 cores, offset: 0x138 */ + uint8_t RESERVED_4[8]; + __IO uint32_t WDOG_ANY_MASK; /**< WDOG any mask, offset: 0x144 */ + __IO uint32_t ELEV1_IPI_NOCLK_REF1; /**< ELEV1_IPI_NOCLK_REF1 clear, offset: 0x148 */ + __IO uint32_t L2_OCRAM_STICKY; /**< L2 ocram enable bit, offset: 0x14C */ +} BLK_CTRL_S_AONMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_S_AONMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_S_AONMIX_Register_Masks BLK_CTRL_S_AONMIX Register Masks + * @{ + */ + +/*! @name CA55_IRQ_MASK0 - CA55_IRQ_MASK0 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK1 - CA55_IRQ_MASK1 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK2 - CA55_IRQ_MASK2 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK3 - CA55_IRQ_MASK3 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK4 - CA55_IRQ_MASK4 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK5 - CA55_IRQ_MASK5 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK6 - CA55_IRQ_MASK6 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_MASK) +/*! @} */ + +/*! @name DAP_ACCESS_STKYBIT - Dap Access Sticky Bit */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT (1U) +/*! A55 - A55 DAP_ACCESS_STKYBIT + * 0b0..A55 core can be accessed by DAP + * 0b1..A55 core cannot be accessed by DAPCore0 works normally + */ +#define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT)) & BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK) +/*! @} */ + +/*! @name LP_HANDSHAKE - Low power handshake enable */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_SHIFT (0U) +/*! CA55_CPU0_COLD_RST_HS_EN - CA55_CPU0 cold reset handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_SHIFT (1U) +/*! CA55_CPU0_LP_HS_EN - CA55_CPU0 low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_SHIFT (2U) +/*! CA55_CPU1_COLD_RST_HS_EN - CA55_CPU1 cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_SHIFT (3U) +/*! CA55_CPU1_LP_HS_EN - CA55_CPU1 low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_SHIFT (4U) +/*! CA55_PLT_COLD_RST_HS_EN - CA55 platform cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_MASK (0x20U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_SHIFT (5U) +/*! CA55_PLT_LP_HS_EN - CA55 platform cold reset handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_MASK (0x80U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_SHIFT (7U) +/*! AONMIX_COLD_RST_HS_EN - AONMIX cold reset handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_SHIFT (8U) +/*! WAKEUPMIX_COLD_RST_HS_EN - WAKEUPMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_MASK (0x200U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_SHIFT (9U) +/*! WAKEUPMIX_LP_HS_EN - WAKEUPMIX low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_MASK (0x400U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_SHIFT (10U) +/*! NICMIX_COLD_RST_HS_EN - NICMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_MASK (0x800U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_SHIFT (11U) +/*! NICMIX_LP_HS_EN - NICMIX low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_MASK (0x1000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_SHIFT (12U) +/*! MEDIAMIX_COLD_RST_HS_EN - MEDIAMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_MASK (0x2000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_SHIFT (13U) +/*! MEDIAMIX_LP_HS_EN - MEDIAMIX low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_MASK (0x4000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_SHIFT (14U) +/*! HSIOMIX_COLD_RST_HS_EN - HSIOMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_MASK (0x8000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_SHIFT (15U) +/*! AON_TRDC_CLK_OFF_HS_EN - AON TRDC clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_MASK (0x10000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_SHIFT (16U) +/*! WAKEUP_TRDC_CLK_OFF_HS_EN - WAKEUP TRDC clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_MASK (0x20000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_SHIFT (17U) +/*! FLEXSPI_CLK_OFF_HS_EN - FLEXSPI clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_MASK (0x40000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_SHIFT (18U) +/*! NIC_APB_CLK_OFF_HS_EN - NIC_APB clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_MASK (0x80000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_SHIFT (19U) +/*! NIC_MEDIA_CLK_OFF_HS_EN - NIC_MEDIA clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_MASK (0x100000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_SHIFT (20U) +/*! USB_CLK_OFF_HS_EN - USB_CLK clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_MASK (0x400000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_SHIFT (22U) +/*! A55_CLK_OFF_HS_EN - A55_CLK clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_MASK (0x800000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_SHIFT (23U) +/*! ELE_CLK_OFF_HS_EN - Edgelock Enclave clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_MASK (0x1000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_SHIFT (24U) +/*! ELE_CLK_ON_HS_EN - Edgelock Enclave clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_MASK (0x2000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_SHIFT (25U) +/*! A55_CLK_ON_HS_EN - A55 clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_MASK (0x8000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_SHIFT (27U) +/*! USB_CLK_ON_HS_EN - USB Controller clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_MASK (0x10000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_SHIFT (28U) +/*! NIC_MEDIA_CLK_ON_HS_EN - NIC_MEDIA clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_MASK (0x20000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_SHIFT (29U) +/*! NIC_APB_CLK_ON_HS_EN - NIC_APB clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_MASK (0x40000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_SHIFT (30U) +/*! FLEXSPI_CLK_ON_HS_EN - FLEXSPI clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_MASK (0x80000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_SHIFT (31U) +/*! WAKEUPMIX_TRDC_CLK_ON_HS_EN - WAKEUPMIX_TRDC clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_MASK) +/*! @} */ + +/*! @name LP_HANDSHAKE2 - Low power handshake enable */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_SHIFT (0U) +/*! ENABLE - AONMIX TRDC clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_MASK) +/*! @} */ + +/*! @name CA55_CPUWAIT - CPUWAIT settings for CA55 CPU */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_SHIFT (0U) +/*! CPU0_WAIT - CPU0_WAIT + * 0b0..Core0 works normally + * 0b1..Core0 stops working + */ +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_MASK) + +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_SHIFT (1U) +/*! CPU1_WAIT - CPU1_WAIT + * 0b0..Core1 works normally + * 0b1..Core1 stops working + */ +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_MASK) +/*! @} */ + +/*! @name CA55_RVBARADDR0_L - CA55_RVBARADDR0_L */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_SHIFT (0U) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_MASK) +/*! @} */ + +/*! @name CA55_RVBARADDR0_H - CA55_RVBARADDR0_H */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_MASK (0x3FU) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_SHIFT (0U) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_MASK) +/*! @} */ + +/*! @name ELE_IRQ_MASK - Mask bits of Edgelock interrupt */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_SHIFT (0U) +/*! NOCLK_REF2 - No Clock Reference 2 + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_SHIFT (1U) +/*! NOCLK_REF1 - No Clock Reference 1 + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_SHIFT (2U) +/*! LMDA_32K_RESET_REQ - Request Edgelock reset from 32 KHz clock domain, active low, interrupt request */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_SHIFT (3U) +/*! LMDA_RESET_REQ - Request Edgelock reset, active low, interrupt request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_SHIFT (4U) +/*! NOCLK_32K - Edgelock FDET clock not detected interrupt mask */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_MASK (0x20U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_SHIFT (5U) +/*! LMDA_SYS_FAIL - System failure, reset chip or Edgelock + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_MASK (0x40U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_SHIFT (6U) +/*! LC_BRICKED - LMDA lifecycle is bricked state */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_SHIFT (8U) +/*! WDG_RESET - Watchdog reset request */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_MASK) +/*! @} */ + +/*! @name ELE_RESET_REQ_MASK - Mask bits of ELE reset */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_SHIFT (0U) +/*! NOCLK_REF2 - No Clock Reference 2 + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_SHIFT (1U) +/*! NOCLK_REF1 - No Clock Reference 1 */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_SHIFT (2U) +/*! LMDA_32K_RESET_REQ - Request Edgelock reset from 32 KHz clock domain, active low, interrupt request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_SHIFT (3U) +/*! LMDA_RESET_REQ - Request Edgelock reset, active low, interrupt request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_SHIFT (4U) +/*! NOCLK_32K - Edgelock FDET clock not detected interrupt mask */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_MASK (0x20U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_SHIFT (5U) +/*! LMDA_SYS_FAIL - System failure, reset chip or Edgelock + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_MASK (0x40U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_SHIFT (6U) +/*! LC_BRICKED - LMDA lifecycle is bricked state */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_MASK (0x80U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_SHIFT (7U) +/*! PUF_RESET - PUF reset request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_SHIFT (8U) +/*! WDG_RESET - Watchdog reset request */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_MASK) +/*! @} */ + +/*! @name ELE_HALT_ST - ELE halt status */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_SHIFT (0U) +/*! ELE_HALT_ACK - EdgeLock halt and clock status + * 0b0..EdgeLock is not fully halted and its clocks must be enabled + * 0b0..Mask interrupt + * 0b1..EdgeLock is fully halted indicating clocks may be removed + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_SHIFT (8U) +/*! ELE_HALT_EXIT_IRQ_CLR - EdgeLock halt exit interrupt clear + * 0b0..Remove the clear signal. This bit is not self-clearing and need SW to clear. + * 0b1..Clear EdgeLock halt exit interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_MASK) +/*! @} */ + +/*! @name CA55_MODE - Control the boot mode of two ca55 cores */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_MASK (0x3U) +#define BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_SHIFT (0U) +/*! AA64NAA32 - Core0 initial mode control + * 0b00..State after reset is aarch32 + * 0b01..State after reset is aarch64 + */ +#define BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_MASK) +/*! @} */ + +/*! @name WDOG_ANY_MASK - WDOG any mask */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_SHIFT (0U) +/*! WDOG1 - WDOG1 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_SHIFT (1U) +/*! WDOG2 - WDOG2 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_SHIFT (2U) +/*! WDOG3 - WDOG3 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_SHIFT (3U) +/*! WDOG4 - WDOG4 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_SHIFT (4U) +/*! WDOG5 - WDOG5 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_MASK) +/*! @} */ + +/*! @name ELEV1_IPI_NOCLK_REF1 - ELEV1_IPI_NOCLK_REF1 clear */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_SHIFT (0U) +/*! SLOW_CLEAR - Interrupt clear + * 0b0..Interrupt not cleared + * 0b1..Interrupt cleared + */ +#define BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_SHIFT)) & BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_MASK) +/*! @} */ + +/*! @name L2_OCRAM_STICKY - L2 ocram enable bit */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_SHIFT (0U) +/*! OCRAM_EN - L2 cache as ocram enable bit + * 0b0..L2 cache used as OCRAM once written to 0, cannot be written to 1 again unless reset + * 0b1..L2 cache used as OCRAM + */ +#define BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_SHIFT)) & BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_S_AONMIX_Register_Masks */ + + +/* BLK_CTRL_S_AONMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_S_AONMIX2 base address */ +#define BLK_CTRL_S_AONMIX2_BASE (0x444F0000u) +/** Peripheral BLK_CTRL_S_AONMIX2 base pointer */ +#define BLK_CTRL_S_AONMIX2 ((BLK_CTRL_S_AONMIX_Type *)BLK_CTRL_S_AONMIX2_BASE) +/** Array initializer of BLK_CTRL_S_AONMIX peripheral base addresses */ +#define BLK_CTRL_S_AONMIX_BASE_ADDRS { BLK_CTRL_S_AONMIX2_BASE } +/** Array initializer of BLK_CTRL_S_AONMIX peripheral base pointers */ +#define BLK_CTRL_S_AONMIX_BASE_PTRS { BLK_CTRL_S_AONMIX2 } + +/*! + * @} + */ /* end of group BLK_CTRL_S_AONMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_WAKEUPMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer BLK_CTRL_WAKEUPMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_WAKEUPMIX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12]; + __IO uint32_t LP_HANDSHAKE; /**< CAN2 and ENET2 low power handshake bits, offset: 0xC */ + uint8_t RESERVED_1[16]; + __IO uint32_t MQS_SETTING; /**< MQS Settings for MQS2, offset: 0x20 */ + __IO uint32_t SAI_CLK_SEL; /**< SAI2 and SAI3 MCLK1~3 CLK root mux settings, offset: 0x24 */ + __IO uint32_t GPR; /**< ENET QOS control signals, offset: 0x28 */ + __IO uint32_t ENET_CLK_SEL; /**< ENET CLK direction selection, offset: 0x2C */ + uint8_t RESERVED_2[4]; + __I uint32_t VOLT_DETECT; /**< Voltage detectors output, offset: 0x34 */ + __IO uint32_t I3C2_WAKEUP; /**< I3C2 WAKEUPX CLR, offset: 0x38 */ + __IO uint32_t IPG_DEBUG_CA55C0; /**< IPG DEBUG mask bit for CA55 core0, offset: 0x3C */ + uint8_t RESERVED_3[4]; + __IO uint32_t AXI_ATTR_CFG; /**< AXI CACHE OVERRITE BIT, offset: 0x44 */ + __IO uint32_t I3C2_SDA_IRQ; /**< I3C SDA IRQ Control, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t SSI_MST_WKUP2AON; /**< Low power control for SSI_MST_WKUP2AON, offset: 0x50 */ + __IO uint32_t SSI_MST_WKUP2NIC; /**< Low power control for SSI_MST_WKUP2NIC, offset: 0x54 */ + __IO uint32_t SSI_SLV_AON2WKUP; /**< Low power control for SSI_SLV_AON2WKUP, offset: 0x58 */ + __IO uint32_t SSI_SLV_NIC2WKUP; /**< Low power control for SSI_SLV_NIC2WKUP, offset: 0x5C */ +} BLK_CTRL_WAKEUPMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_WAKEUPMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_WAKEUPMIX_Register_Masks BLK_CTRL_WAKEUPMIX Register Masks + * @{ + */ + +/*! @name LP_HANDSHAKE - CAN2 and ENET2 low power handshake bits */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_SHIFT (0U) +/*! ENET2_STOP_ACK - ENET1_STOP_ACK */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_MASK) + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_SHIFT (1U) +/*! ENET2_STOP - ENET1_STOP */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_MASK) + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_SHIFT (2U) +/*! CAN2_STOP - CAN2_STOP */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_MASK) + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_MASK (0x3F8U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_SHIFT (3U) +/*! DUMMY - DUMMY + * 0b0000000..Module does not enter debug halted mode with CM33 + * 0b0000001..Module enters debug halted mode when CM33 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_MASK) +/*! @} */ + +/*! @name MQS_SETTING - MQS Settings for MQS2 */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_SHIFT (0U) +/*! SAI_SEL - SAI select + * 0b0..SAI2 + * 0b1..SAI3 + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_SHIFT (1U) +/*! MQS_EN - MQS Enable + * 0b0..MQS2 is disabled + * 0b1..MQS2 is enabled + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_SHIFT (2U) +/*! SOFT_RESET - Software Reset + * 0b0..Reset is enabled + * 0b1..Reset is disabled + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_SHIFT (3U) +/*! OVERSAMPLE - Oversample enable + * 0b0..32 + * 0b1..64 + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_MASK (0xFF00U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_SHIFT (8U) +/*! CLK_DIVIDE - Clock divide factor configuration + * 0b00000000..hmclk frequency + * 0b00000001..hmclk frequency x 1/2 + * 0b00000010..hmclk frequency x 1/3 + * 0b00000011..hmclk frequency x 1/4 + * 0b00000100-0b11111111..mclk frequency = hmclk frequency x 1/(n+1) + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_MASK) +/*! @} */ + +/*! @name SAI_CLK_SEL - SAI2 and SAI3 MCLK1~3 CLK root mux settings */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_SHIFT (0U) +/*! SAI2_MCLK1 - SAI2 MCLK1 clock source selection + * 0b0..SAI2 CLK_ROOT from CCM + * 0b1..SAI2 MCLK + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_MASK (0xEU) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_SHIFT (1U) +/*! SAI2_MCLK2 - SAI2 MCLK2 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_MASK (0x70U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_SHIFT (4U) +/*! SAI2_MCLK3 - SAI2 MCLK3 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_MASK (0x10000U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_SHIFT (16U) +/*! SAI3_MCLK1 - SAI3 MCLK1 clock source selection + * 0b0..SAI3 CLK_ROOT from CCM + * 0b1..SAI3 MCLK + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_MASK (0xE0000U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_SHIFT (17U) +/*! SAI3_MCLK2 - SAI2 MCLK2 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_MASK (0x700000U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_SHIFT (20U) +/*! SAI3_MCLK3 - SAI3 MCLK3 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_MASK) +/*! @} */ + +/*! @name GPR - ENET QOS control signals */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_GPR_ENABLE_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_GPR_ENABLE_SHIFT (0U) +/*! ENABLE - ENET QOS enable + * 0b0..ENET QoS is disabled + * 0b1..ENET QoS is enabled + */ +#define BLK_CTRL_WAKEUPMIX_GPR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_ENABLE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_ENABLE_MASK) + +#define BLK_CTRL_WAKEUPMIX_GPR_MODE_MASK (0xEU) +#define BLK_CTRL_WAKEUPMIX_GPR_MODE_SHIFT (1U) +/*! MODE - ENET QOS mode selection + * 0b000..MII mode is selected + * 0b001..RGMII mode is selected + * 0b100..RMII mode is selected + */ +#define BLK_CTRL_WAKEUPMIX_GPR_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_MODE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_MODE_MASK) + +#define BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_SHIFT (4U) +/*! DIS_CRC_CHK - Disable ENET QoS CRC check + * 0b0..CRC check is disabled + * 0b1..CRC check is enabled + */ +#define BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_MASK) +/*! @} */ + +/*! @name ENET_CLK_SEL - ENET CLK direction selection */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_SHIFT (0U) +/*! enet1_clk_tx_clk_sel - Direction of TX_CLK of ENET QOS + * 0b0..ENET QOS TX CLK is Input + * 0b1..ENET QOS TX CLK is Output + */ +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_SHIFT)) & BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_MASK) + +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_SHIFT (1U) +/*! enet2_regular_tx_clk_sel - Direction of TX_CLK of ENET + * 0b0..ENET TX CLK is Input + * 0b1..ENET TX CLK is Output + */ +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_SHIFT)) & BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_MASK) +/*! @} */ + +/*! @name VOLT_DETECT - Voltage detectors output */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_SHIFT (0U) +/*! SUPPLY_DETECTOR_AON - Voltage detectors output of AON */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_MASK) + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_SHIFT (1U) +/*! SUPPLY_DETECTOR_GPIO - Voltage detectors output of GPIO */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_MASK) + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_SHIFT (2U) +/*! SUPPLY_DETECTOR_SD2 - Voltage detectors output of SD2 */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_MASK) + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_SHIFT (3U) +/*! SUPPLY_DETECTOR_WAKEUP - Voltage detectors output of WAKEUP */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_MASK) +/*! @} */ + +/*! @name I3C2_WAKEUP - I3C2 WAKEUPX CLR */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_SHIFT)) & BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_MASK) +/*! @} */ + +/*! @name IPG_DEBUG_CA55C0 - IPG DEBUG mask bit for CA55 core0 */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_SHIFT (0U) +/*! CAN2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_SHIFT (1U) +/*! EDMA2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_SHIFT (4U) +/*! LPI2C3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_SHIFT (5U) +/*! LPI2C4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_MASK (0x40U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_SHIFT (6U) +/*! LPI2C5 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_MASK (0x80U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_SHIFT (7U) +/*! LPI2C6 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_MASK (0x100U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_SHIFT (8U) +/*! LPI2C7 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_MASK (0x200U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_SHIFT (9U) +/*! LPI2C8 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_MASK (0x400U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_SHIFT (10U) +/*! LPIT2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_MASK (0x800U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_SHIFT (11U) +/*! LPSPI3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_MASK (0x1000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_SHIFT (12U) +/*! LPSPI4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_MASK (0x2000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_SHIFT (13U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_MASK (0x4000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_SHIFT (14U) +/*! LPSPI6 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_MASK (0x8000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_SHIFT (15U) +/*! LPSPI7 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_MASK (0x10000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_SHIFT (16U) +/*! LPSPI8 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_MASK (0x20000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_SHIFT (17U) +/*! LPTMR2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_MASK (0x40000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_SHIFT (18U) +/*! TPM3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_MASK (0x80000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_SHIFT (19U) +/*! TPM4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_MASK (0x100000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_SHIFT (20U) +/*! TPM5 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_MASK (0x200000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_SHIFT (21U) +/*! TPM6 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_MASK (0x400000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_SHIFT (22U) +/*! WDOG3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_MASK (0x800000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_SHIFT (23U) +/*! WDOG4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_MASK (0x1000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_SHIFT (24U) +/*! WDOG5 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_MASK (0x2000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_SHIFT (25U) +/*! I3C2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_MASK (0x4000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_SHIFT (26U) +/*! SAI2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_MASK (0x8000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_SHIFT (27U) +/*! SAI3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_MASK (0x10000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_SHIFT (28U) +/*! ENET2_REGULAR + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_MASK) +/*! @} */ + +/*! @name AXI_ATTR_CFG - AXI CACHE OVERRITE BIT */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_SHIFT (0U) +/*! ARCACHE_USDHC1 - Overwrite arcache of USDHC1 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_SHIFT (1U) +/*! AWCACHE_USDHC1 - Overwrite awcache of USDHC1 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_SHIFT (2U) +/*! ARCACHE_USDHC2 - Overwrite arcache of USDHC2 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_SHIFT (3U) +/*! AWCACHE_USDHC2 - Overwrite awcache of USDHC2 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_SHIFT (4U) +/*! ARCACHE_USDHC3 - Overwrite arcache of USDHC3 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_SHIFT (5U) +/*! AWCACHE_USDHC3 - Overwrite awcache of USDHC3 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_MASK) +/*! @} */ + +/*! @name I3C2_SDA_IRQ - I3C SDA IRQ Control */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_SHIFT (0U) +/*! enable - IRQ enable bit + * 0b0..I3C2 SDA IRQ disable + * 0b1..I3C2 SDA IRQ enable + */ +#define BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_MASK) +/*! @} */ + +/*! @name SSI_MST_WKUP2AON - Low power control for SSI_MST_WKUP2AON */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_SHIFT (2U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_MASK) +/*! @} */ + +/*! @name SSI_MST_WKUP2NIC - Low power control for SSI_MST_WKUP2NIC */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_SHIFT (2U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_AON2WKUP - Low power control for SSI_SLV_AON2WKUP */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_NIC2WKUP - Low power control for SSI_SLV_NIC2WKUP */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_WAKEUPMIX_Register_Masks */ + + +/* BLK_CTRL_WAKEUPMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_WAKEUPMIX1 base address */ +#define BLK_CTRL_WAKEUPMIX1_BASE (0x42420000u) +/** Peripheral BLK_CTRL_WAKEUPMIX1 base pointer */ +#define BLK_CTRL_WAKEUPMIX1 ((BLK_CTRL_WAKEUPMIX_Type *)BLK_CTRL_WAKEUPMIX1_BASE) +/** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base addresses */ +#define BLK_CTRL_WAKEUPMIX_BASE_ADDRS { BLK_CTRL_WAKEUPMIX1_BASE } +/** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base pointers */ +#define BLK_CTRL_WAKEUPMIX_BASE_PTRS { BLK_CTRL_WAKEUPMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_2[24]; + __IO uint32_t IMASK3; /**< Interrupt Masks 3, offset: 0x6C */ + uint8_t RESERVED_3[4]; + __IO uint32_t IFLAG3; /**< Interrupt Flags 3, offset: 0x74 */ + __I uint32_t ET; /**< External Timer, offset: 0x78, available only on: CAN_FD1/CAN1 (missing on CAN_FD2/CAN2) */ + __IO uint32_t FLTCONF_IE; /**< Fault Confinement Interrupt Enable, offset: 0x7C, available only on: CAN_FD1/CAN1 (missing on CAN_FD2/CAN2) */ + uint8_t RESERVED_4[2048]; + __IO uint32_t RXIMR[96]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_5[224]; + __IO uint32_t MECR; /**< Memory Error Control, offset: 0xAE0 */ + __IO uint32_t ERRIAR; /**< Error Injection Address, offset: 0xAE4 */ + __IO uint32_t ERRIDPR; /**< Error Injection Data Pattern, offset: 0xAE8 */ + __IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern, offset: 0xAEC */ + __I uint32_t RERRAR; /**< Error Report Address, offset: 0xAF0 */ + __I uint32_t RERRDR; /**< Error Report Data, offset: 0xAF4 */ + __I uint32_t RERRSYNR; /**< Error Report Syndrome, offset: 0xAF8 */ + __IO uint32_t ERRSR; /**< Error Status, offset: 0xAFC */ + uint8_t RESERVED_6[240]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_7[24]; + __IO uint32_t HR_TIME_STAMP[96]; /**< High-Resolution Timestamp, array offset: 0xC30, array step: 0x4 */ + uint8_t RESERVED_8[8784]; + __IO uint32_t ERFFEL[128]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_TPOE_MASK (0x80U) +#define CAN_MCR_TPOE_SHIFT (7U) +/*! TPOE - TX Pin Override Enable + * 0b0..TX pin forcing is disabled + * 0b1..TX pin forcing is enabled + */ +#define CAN_MCR_TPOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_TPOE_SHIFT)) & CAN_MCR_TPOE_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_TPOV_MASK (0x400U) +#define CAN_MCR_TPOV_SHIFT (10U) +/*! TPOV - TX Pin Override Value + * 0b0..TX pin is forced to be dominant + * 0b1..TX pin is forced to be recessive + */ +#define CAN_MCR_TPOV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_TPOV_SHIFT)) & CAN_MCR_TPOV_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_DOZE_MASK (0x40000U) +#define CAN_MCR_DOZE_SHIFT (18U) +/*! DOZE - Doze Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b0..User mode + * 0b1..Supervisor mode + */ +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_ROM_MASK (0x100U) +#define CAN_CTRL1_ROM_SHIFT (8U) +/*! ROM - Restricted Operation Mode + * 0b0..Restricted operation is disabled + * 0b1..Restricted operation is enabled + */ +#define CAN_CTRL1_ROM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ROM_SHIFT)) & CAN_CTRL1_ROM_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_CLKSRC_MASK (0x2000U) +#define CAN_CTRL1_CLKSRC_SHIFT (13U) +/*! CLKSRC - CAN Engine Clock Source + * 0b0..Peripheral clock + * 0b1..Bus clock + */ +#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_ATP_MASK (0x400000U) +#define CAN_ESR1_ATP_SHIFT (22U) +/*! ATP - Active to Passive State + * 0b0..Does not transition + * 0b1..Transitions + */ +#define CAN_ESR1_ATP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ATP_SHIFT)) & CAN_ESR1_ATP_MASK) + +#define CAN_ESR1_PTA_MASK (0x800000U) +#define CAN_ESR1_PTA_SHIFT (23U) +/*! PTA - Passive to Active State + * 0b0..Does not transition + * 0b1..Transitions + */ +#define CAN_ESR1_PTA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_PTA_SHIFT)) & CAN_ESR1_PTA_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK2 - Interrupt Masks 2 */ +/*! @{ */ + +#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUF63TO32M_SHIFT (0U) +/*! BUF63TO32M - Buffer MBi Mask */ +#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG2 - Interrupt Flags 2 */ +/*! @{ */ + +#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) +/*! BUF63TO32I - Buffer MBi Interrupt */ +#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_RETRY_MASK (0x1CU) +#define CAN_CTRL2_RETRY_SHIFT (2U) +/*! RETRY - Number of Retransmission Requests + * 0b000..No retransmission + * 0b001..Count of re-transmission attempts + * 0b010..Count of re-transmission attempts + * 0b011..Count of re-transmission attempts + * 0b100..Count of re-transmission attempts + * 0b101..Count of re-transmission attempts + * 0b110..Count of re-transmission attempts + * 0b111..Unlimited number of retransmission + */ +#define CAN_CTRL2_RETRY(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RETRY_SHIFT)) & CAN_CTRL2_RETRY_MASK) + +#define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U) +#define CAN_CTRL2_TSTAMPCAP_SHIFT (6U) +/*! TSTAMPCAP - Timestamp Capture Point + * 0b00..Disabled + * 0b01..End of the CAN frame + * 0b10..Start of the CAN frame + * 0b11..Start of frame for classical CAN frames; res bit for CAN FD frames + */ +#define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK) + +#define CAN_CTRL2_MBTSBASE_MASK (0x300U) +#define CAN_CTRL2_MBTSBASE_SHIFT (8U) +/*! MBTSBASE - Message Buffer Timestamp Base + * 0b00..TIMER + * 0b01..Lower 16 bits of high-resolution timer + * 0b10..Upper 16 bits of high-resolution timer + * 0b11..Reserved + */ +#define CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK) + +#define CAN_CTRL2_FLT_RXN_MASK (0x400U) +#define CAN_CTRL2_FLT_RXN_SHIFT (10U) +/*! FLT_RXN - Fault reaction + * 0b0..Fault reaction is disabled + * 0b1..Fault reaction is enabled + */ +#define CAN_CTRL2_FLT_RXN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_FLT_RXN_SHIFT)) & CAN_CTRL2_FLT_RXN_MASK) + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U) +#define CAN_CTRL2_TIMER_SRC_SHIFT (15U) +/*! TIMER_SRC - Timer Source + * 0b0..CAN bit clock + * 0b1..External time tick + */ +#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ - Write Access to Memory in Freeze Mode + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +#define CAN_CTRL2_ECRWRE_MASK (0x20000000U) +#define CAN_CTRL2_ECRWRE_SHIFT (29U) +/*! ECRWRE - Error Correction Configuration Register Write Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_RX_PIN_ST_MASK (0x1000U) +#define CAN_ESR2_RX_PIN_ST_SHIFT (12U) +/*! RX_PIN_ST - RX Pin Status + * 0b0..RX pin is in the dominant state + * 0b1..RX pin is in a recessive state + */ +#define CAN_ESR2_RX_PIN_ST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_RX_PIN_ST_SHIFT)) & CAN_ESR2_RX_PIN_ST_MASK) + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/*! @name IMASK3 - Interrupt Masks 3 */ +/*! @{ */ + +#define CAN_IMASK3_BUF95TO64M_MASK (0xFFFFFFFFU) +#define CAN_IMASK3_BUF95TO64M_SHIFT (0U) +/*! BUF95TO64M - Buffer MBi Mask */ +#define CAN_IMASK3_BUF95TO64M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK3_BUF95TO64M_SHIFT)) & CAN_IMASK3_BUF95TO64M_MASK) +/*! @} */ + +/*! @name IFLAG3 - Interrupt Flags 3 */ +/*! @{ */ + +#define CAN_IFLAG3_BUF95TO64_MASK (0xFFFFFFFFU) +#define CAN_IFLAG3_BUF95TO64_SHIFT (0U) +/*! BUF95TO64 - Buffer MBi Interrupt */ +#define CAN_IFLAG3_BUF95TO64(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG3_BUF95TO64_SHIFT)) & CAN_IFLAG3_BUF95TO64_MASK) +/*! @} */ + +/*! @name ET - External Timer */ +/*! @{ */ + +#define CAN_ET_TIMER_MASK (0xFFFFFFFFU) +#define CAN_ET_TIMER_SHIFT (0U) +/*! TIMER - Timer */ +#define CAN_ET_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ET_TIMER_SHIFT)) & CAN_ET_TIMER_MASK) +/*! @} */ + +/*! @name FLTCONF_IE - Fault Confinement Interrupt Enable */ +/*! @{ */ + +#define CAN_FLTCONF_IE_ATP_IE_MASK (0x1U) +#define CAN_FLTCONF_IE_ATP_IE_SHIFT (0U) +/*! ATP_IE - Active to Passive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FLTCONF_IE_ATP_IE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLTCONF_IE_ATP_IE_SHIFT)) & CAN_FLTCONF_IE_ATP_IE_MASK) + +#define CAN_FLTCONF_IE_PTA_IE_MASK (0x2U) +#define CAN_FLTCONF_IE_PTA_IE_SHIFT (1U) +/*! PTA_IE - Passive to Active Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FLTCONF_IE_PTA_IE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLTCONF_IE_PTA_IE_SHIFT)) & CAN_FLTCONF_IE_PTA_IE_MASK) +/*! @} */ + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (96U) + +/*! @name MECR - Memory Error Control */ +/*! @{ */ + +#define CAN_MECR_NCEFAFRZ_MASK (0x80U) +#define CAN_MECR_NCEFAFRZ_SHIFT (7U) +/*! NCEFAFRZ - Noncorrectable Errors in FlexCAN Access Put Chip in Freeze Mode + * 0b0..Normal operation + * 0b1..Freeze mode + */ +#define CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK) + +#define CAN_MECR_ECCDIS_MASK (0x100U) +#define CAN_MECR_ECCDIS_SHIFT (8U) +/*! ECCDIS - Error Correction Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK) + +#define CAN_MECR_RERRDIS_MASK (0x200U) +#define CAN_MECR_RERRDIS_SHIFT (9U) +/*! RERRDIS - Error Report Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK) + +#define CAN_MECR_EXTERRIE_MASK (0x2000U) +#define CAN_MECR_EXTERRIE_SHIFT (13U) +/*! EXTERRIE - Extended Error Injection Enable + * 0b0..Disable. Apply error injection only to the 32-bit word. + * 0b1..Enable. Apply error injection to the 64-bit word. + */ +#define CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK) + +#define CAN_MECR_FAERRIE_MASK (0x4000U) +#define CAN_MECR_FAERRIE_SHIFT (14U) +/*! FAERRIE - FlexCAN Access Error Injection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK) + +#define CAN_MECR_HAERRIE_MASK (0x8000U) +#define CAN_MECR_HAERRIE_SHIFT (15U) +/*! HAERRIE - Host Access Error Injection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK) + +#define CAN_MECR_CEI_MSK_MASK (0x10000U) +#define CAN_MECR_CEI_MSK_SHIFT (16U) +/*! CEI_MSK - Correctable Errors Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK) + +#define CAN_MECR_FANCEI_MSK_MASK (0x40000U) +#define CAN_MECR_FANCEI_MSK_SHIFT (18U) +/*! FANCEI_MSK - FlexCAN Access with Noncorrectable Errors Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK) + +#define CAN_MECR_HANCEI_MSK_MASK (0x80000U) +#define CAN_MECR_HANCEI_MSK_SHIFT (19U) +/*! HANCEI_MSK - Host Access with Noncorrectable Errors Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK) + +#define CAN_MECR_ECRWRDIS_MASK (0x80000000U) +#define CAN_MECR_ECRWRDIS_SHIFT (31U) +/*! ECRWRDIS - Error Configuration Register Write Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK) +/*! @} */ + +/*! @name ERRIAR - Error Injection Address */ +/*! @{ */ + +#define CAN_ERRIAR_INJADDR_L_MASK (0x3U) +#define CAN_ERRIAR_INJADDR_L_SHIFT (0U) +/*! INJADDR_L - Error Injection Address Low */ +#define CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK) + +#define CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU) +#define CAN_ERRIAR_INJADDR_H_SHIFT (2U) +/*! INJADDR_H - Error Injection Address High */ +#define CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK) +/*! @} */ + +/*! @name ERRIDPR - Error Injection Data Pattern */ +/*! @{ */ + +#define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU) +#define CAN_ERRIDPR_DFLIP_SHIFT (0U) +/*! DFLIP - Data Flip Pattern */ +#define CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK) +/*! @} */ + +/*! @name ERRIPPR - Error Injection Parity Pattern */ +/*! @{ */ + +#define CAN_ERRIPPR_PFLIP0_MASK (0x1FU) +#define CAN_ERRIPPR_PFLIP0_SHIFT (0U) +/*! PFLIP0 - Parity Flip Pattern for Byte 0 (Least Significant) */ +#define CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK) + +#define CAN_ERRIPPR_PFLIP1_MASK (0x1F00U) +#define CAN_ERRIPPR_PFLIP1_SHIFT (8U) +/*! PFLIP1 - Parity Flip Pattern for Byte 1 */ +#define CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK) + +#define CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U) +#define CAN_ERRIPPR_PFLIP2_SHIFT (16U) +/*! PFLIP2 - Parity Flip Pattern for Byte 2 */ +#define CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK) + +#define CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U) +#define CAN_ERRIPPR_PFLIP3_SHIFT (24U) +/*! PFLIP3 - Parity Flip Pattern for Byte 3 (Most Significant) */ +#define CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK) +/*! @} */ + +/*! @name RERRAR - Error Report Address */ +/*! @{ */ + +#define CAN_RERRAR_ERRADDR_MASK (0x3FFFU) +#define CAN_RERRAR_ERRADDR_SHIFT (0U) +/*! ERRADDR - Address Where Error Detected */ +#define CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK) + +#define CAN_RERRAR_SAID_MASK (0x70000U) +#define CAN_RERRAR_SAID_SHIFT (16U) +/*! SAID - SAID */ +#define CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK) + +#define CAN_RERRAR_NCE_MASK (0x1000000U) +#define CAN_RERRAR_NCE_SHIFT (24U) +/*! NCE - Noncorrectable Error + * 0b0..Reporting a correctable error + * 0b1..Reporting a noncorrectable error + */ +#define CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK) +/*! @} */ + +/*! @name RERRDR - Error Report Data */ +/*! @{ */ + +#define CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU) +#define CAN_RERRDR_RDATA_SHIFT (0U) +/*! RDATA - Raw Data Word Read from Memory with Error */ +#define CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK) +/*! @} */ + +/*! @name RERRSYNR - Error Report Syndrome */ +/*! @{ */ + +#define CAN_RERRSYNR_SYND0_MASK (0x1FU) +#define CAN_RERRSYNR_SYND0_SHIFT (0U) +/*! SYND0 - Error Syndrome for Byte 0 (Least Significant) */ +#define CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK) + +#define CAN_RERRSYNR_BE0_MASK (0x80U) +#define CAN_RERRSYNR_BE0_SHIFT (7U) +/*! BE0 - Byte Enabled for Byte 0 (Least Significant) + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK) + +#define CAN_RERRSYNR_SYND1_MASK (0x1F00U) +#define CAN_RERRSYNR_SYND1_SHIFT (8U) +/*! SYND1 - Error Syndrome for Byte 1 */ +#define CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK) + +#define CAN_RERRSYNR_BE1_MASK (0x8000U) +#define CAN_RERRSYNR_BE1_SHIFT (15U) +/*! BE1 - Byte Enabled for Byte 1 + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK) + +#define CAN_RERRSYNR_SYND2_MASK (0x1F0000U) +#define CAN_RERRSYNR_SYND2_SHIFT (16U) +/*! SYND2 - Error Syndrome for Byte 2 */ +#define CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK) + +#define CAN_RERRSYNR_BE2_MASK (0x800000U) +#define CAN_RERRSYNR_BE2_SHIFT (23U) +/*! BE2 - Byte Enabled for Byte 2 + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK) + +#define CAN_RERRSYNR_SYND3_MASK (0x1F000000U) +#define CAN_RERRSYNR_SYND3_SHIFT (24U) +/*! SYND3 - Error Syndrome for Byte 3 (Most Significant) */ +#define CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK) + +#define CAN_RERRSYNR_BE3_MASK (0x80000000U) +#define CAN_RERRSYNR_BE3_SHIFT (31U) +/*! BE3 - Byte Enabled for Byte 3 (Most Significant) + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK) +/*! @} */ + +/*! @name ERRSR - Error Status */ +/*! @{ */ + +#define CAN_ERRSR_CEIOF_MASK (0x1U) +#define CAN_ERRSR_CEIOF_SHIFT (0U) +/*! CEIOF - Correctable Error Interrupt Overrun Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK) + +#define CAN_ERRSR_FANCEIOF_MASK (0x4U) +#define CAN_ERRSR_FANCEIOF_SHIFT (2U) +/*! FANCEIOF - FlexCAN Access with Noncorrectable Error Interrupt Overrun Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK) + +#define CAN_ERRSR_HANCEIOF_MASK (0x8U) +#define CAN_ERRSR_HANCEIOF_SHIFT (3U) +/*! HANCEIOF - Host Access With Noncorrectable Error Interrupt Overrun Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK) + +#define CAN_ERRSR_CEIF_MASK (0x10000U) +#define CAN_ERRSR_CEIF_SHIFT (16U) +/*! CEIF - Correctable Error Interrupt Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK) + +#define CAN_ERRSR_FANCEIF_MASK (0x40000U) +#define CAN_ERRSR_FANCEIF_SHIFT (18U) +/*! FANCEIF - FlexCAN Access with Noncorrectable Error Interrupt Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK) + +#define CAN_ERRSR_HANCEIF_MASK (0x80000U) +#define CAN_ERRSR_HANCEIF_SHIFT (19U) +/*! HANCEIF - Host Access with Noncorrectable Error Interrupt Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK) +/*! @} */ + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_MBDSR1_MASK (0x180000U) +#define CAN_FDCTRL_MBDSR1_SHIFT (19U) +/*! MBDSR1 - Message Buffer Data Size for Region 1 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) + +#define CAN_FDCTRL_MBDSR2_MASK (0xC00000U) +#define CAN_FDCTRL_MBDSR2_SHIFT (22U) +/*! MBDSR2 - Message Buffer Data Size for Region 2 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR2_SHIFT)) & CAN_FDCTRL_MBDSR2_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name HR_TIME_STAMP - High-Resolution Timestamp */ +/*! @{ */ + +#define CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU) +#define CAN_HR_TIME_STAMP_TS_SHIFT (0U) +/*! TS - High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK) +/*! @} */ + +/* The count of CAN_HR_TIME_STAMP */ +#define CAN_HR_TIME_STAMP_COUNT (96U) + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + +/* The count of CAN_ERFFEL */ +#define CAN_ERFFEL_COUNT (128U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x443A0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x425B0000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x80 */ + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Clock Root Control Register, offset: 0x0 */ + __IO uint32_t SET; /**< Clock Root Control Register, offset: 0x4 */ + __IO uint32_t CLR; /**< Clock Root Control Register, offset: 0x8 */ + __IO uint32_t TOG; /**< Clock Root Control Register, offset: 0xC */ + } CLOCK_ROOT_CONTROL; + uint8_t RESERVED_0[16]; + __IO uint32_t STATUS0; /**< Clock root working status, array offset: 0x20, array step: 0x80 */ + uint8_t RESERVED_1[12]; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Clock root access control, offset: 0x30 */ + __IO uint32_t SET; /**< Clock root access control, offset: 0x34 */ + __IO uint32_t CLR; /**< Clock root access control, offset: 0x38 */ + __IO uint32_t TOG; /**< Clock root access control, offset: 0x3C */ + } CLOCK_ROOT_AUTHEN; + uint8_t RESERVED_2[64]; + } CLOCK_ROOT[95]; + uint8_t RESERVED_0[6272]; + struct { /* offset: 0x4800 */ + uint32_t RW; /**< General Purpose Register, offset: 0x4800 */ + uint32_t SET; /**< General Purpose Register, offset: 0x4804 */ + uint32_t CLR; /**< General Purpose Register, offset: 0x4808 */ + uint32_t TOG; /**< General Purpose Register, offset: 0x480C */ + } GPR_SHARED0; + struct { /* offset: 0x4810 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4810 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4814 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4818 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x481C */ + } GPR_SHARED0_AUTHEN; + struct { /* offset: 0x4820 */ + __IO uint32_t RW; /**< General Purpose Register, offset: 0x4820 */ + __IO uint32_t SET; /**< General Purpose Register, offset: 0x4824 */ + __IO uint32_t CLR; /**< General Purpose Register, offset: 0x4828 */ + __IO uint32_t TOG; /**< General Purpose Register, offset: 0x482C */ + } GPR_SHARED1; + struct { /* offset: 0x4830 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4830 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4834 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4838 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x483C */ + } GPR_SHARED1_AUTHEN; + struct { /* offset: 0x4840 */ + __IO uint32_t RW; /**< General Purpose Register, offset: 0x4840 */ + __IO uint32_t SET; /**< General Purpose Register, offset: 0x4844 */ + __IO uint32_t CLR; /**< General Purpose Register, offset: 0x4848 */ + __IO uint32_t TOG; /**< General Purpose Register, offset: 0x484C */ + } GPR_SHARED2; + struct { /* offset: 0x4850 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4850 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4854 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4858 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x485C */ + } GPR_SHARED2_AUTHEN; + struct { /* offset: 0x4860, array step: 0x20 */ + struct { /* offset: 0x4860 */ + uint32_t RW; /**< General Purpose Register, offset: 0x4860 */ + uint32_t SET; /**< General Purpose Register, offset: 0x4864 */ + uint32_t CLR; /**< General Purpose Register, offset: 0x4868 */ + uint32_t TOG; /**< General Purpose Register, offset: 0x486C */ + } GPR_SHARED; + struct { /* offset: 0x4870 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4870 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4874 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4878 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x487C */ + } GPR_SHARED_AUTHEN; + } GPR_SHARED[5]; + uint8_t RESERVED_1[768]; + struct { /* offset: 0x4C00, array step: 0x20 */ + struct { /* offset: 0x4C00 */ + __IO uint32_t RW; /**< General puspose register, offset: 0x4C00 */ + __IO uint32_t SET; /**< General puspose register, offset: 0x4C04 */ + __IO uint32_t CLR; /**< General puspose register, offset: 0x4C08 */ + __IO uint32_t TOG; /**< General puspose register, offset: 0x4C0C */ + } GPR_PRIVATE; + struct { /* offset: 0x4C10 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4C10 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4C14 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4C18 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x4C1C */ + } GPR_PRIVATE_AUTHEN; + } GPR_PRIVATE[8]; + uint8_t RESERVED_2[768]; + struct { /* offset: 0x5000, array step: 0x40 */ + __IO uint32_t DIRECT; /**< Clock source direct control, array offset: 0x5000, array step: 0x40 */ + __I uint32_t LPM_STATUS0; /**< Low power mode information transfer status, array offset: 0x5004, array step: 0x40 */ + __I uint32_t LPM_STATUS1; /**< Low power mode information transfer status, array offset: 0x5008, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPM0; /**< Clock source low power mode setting, array offset: 0x5010, array step: 0x40 */ + __IO uint32_t LPM1; /**< clock source low power mode setting, array offset: 0x5014, array step: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t LPM_CUR; /**< LPM setting of current CPU domain, array offset: 0x501C, array step: 0x40 */ + __I uint32_t STATUS0; /**< Clock source working status, array offset: 0x5020, array step: 0x40 */ + __I uint32_t STATUS1; /**< Clock source domain status, array offset: 0x5024, array step: 0x40 */ + uint8_t RESERVED_2[8]; + __IO uint32_t AUTHEN; /**< Clock Source access control, array offset: 0x5030, array step: 0x40 */ + uint8_t RESERVED_3[12]; + } OSCPLL[20]; + uint8_t RESERVED_3[11008]; + struct { /* offset: 0x8000, array step: 0x40 */ + __IO uint32_t DIRECT; /**< LPCG direct control, array offset: 0x8000, array step: 0x40 */ + __I uint32_t LPM_STATUS0; /**< Low power mode information transfer status, array offset: 0x8004, array step: 0x40 */ + __I uint32_t LPM_STATUS1; /**< Low power mode information transfer status, array offset: 0x8008, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPM0; /**< LPCG low power mode setting, array offset: 0x8010, array step: 0x40 */ + __IO uint32_t LPM1; /**< LPCG low power mode setting, array offset: 0x8014, array step: 0x40 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPM_CUR; /**< LPM setting of current CPU domain, array offset: 0x801C, array step: 0x40 */ + __I uint32_t STATUS0; /**< LPCG working status, array offset: 0x8020, array step: 0x40 */ + __I uint32_t STATUS1; /**< LPCG domain status, array offset: 0x8024, array step: 0x40 */ + uint8_t RESERVED_2[8]; + __IO uint32_t AUTHEN; /**< LPCG access control, array offset: 0x8030, array step: 0x40 */ + uint8_t RESERVED_3[12]; + } LPCG[127]; +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CLOCK_ROOT - Clock Root Control Register */ +/*! @{ */ + +#define CCM_CLOCK_ROOT_DIV_MASK (0xFFU) +#define CCM_CLOCK_ROOT_DIV_SHIFT (0U) +/*! DIV - Clock division fraction. */ +#define CCM_CLOCK_ROOT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_DIV_SHIFT)) & CCM_CLOCK_ROOT_DIV_MASK) + +#define CCM_CLOCK_ROOT_MUX_MASK (0x300U) +#define CCM_CLOCK_ROOT_MUX_SHIFT (8U) +/*! MUX - Clock multiplexer. + * 0b00..Select clock source 0 + * 0b01..Select clock source 1 + * 0b10..Select clock source 2 + * 0b11..Select clock source 3 + */ +#define CCM_CLOCK_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_MUX_SHIFT)) & CCM_CLOCK_ROOT_MUX_MASK) + +#define CCM_CLOCK_ROOT_OFF_MASK (0x1000000U) +#define CCM_CLOCK_ROOT_OFF_SHIFT (24U) +/*! OFF - Shutdown clock root. + * 0b0..Clock is running. + * 0b1..Turn off clock. + */ +#define CCM_CLOCK_ROOT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OFF_SHIFT)) & CCM_CLOCK_ROOT_OFF_MASK) +/*! @} */ + +/*! @name CLOCK_ROOT_STATUS0 - Clock root working status */ +/*! @{ */ + +#define CCM_CLOCK_ROOT_STATUS0_DIV_MASK (0xFFU) +#define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT (0U) +/*! DIV - Current clock root DIV setting */ +#define CCM_CLOCK_ROOT_STATUS0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_MUX_MASK (0x300U) +#define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT (8U) +/*! MUX - Current clock root MUX setting */ +#define CCM_CLOCK_ROOT_STATUS0_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_OFF_MASK (0x1000000U) +#define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT (24U) +/*! OFF - Current clock root OFF setting + * 0b0..Clock is running. + * 0b1..Turn off clock. + */ +#define CCM_CLOCK_ROOT_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK (0x10000000U) +#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT (28U) +/*! SLICE_BUSY - Indication for clock generation logic is applying new setting. + * 0b0..Clock generation logic is not busy. + * 0b1..Clock generation logic is applying new setting. + */ +#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK (0x80000000U) +#define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT (31U) +/*! CHANGING - Internal updating in clock root + * 0b0..Clock Status is not updating currently + * 0b1..Clock generation logic is updating currently + */ +#define CCM_CLOCK_ROOT_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK) +/*! @} */ + +/* The count of CCM_CLOCK_ROOT_STATUS0 */ +#define CCM_CLOCK_ROOT_STATUS0_COUNT (95U) + +/*! @name CLOCK_ROOT - Clock root access control */ +/*! @{ */ + +#define CCM_CLOCK_ROOT_TZ_USER_MASK (0x100U) +#define CCM_CLOCK_ROOT_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Clock Root settings cannot be changed in user mode. + * 0b1..Clock Root settings can be changed in user mode. + */ +#define CCM_CLOCK_ROOT_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_TZ_USER_MASK) + +#define CCM_CLOCK_ROOT_TZ_NS_MASK (0x200U) +#define CCM_CLOCK_ROOT_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_CLOCK_ROOT_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_TZ_NS_MASK) + +#define CCM_CLOCK_ROOT_LOCK_TZ_MASK (0x800U) +#define CCM_CLOCK_ROOT_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone setting is not locked. + * 0b1..TrustZone setting is locked. + */ +#define CCM_CLOCK_ROOT_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_LOCK_TZ_MASK) + +#define CCM_CLOCK_ROOT_LOCK_LIST_MASK (0x8000U) +#define CCM_CLOCK_ROOT_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_CLOCK_ROOT_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_LOCK_LIST_MASK) + +#define CCM_CLOCK_ROOT_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_CLOCK_ROOT_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_CLOCK_ROOT_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED0_AUTHEN - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED0_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED0_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED1 - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_SHARED1_CA55_CLOCK_SELECT_MASK (0x1U) +#define CCM_GPR_SHARED1_CA55_CLOCK_SELECT_SHIFT (0U) +/*! CA55_CLOCK_SELECT - Clock select signal between ccm clock root and ARM PLL clock + * 0b0..Clkroot_arm_a55 is used. + * 0b1..The clock output of ARM PLL is selected. + */ +#define CCM_GPR_SHARED1_CA55_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CLOCK_SELECT_MASK) +/*! @} */ + +/*! @name GPR_SHARED1_AUTHEN - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED1_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED2 - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK (0x1U) +#define CCM_GPR_SHARED2_DRAM_PLL_BYPASS_SHIFT (0U) +/*! DRAM_PLL_BYPASS - Clock select signal between ccm clock root and DRAM PLL clock + * 0b0..The clock output of DRAM PLL is selected. + * 0b1..Dram_alt_clk_root is selected. + */ +#define CCM_GPR_SHARED2_DRAM_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_DRAM_PLL_BYPASS_SHIFT)) & CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK) +/*! @} */ + +/*! @name GPR_SHARED2_AUTHEN - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED2_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TZ_USER_SHIFT)) & CCM_GPR_SHARED_TZ_USER_MASK) + +#define CCM_GPR_SHARED_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TZ_NS_SHIFT)) & CCM_GPR_SHARED_TZ_NS_MASK) + +#define CCM_GPR_SHARED_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE - General puspose register */ +/*! @{ */ + +#define CCM_GPR_PRIVATE_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE_GPR_SHIFT (0U) +/*! GPR - GP register */ +#define CCM_GPR_PRIVATE_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_GPR_SHIFT)) & CCM_GPR_PRIVATE_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE_TZ_USER_MASK (0x100U) +#define CCM_GPR_PRIVATE_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of privat GPR cannot be changed in user mode. + * 0b1..Registers of private GPR can be changed in user mode. + */ +#define CCM_GPR_PRIVATE_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE_TZ_NS_MASK (0x200U) +#define CCM_GPR_PRIVATE_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_PRIVATE_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_PRIVATE_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_PRIVATE_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_PRIVATE_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_PRIVATE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_PRIVATE_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_PRIVATE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_WHITE_LIST_MASK) +/*! @} */ + +/*! @name OSCPLL_DIRECT - Clock source direct control */ +/*! @{ */ + +#define CCM_OSCPLL_DIRECT_ON_MASK (0x1U) +#define CCM_OSCPLL_DIRECT_ON_SHIFT (0U) +/*! ON - Turn on clock source + * 0b0..Clock source is OFF. + * 0b1..Clock source is ON. + */ +#define CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_DIRECT */ +#define CCM_OSCPLL_DIRECT_COUNT (20U) + +/*! @name OSCPLL_LPM_STATUS0 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK (0x3U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT (0U) +/*! CPU_MODE_DOMAIN0 - Current mode of CPU domain 0 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK (0x4U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT (2U) +/*! TRANS_REQ_DOMAIN0 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK (0x30U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT (4U) +/*! CPU_MODE_DOMAIN1 - Current mode of CPU domain 1 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK (0x40U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT (6U) +/*! TRANS_REQ_DOMAIN1 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK (0x300U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT (8U) +/*! CPU_MODE_DOMAIN2 - Current mode of CPU domain 2 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK (0x400U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT (10U) +/*! TRANS_REQ_DOMAIN2 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK (0x3000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT (12U) +/*! CPU_MODE_DOMAIN3 - Current mode of CPU domain 3 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK (0x4000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT (14U) +/*! TRANS_REQ_DOMAIN3 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK (0x30000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT (16U) +/*! CPU_MODE_DOMAIN4 - Current mode of CPU domain 4 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK (0x40000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT (18U) +/*! TRANS_REQ_DOMAIN4 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK (0x300000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT (20U) +/*! CPU_MODE_DOMAIN5 - Current mode of CPU domain 5 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK (0x400000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT (22U) +/*! TRANS_REQ_DOMAIN5 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK (0x3000000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT (24U) +/*! CPU_MODE_DOMAIN6 - Current mode of CPU domain 6 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK (0x4000000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT (26U) +/*! TRANS_REQ_DOMAIN6 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK (0x30000000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT (28U) +/*! CPU_MODE_DOMAIN7 - Current mode of CPU domain 7 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK (0x40000000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT (30U) +/*! TRANS_REQ_DOMAIN7 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM_STATUS0 */ +#define CCM_OSCPLL_LPM_STATUS0_COUNT (20U) + +/*! @name OSCPLL_LPM_STATUS1 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK (0x3U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT (0U) +/*! CPU_MODE_DOMAIN8 - Current mode of CPU domain 8 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK (0x4U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT (2U) +/*! TRANS_REQ_DOMAIN8 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK (0x30U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT (4U) +/*! CPU_MODE_DOMAIN9 - Current mode of CPU domain 9 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK (0x40U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT (6U) +/*! TRANS_REQ_DOMAIN9 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK (0x300U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT (8U) +/*! CPU_MODE_DOMAIN10 - Current mode of CPU domain 10 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK (0x400U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT (10U) +/*! TRANS_REQ_DOMAIN10 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK (0x3000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT (12U) +/*! CPU_MODE_DOMAIN11 - Current mode of CPU domain 11 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK (0x4000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT (14U) +/*! TRANS_REQ_DOMAIN11 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK (0x30000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT (16U) +/*! CPU_MODE_DOMAIN12 - Current mode of CPU domain 12 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK (0x40000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT (18U) +/*! TRANS_REQ_DOMAIN12 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK (0x300000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT (20U) +/*! CPU_MODE_DOMAIN13 - Current mode of CPU domain 13 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK (0x400000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT (22U) +/*! TRANS_REQ_DOMAIN13 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK (0x3000000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT (24U) +/*! CPU_MODE_DOMAIN14 - Current mode of CPU domain 14 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK (0x4000000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT (26U) +/*! TRANS_REQ_DOMAIN14 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK (0x30000000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT (28U) +/*! CPU_MODE_DOMAIN15 - Current mode of CPU domain 15 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK (0x40000000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT (30U) +/*! TRANS_REQ_DOMAIN15 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM_STATUS1 */ +#define CCM_OSCPLL_LPM_STATUS1_COUNT (20U) + +/*! @name OSCPLL_LPM0 - Clock source low power mode setting */ +/*! @{ */ + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK (0x7U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT (0U) +/*! LPM_SETTING_D0 - Clock Source LPM in DOMAIN0 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK (0x70U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT (4U) +/*! LPM_SETTING_D1 - Clock Source LPM in DOMAIN1 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK (0x700U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT (8U) +/*! LPM_SETTING_D2 - Clock Source LPM in DOMAIN2 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK (0x7000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT (12U) +/*! LPM_SETTING_D3 - Clock Source LPM in DOMAIN3 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK (0x70000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT (16U) +/*! LPM_SETTING_D4 - Clock Source LPM in DOMAIN4 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK (0x700000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT (20U) +/*! LPM_SETTING_D5 - Clock Source LPM in DOMAIN5 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK (0x7000000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT (24U) +/*! LPM_SETTING_D6 - Clock Source LPM in DOMAIN6 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK (0x70000000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT (28U) +/*! LPM_SETTING_D7 - Clock Source LPM in DOMAIN7 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM0 */ +#define CCM_OSCPLL_LPM0_COUNT (20U) + +/*! @name OSCPLL_LPM1 - clock source low power mode setting */ +/*! @{ */ + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK (0x7U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT (0U) +/*! LPM_SETTING_D8 - Clock Source LPM in DOMAIN8 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK (0x70U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT (4U) +/*! LPM_SETTING_D9 - Clock Source LPM in DOMAIN9 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK (0x700U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT (8U) +/*! LPM_SETTING_D10 - Clock Source LPM in DOMAIN10 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK (0x7000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT (12U) +/*! LPM_SETTING_D11 - Clock Source LPM in DOMAIN11 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK (0x70000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT (16U) +/*! LPM_SETTING_D12 - Clock Source LPM in DOMAIN12 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK (0x700000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT (20U) +/*! LPM_SETTING_D13 - Clock Source LPM in DOMAIN13 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK (0x7000000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT (24U) +/*! LPM_SETTING_D14 - Clock Source LPM in DOMAIN14 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK (0x70000000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT (28U) +/*! LPM_SETTING_D15 - Clock Source LPM in DOMAIN15 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM1 */ +#define CCM_OSCPLL_LPM1_COUNT (20U) + +/*! @name OSCPLL_LPM_CUR - LPM setting of current CPU domain */ +/*! @{ */ + +#define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK (0x7U) +#define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT (0U) +/*! LPM_SETTING_CUR - LPM SETTING of current CPU DOMAIN */ +#define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM_CUR */ +#define CCM_OSCPLL_LPM_CUR_COUNT (20U) + +/*! @name OSCPLL_STATUS0 - Clock source working status */ +/*! @{ */ + +#define CCM_OSCPLL_STATUS0_ON_MASK (0x1U) +#define CCM_OSCPLL_STATUS0_ON_SHIFT (0U) +/*! ON - Clock source current state + * 0b0..Clock source is OFF. + * 0b1..Clock source is ON. + */ +#define CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK) + +#define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U) +#define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U) +#define CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK) + +#define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U) +#define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U) +#define CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK) + +#define CCM_OSCPLL_STATUS0_IN_USE_MASK (0x1000U) +#define CCM_OSCPLL_STATUS0_IN_USE_SHIFT (12U) +/*! IN_USE - This Clock Source is being used or not. + * 0b0..Clock Source is not being used. + * 0b1..Clock Source is being used. + */ +#define CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_STATUS0 */ +#define CCM_OSCPLL_STATUS0_COUNT (20U) + +/*! @name OSCPLL_STATUS1 - Clock source domain status */ +/*! @{ */ + +#define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK (0xFFFFU) +#define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT (0U) +/*! DOMAIN_ACTIVE - Domain active */ +#define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK) + +#define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK (0xFFFF0000U) +#define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT (16U) +/*! DOMAIN_ENABLE - Domain enable */ +#define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_STATUS1 */ +#define CCM_OSCPLL_STATUS1_COUNT (20U) + +/*! @name OSCPLL_AUTHEN - Clock Source access control */ +/*! @{ */ + +#define CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK (0x4U) +#define CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT (2U) +/*! CPULPM_MODE - CPULPM mode enable + * 0b0..Disable CPULPM mode. + * 0b1..Enable CPULPM mode. + */ +#define CCM_OSCPLL_AUTHEN_CPULPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK) + +#define CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK (0x8U) +#define CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT (3U) +/*! AUTO_CTRL - Auto mode enable + * 0b0..Disable Auto mode + * 0b1..Enable Auto mode + */ +#define CCM_OSCPLL_AUTHEN_AUTO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT)) & CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x80U) +#define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (7U) +/*! LOCK_MODE + * 0b0..CPULPM_MODE and AUTO_CTRL is not locked. + * 0b1..CPULPM_MODE and AUTO_CTRL is locked. + */ +#define CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK) + +#define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Clock Source settings cannot be changed in user mode. + * 0b1..Clock Source settings can be changed in user mode. + */ +#define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK) + +#define CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK) + +#define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist */ +#define CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_AUTHEN */ +#define CCM_OSCPLL_AUTHEN_COUNT (20U) + +/*! @name LPCG_DIRECT - LPCG direct control */ +/*! @{ */ + +#define CCM_LPCG_DIRECT_ON_MASK (0x1U) +#define CCM_LPCG_DIRECT_ON_SHIFT (0U) +/*! ON - Turn on LPCG + * 0b0..LPCG gate clock + * 0b1..LPCG ungate clock + */ +#define CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK) + +#define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK (0x4U) +#define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT (2U) +/*! CLKOFF_ACK_TIMEOUT_EN - Clock off handshake timeout enable + * 0b0..disable + * 0b1..enable + */ +#define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT)) & CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK) +/*! @} */ + +/* The count of CCM_LPCG_DIRECT */ +#define CCM_LPCG_DIRECT_COUNT (127U) + +/*! @name LPCG_LPM_STATUS0 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK (0x3U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT (0U) +/*! CPU_MODE_DOMAIN0 - Current mode of CPU domain 0 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK (0x4U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT (2U) +/*! TRANS_REQ_DOMAIN0 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK (0x30U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT (4U) +/*! CPU_MODE_DOMAIN1 - Current mode of CPU domain 1 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK (0x40U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT (6U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK (0x300U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT (8U) +/*! CPU_MODE_DOMAIN2 - Current mode of CPU domain 2 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK (0x400U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT (10U) +/*! TRANS_REQ_DOMAIN2 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK (0x3000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT (12U) +/*! CPU_MODE_DOMAIN3 - Current mode of CPU domain 3 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK (0x4000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT (14U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK (0x30000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT (16U) +/*! CPU_MODE_DOMAIN4 - Current mode of CPU domain 4 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK (0x40000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT (18U) +/*! TRANS_REQ_DOMAIN4 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK (0x300000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT (20U) +/*! CPU_MODE_DOMAIN5 - Current mode of CPU domain 5 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK (0x400000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT (22U) +/*! TRANS_REQ_DOMAIN5 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK (0x3000000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT (24U) +/*! CPU_MODE_DOMAIN6 - Current mode of CPU domain 6 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK (0x4000000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT (26U) +/*! TRANS_REQ_DOMAIN6 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK (0x30000000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT (28U) +/*! CPU_MODE_DOMAIN7 - Current mode of CPU domain 7 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK (0x40000000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT (30U) +/*! TRANS_REQ_DOMAIN7 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM_STATUS0 */ +#define CCM_LPCG_LPM_STATUS0_COUNT (127U) + +/*! @name LPCG_LPM_STATUS1 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK (0x3U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT (0U) +/*! CPU_MODE_DOMAIN8 - Current mode of CPU domain 8 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK (0x4U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT (2U) +/*! TRANS_REQ_DOMAIN8 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK (0x30U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT (4U) +/*! CPU_MODE_DOMAIN9 - Current mode of CPU domain 9 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK (0x40U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT (6U) +/*! TRANS_REQ_DOMAIN9 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK (0x300U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT (8U) +/*! CPU_MODE_DOMAIN10 - Current mode of CPU domain 10 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK (0x400U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT (10U) +/*! TRANS_REQ_DOMAIN10 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK (0x3000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT (12U) +/*! CPU_MODE_DOMAIN11 - Current mode of CPU domain 11 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK (0x4000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT (14U) +/*! TRANS_REQ_DOMAIN11 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK (0x30000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT (16U) +/*! CPU_MODE_DOMAIN12 - Current mode of CPU domain 12 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK (0x40000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT (18U) +/*! TRANS_REQ_DOMAIN12 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK (0x300000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT (20U) +/*! CPU_MODE_DOMAIN13 - Current mode of CPU domain 13 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK (0x400000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT (22U) +/*! TRANS_REQ_DOMAIN13 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK (0x3000000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT (24U) +/*! CPU_MODE_DOMAIN14 - Current mode of CPU domain 14 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK (0x4000000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT (26U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK (0x30000000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT (28U) +/*! CPU_MODE_DOMAIN15 - Current mode of CPU domain 15 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK (0x40000000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT (30U) +/*! TRANS_REQ_DOMAIN15 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM_STATUS1 */ +#define CCM_LPCG_LPM_STATUS1_COUNT (127U) + +/*! @name LPCG_LPM0 - LPCG low power mode setting */ +/*! @{ */ + +#define CCM_LPCG_LPM0_LPM_SETTING_D0_MASK (0x7U) +#define CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT (0U) +/*! LPM_SETTING_D0 - LPCG LPM in DOMAIN0 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D0_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D1_MASK (0x70U) +#define CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT (4U) +/*! LPM_SETTING_D1 - LPCG LPM in DOMAIN1 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D1_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D2_MASK (0x700U) +#define CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT (8U) +/*! LPM_SETTING_D2 - LPCG LPM in DOMAIN2 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D2_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D3_MASK (0x7000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT (12U) +/*! LPM_SETTING_D3 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D3_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D4_MASK (0x70000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT (16U) +/*! LPM_SETTING_D4 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D4_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D5_MASK (0x700000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT (20U) +/*! LPM_SETTING_D5 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D5_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D6_MASK (0x7000000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT (24U) +/*! LPM_SETTING_D6 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D6_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D7_MASK (0x70000000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT (28U) +/*! LPM_SETTING_D7 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D7_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM0 */ +#define CCM_LPCG_LPM0_COUNT (127U) + +/*! @name LPCG_LPM1 - LPCG low power mode setting */ +/*! @{ */ + +#define CCM_LPCG_LPM1_LPM_SETTING_D8_MASK (0x7U) +#define CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT (0U) +/*! LPM_SETTING_D8 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D8_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D9_MASK (0x70U) +#define CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT (4U) +/*! LPM_SETTING_D9 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D9_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D10_MASK (0x700U) +#define CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT (8U) +/*! LPM_SETTING_D10 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D10_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D11_MASK (0x7000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT (12U) +/*! LPM_SETTING_D11 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D11_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D12_MASK (0x70000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT (16U) +/*! LPM_SETTING_D12 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D12_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D13_MASK (0x700000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT (20U) +/*! LPM_SETTING_D13 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D13_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D14_MASK (0x7000000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT (24U) +/*! LPM_SETTING_D14 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D14_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D15_MASK (0x70000000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT (28U) +/*! LPM_SETTING_D15 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D15_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM1 */ +#define CCM_LPCG_LPM1_COUNT (127U) + +/*! @name LPCG_LPM_CUR - LPM setting of current CPU domain */ +/*! @{ */ + +#define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK (0x7U) +#define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT (0U) +/*! LPM_SETTING_CUR - LPM SETTING of current CPU DOMAIN */ +#define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM_CUR */ +#define CCM_LPCG_LPM_CUR_COUNT (127U) + +/*! @name LPCG_STATUS0 - LPCG working status */ +/*! @{ */ + +#define CCM_LPCG_STATUS0_ON_MASK (0x1U) +#define CCM_LPCG_STATUS0_ON_SHIFT (0U) +/*! ON - LPCG work status + * 0b0..LPCG is OFF. + * 0b1..LPCG is ON. + */ +#define CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK) +/*! @} */ + +/* The count of CCM_LPCG_STATUS0 */ +#define CCM_LPCG_STATUS0_COUNT (127U) + +/*! @name LPCG_STATUS1 - LPCG domain status */ +/*! @{ */ + +#define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK (0xFFFFU) +#define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT (0U) +/*! DOMAIN_ACTIVE - Domain active */ +#define CCM_LPCG_STATUS1_DOMAIN_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK) + +#define CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK (0xFFFF0000U) +#define CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT (16U) +/*! DOMAIN_ENABLE - Domain enable */ +#define CCM_LPCG_STATUS1_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_LPCG_STATUS1 */ +#define CCM_LPCG_STATUS1_COUNT (127U) + +/*! @name LPCG_AUTHEN - LPCG access control */ +/*! @{ */ + +#define CCM_LPCG_AUTHEN_CPULPM_MODE_MASK (0x4U) +#define CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT (2U) +/*! CPULPM_MODE - CPULPM mode enable + * 0b0..Disable CPULPM mode, this LPCG is in Direct Control mode. + * 0b1..Enable CPULPM mode, this LPCG is in CPULPM mode. + */ +#define CCM_LPCG_AUTHEN_CPULPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MODE_MASK) + +#define CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x80U) +#define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (7U) +/*! LOCK_MODE + * 0b0..CPULPM_MODE is not locked. + * 0b1..CPULPM_MODE is locked. + */ +#define CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK) + +#define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..LPCG settings cannot be changed in user mode. + * 0b1..LPCG settings can be changed in user mode. + */ +#define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK) + +#define CCM_LPCG_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_LPCG_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK) + +#define CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK) + +#define CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK) + +#define CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist */ +#define CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/* The count of CCM_LPCG_AUTHEN */ +#define CCM_LPCG_AUTHEN_COUNT (127U) + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM_CTRL base address */ +#define CCM_CTRL_BASE (0x44450000u) +/** Peripheral CCM_CTRL base pointer */ +extern CCM_Type* CCM_CTRL; +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_CTRL_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM_CTRL } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DDRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer + * @{ + */ + +/** DDRC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x8 */ + __IO uint32_t CS_BNDS; /**< Rank 0 Memory Bounds..Rank 1 Memory Bounds, array offset: 0x0, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } CS_BNDS[2]; + uint8_t RESERVED_0[16]; + __IO uint32_t REMAP_0A; /**< Remap Region 0A Configuration, offset: 0x20 */ + __IO uint32_t REMAP_0B; /**< Remap Region 0B Configuration, offset: 0x24 */ + __IO uint32_t REMAP_1A; /**< Remap Region 1A Configuration, offset: 0x28 */ + __IO uint32_t REMAP_1B; /**< Remap Region 1B Configuration, offset: 0x2C */ + __IO uint32_t REMAP_2A; /**< Remap Region 2A Configuration, offset: 0x30 */ + __IO uint32_t REMAP_2B; /**< Remap Region 2B Configuration, offset: 0x34 */ + __IO uint32_t REMAP_3A; /**< Remap Region 3A Configuration, offset: 0x38 */ + __IO uint32_t REMAP_3B; /**< Remap Region 3B Configuration, offset: 0x3C */ + __IO uint32_t DDR_ADDR_DEC_0; /**< DDRC Address Decode 0, offset: 0x40 */ + __IO uint32_t DDR_ADDR_DEC_1; /**< DDRC Address Decode 1, offset: 0x44 */ + __IO uint32_t DDR_ADDR_DEC_2; /**< DDRC Address Decode 2, offset: 0x48 */ + __IO uint32_t DDR_ADDR_DEC_3; /**< DDRC Address Decode 3, offset: 0x4C */ + __IO uint32_t DDR_ADDR_DEC_4; /**< DDRC Address Decode 4, offset: 0x50 */ + __IO uint32_t DDR_ADDR_DEC_5; /**< DDRC Address Decode 5, offset: 0x54 */ + __IO uint32_t DDR_ADDR_DEC_6; /**< DDRC Address Decode 6, offset: 0x58 */ + __IO uint32_t DDR_ADDR_DEC_7; /**< DDRC Address Decode 7, offset: 0x5C */ + __IO uint32_t DDR_ADDR_DEC_8; /**< DDRC Address Decode 8, offset: 0x60 */ + __IO uint32_t DDR_ADDR_DEC_9; /**< DDRC Address Decode 9, offset: 0x64 */ + uint8_t RESERVED_1[24]; + __IO uint32_t CS_CONFIG[2]; /**< Rank 0 Configuration..Rank 1 Configuration, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t TIMING_CFG_3; /**< DDR SDRAM Timing Configuration 3, offset: 0x100 */ + __IO uint32_t TIMING_CFG_0; /**< DDR SDRAM Timing Configuration 0, offset: 0x104 */ + __IO uint32_t TIMING_CFG_1; /**< DDR SDRAM Timing Configuration 1, offset: 0x108 */ + __IO uint32_t TIMING_CFG_2; /**< DDR SDRAM Timing Configuration 2, offset: 0x10C */ + __IO uint32_t DDR_SDRAM_CFG; /**< DDR SDRAM Control Configuration, offset: 0x110 */ + __IO uint32_t DDR_SDRAM_CFG_2; /**< DDR SDRAM Control Configuration 2, offset: 0x114 */ + uint8_t RESERVED_3[8]; + __IO uint32_t DDR_SDRAM_MD_CNTL; /**< DDR SDRAM Mode Control, offset: 0x120 */ + __IO uint32_t DDR_SDRAM_INTERVAL; /**< DDR SDRAM Interval Configuration, offset: 0x124 */ + __IO uint32_t DDR_DATA_INIT; /**< DDR SDRAM Data Initialization, offset: 0x128 */ + uint8_t RESERVED_4[52]; + __IO uint32_t TIMING_CFG_4; /**< DDR SDRAM Timing Configuration 4, offset: 0x160 */ + uint8_t RESERVED_5[8]; + __IO uint32_t TIMING_CFG_7; /**< DDR SDRAM Timing Configuration 7, offset: 0x16C */ + __IO uint32_t DDR_ZQ_CNTL; /**< DDR SDRAM ZQ Calibration Control, offset: 0x170 */ + uint8_t RESERVED_6[8]; + __IO uint32_t DDR_SR_CNTR; /**< DDR SDRAM Self-Refresh Counter, offset: 0x17C */ + uint8_t RESERVED_7[208]; + __IO uint32_t TIMING_CFG_8; /**< DDR SDRAM Timing Configuration 8, offset: 0x250 */ + __IO uint32_t TIMING_CFG_9; /**< DDR SDRAM timing configuration 9, offset: 0x254 */ + __IO uint32_t TIMING_CFG_10; /**< DDR SDRAM Timing Configuration 10, offset: 0x258 */ + __IO uint32_t TIMING_CFG_11; /**< DDR SDRAM Timing Configuration 11, offset: 0x25C */ + __IO uint32_t DDR_SDRAM_CFG_3; /**< DDR SDRAM Control Configuration 3, offset: 0x260 */ + __IO uint32_t DDR_SDRAM_CFG_4; /**< DDR SDRAM Control Configuration 4, offset: 0x264 */ + uint8_t RESERVED_8[88]; + __I uint32_t DDR_SDRAM_REF_RATE; /**< DDR Refresh Rate, offset: 0x2C0 */ + uint8_t RESERVED_9[60]; + __IO uint32_t TIMING_CFG_12; /**< DDR SDRAM Timing Configuration 12, offset: 0x300 */ + __IO uint32_t TIMING_CFG_13; /**< DDR SDRAM Timing Configuration 13, offset: 0x304 */ + __IO uint32_t TIMING_CFG_14; /**< DDR SDRAM Timing Configuration 14, offset: 0x308 */ + uint8_t RESERVED_10[1268]; + __IO uint32_t TX_CFG_1; /**< Transaction Configuration Register 1, offset: 0x800 */ + uint8_t RESERVED_11[800]; + __IO uint32_t DDRDSR_2; /**< DDR SDRAM Debug Status 2, offset: 0xB24 */ + uint8_t RESERVED_12[208]; + __I uint32_t DDR_IP_REV1; /**< DDRC Revision 1, offset: 0xBF8 */ + uint8_t RESERVED_13[260]; + __IO uint32_t DDR_MTCR; /**< DDR SDRAM Memory Test Control, offset: 0xD00 */ + uint8_t RESERVED_14[28]; + __IO uint32_t DDR_MTP[10]; /**< DDR SDRAM Memory Test Pattern n, array offset: 0xD20, array step: 0x4 */ + uint8_t RESERVED_15[24]; + __IO uint32_t DDR_MT_ST_EXT_ADDR; /**< DDR SDRAM Memory Test Start Extended Address, offset: 0xD60 */ + __IO uint32_t DDR_MT_ST_ADDR; /**< DDR SDRAM Memory Test Start Address, offset: 0xD64 */ + __IO uint32_t DDR_MT_END_EXT_ADDR; /**< DDR SDRAM Memory Test End Extended Address, offset: 0xD68 */ + __IO uint32_t DDR_MT_END_ADDR; /**< DDR SDRAM Memory Test End Address, offset: 0xD6C */ + uint8_t RESERVED_16[144]; + __IO uint32_t PMGC0; /**< Performance Monitor Global Control, offset: 0xE00 */ + uint8_t RESERVED_17[12]; + __IO uint32_t PMLCA0; /**< Performance Monitor Local Control A0, offset: 0xE10 */ + __IO uint32_t PMLCB0; /**< Performance Monitor Local Control B0, offset: 0xE14 */ + __IO uint32_t PMC0A; /**< PMC 0a, offset: 0xE18 */ + __IO uint32_t PMC0B; /**< PMC 0b, offset: 0xE1C */ + __IO uint32_t PMLCA1; /**< Performance Monitor Local Control A, offset: 0xE20 */ + __IO uint32_t PMLCB1; /**< Performance Monitor Local Control B, offset: 0xE24 */ + __IO uint32_t PMC1; /**< Performance Monitor Counter, offset: 0xE28 */ + uint8_t RESERVED_18[4]; + __IO uint32_t PMLCA2; /**< Performance Monitor Local Control A, offset: 0xE30 */ + __IO uint32_t PMLCB2; /**< Performance Monitor Local Control B, offset: 0xE34 */ + __IO uint32_t PMC2; /**< Performance Monitor Counter, offset: 0xE38 */ + uint8_t RESERVED_19[4]; + __IO uint32_t PMLCA3; /**< Performance Monitor Local Control A, offset: 0xE40 */ + __IO uint32_t PMLCB3; /**< Performance Monitor Local Control B, offset: 0xE44 */ + __IO uint32_t PMC3; /**< Performance Monitor Counter, offset: 0xE48 */ + uint8_t RESERVED_20[4]; + __IO uint32_t PMLCA4; /**< Performance Monitor Local Control A, offset: 0xE50 */ + __IO uint32_t PMLCB4; /**< Performance Monitor Local Control B, offset: 0xE54 */ + __IO uint32_t PMC4; /**< Performance Monitor Counter, offset: 0xE58 */ + uint8_t RESERVED_21[4]; + __IO uint32_t PMLCA5; /**< Performance Monitor Local Control A, offset: 0xE60 */ + __IO uint32_t PMLCB5; /**< Performance Monitor Local Control B, offset: 0xE64 */ + __IO uint32_t PMC5; /**< Performance Monitor Counter, offset: 0xE68 */ + uint8_t RESERVED_22[4]; + __IO uint32_t PMLCA6; /**< Performance Monitor Local Control A, offset: 0xE70 */ + __IO uint32_t PMLCB6; /**< Performance Monitor Local Control B, offset: 0xE74 */ + __IO uint32_t PMC6; /**< Performance Monitor Counter, offset: 0xE78 */ + uint8_t RESERVED_23[4]; + __IO uint32_t PMLCA7; /**< Performance Monitor Local Control A, offset: 0xE80 */ + __IO uint32_t PMLCB7; /**< Performance Monitor Local Control B, offset: 0xE84 */ + __IO uint32_t PMC7; /**< Performance Monitor Counter, offset: 0xE88 */ + uint8_t RESERVED_24[4]; + __IO uint32_t PMLCA8; /**< Performance Monitor Local Control A, offset: 0xE90 */ + __IO uint32_t PMLCB8; /**< Performance Monitor Local Control B, offset: 0xE94 */ + __IO uint32_t PMC8; /**< Performance Monitor Counter, offset: 0xE98 */ + uint8_t RESERVED_25[4]; + __IO uint32_t PMLCA9; /**< Performance Monitor Local Control A, offset: 0xEA0 */ + __IO uint32_t PMLCB9; /**< Performance Monitor Local Control B, offset: 0xEA4 */ + __IO uint32_t PMC9; /**< Performance Monitor Counter, offset: 0xEA8 */ + uint8_t RESERVED_26[4]; + __IO uint32_t PMLCA10; /**< Performance Monitor Local Control A, offset: 0xEB0 */ + __IO uint32_t PMLCB10; /**< Performance Monitor Local Control B, offset: 0xEB4 */ + __IO uint32_t PMC10; /**< Performance Monitor Counter, offset: 0xEB8 */ + uint8_t RESERVED_27[324]; + __IO uint32_t ERR_EN; /**< Error Enable, offset: 0x1000 */ + uint8_t RESERVED_28[252]; + __IO uint32_t DATA_ERR_INJECT_HI; /**< Memory Data Path Error Injection Mask High, offset: 0x1100 */ + __IO uint32_t DATA_ERR_INJECT_LO; /**< Memory Data Path Error Injection Mask Low, offset: 0x1104 */ + __IO uint32_t ERR_INJECT; /**< Memory Data Path Error Injection Mask ECC, offset: 0x1108 */ + __IO uint32_t ADDR_ERR_INJ; /**< Address Error Inject, offset: 0x110C */ + uint8_t RESERVED_29[8]; + __IO uint32_t CAPTURE_EXT_DATA_HI; /**< Memory Extended Data Path Read Capture High, offset: 0x1118 */ + __IO uint32_t CAPTURE_EXT_DATA_LO; /**< Memory Extended Data Path Read Capture Low, offset: 0x111C */ + __IO uint32_t CAPTURE_DATA_HI; /**< Memory Data Path Read Capture High, offset: 0x1120 */ + __IO uint32_t CAPTURE_DATA_LO; /**< Memory Data Path Read Capture Low, offset: 0x1124 */ + __IO uint32_t CAPTURE_ECC; /**< Memory Data Path Read Capture ECC, offset: 0x1128 */ + uint8_t RESERVED_30[20]; + __IO uint32_t ERR_DETECT; /**< Memory Error Detect, offset: 0x1140 */ + __IO uint32_t ERR_DISABLE; /**< Memory Error Disable, offset: 0x1144 */ + __IO uint32_t ERR_INT_EN; /**< Memory Error Interrupt Enable, offset: 0x1148 */ + __IO uint32_t CAPTURE_ATTRIBUTES; /**< Memory Error Attributes Capture, offset: 0x114C */ + __IO uint32_t CAPTURE_ADDRESS; /**< Memory Error Address Capture, offset: 0x1150 */ + __IO uint32_t CAPTURE_EXT_ADDRESS; /**< Memory Error Extended Address Capture, offset: 0x1154 */ + __IO uint32_t ERR_SBE; /**< Single-Bit ECC Memory Error Management, offset: 0x1158 */ + uint8_t RESERVED_31[228]; + __IO uint32_t ECC_REG_0; /**< ECC Region 0 Configuration, offset: 0x1240 */ + __IO uint32_t ECC_REG_1; /**< ECC Region 1 Configuration, offset: 0x1244 */ + __IO uint32_t ECC_REG_2; /**< ECC Region 2 Configuration, offset: 0x1248 */ + __IO uint32_t ECC_REG_3; /**< ECC Region 3 Configuration, offset: 0x124C */ + __IO uint32_t ECC_REG_4; /**< ECC Region 4 Configuration, offset: 0x1250 */ + __IO uint32_t ECC_REG_5; /**< ECC Region 5 Configuration, offset: 0x1254 */ + __IO uint32_t ECC_REG_6; /**< ECC Region 6 Configuration, offset: 0x1258 */ + __IO uint32_t ECC_REG_7; /**< ECC Region 7 Configuration, offset: 0x125C */ +} DDRC_Type; + +/* ---------------------------------------------------------------------------- + -- DDRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Masks DDRC Register Masks + * @{ + */ + +/*! @name CS_BNDS - Rank 0 Memory Bounds..Rank 1 Memory Bounds */ +/*! @{ */ + +#define DDRC_CS_BNDS_EA_MASK (0xFFFFU) +#define DDRC_CS_BNDS_EA_SHIFT (0U) +/*! EA - Ending Address */ +#define DDRC_CS_BNDS_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_EA_SHIFT)) & DDRC_CS_BNDS_EA_MASK) + +#define DDRC_CS_BNDS_SA_MASK (0xFFFF0000U) +#define DDRC_CS_BNDS_SA_SHIFT (16U) +/*! SA - Starting Address */ +#define DDRC_CS_BNDS_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_SA_SHIFT)) & DDRC_CS_BNDS_SA_MASK) +/*! @} */ + +/* The count of DDRC_CS_BNDS */ +#define DDRC_CS_BNDS_COUNT (2U) + +/*! @name REMAP_0A - Remap Region 0A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT (0U) +/*! REG_0_REMAP_ADDR - Region 0 Remap Starting Address */ +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK) + +#define DDRC_REMAP_0A_REG_0_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT (31U) +/*! REG_0_REMAP_EN - Region 0 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_0A_REG_0_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_0B - Remap Region 0B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_0B_REG_0_EA_MASK (0xFFFU) +#define DDRC_REMAP_0B_REG_0_EA_SHIFT (0U) +/*! REG_0_EA - Region 0 Ending Address */ +#define DDRC_REMAP_0B_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_EA_SHIFT)) & DDRC_REMAP_0B_REG_0_EA_MASK) + +#define DDRC_REMAP_0B_REG_0_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_0B_REG_0_SA_SHIFT (16U) +/*! REG_0_SA - Region 0 Starting Address */ +#define DDRC_REMAP_0B_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_SA_SHIFT)) & DDRC_REMAP_0B_REG_0_SA_MASK) +/*! @} */ + +/*! @name REMAP_1A - Remap Region 1A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT (0U) +/*! REG_1_REMAP_ADDR - Region 1 Remap Starting Address */ +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK) + +#define DDRC_REMAP_1A_REG_1_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT (31U) +/*! REG_1_REMAP_EN - Region 1 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_1A_REG_1_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_1B - Remap Region 1B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_1B_REG_1_EA_MASK (0xFFFU) +#define DDRC_REMAP_1B_REG_1_EA_SHIFT (0U) +/*! REG_1_EA - Region 1 Ending Address */ +#define DDRC_REMAP_1B_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_EA_SHIFT)) & DDRC_REMAP_1B_REG_1_EA_MASK) + +#define DDRC_REMAP_1B_REG_1_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_1B_REG_1_SA_SHIFT (16U) +/*! REG_1_SA - Region 1 Starting Address */ +#define DDRC_REMAP_1B_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_SA_SHIFT)) & DDRC_REMAP_1B_REG_1_SA_MASK) +/*! @} */ + +/*! @name REMAP_2A - Remap Region 2A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT (0U) +/*! REG_2_REMAP_ADDR - Region 2 Remap Starting Address */ +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK) + +#define DDRC_REMAP_2A_REG_2_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT (31U) +/*! REG_2_REMAP_EN - Region 2 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_2A_REG_2_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_2B - Remap Region 2B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_2B_REG_2_EA_MASK (0xFFFU) +#define DDRC_REMAP_2B_REG_2_EA_SHIFT (0U) +/*! REG_2_EA - Region 2 Ending Address */ +#define DDRC_REMAP_2B_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_EA_SHIFT)) & DDRC_REMAP_2B_REG_2_EA_MASK) + +#define DDRC_REMAP_2B_REG_2_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_2B_REG_2_SA_SHIFT (16U) +/*! REG_2_SA - Region 2 Starting Address */ +#define DDRC_REMAP_2B_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_SA_SHIFT)) & DDRC_REMAP_2B_REG_2_SA_MASK) +/*! @} */ + +/*! @name REMAP_3A - Remap Region 3A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT (0U) +/*! REG_3_REMAP_ADDR - Region 3 Remap Starting Address */ +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK) + +#define DDRC_REMAP_3A_REG_3_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT (31U) +/*! REG_3_REMAP_EN - Region 3 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_3A_REG_3_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_3B - Remap Region 3B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_3B_REG_3_EA_MASK (0xFFFU) +#define DDRC_REMAP_3B_REG_3_EA_SHIFT (0U) +/*! REG_3_EA - Region 3 Ending Address */ +#define DDRC_REMAP_3B_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_EA_SHIFT)) & DDRC_REMAP_3B_REG_3_EA_MASK) + +#define DDRC_REMAP_3B_REG_3_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_3B_REG_3_SA_SHIFT (16U) +/*! REG_3_SA - Region 3 Starting Address */ +#define DDRC_REMAP_3B_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_SA_SHIFT)) & DDRC_REMAP_3B_REG_3_SA_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_0 - DDRC Address Decode 0 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT (2U) +/*! ROW14_OVRD - Row 14 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT (10U) +/*! ROW15_OVRD - Row 15 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT (18U) +/*! ROW16_OVRD - Row 16 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT (26U) +/*! ROW17_OVRD - Row 17 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_1 - DDRC Address Decode 1 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT (2U) +/*! ROW10_OVRD - Row 10 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT (10U) +/*! ROW11_OVRD - Row 11 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT (18U) +/*! ROW12_OVRD - Row 12 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT (26U) +/*! ROW13_OVRD - Row 13 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_2 - DDRC Address Decode 2 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT (2U) +/*! ROW6_OVRD - Row 6 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT (10U) +/*! ROW7_OVRD - Row 7 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT (18U) +/*! ROW8_OVRD - Row 8 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT (26U) +/*! ROW9_OVRD - Row 9 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_3 - DDRC Address Decode 3 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT (2U) +/*! ROW2_OVRD - Row 2 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT (10U) +/*! ROW3_OVRD - Row 3 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT (18U) +/*! ROW4_OVRD - Row 4 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT (26U) +/*! ROW5_OVRD - Row 5 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_4 - DDRC Address Decode 4 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT (2U) +/*! COL9_OVRD - Col 9 Override */ +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT (10U) +/*! COL10_OVRD - Col 10 Override */ +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT (18U) +/*! ROW0_OVRD - Row 0 Override */ +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT (26U) +/*! ROW1_OVRD - Row 1 Override */ +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_5 - DDRC Address Decode 5 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT (2U) +/*! COL5_OVRD - Col 5 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT (10U) +/*! COL6_OVRD - Col 6 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT (18U) +/*! COL7_OVRD - Col 7 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT (26U) +/*! COL8_OVRD - Col 8 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_6 - DDRC Address Decode 6 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT (2U) +/*! COL1_OVRD - Col 1 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT (10U) +/*! COL2_OVRD - Col 2 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT (18U) +/*! COL3_OVRD - Col 3 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT (26U) +/*! COL4_OVRD - Col 4 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_7 - DDRC Address Decode 7 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT (2U) +/*! CID1_OVRD - CID 1 Override */ +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT (10U) +/*! BA0_OVRD - Bank 0 Override */ +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT (18U) +/*! BA1_OVRD - Bank 1 Override */ +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT (26U) +/*! COL0_OVRD - Col 0 Override */ +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_8 - DDRC Address Decode 8 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT (2U) +/*! BG1_OVRD - Bank Group 1 Override */ +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT (10U) +/*! CS0_OVRD - Interleaved Rank 0 Override */ +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT (18U) +/*! CS1_OVRD - Interleaved Rank 1 Override */ +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT (26U) +/*! CID0_OVRD - CID 0 Override */ +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_9 - DDRC Address Decode 9 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK (0x1U) +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT (0U) +/*! ADDR_DEC_OVRD - Address Decode Override */ +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT (26U) +/*! BG0_OVRD - Bank Group 0 Override */ +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK) +/*! @} */ + +/*! @name CS_CONFIG - Rank 0 Configuration..Rank 1 Configuration */ +/*! @{ */ + +#define DDRC_CS_CONFIG_COL_BITS_CS_MASK (0x7U) +#define DDRC_CS_CONFIG_COL_BITS_CS_SHIFT (0U) +/*! COL_BITS_CS - Column Bits + * 0b000..8 + * 0b001..9 + * 0b010..10 + * 0b011..11 + * 0b111..7 + */ +#define DDRC_CS_CONFIG_COL_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_COL_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_COL_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_BG_BITS_CS_MASK (0x30U) +#define DDRC_CS_CONFIG_BG_BITS_CS_SHIFT (4U) +/*! BG_BITS_CS - Bank Group Bits + * 0b00..0 + * 0b01..Must be set to 1 to enable the 3rd bank address bit for LPDDR4, memories. + * 0b10..Reserved for LPDDR4 + * 0b11..Reserved + */ +#define DDRC_CS_CONFIG_BG_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_BG_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_BG_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_ROW_BITS_CS_MASK (0x700U) +#define DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT (8U) +/*! ROW_BITS_CS - Row Bits + * 0b000..12 + * 0b001..13 + * 0b010..14 + * 0b011..15 + * 0b100..16 + * 0b101..17 + */ +#define DDRC_CS_CONFIG_ROW_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_ROW_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_AP_EN_MASK (0x800000U) +#define DDRC_CS_CONFIG_AP_EN_SHIFT (23U) +/*! AP_EN - Auto-Precharge Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_CS_CONFIG_AP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_AP_EN_SHIFT)) & DDRC_CS_CONFIG_AP_EN_MASK) + +#define DDRC_CS_CONFIG_CS_EN_MASK (0x80000000U) +#define DDRC_CS_CONFIG_CS_EN_SHIFT (31U) +/*! CS_EN - Rank Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_CS_CONFIG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_CS_EN_SHIFT)) & DDRC_CS_CONFIG_CS_EN_MASK) +/*! @} */ + +/* The count of DDRC_CS_CONFIG */ +#define DDRC_CS_CONFIG_COUNT (2U) + +/*! @name TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_3_EXT_WRTORD_MASK (0x1U) +#define DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT (0U) +/*! EXT_WRTORD - Extended Write-To-Read Time */ +#define DDRC_TIMING_CFG_3_EXT_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRTORD_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK (0x2U) +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT (1U) +/*! EXT_ACTTOACT - Extended Activate-To-Activate Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK (0x8U) +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT (3U) +/*! EXT_FOUR_ACT - Extended Four Activate */ +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK (0x30U) +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT (4U) +/*! EXT_CKE_PLS - Extended MCKE Pulse */ +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK) + +#define DDRC_TIMING_CFG_3_EXT_WRREC_MASK (0x300U) +#define DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT (8U) +/*! EXT_WRREC - Extended Write Recovery + * 0b11.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_3_EXT_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRREC_MASK) + +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK (0x800U) +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT (11U) +/*! EXT_WR_LAT_2 - Extended Write Latency 2 */ +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK) + +#define DDRC_TIMING_CFG_3_EXT_CASLAT_MASK (0x7000U) +#define DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT (12U) +/*! EXT_CASLAT - Extended CAS Latency */ +#define DDRC_TIMING_CFG_3_EXT_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CASLAT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_REFREC_MASK (0x3F0000U) +#define DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT (16U) +/*! EXT_REFREC - Extended Refresh Recovery */ +#define DDRC_TIMING_CFG_3_EXT_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_REFREC_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK (0xC00000U) +#define DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT (22U) +/*! EXT_ACTTORW - Extended Activate To Read Or Write Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK (0x7000000U) +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT (24U) +/*! EXT_ACTTOPRE - Extended Activate-To-Precharge Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK) + +#define DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK (0x30000000U) +#define DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT (28U) +/*! EXT_PRETOACT - Extended Precharge-To-Activate Time */ +#define DDRC_TIMING_CFG_3_EXT_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_0_MRS_CYC_MASK (0x3FU) +#define DDRC_TIMING_CFG_0_MRS_CYC_SHIFT (0U) +/*! MRS_CYC - MRW Cycle Time + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_MRS_CYC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_MRS_CYC_SHIFT)) & DDRC_TIMING_CFG_0_MRS_CYC_MASK) + +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK (0x1000U) +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT (12U) +/*! EXT_ACT_PD_EXIT - Extended Active Power-Down Exit */ +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK (0xC000U) +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT (14U) +/*! EXT_PRE_PD_EXIT - Extended Precharge Power-Down Exit */ +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK (0xF0000U) +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT (16U) +/*! PRE_PD_EXIT - Precharge Power-Down Exit + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK (0xF00000U) +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT (20U) +/*! ACT_PD_EXIT - Active Powerdown Exit + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_WWT_MASK (0x3000000U) +#define DDRC_TIMING_CFG_0_WWT_SHIFT (24U) +/*! WWT - Write-To-Write Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WWT_SHIFT)) & DDRC_TIMING_CFG_0_WWT_MASK) + +#define DDRC_TIMING_CFG_0_RRT_MASK (0xC000000U) +#define DDRC_TIMING_CFG_0_RRT_SHIFT (26U) +/*! RRT - Read-To-Read Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RRT_SHIFT)) & DDRC_TIMING_CFG_0_RRT_MASK) + +#define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) +#define DDRC_TIMING_CFG_0_WRT_SHIFT (28U) +/*! WRT - Write-To-Read Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK) + +#define DDRC_TIMING_CFG_0_RWT_MASK (0xC0000000U) +#define DDRC_TIMING_CFG_0_RWT_SHIFT (30U) +/*! RWT - Read-To-Write Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RWT_SHIFT)) & DDRC_TIMING_CFG_0_RWT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_1_WRTORD_MASK (0xFU) +#define DDRC_TIMING_CFG_1_WRTORD_SHIFT (0U) +/*! WRTORD - Write-To-Read Interval + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRTORD_SHIFT)) & DDRC_TIMING_CFG_1_WRTORD_MASK) + +#define DDRC_TIMING_CFG_1_ACTTOACT_MASK (0xF0U) +#define DDRC_TIMING_CFG_1_ACTTOACT_SHIFT (4U) +/*! ACTTOACT - Activate-To-Activate Interval + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOACT_MASK) + +#define DDRC_TIMING_CFG_1_WRREC_MASK (0xF00U) +#define DDRC_TIMING_CFG_1_WRREC_SHIFT (8U) +/*! WRREC - Write Recovery */ +#define DDRC_TIMING_CFG_1_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRREC_SHIFT)) & DDRC_TIMING_CFG_1_WRREC_MASK) + +#define DDRC_TIMING_CFG_1_REFREC_MASK (0xF000U) +#define DDRC_TIMING_CFG_1_REFREC_SHIFT (12U) +/*! REFREC - Refresh Recovery */ +#define DDRC_TIMING_CFG_1_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_REFREC_SHIFT)) & DDRC_TIMING_CFG_1_REFREC_MASK) + +#define DDRC_TIMING_CFG_1_CASLAT_MASK (0xE0000U) +#define DDRC_TIMING_CFG_1_CASLAT_SHIFT (17U) +/*! CASLAT - CAS Latency */ +#define DDRC_TIMING_CFG_1_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_CASLAT_SHIFT)) & DDRC_TIMING_CFG_1_CASLAT_MASK) + +#define DDRC_TIMING_CFG_1_ACTTORW_MASK (0xF00000U) +#define DDRC_TIMING_CFG_1_ACTTORW_SHIFT (20U) +/*! ACTTORW - Activate To Read Or Write + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_1_ACTTORW_MASK) + +#define DDRC_TIMING_CFG_1_ACTTOPRE_MASK (0xF000000U) +#define DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT (24U) +/*! ACTTOPRE - Activate-To-Precharge Time */ +#define DDRC_TIMING_CFG_1_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOPRE_MASK) + +#define DDRC_TIMING_CFG_1_PRETOACT_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_1_PRETOACT_SHIFT (28U) +/*! PRETOACT - Precharge-To-Activate Time + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_1_PRETOACT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_2_FOUR_ACT_MASK (0x3FU) +#define DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT (0U) +/*! FOUR_ACT - Four Activate */ +#define DDRC_TIMING_CFG_2_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_2_FOUR_ACT_MASK) + +#define DDRC_TIMING_CFG_2_CKE_PLS_MASK (0x1C0U) +#define DDRC_TIMING_CFG_2_CKE_PLS_SHIFT (6U) +/*! CKE_PLS - MCKE Pulse */ +#define DDRC_TIMING_CFG_2_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_2_CKE_PLS_MASK) + +#define DDRC_TIMING_CFG_2_RD_TO_PRE_MASK (0x3E000U) +#define DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT (13U) +/*! RD_TO_PRE - Read-To-Precharge Time + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_2_RD_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_2_RD_TO_PRE_MASK) + +#define DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK (0x40000U) +#define DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT (18U) +/*! EXT_WR_LAT - Extended Write Latency */ +#define DDRC_TIMING_CFG_2_EXT_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK) + +#define DDRC_TIMING_CFG_2_WR_LAT_MASK (0x780000U) +#define DDRC_TIMING_CFG_2_WR_LAT_SHIFT (19U) +/*! WR_LAT - Write Latency */ +#define DDRC_TIMING_CFG_2_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_WR_LAT_MASK) + +#define DDRC_TIMING_CFG_2_DERATE_VAL_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT (28U) +/*! DERATE_VAL - Derate Value */ +#define DDRC_TIMING_CFG_2_DERATE_VAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT)) & DDRC_TIMING_CFG_2_DERATE_VAL_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_BI_MASK (0x1U) +#define DDRC_DDR_SDRAM_CFG_BI_SHIFT (0U) +/*! BI - Bypass Initialization + * 0b0..Reserved; do not use + * 0b1..Initialization routine is bypassed + */ +#define DDRC_DDR_SDRAM_CFG_BI(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BI_SHIFT)) & DDRC_DDR_SDRAM_CFG_BI_MASK) + +#define DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK (0x2U) +#define DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT (1U) +/*! MEM_HALT - DDRC Halt + * 0b0..Accepts new transactions + * 0b1..Completes any remaining transactions and remains halted until you write 0 to this field + */ +#define DDRC_DDR_SDRAM_CFG_MEM_HALT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK) + +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK (0x7F00U) +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT (8U) +/*! BA_INTLV_CTL - Rank Interleaving Control + * 0b0000000..No external ranks are interleaved. + * 0b1000000..External ranks 0 and 1 are interleaved. + */ +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT)) & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK) + +#define DDRC_DDR_SDRAM_CFG_DBW_MASK (0x180000U) +#define DDRC_DDR_SDRAM_CFG_DBW_SHIFT (19U) +/*! DBW - DDR SDRAM Data Bus Width + * 0b10..16 bits + */ +#define DDRC_DDR_SDRAM_CFG_DBW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DBW_SHIFT)) & DDRC_DDR_SDRAM_CFG_DBW_MASK) + +#define DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK (0x200000U) +#define DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT (21U) +/*! DYN_PWR - Dynamic Power Management + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_CFG_DYN_PWR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT)) & DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK) + +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK (0x7000000U) +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT (24U) +/*! SDRAM_TYPE - DDR SDRAM Type + * 0b100..LPDDR4, SDRAM + */ +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT)) & DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK) + +#define DDRC_DDR_SDRAM_CFG_SREN_MASK (0x40000000U) +#define DDRC_DDR_SDRAM_CFG_SREN_SHIFT (30U) +/*! SREN - Self-Refresh Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_SREN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SREN_SHIFT)) & DDRC_DDR_SDRAM_CFG_SREN_MASK) + +#define DDRC_DDR_SDRAM_CFG_MEM_EN_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT (31U) +/*! MEM_EN - DDRC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_MEM_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_EN_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_2 - DDR SDRAM Control Configuration 2 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK (0x10U) +#define DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT (4U) +/*! D_INIT - DDR SDRAM Data Initialization + * 0b0..No data initialization in progress, and none scheduled + * 0b1..DDRC to initialize the DDR SDRAM after DDRC is enabled + */ +#define DDRC_DDR_SDRAM_CFG_2_D_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK (0xF000U) +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT (12U) +/*! NUM_PR - Number Of Posted Refreshes + * 0b0000, 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0100..4 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + */ +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT (24U) +/*! MCK_DIS - MCK Disable */ +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT (31U) +/*! FRC_SR - Force Self-Refresh + * 0b0..Normal mode + * 0b1..Self-Refresh mode + */ +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_MD_CNTL - DDR SDRAM Mode Control */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK (0x3FFFFU) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT (0U) +/*! MD_VALUE - Mode Register Value */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK (0x300000U) +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT (20U) +/*! CKE_CNTL - Clock Enable Control + * 0b00..Not forced + * 0b01..Forced to a lower value + * 0b10..Forced to a higher value + * 0b11.. + */ +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_MASK (0x400000U) +#define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_SHIFT (22U) +/*! SET_PRE - Set Precharge + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_SET_REF_MASK (0x800000U) +#define DDRC_DDR_SDRAM_MD_CNTL_SET_REF_SHIFT (23U) +/*! SET_REF - Set Refresh + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_MD_CNTL_SET_REF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_SET_REF_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_SET_REF_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT (24U) +/*! MD_SEL - Mode Register Select + * 0b0000..MR + * 0b0001..EMR + * 0b0010..EMR2 + * 0b0011..EMR3 + */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK (0x70000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT (28U) +/*! CS_SEL - Select Rank + * 0b000..0 + * 0b001..1 + * 0b100..0 and 1 + */ +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT (31U) +/*! MD_EN - Mode Enable + * 0b0..Does not need to be issued + * 0b1..Valid data contained in the register ready to be issued as an MRW command + */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_INTERVAL - DDR SDRAM Interval Configuration */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK (0x3FFFU) +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT (0U) +/*! BSTOPRE - Precharge Interval */ +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK) + +#define DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK (0xFFFF0000U) +#define DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT (16U) +/*! REFINT - Refresh Interval */ +#define DDRC_DDR_SDRAM_INTERVAL_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK) +/*! @} */ + +/*! @name DDR_DATA_INIT - DDR SDRAM Data Initialization */ +/*! @{ */ + +#define DDRC_DDR_DATA_INIT_INIT_VALUE_MASK (0xFFFFFFFFU) +#define DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT (0U) +/*! INIT_VALUE - Initialization Value */ +#define DDRC_DDR_DATA_INIT_INIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT)) & DDRC_DDR_DATA_INIT_INIT_VALUE_MASK) +/*! @} */ + +/*! @name TIMING_CFG_4 - DDR SDRAM Timing Configuration 4 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_4_DLL_LOCK_MASK (0x3U) +#define DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT (0U) +/*! DLL_LOCK - DDR SDRAM DLL Lock Time + * 0b10..1024 clocks + * 0b11..2048 clocks + */ +#define DDRC_TIMING_CFG_4_DLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT)) & DDRC_TIMING_CFG_4_DLL_LOCK_MASK) + +#define DDRC_TIMING_CFG_4_EXT_REFINT_MASK (0x10U) +#define DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT (4U) +/*! EXT_REFINT - Extended Refresh Interval + * 0b0..0 + * 0b1..65,536 + */ +#define DDRC_TIMING_CFG_4_EXT_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_REFINT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_WWT_MASK (0x300U) +#define DDRC_TIMING_CFG_4_EXT_WWT_SHIFT (8U) +/*! EXT_WWT - Extended Write-To-Write Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WWT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_RRT_MASK (0xC00U) +#define DDRC_TIMING_CFG_4_EXT_RRT_SHIFT (10U) +/*! EXT_RRT - Extended Read-To-Read Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RRT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_WRT_MASK (0x3000U) +#define DDRC_TIMING_CFG_4_EXT_WRT_SHIFT (12U) +/*! EXT_WRT - Extended Write-To-Read Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WRT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_RWT_MASK (0xC000U) +#define DDRC_TIMING_CFG_4_EXT_RWT_SHIFT (14U) +/*! EXT_RWT - Extended Read-To-Write Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RWT_MASK) + +#define DDRC_TIMING_CFG_4_WWT_MASK (0xF0000U) +#define DDRC_TIMING_CFG_4_WWT_SHIFT (16U) +/*! WWT - Write-To-Write Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WWT_SHIFT)) & DDRC_TIMING_CFG_4_WWT_MASK) + +#define DDRC_TIMING_CFG_4_RRT_MASK (0xF00000U) +#define DDRC_TIMING_CFG_4_RRT_SHIFT (20U) +/*! RRT - Read-To-Read Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RRT_SHIFT)) & DDRC_TIMING_CFG_4_RRT_MASK) + +#define DDRC_TIMING_CFG_4_WRT_MASK (0xF000000U) +#define DDRC_TIMING_CFG_4_WRT_SHIFT (24U) +/*! WRT - Write-To-Read Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WRT_SHIFT)) & DDRC_TIMING_CFG_4_WRT_MASK) + +#define DDRC_TIMING_CFG_4_RWT_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_4_RWT_SHIFT (28U) +/*! RWT - Read-To-Write Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RWT_SHIFT)) & DDRC_TIMING_CFG_4_RWT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_7 - DDR SDRAM Timing Configuration 7 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_7_CKSRX_MASK (0xF00000U) +#define DDRC_TIMING_CFG_7_CKSRX_SHIFT (20U) +/*! CKSRX - Clock After Self-Refresh Exit + * 0b0000, 0b1010..15 + * 0b0001..6 + * 0b0010..7 + * 0b0011..8 + * 0b0100..9 + * 0b0101..10 + * 0b0110..11 + * 0b0111..12 + * 0b1000..13 + * 0b1001..14 + * 0b1011..16 + * 0b1100..17 + * 0b1101..18 + * 0b1110..19 + * 0b1111..32 + */ +#define DDRC_TIMING_CFG_7_CKSRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRX_SHIFT)) & DDRC_TIMING_CFG_7_CKSRX_MASK) + +#define DDRC_TIMING_CFG_7_CKSRE_MASK (0xF000000U) +#define DDRC_TIMING_CFG_7_CKSRE_SHIFT (24U) +/*! CKSRE - Clock After Self-Refresh Entry + * 0b0000, 0b1010..15 + * 0b0001..6 + * 0b0010..7 + * 0b0011..8 + * 0b0100..9 + * 0b0101..10 + * 0b0110..11 + * 0b0111..12 + * 0b1000..13 + * 0b1001..14 + * 0b1011..16 + * 0b1100..17 + * 0b1101..18 + * 0b1110..19 + * 0b1111..32 + */ +#define DDRC_TIMING_CFG_7_CKSRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRE_SHIFT)) & DDRC_TIMING_CFG_7_CKSRE_MASK) + +#define DDRC_TIMING_CFG_7_CKE_RST_MASK (0x30000000U) +#define DDRC_TIMING_CFG_7_CKE_RST_SHIFT (28U) +/*! CKE_RST - MCKE Reset Time + * 0b00..200 + * 0b01..256 + * 0b10..512 + * 0b11..4096 + */ +#define DDRC_TIMING_CFG_7_CKE_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKE_RST_SHIFT)) & DDRC_TIMING_CFG_7_CKE_RST_MASK) +/*! @} */ + +/*! @name DDR_ZQ_CNTL - DDR SDRAM ZQ Calibration Control */ +/*! @{ */ + +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK (0xFU) +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT (0U) +/*! ZQCS_INT - ZQCS Interval + * 0b0000..32 + * 0b0001..64 + * 0b0010..128 + * 0b0011..256 + * 0b0100..512 + * 0b0101..1024 + * 0b0110..2048 + * 0b0111..4096 + * 0b1000..8192 + * 0b1001..16384 + * 0b1010..32768 + * 0b1111..ZQCS calibration disabled + */ +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQCS_MASK (0xF00U) +#define DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT (8U) +/*! ZQCS - ZQ Calibration Short Time + * 0b0000..1 + * 0b0001..2 + * 0b0010..4 + * 0b0011..8 + * 0b0100..16 + * 0b0101..32 + * 0b0110..64 + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + */ +#define DDRC_DDR_ZQ_CNTL_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQOPER_MASK (0xF0000U) +#define DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT (16U) +/*! ZQOPER - ZQ Calibration Operation Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + */ +#define DDRC_DDR_ZQ_CNTL_ZQOPER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQOPER_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQINIT_MASK (0xF000000U) +#define DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT (24U) +/*! ZQINIT - ZQ Calibration Initialization Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + */ +#define DDRC_DDR_ZQ_CNTL_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQINIT_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK (0x80000000U) +#define DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT (31U) +/*! ZQ_EN - ZQ Calibration Enable + * 0b0..Not used + * 0b1..Used + */ +#define DDRC_DDR_ZQ_CNTL_ZQ_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK) +/*! @} */ + +/*! @name DDR_SR_CNTR - DDR SDRAM Self-Refresh Counter */ +/*! @{ */ + +#define DDRC_DDR_SR_CNTR_SR_IT_MASK (0xF0000U) +#define DDRC_DDR_SR_CNTR_SR_IT_SHIFT (16U) +/*! SR_IT - Self-Refresh Idle Threshold */ +#define DDRC_DDR_SR_CNTR_SR_IT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SR_CNTR_SR_IT_SHIFT)) & DDRC_DDR_SR_CNTR_SR_IT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_8 - DDR SDRAM Timing Configuration 8 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK (0x3FU) +#define DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT (0U) +/*! PRE_ALL_REC - Precharge All-To-Activate Interval */ +#define DDRC_TIMING_CFG_8_PRE_ALL_REC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT)) & DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK) +/*! @} */ + +/*! @name TIMING_CFG_9 - DDR SDRAM timing configuration 9 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_9_REFTOREF_PB_MASK (0x3FFU) +#define DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT (0U) +/*! REFTOREF_PB - Refresh-to-refresh interval for per-bank refresh. + * 0b0000000000..disable PB refresh + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_9_REFTOREF_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFTOREF_PB_MASK) + +#define DDRC_TIMING_CFG_9_REFREC_PB_MASK (0x3FF0000U) +#define DDRC_TIMING_CFG_9_REFREC_PB_SHIFT (16U) +/*! REFREC_PB - Refresh Recovery Per-Bank Refresh + * 0b0000000000..8 clocks + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_9_REFREC_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFREC_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFREC_PB_MASK) +/*! @} */ + +/*! @name TIMING_CFG_10 - DDR SDRAM Timing Configuration 10 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_10_T_STAB_MASK (0x7FFFU) +#define DDRC_TIMING_CFG_10_T_STAB_SHIFT (0U) +/*! T_STAB - Stabilization Wait Time */ +#define DDRC_TIMING_CFG_10_T_STAB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_10_T_STAB_SHIFT)) & DDRC_TIMING_CFG_10_T_STAB_MASK) +/*! @} */ + +/*! @name TIMING_CFG_11 - DDR SDRAM Timing Configuration 11 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_11_MWWT_MASK (0xFU) +#define DDRC_TIMING_CFG_11_MWWT_SHIFT (0U) +/*! MWWT - Masked Write-To-Write Turnaround (tCCDMW) */ +#define DDRC_TIMING_CFG_11_MWWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_MWWT_SHIFT)) & DDRC_TIMING_CFG_11_MWWT_MASK) + +#define DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK (0xF00U) +#define DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT (8U) +/*! PRE_TO_PRE - Precharge-To-Precharge Time + * 0b0000, 0b0100..4 + * 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + * 0b1011..11 + * 0b1100..12 + * 0b1101..13 + * 0b1110..14 + * 0b1111..15 + */ +#define DDRC_TIMING_CFG_11_PRE_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_3 - DDR SDRAM Control Configuration 3 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK (0x2U) +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT (1U) +/*! SR_FAST_WK_EN - Self Refresh Fast Wakeup Enable + * 0b0..Slow + * 0b1..Fast + */ +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_MASK (0x8U) +#define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_SHIFT (3U) +/*! NON_PWR_2 - Non Power of 2 Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK (0x80U) +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT (7U) +/*! DYN_REF_RATE_EN - Dynamic Refresh Rate Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK (0x800U) +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT (11U) +/*! DRAIN_FOR_SR - Drain Queues For Self-Refresh + * 0b0..Do not drain + * 0b1..Drain + */ +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK (0x7000U) +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT (12U) +/*! DM_CFG - Data Mask Configuration + * 0b000..Normal data masks based on the settings defined in DDR_SDRAM_CFG[SDRAM_TYPE] + * 0b010..DBI + * 0b011..Neither data masks nor DBI + * 0b100..DBI with data masks + */ +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT (31U) +/*! DDRC_RST - DDRC Reset + * 0b0..Operating normally + * 0b1..Undergoing reset + */ +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_4 - DDR SDRAM Control Configuration 4 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_MASK (0x1F000U) +#define DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_SHIFT (12U) +/*! FRQCH_RET - Frequency Change and Retention Setup */ +#define DDRC_DDR_SDRAM_CFG_4_FRQCH_RET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_SHIFT)) & DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_REF_RATE - DDR Refresh Rate */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK (0xFFU) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT (0U) +/*! REF_RATE_CS1 - Refresh Rate Rank 1 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK) + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK (0xFF00U) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT (8U) +/*! REF_RATE_CS0 - Refresh Rate Rank 0 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK) +/*! @} */ + +/*! @name TIMING_CFG_12 - DDR SDRAM Timing Configuration 12 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_12_CASLAT_HS_MASK (0x3FU) +#define DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT (0U) +/*! CASLAT_HS - CAS Latency For Half Speed */ +#define DDRC_TIMING_CFG_12_CASLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT)) & DDRC_TIMING_CFG_12_CASLAT_HS_MASK) + +#define DDRC_TIMING_CFG_12_ACTTORW_HS_MASK (0x3F00U) +#define DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT (8U) +/*! ACTTORW_HS - Activate To Read Or Write For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_12_ACTTORW_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT)) & DDRC_TIMING_CFG_12_ACTTORW_HS_MASK) + +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK (0x7F0000U) +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT (16U) +/*! ACTTOPRE_HS - Activate-To-Precharge Time For Half Speed */ +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT)) & DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK) + +#define DDRC_TIMING_CFG_12_PRETOACT_HS_MASK (0x3F000000U) +#define DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT (24U) +/*! PRETOACT_HS - Precharge-To-Activate Time For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_12_PRETOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT)) & DDRC_TIMING_CFG_12_PRETOACT_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_13 - DDR SDRAM Timing Configuration 13 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK (0x1FU) +#define DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT (0U) +/*! ACTTOACT_HS - Activate-To-Activate Interval For Half Speed + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_13_ACTTOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT)) & DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK) + +#define DDRC_TIMING_CFG_13_WRREC_HS_MASK (0x3F00U) +#define DDRC_TIMING_CFG_13_WRREC_HS_SHIFT (8U) +/*! WRREC_HS - Write Recovery For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_13_WRREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_WRREC_HS_SHIFT)) & DDRC_TIMING_CFG_13_WRREC_HS_MASK) + +#define DDRC_TIMING_CFG_13_REFREC_HS_MASK (0x3FF0000U) +#define DDRC_TIMING_CFG_13_REFREC_HS_SHIFT (16U) +/*! REFREC_HS - Refresh Recovery For Half Speed */ +#define DDRC_TIMING_CFG_13_REFREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_REFREC_HS_SHIFT)) & DDRC_TIMING_CFG_13_REFREC_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_14 - DDR SDRAM Timing Configuration 14 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_14_REFINT_HS_MASK (0x1FFFFU) +#define DDRC_TIMING_CFG_14_REFINT_HS_SHIFT (0U) +/*! REFINT_HS - Refresh Interval For Half Speed */ +#define DDRC_TIMING_CFG_14_REFINT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_REFINT_HS_SHIFT)) & DDRC_TIMING_CFG_14_REFINT_HS_MASK) + +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK (0x7C0000U) +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT (18U) +/*! RD_TO_PRE_HS - Read-To-Precharge Time For Half Speed + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT)) & DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK) + +#define DDRC_TIMING_CFG_14_WRLAT_HS_MASK (0x3F000000U) +#define DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT (24U) +/*! WRLAT_HS - Write Latency For Half Speed */ +#define DDRC_TIMING_CFG_14_WRLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT)) & DDRC_TIMING_CFG_14_WRLAT_HS_MASK) +/*! @} */ + +/*! @name TX_CFG_1 - Transaction Configuration Register 1 */ +/*! @{ */ + +#define DDRC_TX_CFG_1_WWATER_MASK (0xFU) +#define DDRC_TX_CFG_1_WWATER_SHIFT (0U) +/*! WWATER - Write Watermark. */ +#define DDRC_TX_CFG_1_WWATER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_WWATER_SHIFT)) & DDRC_TX_CFG_1_WWATER_MASK) + +#define DDRC_TX_CFG_1_TS_DEPTH_MASK (0xF80U) +#define DDRC_TX_CFG_1_TS_DEPTH_SHIFT (7U) +/*! TS_DEPTH - Transaction Scheduler Depth */ +#define DDRC_TX_CFG_1_TS_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_TS_DEPTH_SHIFT)) & DDRC_TX_CFG_1_TS_DEPTH_MASK) +/*! @} */ + +/*! @name DDRDSR_2 - DDR SDRAM Debug Status 2 */ +/*! @{ */ + +#define DDRC_DDRDSR_2_RPD_END_MASK (0x1U) +#define DDRC_DDRDSR_2_RPD_END_SHIFT (0U) +/*! RPD_END - Rapid Clear Of Memory End + * 0b0..Not complete + * 0b1..Complete + */ +#define DDRC_DDRDSR_2_RPD_END(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_END_SHIFT)) & DDRC_DDRDSR_2_RPD_END_MASK) + +#define DDRC_DDRDSR_2_RPD_ST_MASK (0x2U) +#define DDRC_DDRDSR_2_RPD_ST_SHIFT (1U) +/*! RPD_ST - Rapid Clear Of Memory Start + * 0b0..Not started + * 0b1..Started + */ +#define DDRC_DDRDSR_2_RPD_ST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_ST_SHIFT)) & DDRC_DDRDSR_2_RPD_ST_MASK) + +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK (0x4U) +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT (2U) +/*! PHY_INIT_CMPLT - DDR PHY Initialization Complete + * 0b0..Not complete + * 0b1..Complete + */ +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT)) & DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK) + +#define DDRC_DDRDSR_2_NML_MASK (0x40000000U) +#define DDRC_DDRDSR_2_NML_SHIFT (30U) +/*! NML - No Modified Lines + * 0b0..Exist + * 0b1..Do not exist + */ +#define DDRC_DDRDSR_2_NML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_NML_SHIFT)) & DDRC_DDRDSR_2_NML_MASK) + +#define DDRC_DDRDSR_2_IDLE_MASK (0x80000000U) +#define DDRC_DDRDSR_2_IDLE_SHIFT (31U) +/*! IDLE - Memory controller idle (read only). + * 0b0..Memory controller is busy. + * 0b1..Memory controller is idle. + */ +#define DDRC_DDRDSR_2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_IDLE_SHIFT)) & DDRC_DDRDSR_2_IDLE_MASK) +/*! @} */ + +/*! @name DDR_IP_REV1 - DDRC Revision 1 */ +/*! @{ */ + +#define DDRC_DDR_IP_REV1_IP_MN_MASK (0xFFU) +#define DDRC_DDR_IP_REV1_IP_MN_SHIFT (0U) +/*! IP_MN - Minor Revision */ +#define DDRC_DDR_IP_REV1_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MN_SHIFT)) & DDRC_DDR_IP_REV1_IP_MN_MASK) + +#define DDRC_DDR_IP_REV1_IP_MJ_MASK (0xFF00U) +#define DDRC_DDR_IP_REV1_IP_MJ_SHIFT (8U) +/*! IP_MJ - Major Revision */ +#define DDRC_DDR_IP_REV1_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MJ_SHIFT)) & DDRC_DDR_IP_REV1_IP_MJ_MASK) + +#define DDRC_DDR_IP_REV1_IP_ID_MASK (0xFFFF0000U) +#define DDRC_DDR_IP_REV1_IP_ID_SHIFT (16U) +/*! IP_ID - IP Block ID */ +#define DDRC_DDR_IP_REV1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_ID_SHIFT)) & DDRC_DDR_IP_REV1_IP_ID_MASK) +/*! @} */ + +/*! @name DDR_MTCR - DDR SDRAM Memory Test Control */ +/*! @{ */ + +#define DDRC_DDR_MTCR_MT_STAT_MASK (0x1U) +#define DDRC_DDR_MTCR_MT_STAT_SHIFT (0U) +/*! MT_STAT - Memory Test Status + * 0b0..No fail detected + * 0b1..Data miscompare detected + */ +#define DDRC_DDR_MTCR_MT_STAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_STAT_SHIFT)) & DDRC_DDR_MTCR_MT_STAT_MASK) + +#define DDRC_DDR_MTCR_MT_ADDR_EN_MASK (0x200U) +#define DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT (9U) +/*! MT_ADDR_EN - Memory Test Address Range Enable + * 0b0..Memory range that the CSn_BNDS registers define + * 0b1..Memory range that the DDR_MT_ST_EXT_ADDR, DDR_MT_ST_ADDR, DDR_MT_END_EXT_ADDR, and DDR_MT_END_ADDR registers define + */ +#define DDRC_DDR_MTCR_MT_ADDR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT)) & DDRC_DDR_MTCR_MT_ADDR_EN_MASK) + +#define DDRC_DDR_MTCR_MT_TRNARND_MASK (0xF0000U) +#define DDRC_DDR_MTCR_MT_TRNARND_SHIFT (16U) +/*! MT_TRNARND - Memory Test Turnaround + * 0b0000..Entire memory is written to before read transactions are issued. + * 0b0001..Total write and read streams are one transaction each. + * 0b0010..Total write and read streams are two transactions each. + * 0b0011..Total write and read streams are four transactions each. + */ +#define DDRC_DDR_MTCR_MT_TRNARND(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TRNARND_SHIFT)) & DDRC_DDR_MTCR_MT_TRNARND_MASK) + +#define DDRC_DDR_MTCR_MT_TYP_MASK (0x3000000U) +#define DDRC_DDR_MTCR_MT_TYP_SHIFT (24U) +/*! MT_TYP - Memory Test Type + * 0b00..Both writes and reads + * 0b01..Only writes + * 0b10..Only reads + * 0b11..Reserved + */ +#define DDRC_DDR_MTCR_MT_TYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TYP_SHIFT)) & DDRC_DDR_MTCR_MT_TYP_MASK) + +#define DDRC_DDR_MTCR_MT_EN_MASK (0x80000000U) +#define DDRC_DDR_MTCR_MT_EN_SHIFT (31U) +/*! MT_EN - Memory Test Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_MTCR_MT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_EN_SHIFT)) & DDRC_DDR_MTCR_MT_EN_MASK) +/*! @} */ + +/*! @name DDR_MTP - DDR SDRAM Memory Test Pattern n */ +/*! @{ */ + +#define DDRC_DDR_MTP_DDR_PATT_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MTP_DDR_PATT_SHIFT (0U) +/*! DDR_PATT - DDR SDRAM Pattern */ +#define DDRC_DDR_MTP_DDR_PATT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTP_DDR_PATT_SHIFT)) & DDRC_DDR_MTP_DDR_PATT_MASK) +/*! @} */ + +/* The count of DDRC_DDR_MTP */ +#define DDRC_DDR_MTP_COUNT (10U) + +/*! @name DDR_MT_ST_EXT_ADDR - DDR SDRAM Memory Test Start Extended Address */ +/*! @{ */ + +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK (0xFFU) +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT (0U) +/*! MT_ST_EXT_ADDR - Memory Test Start Extended Address */ +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_ST_ADDR - DDR SDRAM Memory Test Start Address */ +/*! @{ */ + +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT (0U) +/*! MT_ST_ADDR - Memory Test Start Address */ +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT)) & DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_END_EXT_ADDR - DDR SDRAM Memory Test End Extended Address */ +/*! @{ */ + +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK (0xFFU) +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT (0U) +/*! MT_END_EXT_ADDR - Memory Test End Extended Address */ +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_END_ADDR - DDR SDRAM Memory Test End Address */ +/*! @{ */ + +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT (0U) +/*! MT_END_ADDR - Memory Test End Address */ +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT)) & DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK) +/*! @} */ + +/*! @name PMGC0 - Performance Monitor Global Control */ +/*! @{ */ + +#define DDRC_PMGC0_FCECE_MASK (0x20000000U) +#define DDRC_PMGC0_FCECE_SHIFT (29U) +/*! FCECE - Freeze Counters On Enabled Condition Or Event + * 0b0..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. + * 0b1..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. At this point, if PMGC0[FAC] = 1, you must write 0 to it. + */ +#define DDRC_PMGC0_FCECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FCECE_SHIFT)) & DDRC_PMGC0_FCECE_MASK) + +#define DDRC_PMGC0_PMIE_MASK (0x40000000U) +#define DDRC_PMGC0_PMIE_SHIFT (30U) +/*! PMIE - Performance Monitor Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_PMGC0_PMIE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_PMIE_SHIFT)) & DDRC_PMGC0_PMIE_MASK) + +#define DDRC_PMGC0_FAC_MASK (0x80000000U) +#define DDRC_PMGC0_FAC_SHIFT (31U) +/*! FAC - Freeze All Counters + * 0b0..Incremented + * 0b1..Not incremented + */ +#define DDRC_PMGC0_FAC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FAC_SHIFT)) & DDRC_PMGC0_FAC_MASK) +/*! @} */ + +/*! @name PMLCA0 - Performance Monitor Local Control A0 */ +/*! @{ */ + +#define DDRC_PMLCA0_CE_MASK (0x4000000U) +#define DDRC_PMLCA0_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions for PMC0n cannot occur (PMC0n cannot cause interrupts or freeze counters) + * 0b1..Counter overflow conditions occur when the most-significant bit of PMC0n is 1 + */ +#define DDRC_PMLCA0_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_CE_SHIFT)) & DDRC_PMLCA0_CE_MASK) + +#define DDRC_PMLCA0_FC_MASK (0x80000000U) +#define DDRC_PMLCA0_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA0_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_FC_SHIFT)) & DDRC_PMLCA0_FC_MASK) +/*! @} */ + +/*! @name PMLCB0 - Performance Monitor Local Control B0 */ +/*! @{ */ + +#define DDRC_PMLCB0_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB0_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB0_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB0_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB0_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB0_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB0_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONCNTL_SHIFT)) & DDRC_PMLCB0_TRIGONCNTL_MASK) + +#define DDRC_PMLCB0_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB0_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB0_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB0_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB0_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB0_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB0_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONSEL_SHIFT)) & DDRC_PMLCB0_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC0A - PMC 0a */ +/*! @{ */ + +#define DDRC_PMC0A_PMC0_MASK (0xFFFFFFFFU) +#define DDRC_PMC0A_PMC0_SHIFT (0U) +/*! PMC0 - Counter 0 */ +#define DDRC_PMC0A_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0A_PMC0_SHIFT)) & DDRC_PMC0A_PMC0_MASK) +/*! @} */ + +/*! @name PMC0B - PMC 0b */ +/*! @{ */ + +#define DDRC_PMC0B_PMC0_MASK (0xFFFFFFFFU) +#define DDRC_PMC0B_PMC0_SHIFT (0U) +/*! PMC0 - Counter 0 */ +#define DDRC_PMC0B_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0B_PMC0_SHIFT)) & DDRC_PMC0B_PMC0_MASK) +/*! @} */ + +/*! @name PMLCA1 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA1_BDIST_MASK (0x3FU) +#define DDRC_PMLCA1_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA1_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BDIST_SHIFT)) & DDRC_PMLCA1_BDIST_MASK) + +#define DDRC_PMLCA1_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA1_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA1_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BGRAN_SHIFT)) & DDRC_PMLCA1_BGRAN_MASK) + +#define DDRC_PMLCA1_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA1_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA1_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BSIZE_SHIFT)) & DDRC_PMLCA1_BSIZE_MASK) + +#define DDRC_PMLCA1_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA1_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA1_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_EVENT_SHIFT)) & DDRC_PMLCA1_EVENT_MASK) + +#define DDRC_PMLCA1_CE_MASK (0x4000000U) +#define DDRC_PMLCA1_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA1_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_CE_SHIFT)) & DDRC_PMLCA1_CE_MASK) + +#define DDRC_PMLCA1_FC_MASK (0x80000000U) +#define DDRC_PMLCA1_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA1_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_FC_SHIFT)) & DDRC_PMLCA1_FC_MASK) +/*! @} */ + +/*! @name PMLCB1 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB1_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB1_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB1_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_THRESHOLD_SHIFT)) & DDRC_PMLCB1_THRESHOLD_MASK) + +#define DDRC_PMLCB1_TBMULT_MASK (0x700U) +#define DDRC_PMLCB1_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB1_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TBMULT_SHIFT)) & DDRC_PMLCB1_TBMULT_MASK) + +#define DDRC_PMLCB1_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB1_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB1_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB1_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB1_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB1_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB1_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONCNTL_SHIFT)) & DDRC_PMLCB1_TRIGONCNTL_MASK) + +#define DDRC_PMLCB1_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB1_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB1_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB1_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB1_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB1_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB1_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONSEL_SHIFT)) & DDRC_PMLCB1_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC1 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC1_PMC1_MASK (0xFFFFFFFFU) +#define DDRC_PMC1_PMC1_SHIFT (0U) +/*! PMC1 - Event Count */ +#define DDRC_PMC1_PMC1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC1_PMC1_SHIFT)) & DDRC_PMC1_PMC1_MASK) +/*! @} */ + +/*! @name PMLCA2 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA2_BDIST_MASK (0x3FU) +#define DDRC_PMLCA2_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA2_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BDIST_SHIFT)) & DDRC_PMLCA2_BDIST_MASK) + +#define DDRC_PMLCA2_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA2_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA2_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BGRAN_SHIFT)) & DDRC_PMLCA2_BGRAN_MASK) + +#define DDRC_PMLCA2_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA2_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA2_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BSIZE_SHIFT)) & DDRC_PMLCA2_BSIZE_MASK) + +#define DDRC_PMLCA2_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA2_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA2_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_EVENT_SHIFT)) & DDRC_PMLCA2_EVENT_MASK) + +#define DDRC_PMLCA2_CE_MASK (0x4000000U) +#define DDRC_PMLCA2_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA2_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_CE_SHIFT)) & DDRC_PMLCA2_CE_MASK) + +#define DDRC_PMLCA2_FC_MASK (0x80000000U) +#define DDRC_PMLCA2_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA2_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_FC_SHIFT)) & DDRC_PMLCA2_FC_MASK) +/*! @} */ + +/*! @name PMLCB2 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB2_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB2_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB2_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_THRESHOLD_SHIFT)) & DDRC_PMLCB2_THRESHOLD_MASK) + +#define DDRC_PMLCB2_TBMULT_MASK (0x700U) +#define DDRC_PMLCB2_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB2_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TBMULT_SHIFT)) & DDRC_PMLCB2_TBMULT_MASK) + +#define DDRC_PMLCB2_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB2_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB2_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB2_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB2_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB2_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB2_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONCNTL_SHIFT)) & DDRC_PMLCB2_TRIGONCNTL_MASK) + +#define DDRC_PMLCB2_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB2_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB2_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB2_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB2_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB2_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB2_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONSEL_SHIFT)) & DDRC_PMLCB2_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC2 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC2_PMC2_MASK (0xFFFFFFFFU) +#define DDRC_PMC2_PMC2_SHIFT (0U) +/*! PMC2 - Event Count */ +#define DDRC_PMC2_PMC2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC2_PMC2_SHIFT)) & DDRC_PMC2_PMC2_MASK) +/*! @} */ + +/*! @name PMLCA3 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA3_BDIST_MASK (0x3FU) +#define DDRC_PMLCA3_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA3_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BDIST_SHIFT)) & DDRC_PMLCA3_BDIST_MASK) + +#define DDRC_PMLCA3_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA3_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA3_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BGRAN_SHIFT)) & DDRC_PMLCA3_BGRAN_MASK) + +#define DDRC_PMLCA3_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA3_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA3_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BSIZE_SHIFT)) & DDRC_PMLCA3_BSIZE_MASK) + +#define DDRC_PMLCA3_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA3_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA3_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_EVENT_SHIFT)) & DDRC_PMLCA3_EVENT_MASK) + +#define DDRC_PMLCA3_CE_MASK (0x4000000U) +#define DDRC_PMLCA3_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA3_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_CE_SHIFT)) & DDRC_PMLCA3_CE_MASK) + +#define DDRC_PMLCA3_FC_MASK (0x80000000U) +#define DDRC_PMLCA3_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA3_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_FC_SHIFT)) & DDRC_PMLCA3_FC_MASK) +/*! @} */ + +/*! @name PMLCB3 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB3_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB3_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB3_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_THRESHOLD_SHIFT)) & DDRC_PMLCB3_THRESHOLD_MASK) + +#define DDRC_PMLCB3_TBMULT_MASK (0x700U) +#define DDRC_PMLCB3_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB3_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TBMULT_SHIFT)) & DDRC_PMLCB3_TBMULT_MASK) + +#define DDRC_PMLCB3_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB3_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB3_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB3_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB3_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB3_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB3_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONCNTL_SHIFT)) & DDRC_PMLCB3_TRIGONCNTL_MASK) + +#define DDRC_PMLCB3_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB3_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB3_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB3_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB3_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB3_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB3_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONSEL_SHIFT)) & DDRC_PMLCB3_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC3 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC3_PMC3_MASK (0xFFFFFFFFU) +#define DDRC_PMC3_PMC3_SHIFT (0U) +/*! PMC3 - Event Count */ +#define DDRC_PMC3_PMC3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC3_PMC3_SHIFT)) & DDRC_PMC3_PMC3_MASK) +/*! @} */ + +/*! @name PMLCA4 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA4_BDIST_MASK (0x3FU) +#define DDRC_PMLCA4_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA4_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BDIST_SHIFT)) & DDRC_PMLCA4_BDIST_MASK) + +#define DDRC_PMLCA4_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA4_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA4_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BGRAN_SHIFT)) & DDRC_PMLCA4_BGRAN_MASK) + +#define DDRC_PMLCA4_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA4_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA4_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BSIZE_SHIFT)) & DDRC_PMLCA4_BSIZE_MASK) + +#define DDRC_PMLCA4_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA4_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA4_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_EVENT_SHIFT)) & DDRC_PMLCA4_EVENT_MASK) + +#define DDRC_PMLCA4_CE_MASK (0x4000000U) +#define DDRC_PMLCA4_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA4_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_CE_SHIFT)) & DDRC_PMLCA4_CE_MASK) + +#define DDRC_PMLCA4_FC_MASK (0x80000000U) +#define DDRC_PMLCA4_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA4_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_FC_SHIFT)) & DDRC_PMLCA4_FC_MASK) +/*! @} */ + +/*! @name PMLCB4 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB4_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB4_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB4_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_THRESHOLD_SHIFT)) & DDRC_PMLCB4_THRESHOLD_MASK) + +#define DDRC_PMLCB4_TBMULT_MASK (0x700U) +#define DDRC_PMLCB4_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB4_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TBMULT_SHIFT)) & DDRC_PMLCB4_TBMULT_MASK) + +#define DDRC_PMLCB4_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB4_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB4_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB4_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB4_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB4_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB4_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONCNTL_SHIFT)) & DDRC_PMLCB4_TRIGONCNTL_MASK) + +#define DDRC_PMLCB4_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB4_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB4_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB4_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB4_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB4_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB4_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONSEL_SHIFT)) & DDRC_PMLCB4_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC4 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC4_PMC4_MASK (0xFFFFFFFFU) +#define DDRC_PMC4_PMC4_SHIFT (0U) +/*! PMC4 - Event Count */ +#define DDRC_PMC4_PMC4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC4_PMC4_SHIFT)) & DDRC_PMC4_PMC4_MASK) +/*! @} */ + +/*! @name PMLCA5 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA5_BDIST_MASK (0x3FU) +#define DDRC_PMLCA5_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA5_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BDIST_SHIFT)) & DDRC_PMLCA5_BDIST_MASK) + +#define DDRC_PMLCA5_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA5_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA5_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BGRAN_SHIFT)) & DDRC_PMLCA5_BGRAN_MASK) + +#define DDRC_PMLCA5_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA5_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA5_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BSIZE_SHIFT)) & DDRC_PMLCA5_BSIZE_MASK) + +#define DDRC_PMLCA5_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA5_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA5_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_EVENT_SHIFT)) & DDRC_PMLCA5_EVENT_MASK) + +#define DDRC_PMLCA5_CE_MASK (0x4000000U) +#define DDRC_PMLCA5_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA5_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_CE_SHIFT)) & DDRC_PMLCA5_CE_MASK) + +#define DDRC_PMLCA5_FC_MASK (0x80000000U) +#define DDRC_PMLCA5_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA5_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_FC_SHIFT)) & DDRC_PMLCA5_FC_MASK) +/*! @} */ + +/*! @name PMLCB5 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB5_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB5_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB5_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_THRESHOLD_SHIFT)) & DDRC_PMLCB5_THRESHOLD_MASK) + +#define DDRC_PMLCB5_TBMULT_MASK (0x700U) +#define DDRC_PMLCB5_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB5_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TBMULT_SHIFT)) & DDRC_PMLCB5_TBMULT_MASK) + +#define DDRC_PMLCB5_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB5_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB5_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB5_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB5_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB5_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB5_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONCNTL_SHIFT)) & DDRC_PMLCB5_TRIGONCNTL_MASK) + +#define DDRC_PMLCB5_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB5_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB5_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB5_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB5_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB5_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB5_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONSEL_SHIFT)) & DDRC_PMLCB5_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC5 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC5_PMC5_MASK (0xFFFFFFFFU) +#define DDRC_PMC5_PMC5_SHIFT (0U) +/*! PMC5 - Event Count */ +#define DDRC_PMC5_PMC5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC5_PMC5_SHIFT)) & DDRC_PMC5_PMC5_MASK) +/*! @} */ + +/*! @name PMLCA6 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA6_BDIST_MASK (0x3FU) +#define DDRC_PMLCA6_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA6_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BDIST_SHIFT)) & DDRC_PMLCA6_BDIST_MASK) + +#define DDRC_PMLCA6_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA6_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA6_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BGRAN_SHIFT)) & DDRC_PMLCA6_BGRAN_MASK) + +#define DDRC_PMLCA6_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA6_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA6_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BSIZE_SHIFT)) & DDRC_PMLCA6_BSIZE_MASK) + +#define DDRC_PMLCA6_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA6_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA6_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_EVENT_SHIFT)) & DDRC_PMLCA6_EVENT_MASK) + +#define DDRC_PMLCA6_CE_MASK (0x4000000U) +#define DDRC_PMLCA6_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA6_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_CE_SHIFT)) & DDRC_PMLCA6_CE_MASK) + +#define DDRC_PMLCA6_FC_MASK (0x80000000U) +#define DDRC_PMLCA6_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA6_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_FC_SHIFT)) & DDRC_PMLCA6_FC_MASK) +/*! @} */ + +/*! @name PMLCB6 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB6_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB6_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB6_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_THRESHOLD_SHIFT)) & DDRC_PMLCB6_THRESHOLD_MASK) + +#define DDRC_PMLCB6_TBMULT_MASK (0x700U) +#define DDRC_PMLCB6_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB6_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TBMULT_SHIFT)) & DDRC_PMLCB6_TBMULT_MASK) + +#define DDRC_PMLCB6_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB6_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB6_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB6_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB6_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB6_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB6_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONCNTL_SHIFT)) & DDRC_PMLCB6_TRIGONCNTL_MASK) + +#define DDRC_PMLCB6_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB6_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB6_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB6_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB6_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB6_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB6_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONSEL_SHIFT)) & DDRC_PMLCB6_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC6 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC6_PMC6_MASK (0xFFFFFFFFU) +#define DDRC_PMC6_PMC6_SHIFT (0U) +/*! PMC6 - Event Count */ +#define DDRC_PMC6_PMC6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC6_PMC6_SHIFT)) & DDRC_PMC6_PMC6_MASK) +/*! @} */ + +/*! @name PMLCA7 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA7_BDIST_MASK (0x3FU) +#define DDRC_PMLCA7_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA7_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BDIST_SHIFT)) & DDRC_PMLCA7_BDIST_MASK) + +#define DDRC_PMLCA7_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA7_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA7_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BGRAN_SHIFT)) & DDRC_PMLCA7_BGRAN_MASK) + +#define DDRC_PMLCA7_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA7_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA7_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BSIZE_SHIFT)) & DDRC_PMLCA7_BSIZE_MASK) + +#define DDRC_PMLCA7_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA7_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA7_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_EVENT_SHIFT)) & DDRC_PMLCA7_EVENT_MASK) + +#define DDRC_PMLCA7_CE_MASK (0x4000000U) +#define DDRC_PMLCA7_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA7_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_CE_SHIFT)) & DDRC_PMLCA7_CE_MASK) + +#define DDRC_PMLCA7_FC_MASK (0x80000000U) +#define DDRC_PMLCA7_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA7_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_FC_SHIFT)) & DDRC_PMLCA7_FC_MASK) +/*! @} */ + +/*! @name PMLCB7 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB7_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB7_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB7_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_THRESHOLD_SHIFT)) & DDRC_PMLCB7_THRESHOLD_MASK) + +#define DDRC_PMLCB7_TBMULT_MASK (0x700U) +#define DDRC_PMLCB7_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB7_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TBMULT_SHIFT)) & DDRC_PMLCB7_TBMULT_MASK) + +#define DDRC_PMLCB7_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB7_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB7_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB7_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB7_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB7_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB7_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONCNTL_SHIFT)) & DDRC_PMLCB7_TRIGONCNTL_MASK) + +#define DDRC_PMLCB7_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB7_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB7_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB7_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB7_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB7_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB7_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONSEL_SHIFT)) & DDRC_PMLCB7_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC7 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC7_PMC7_MASK (0xFFFFFFFFU) +#define DDRC_PMC7_PMC7_SHIFT (0U) +/*! PMC7 - Event Count */ +#define DDRC_PMC7_PMC7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC7_PMC7_SHIFT)) & DDRC_PMC7_PMC7_MASK) +/*! @} */ + +/*! @name PMLCA8 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA8_BDIST_MASK (0x3FU) +#define DDRC_PMLCA8_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA8_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BDIST_SHIFT)) & DDRC_PMLCA8_BDIST_MASK) + +#define DDRC_PMLCA8_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA8_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA8_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BGRAN_SHIFT)) & DDRC_PMLCA8_BGRAN_MASK) + +#define DDRC_PMLCA8_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA8_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA8_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BSIZE_SHIFT)) & DDRC_PMLCA8_BSIZE_MASK) + +#define DDRC_PMLCA8_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA8_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA8_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_EVENT_SHIFT)) & DDRC_PMLCA8_EVENT_MASK) + +#define DDRC_PMLCA8_CE_MASK (0x4000000U) +#define DDRC_PMLCA8_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA8_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_CE_SHIFT)) & DDRC_PMLCA8_CE_MASK) + +#define DDRC_PMLCA8_FC_MASK (0x80000000U) +#define DDRC_PMLCA8_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA8_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_FC_SHIFT)) & DDRC_PMLCA8_FC_MASK) +/*! @} */ + +/*! @name PMLCB8 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB8_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB8_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB8_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_THRESHOLD_SHIFT)) & DDRC_PMLCB8_THRESHOLD_MASK) + +#define DDRC_PMLCB8_TBMULT_MASK (0x700U) +#define DDRC_PMLCB8_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB8_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TBMULT_SHIFT)) & DDRC_PMLCB8_TBMULT_MASK) + +#define DDRC_PMLCB8_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB8_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB8_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB8_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB8_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB8_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB8_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONCNTL_SHIFT)) & DDRC_PMLCB8_TRIGONCNTL_MASK) + +#define DDRC_PMLCB8_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB8_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB8_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB8_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB8_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB8_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB8_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONSEL_SHIFT)) & DDRC_PMLCB8_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC8 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC8_PMC8_MASK (0xFFFFFFFFU) +#define DDRC_PMC8_PMC8_SHIFT (0U) +/*! PMC8 - Event Count */ +#define DDRC_PMC8_PMC8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC8_PMC8_SHIFT)) & DDRC_PMC8_PMC8_MASK) +/*! @} */ + +/*! @name PMLCA9 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA9_BDIST_MASK (0x3FU) +#define DDRC_PMLCA9_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA9_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BDIST_SHIFT)) & DDRC_PMLCA9_BDIST_MASK) + +#define DDRC_PMLCA9_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA9_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA9_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BGRAN_SHIFT)) & DDRC_PMLCA9_BGRAN_MASK) + +#define DDRC_PMLCA9_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA9_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA9_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BSIZE_SHIFT)) & DDRC_PMLCA9_BSIZE_MASK) + +#define DDRC_PMLCA9_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA9_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA9_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_EVENT_SHIFT)) & DDRC_PMLCA9_EVENT_MASK) + +#define DDRC_PMLCA9_CE_MASK (0x4000000U) +#define DDRC_PMLCA9_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA9_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_CE_SHIFT)) & DDRC_PMLCA9_CE_MASK) + +#define DDRC_PMLCA9_FC_MASK (0x80000000U) +#define DDRC_PMLCA9_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA9_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_FC_SHIFT)) & DDRC_PMLCA9_FC_MASK) +/*! @} */ + +/*! @name PMLCB9 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB9_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB9_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB9_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_THRESHOLD_SHIFT)) & DDRC_PMLCB9_THRESHOLD_MASK) + +#define DDRC_PMLCB9_TBMULT_MASK (0x700U) +#define DDRC_PMLCB9_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB9_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TBMULT_SHIFT)) & DDRC_PMLCB9_TBMULT_MASK) + +#define DDRC_PMLCB9_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB9_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB9_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB9_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB9_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB9_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB9_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONCNTL_SHIFT)) & DDRC_PMLCB9_TRIGONCNTL_MASK) + +#define DDRC_PMLCB9_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB9_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB9_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB9_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB9_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB9_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB9_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONSEL_SHIFT)) & DDRC_PMLCB9_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC9 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC9_PMC9_MASK (0xFFFFFFFFU) +#define DDRC_PMC9_PMC9_SHIFT (0U) +/*! PMC9 - Event Count */ +#define DDRC_PMC9_PMC9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC9_PMC9_SHIFT)) & DDRC_PMC9_PMC9_MASK) +/*! @} */ + +/*! @name PMLCA10 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA10_BDIST_MASK (0x3FU) +#define DDRC_PMLCA10_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA10_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BDIST_SHIFT)) & DDRC_PMLCA10_BDIST_MASK) + +#define DDRC_PMLCA10_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA10_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA10_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BGRAN_SHIFT)) & DDRC_PMLCA10_BGRAN_MASK) + +#define DDRC_PMLCA10_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA10_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA10_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BSIZE_SHIFT)) & DDRC_PMLCA10_BSIZE_MASK) + +#define DDRC_PMLCA10_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA10_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA10_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_EVENT_SHIFT)) & DDRC_PMLCA10_EVENT_MASK) + +#define DDRC_PMLCA10_CE_MASK (0x4000000U) +#define DDRC_PMLCA10_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA10_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_CE_SHIFT)) & DDRC_PMLCA10_CE_MASK) + +#define DDRC_PMLCA10_FC_MASK (0x80000000U) +#define DDRC_PMLCA10_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA10_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_FC_SHIFT)) & DDRC_PMLCA10_FC_MASK) +/*! @} */ + +/*! @name PMLCB10 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB10_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB10_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB10_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_THRESHOLD_SHIFT)) & DDRC_PMLCB10_THRESHOLD_MASK) + +#define DDRC_PMLCB10_TBMULT_MASK (0x700U) +#define DDRC_PMLCB10_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB10_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TBMULT_SHIFT)) & DDRC_PMLCB10_TBMULT_MASK) + +#define DDRC_PMLCB10_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB10_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB10_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB10_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB10_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB10_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB10_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONCNTL_SHIFT)) & DDRC_PMLCB10_TRIGONCNTL_MASK) + +#define DDRC_PMLCB10_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB10_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB10_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB10_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB10_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB10_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB10_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONSEL_SHIFT)) & DDRC_PMLCB10_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC10 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC10_PMC10_MASK (0xFFFFFFFFU) +#define DDRC_PMC10_PMC10_SHIFT (0U) +/*! PMC10 - Event Count */ +#define DDRC_PMC10_PMC10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC10_PMC10_SHIFT)) & DDRC_PMC10_PMC10_MASK) +/*! @} */ + +/*! @name ERR_EN - Error Enable */ +/*! @{ */ + +#define DDRC_ERR_EN_ECC_EN_RAM_2_MASK (0x40U) +#define DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT (6U) +/*! ECC_EN_RAM_2 - ECC Enable For On-Chip RAM 2 + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN_RAM_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_2_MASK) + +#define DDRC_ERR_EN_ECC_EN_RAM_1_MASK (0x80U) +#define DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT (7U) +/*! ECC_EN_RAM_1 - ECC Enable For On-Chip RAM 1 + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN_RAM_1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_1_MASK) + +#define DDRC_ERR_EN_INLINE_ECC_EN_MASK (0x40000000U) +#define DDRC_ERR_EN_INLINE_ECC_EN_SHIFT (30U) +/*! INLINE_ECC_EN - Inline ECC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_INLINE_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_INLINE_ECC_EN_SHIFT)) & DDRC_ERR_EN_INLINE_ECC_EN_MASK) + +#define DDRC_ERR_EN_ECC_EN_MASK (0x80000000U) +#define DDRC_ERR_EN_ECC_EN_SHIFT (31U) +/*! ECC_EN - ECC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_SHIFT)) & DDRC_ERR_EN_ECC_EN_MASK) +/*! @} */ + +/*! @name DATA_ERR_INJECT_HI - Memory Data Path Error Injection Mask High */ +/*! @{ */ + +#define DDRC_DATA_ERR_INJECT_HI_EIMH_MASK (0xFFFFFFFFU) +#define DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT (0U) +/*! EIMH - Error Injection Mask High Data Path */ +#define DDRC_DATA_ERR_INJECT_HI_EIMH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT)) & DDRC_DATA_ERR_INJECT_HI_EIMH_MASK) +/*! @} */ + +/*! @name DATA_ERR_INJECT_LO - Memory Data Path Error Injection Mask Low */ +/*! @{ */ + +#define DDRC_DATA_ERR_INJECT_LO_EIML_MASK (0xFFFFFFFFU) +#define DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT (0U) +/*! EIML - Error Injection Mask Low Data Bit */ +#define DDRC_DATA_ERR_INJECT_LO_EIML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT)) & DDRC_DATA_ERR_INJECT_LO_EIML_MASK) +/*! @} */ + +/*! @name ERR_INJECT - Memory Data Path Error Injection Mask ECC */ +/*! @{ */ + +#define DDRC_ERR_INJECT_EEIM_MASK (0xFFU) +#define DDRC_ERR_INJECT_EEIM_SHIFT (0U) +/*! EEIM - ECC Error Injection Mask */ +#define DDRC_ERR_INJECT_EEIM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EEIM_SHIFT)) & DDRC_ERR_INJECT_EEIM_MASK) + +#define DDRC_ERR_INJECT_EIEN_MASK (0x100U) +#define DDRC_ERR_INJECT_EIEN_SHIFT (8U) +/*! EIEN - Error Injection Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_EIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EIEN_SHIFT)) & DDRC_ERR_INJECT_EIEN_MASK) + +#define DDRC_ERR_INJECT_NUM_ECC_INJ_MASK (0xF000U) +#define DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT (12U) +/*! NUM_ECC_INJ - Number Of ECC Errors Injected + * 0b0000..ECC errors are injected until the error injection is disabled + * 0b0001..4 + * 0b0010..8 + * 0b0011..16 + * 0b0100..20 + * 0b0101..24 + * 0b0110..28 + * 0b0111..32 + * 0b1000..36 + * 0b1001..40 + * 0b1010..44 + * 0b1011..48 + * 0b1100..52 + * 0b1101..56 + * 0b1110..60 + * 0b1111..64 + */ +#define DDRC_ERR_INJECT_NUM_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT)) & DDRC_ERR_INJECT_NUM_ECC_INJ_MASK) + +#define DDRC_ERR_INJECT_ECC_INJ_SRC_MASK (0x600000U) +#define DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT (21U) +/*! ECC_INJ_SRC - ECC Injection Source + * 0b00..DDR SDRAM ECC using programmed data and ECC injection masks + * 0b01..On-chip RAM ECC 1 + * 0b10..On-chip RAM ECC 2 + * 0b11..DDR SDRAM ECC. This setting forces a 1 or 2-bit ECC syndrome error based on the value of FRC2B + */ +#define DDRC_ERR_INJECT_ECC_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT)) & DDRC_ERR_INJECT_ECC_INJ_SRC_MASK) + +#define DDRC_ERR_INJECT_FRC2B_MASK (0x800000U) +#define DDRC_ERR_INJECT_FRC2B_SHIFT (23U) +/*! FRC2B - Force 2-Bit Error + * 0b0..SBE + * 0b1..2-bit error + */ +#define DDRC_ERR_INJECT_FRC2B(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_FRC2B_SHIFT)) & DDRC_ERR_INJECT_FRC2B_MASK) + +#define DDRC_ERR_INJECT_ADDR_TEN_MASK (0x80000000U) +#define DDRC_ERR_INJECT_ADDR_TEN_SHIFT (31U) +/*! ADDR_TEN - Address Trigger Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_ADDR_TEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ADDR_TEN_SHIFT)) & DDRC_ERR_INJECT_ADDR_TEN_MASK) +/*! @} */ + +/*! @name ADDR_ERR_INJ - Address Error Inject */ +/*! @{ */ + +#define DDRC_ADDR_ERR_INJ_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_ADDR_ERR_INJ_ADDR_SHIFT (0U) +/*! ADDR - Address */ +#define DDRC_ADDR_ERR_INJ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDR_ERR_INJ_ADDR_SHIFT)) & DDRC_ADDR_ERR_INJ_ADDR_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_DATA_HI - Memory Extended Data Path Read Capture High */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT (0U) +/*! ECEHD - Error Capture Extended High Data Path */ +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_DATA_LO - Memory Extended Data Path Read Capture Low */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT (0U) +/*! ECELD - Error Capture Extended Low Data Path */ +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK) +/*! @} */ + +/*! @name CAPTURE_DATA_HI - Memory Data Path Read Capture High */ +/*! @{ */ + +#define DDRC_CAPTURE_DATA_HI_ECHD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_DATA_HI_ECHD_SHIFT (0U) +/*! ECHD - Error Capture High Data Path */ +#define DDRC_CAPTURE_DATA_HI_ECHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_HI_ECHD_SHIFT)) & DDRC_CAPTURE_DATA_HI_ECHD_MASK) +/*! @} */ + +/*! @name CAPTURE_DATA_LO - Memory Data Path Read Capture Low */ +/*! @{ */ + +#define DDRC_CAPTURE_DATA_LO_ECLD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_DATA_LO_ECLD_SHIFT (0U) +/*! ECLD - Error Capture Low Data Path */ +#define DDRC_CAPTURE_DATA_LO_ECLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_LO_ECLD_SHIFT)) & DDRC_CAPTURE_DATA_LO_ECLD_MASK) +/*! @} */ + +/*! @name CAPTURE_ECC - Memory Data Path Read Capture ECC */ +/*! @{ */ + +#define DDRC_CAPTURE_ECC_ECE_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_ECC_ECE_SHIFT (0U) +/*! ECE - Error Capture ECC */ +#define DDRC_CAPTURE_ECC_ECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ECC_ECE_SHIFT)) & DDRC_CAPTURE_ECC_ECE_MASK) +/*! @} */ + +/*! @name ERR_DETECT - Memory Error Detect */ +/*! @{ */ + +#define DDRC_ERR_DETECT_MSE_MASK (0x1U) +#define DDRC_ERR_DETECT_MSE_SHIFT (0U) +/*! MSE - Memory-Select Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MSE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MSE_SHIFT)) & DDRC_ERR_DETECT_MSE_MASK) + +#define DDRC_ERR_DETECT_SBE_MASK (0x4U) +#define DDRC_ERR_DETECT_SBE_SHIFT (2U) +/*! SBE - Single-Bit ECC Errors + * 0b0..Did not cross + * 0b1..Crossed + */ +#define DDRC_ERR_DETECT_SBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SBE_SHIFT)) & DDRC_ERR_DETECT_SBE_MASK) + +#define DDRC_ERR_DETECT_MBE_MASK (0x8U) +#define DDRC_ERR_DETECT_MBE_SHIFT (3U) +/*! MBE - Multiple-Bit Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MBE_SHIFT)) & DDRC_ERR_DETECT_MBE_MASK) + +#define DDRC_ERR_DETECT_REFRATEE_MASK (0x80U) +#define DDRC_ERR_DETECT_REFRATEE_SHIFT (7U) +/*! REFRATEE - Refresh rate error. + * 0b0..A refresh rate error has not been detected. + * 0b1..A refresh rate error has been detected. + */ +#define DDRC_ERR_DETECT_REFRATEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_REFRATEE_SHIFT)) & DDRC_ERR_DETECT_REFRATEE_MASK) + +#define DDRC_ERR_DETECT_PHYE_MASK (0x10000U) +#define DDRC_ERR_DETECT_PHYE_SHIFT (16U) +/*! PHYE - PHY error. + * 0b0..A DDR PHY error has not been detected. + * 0b1..An error has been detected by the DDR PHY. + */ +#define DDRC_ERR_DETECT_PHYE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_PHYE_SHIFT)) & DDRC_ERR_DETECT_PHYE_MASK) + +#define DDRC_ERR_DETECT_UPDTMTE_MASK (0x100000U) +#define DDRC_ERR_DETECT_UPDTMTE_SHIFT (20U) +/*! UPDTMTE - Update Timeout Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_UPDTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_UPDTMTE_SHIFT)) & DDRC_ERR_DETECT_UPDTMTE_MASK) + +#define DDRC_ERR_DETECT_SMBE2_MASK (0x400000U) +#define DDRC_ERR_DETECT_SMBE2_SHIFT (22U) +/*! SMBE2 - SRAM Multi-Bit Error 2 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SMBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE2_SHIFT)) & DDRC_ERR_DETECT_SMBE2_MASK) + +#define DDRC_ERR_DETECT_SMBE1_MASK (0x800000U) +#define DDRC_ERR_DETECT_SMBE1_SHIFT (23U) +/*! SMBE1 - SRAM Multi-Bit Error 1 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SMBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE1_SHIFT)) & DDRC_ERR_DETECT_SMBE1_MASK) + +#define DDRC_ERR_DETECT_SSBE2_MASK (0x1000000U) +#define DDRC_ERR_DETECT_SSBE2_SHIFT (24U) +/*! SSBE2 - SRAM SBE 2 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SSBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE2_SHIFT)) & DDRC_ERR_DETECT_SSBE2_MASK) + +#define DDRC_ERR_DETECT_SSBE1_MASK (0x2000000U) +#define DDRC_ERR_DETECT_SSBE1_SHIFT (25U) +/*! SSBE1 - SRAM SBE 1 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SSBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE1_SHIFT)) & DDRC_ERR_DETECT_SSBE1_MASK) + +#define DDRC_ERR_DETECT_MME_MASK (0x80000000U) +#define DDRC_ERR_DETECT_MME_SHIFT (31U) +/*! MME - Multiple Memory Errors + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MME(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MME_SHIFT)) & DDRC_ERR_DETECT_MME_MASK) +/*! @} */ + +/*! @name ERR_DISABLE - Memory Error Disable */ +/*! @{ */ + +#define DDRC_ERR_DISABLE_MSED_MASK (0x1U) +#define DDRC_ERR_DISABLE_MSED_SHIFT (0U) +/*! MSED - Memory-Select Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_MSED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MSED_SHIFT)) & DDRC_ERR_DISABLE_MSED_MASK) + +#define DDRC_ERR_DISABLE_SBED_MASK (0x4U) +#define DDRC_ERR_DISABLE_SBED_SHIFT (2U) +/*! SBED - Single-Bit ECC Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_SBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_SBED_SHIFT)) & DDRC_ERR_DISABLE_SBED_MASK) + +#define DDRC_ERR_DISABLE_MBED_MASK (0x8U) +#define DDRC_ERR_DISABLE_MBED_SHIFT (3U) +/*! MBED - Multiple-Bit ECC Error Disable + * 0b0..Detected + * 0b1..Not detected or reported + */ +#define DDRC_ERR_DISABLE_MBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MBED_SHIFT)) & DDRC_ERR_DISABLE_MBED_MASK) + +#define DDRC_ERR_DISABLE_REFRATEED_MASK (0x80U) +#define DDRC_ERR_DISABLE_REFRATEED_SHIFT (7U) +/*! REFRATEED - Refresh Rate Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_REFRATEED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_REFRATEED_SHIFT)) & DDRC_ERR_DISABLE_REFRATEED_MASK) + +#define DDRC_ERR_DISABLE_PHYED_MASK (0x10000U) +#define DDRC_ERR_DISABLE_PHYED_SHIFT (16U) +/*! PHYED - PHY Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_PHYED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_PHYED_SHIFT)) & DDRC_ERR_DISABLE_PHYED_MASK) + +#define DDRC_ERR_DISABLE_UPDTMTED_MASK (0x100000U) +#define DDRC_ERR_DISABLE_UPDTMTED_SHIFT (20U) +/*! UPDTMTED - Update Timeout Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_UPDTMTED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_UPDTMTED_SHIFT)) & DDRC_ERR_DISABLE_UPDTMTED_MASK) +/*! @} */ + +/*! @name ERR_INT_EN - Memory Error Interrupt Enable */ +/*! @{ */ + +#define DDRC_ERR_INT_EN_MSEE_MASK (0x1U) +#define DDRC_ERR_INT_EN_MSEE_SHIFT (0U) +/*! MSEE - Memory-Select Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_MSEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MSEE_SHIFT)) & DDRC_ERR_INT_EN_MSEE_MASK) + +#define DDRC_ERR_INT_EN_SBEE_MASK (0x4U) +#define DDRC_ERR_INT_EN_SBEE_SHIFT (2U) +/*! SBEE - Single-Bit ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_SBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SBEE_SHIFT)) & DDRC_ERR_INT_EN_SBEE_MASK) + +#define DDRC_ERR_INT_EN_MBEE_MASK (0x8U) +#define DDRC_ERR_INT_EN_MBEE_SHIFT (3U) +/*! MBEE - Multiple-Bit ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_MBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MBEE_SHIFT)) & DDRC_ERR_INT_EN_MBEE_MASK) + +#define DDRC_ERR_INT_EN_SSBE12E_MASK (0x10U) +#define DDRC_ERR_INT_EN_SSBE12E_SHIFT (4U) +/*! SSBE12E - SRAM Single-Bit Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_SSBE12E(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SSBE12E_SHIFT)) & DDRC_ERR_INT_EN_SSBE12E_MASK) + +#define DDRC_ERR_INT_EN_REFRATEEE_MASK (0x80U) +#define DDRC_ERR_INT_EN_REFRATEEE_SHIFT (7U) +/*! REFRATEEE - Refresh Rate Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_REFRATEEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_REFRATEEE_SHIFT)) & DDRC_ERR_INT_EN_REFRATEEE_MASK) + +#define DDRC_ERR_INT_EN_PHYEE_MASK (0x10000U) +#define DDRC_ERR_INT_EN_PHYEE_SHIFT (16U) +/*! PHYEE - PHY error interrupt enable. + * 0b0..PHY errors cannot generate interrupts. + * 0b1..PHY errors generate interrupts. + */ +#define DDRC_ERR_INT_EN_PHYEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_PHYEE_SHIFT)) & DDRC_ERR_INT_EN_PHYEE_MASK) + +#define DDRC_ERR_INT_EN_UPDTMTEE_MASK (0x100000U) +#define DDRC_ERR_INT_EN_UPDTMTEE_SHIFT (20U) +/*! UPDTMTEE - Update Timeout Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_UPDTMTEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_UPDTMTEE_SHIFT)) & DDRC_ERR_INT_EN_UPDTMTEE_MASK) +/*! @} */ + +/*! @name CAPTURE_ATTRIBUTES - Memory Error Attributes Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_ATTRIBUTES_VLD_MASK (0x1U) +#define DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define DDRC_CAPTURE_ATTRIBUTES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_VLD_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK (0x3000U) +#define DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT (12U) +/*! TTYP - Error Transaction Type + * 0b00..Reserved + * 0b01..Write + * 0b10..Read + * 0b11..Read-modify-write + */ +#define DDRC_CAPTURE_ATTRIBUTES_TTYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK (0x7000000U) +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT (24U) +/*! TSIZ - Error Transaction Size + * 0b000..8 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..5 + * 0b110..6 + * 0b111..7 + */ +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK (0x70000000U) +#define DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT (28U) +/*! BNUM - Data Beat Number */ +#define DDRC_CAPTURE_ATTRIBUTES_BNUM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK) +/*! @} */ + +/*! @name CAPTURE_ADDRESS - Memory Error Address Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_ADDRESS_CADDR_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_ADDRESS_CADDR_SHIFT (0U) +/*! CADDR - Captured Address */ +#define DDRC_CAPTURE_ADDRESS_CADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ADDRESS_CADDR_SHIFT)) & DDRC_CAPTURE_ADDRESS_CADDR_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_ADDRESS - Memory Error Extended Address Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK (0xFFU) +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT (0U) +/*! CEADDR - Captured Extended Address */ +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT)) & DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK) +/*! @} */ + +/*! @name ERR_SBE - Single-Bit ECC Memory Error Management */ +/*! @{ */ + +#define DDRC_ERR_SBE_SBEC_MASK (0xFFU) +#define DDRC_ERR_SBE_SBEC_SHIFT (0U) +/*! SBEC - SBE Counter */ +#define DDRC_ERR_SBE_SBEC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBEC_SHIFT)) & DDRC_ERR_SBE_SBEC_MASK) + +#define DDRC_ERR_SBE_SBET_MASK (0xFF0000U) +#define DDRC_ERR_SBE_SBET_SHIFT (16U) +/*! SBET - SBE Threshold */ +#define DDRC_ERR_SBE_SBET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBET_SHIFT)) & DDRC_ERR_SBE_SBET_MASK) +/*! @} */ + +/*! @name ECC_REG_0 - ECC Region 0 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_0_REG_0_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_0_REG_0_EA_SHIFT (0U) +/*! REG_0_EA - Region 0 End Address */ +#define DDRC_ECC_REG_0_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EA_SHIFT)) & DDRC_ECC_REG_0_REG_0_EA_MASK) + +#define DDRC_ECC_REG_0_REG_0_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_0_REG_0_SA_SHIFT (16U) +/*! REG_0_SA - Region 0 Start Address */ +#define DDRC_ECC_REG_0_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_SA_SHIFT)) & DDRC_ECC_REG_0_REG_0_SA_MASK) + +#define DDRC_ECC_REG_0_REG_0_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_0_REG_0_EN_SHIFT (31U) +/*! REG_0_EN - Region 0 Enable + * 0b0..Does not use region 0 for ECC enablement + * 0b1..Protects addresses from region 0 with ECC + */ +#define DDRC_ECC_REG_0_REG_0_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EN_SHIFT)) & DDRC_ECC_REG_0_REG_0_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_1 - ECC Region 1 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_1_REG_1_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_1_REG_1_EA_SHIFT (0U) +/*! REG_1_EA - Region 1 End Address */ +#define DDRC_ECC_REG_1_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EA_SHIFT)) & DDRC_ECC_REG_1_REG_1_EA_MASK) + +#define DDRC_ECC_REG_1_REG_1_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_1_REG_1_SA_SHIFT (16U) +/*! REG_1_SA - Region 1 Start Address */ +#define DDRC_ECC_REG_1_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_SA_SHIFT)) & DDRC_ECC_REG_1_REG_1_SA_MASK) + +#define DDRC_ECC_REG_1_REG_1_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_1_REG_1_EN_SHIFT (31U) +/*! REG_1_EN - Region 1 Enable + * 0b0..Does not use region 1 for ECC enablement + * 0b1..Protects addresses from region 1 with ECC + */ +#define DDRC_ECC_REG_1_REG_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EN_SHIFT)) & DDRC_ECC_REG_1_REG_1_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_2 - ECC Region 2 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_2_REG_2_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_2_REG_2_EA_SHIFT (0U) +/*! REG_2_EA - Region 2 End Address */ +#define DDRC_ECC_REG_2_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EA_SHIFT)) & DDRC_ECC_REG_2_REG_2_EA_MASK) + +#define DDRC_ECC_REG_2_REG_2_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_2_REG_2_SA_SHIFT (16U) +/*! REG_2_SA - Region 2 Start Address */ +#define DDRC_ECC_REG_2_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_SA_SHIFT)) & DDRC_ECC_REG_2_REG_2_SA_MASK) + +#define DDRC_ECC_REG_2_REG_2_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_2_REG_2_EN_SHIFT (31U) +/*! REG_2_EN - Region 2 Enable + * 0b0..Does not use region 2 for ECC enablement + * 0b1..Protects addresses from region 2 with ECC + */ +#define DDRC_ECC_REG_2_REG_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EN_SHIFT)) & DDRC_ECC_REG_2_REG_2_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_3 - ECC Region 3 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_3_REG_3_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_3_REG_3_EA_SHIFT (0U) +/*! REG_3_EA - Region 3 End Address */ +#define DDRC_ECC_REG_3_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EA_SHIFT)) & DDRC_ECC_REG_3_REG_3_EA_MASK) + +#define DDRC_ECC_REG_3_REG_3_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_3_REG_3_SA_SHIFT (16U) +/*! REG_3_SA - Region 3 Start Address */ +#define DDRC_ECC_REG_3_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_SA_SHIFT)) & DDRC_ECC_REG_3_REG_3_SA_MASK) + +#define DDRC_ECC_REG_3_REG_3_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_3_REG_3_EN_SHIFT (31U) +/*! REG_3_EN - Region 3 Enable + * 0b0..Does not use region 3 for ECC enablement + * 0b1..Protects addresses from region 3 with ECC + */ +#define DDRC_ECC_REG_3_REG_3_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EN_SHIFT)) & DDRC_ECC_REG_3_REG_3_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_4 - ECC Region 4 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_4_REG_4_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_4_REG_4_EA_SHIFT (0U) +/*! REG_4_EA - Region 4 End Address */ +#define DDRC_ECC_REG_4_REG_4_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EA_SHIFT)) & DDRC_ECC_REG_4_REG_4_EA_MASK) + +#define DDRC_ECC_REG_4_REG_4_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_4_REG_4_SA_SHIFT (16U) +/*! REG_4_SA - Region 4 Start Address */ +#define DDRC_ECC_REG_4_REG_4_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_SA_SHIFT)) & DDRC_ECC_REG_4_REG_4_SA_MASK) + +#define DDRC_ECC_REG_4_REG_4_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_4_REG_4_EN_SHIFT (31U) +/*! REG_4_EN - Region 4 Enable + * 0b0..Does not use region 4 for ECC enablement + * 0b1..Protects addresses from region 4 with ECC + */ +#define DDRC_ECC_REG_4_REG_4_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EN_SHIFT)) & DDRC_ECC_REG_4_REG_4_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_5 - ECC Region 5 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_5_REG_5_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_5_REG_5_EA_SHIFT (0U) +/*! REG_5_EA - Region 5 End Address */ +#define DDRC_ECC_REG_5_REG_5_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EA_SHIFT)) & DDRC_ECC_REG_5_REG_5_EA_MASK) + +#define DDRC_ECC_REG_5_REG_5_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_5_REG_5_SA_SHIFT (16U) +/*! REG_5_SA - Region 5 Start Address */ +#define DDRC_ECC_REG_5_REG_5_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_SA_SHIFT)) & DDRC_ECC_REG_5_REG_5_SA_MASK) + +#define DDRC_ECC_REG_5_REG_5_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_5_REG_5_EN_SHIFT (31U) +/*! REG_5_EN - Region 5 Enable + * 0b0..Does not use region 5 for ECC enablement + * 0b1..Protects addresses from region 5 with ECC + */ +#define DDRC_ECC_REG_5_REG_5_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EN_SHIFT)) & DDRC_ECC_REG_5_REG_5_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_6 - ECC Region 6 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_6_REG_6_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_6_REG_6_EA_SHIFT (0U) +/*! REG_6_EA - Region 6 End Address */ +#define DDRC_ECC_REG_6_REG_6_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EA_SHIFT)) & DDRC_ECC_REG_6_REG_6_EA_MASK) + +#define DDRC_ECC_REG_6_REG_6_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_6_REG_6_SA_SHIFT (16U) +/*! REG_6_SA - Region 6 Start Address */ +#define DDRC_ECC_REG_6_REG_6_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_SA_SHIFT)) & DDRC_ECC_REG_6_REG_6_SA_MASK) + +#define DDRC_ECC_REG_6_REG_6_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_6_REG_6_EN_SHIFT (31U) +/*! REG_6_EN - Region 6 Enable + * 0b0..Does not use region 6 for ECC enablement + * 0b1..Protects addresses from region 6 with ECC + */ +#define DDRC_ECC_REG_6_REG_6_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EN_SHIFT)) & DDRC_ECC_REG_6_REG_6_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_7 - ECC Region 7 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_7_REG_7_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_7_REG_7_EA_SHIFT (0U) +/*! REG_7_EA - Region 7 End Address */ +#define DDRC_ECC_REG_7_REG_7_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EA_SHIFT)) & DDRC_ECC_REG_7_REG_7_EA_MASK) + +#define DDRC_ECC_REG_7_REG_7_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_7_REG_7_SA_SHIFT (16U) +/*! REG_7_SA - Region 7 Start Address */ +#define DDRC_ECC_REG_7_REG_7_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_SA_SHIFT)) & DDRC_ECC_REG_7_REG_7_SA_MASK) + +#define DDRC_ECC_REG_7_REG_7_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_7_REG_7_EN_SHIFT (31U) +/*! REG_7_EN - Region 7 Enable + * 0b0..Does not use region 7 for ECC enablement + * 0b1..Protects addresses from region 7 with ECC + */ +#define DDRC_ECC_REG_7_REG_7_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EN_SHIFT)) & DDRC_ECC_REG_7_REG_7_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DDRC_Register_Masks */ + + +/* DDRC - Peripheral instance base addresses */ +/** Peripheral DDR_CTRL base address */ +#define DDR_CTRL_BASE (0x4E300000u) +/** Peripheral DDR_CTRL base pointer */ +#define DDR_CTRL ((DDRC_Type *)DDR_CTRL_BASE) +/** Array initializer of DDRC peripheral base addresses */ +#define DDRC_BASE_ADDRS { DDR_CTRL_BASE } +/** Array initializer of DDRC peripheral base pointers */ +#define DDRC_BASE_PTRS { DDR_CTRL } + +/*! + * @} + */ /* end of group DDRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[31]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication disabled for all channels + * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0x1F000000U) +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0x7FFFFFFFU) +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (31U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA3 base address */ +#define DMA3_BASE (0x44000000u) +/** Peripheral DMA3 base pointer */ +#define DMA3 ((DMA_Type *)DMA3_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA3_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA3 } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA4 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_Peripheral_Access_Layer DMA4 Peripheral Access Layer + * @{ + */ + +/** DMA4 - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Management Page Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Management Page Error Status Register, offset: 0x4 */ + __I uint32_t INT_LOW; /**< Management Page Interrupt Request Status Register - Low, offset: 0x8 */ + __I uint32_t INT_HIGH; /**< Management Page Interrupt Request Status Register- High, offset: 0xC */ + __I uint32_t HRS_LOW; /**< Management Page Hardware Request Status Register - Low, offset: 0x10 */ + __I uint32_t HRS_HIGH; /**< Management Page Hardware Request Status Register - High, offset: 0x14 */ + uint8_t RESERVED_0[232]; + __IO uint32_t CH_GRPRI[64]; /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */ +} DMA4_Type; + +/* ---------------------------------------------------------------------------- + -- DMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_Register_Masks DMA4 Register Masks + * @{ + */ + +/*! @name CSR - Management Page Control Register */ +/*! @{ */ + +#define DMA4_CSR_EDBG_MASK (0x2U) +#define DMA4_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode is disabled. + * 0b1..Debug mode is enabled. + */ +#define DMA4_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_EDBG_SHIFT)) & DMA4_CSR_EDBG_MASK) + +#define DMA4_CSR_ERCA_MASK (0x4U) +#define DMA4_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round robin channel arbitration is disabled. + * 0b1..Round robin channel arbitration is enabled. + */ +#define DMA4_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ERCA_SHIFT)) & DMA4_CSR_ERCA_MASK) + +#define DMA4_CSR_HAE_MASK (0x10U) +#define DMA4_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ +#define DMA4_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_HAE_SHIFT)) & DMA4_CSR_HAE_MASK) + +#define DMA4_CSR_HALT_MASK (0x20U) +#define DMA4_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ +#define DMA4_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_HALT_SHIFT)) & DMA4_CSR_HALT_MASK) + +#define DMA4_CSR_GCLC_MASK (0x40U) +#define DMA4_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking is disabled for all channels. + * 0b1..Channel linking is available and controlled by each channel's link settings. + */ +#define DMA4_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_GCLC_SHIFT)) & DMA4_CSR_GCLC_MASK) + +#define DMA4_CSR_GMRC_MASK (0x80U) +#define DMA4_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication is disabled for all channels. + * 0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting. + */ +#define DMA4_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_GMRC_SHIFT)) & DMA4_CSR_GMRC_MASK) + +#define DMA4_CSR_ECX_MASK (0x100U) +#define DMA4_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer with Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and + * force the minor loop to finish. The cancel takes effect after the last write of the current read/write + * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX + * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an + * optional error interrupt. + */ +#define DMA4_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ECX_SHIFT)) & DMA4_CSR_ECX_MASK) + +#define DMA4_CSR_CX_MASK (0x200U) +#define DMA4_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The + * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after + * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ +#define DMA4_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_CX_SHIFT)) & DMA4_CSR_CX_MASK) + +#define DMA4_CSR_VER_MASK (0xFF0000U) +#define DMA4_CSR_VER_SHIFT (16U) +/*! VER - eDMA version */ +#define DMA4_CSR_VER(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_VER_SHIFT)) & DMA4_CSR_VER_MASK) + +#define DMA4_CSR_ACTIVE_ID_MASK (0x3F000000U) +#define DMA4_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active channel ID */ +#define DMA4_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ACTIVE_ID_SHIFT)) & DMA4_CSR_ACTIVE_ID_MASK) + +#define DMA4_CSR_ACTIVE_MASK (0x80000000U) +#define DMA4_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ +#define DMA4_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ACTIVE_SHIFT)) & DMA4_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Management Page Error Status Register */ +/*! @{ */ + +#define DMA4_ES_DBE_MASK (0x1U) +#define DMA4_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA4_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_DBE_SHIFT)) & DMA4_ES_DBE_MASK) + +#define DMA4_ES_SBE_MASK (0x2U) +#define DMA4_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA4_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SBE_SHIFT)) & DMA4_ES_SBE_MASK) + +#define DMA4_ES_SGE_MASK (0x4U) +#define DMA4_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is + * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is + * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA4_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SGE_SHIFT)) & DMA4_ES_SGE_MASK) + +#define DMA4_ES_NCE_MASK (0x8U) +#define DMA4_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA4_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_NCE_SHIFT)) & DMA4_ES_NCE_MASK) + +#define DMA4_ES_DOE_MASK (0x10U) +#define DMA4_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_DOE_SHIFT)) & DMA4_ES_DOE_MASK) + +#define DMA4_ES_DAE_MASK (0x20U) +#define DMA4_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_DAE_SHIFT)) & DMA4_ES_DAE_MASK) + +#define DMA4_ES_SOE_MASK (0x40U) +#define DMA4_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SOE_SHIFT)) & DMA4_ES_SOE_MASK) + +#define DMA4_ES_SAE_MASK (0x80U) +#define DMA4_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SAE_SHIFT)) & DMA4_ES_SAE_MASK) + +#define DMA4_ES_ECX_MASK (0x100U) +#define DMA4_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input. + */ +#define DMA4_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_ECX_SHIFT)) & DMA4_ES_ECX_MASK) + +#define DMA4_ES_ERRCHN_MASK (0x3F000000U) +#define DMA4_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA4_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_ERRCHN_SHIFT)) & DMA4_ES_ERRCHN_MASK) + +#define DMA4_ES_VLD_MASK (0x80000000U) +#define DMA4_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ +#define DMA4_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_VLD_SHIFT)) & DMA4_ES_VLD_MASK) +/*! @} */ + +/*! @name INT_LOW - Management Page Interrupt Request Status Register - Low */ +/*! @{ */ + +#define DMA4_INT_LOW_INT_MASK (0xFFFFFFFFU) +#define DMA4_INT_LOW_INT_SHIFT (0U) +/*! INT - Interrupt Request Status for channels 31 - 0 */ +#define DMA4_INT_LOW_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_INT_LOW_INT_SHIFT)) & DMA4_INT_LOW_INT_MASK) +/*! @} */ + +/*! @name INT_HIGH - Management Page Interrupt Request Status Register- High */ +/*! @{ */ + +#define DMA4_INT_HIGH_INT_MASK (0xFFFFFFFFU) +#define DMA4_INT_HIGH_INT_SHIFT (0U) +/*! INT - Interrupt Request Status for channels 63-32 */ +#define DMA4_INT_HIGH_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_INT_HIGH_INT_SHIFT)) & DMA4_INT_HIGH_INT_MASK) +/*! @} */ + +/*! @name HRS_LOW - Management Page Hardware Request Status Register - Low */ +/*! @{ */ + +#define DMA4_HRS_LOW_HRS_MASK (0xFFFFFFFFU) +#define DMA4_HRS_LOW_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status for channels 31 - 0 + * 0b00000000000000000000000000000000..A hardware service request for the channel is not present + * 0b00000000000000000000000000000001..A hardware service request for channel 0 is present + */ +#define DMA4_HRS_LOW_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA4_HRS_LOW_HRS_SHIFT)) & DMA4_HRS_LOW_HRS_MASK) +/*! @} */ + +/*! @name HRS_HIGH - Management Page Hardware Request Status Register - High */ +/*! @{ */ + +#define DMA4_HRS_HIGH_HRS_MASK (0xFFFFFFFFU) +#define DMA4_HRS_HIGH_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status for channels 63-32 + * 0b00000000000000000000000000000000..A hardware service request for the channel is not present + * 0b00000000000000000000000000000001..A hardware service request for channel 0 is present + */ +#define DMA4_HRS_HIGH_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA4_HRS_HIGH_HRS_SHIFT)) & DMA4_HRS_HIGH_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group Register */ +/*! @{ */ + +#define DMA4_CH_GRPRI_GRPRI_MASK (0x3FU) +#define DMA4_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration group per channel. */ +#define DMA4_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CH_GRPRI_GRPRI_SHIFT)) & DMA4_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA4_CH_GRPRI */ +#define DMA4_CH_GRPRI_COUNT (64U) + + +/*! + * @} + */ /* end of group DMA4_Register_Masks */ + + +/* DMA4 - Peripheral instance base addresses */ +/** Peripheral DMA4 base address */ +#define DMA4_BASE (0u) +/** Peripheral DMA4 base pointer */ +#define DMA4 ((DMA4_Type *)DMA4_BASE) +/** Array initializer of DMA4 peripheral base addresses */ +#define DMA4_BASE_ADDRS { DMA4_BASE } +/** Array initializer of DMA4 peripheral base pointers */ +#define DMA4_BASE_PTRS { DMA4 } + +/*! + * @} + */ /* end of group DMA4_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA4_TCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_TCD_Peripheral_Access_Layer DMA4_TCD Peripheral Access Layer + * @{ + */ + +/** DMA4_TCD - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status Register, array offset: 0x0, array step: 0x1000 */ + __IO uint32_t CH_ES; /**< Channel Error Status Register, array offset: 0x4, array step: 0x1000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array offset: 0x8, array step: 0x1000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus Register, array offset: 0xC, array step: 0x1000 */ + __IO uint32_t CH_PRI; /**< Channel Priority Register, array offset: 0x10, array step: 0x1000 */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x14, array step: 0x1000 */ + __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x18, array step: 0x1000 */ + uint8_t RESERVED_0[6]; + __IO uint32_t SADDR; /**< TCD Source Address Register, array offset: 0x20, array step: 0x1000 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset Register, array offset: 0x24, array step: 0x1000 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes Register, array offset: 0x26, array step: 0x1000 */ + union { /* offset: 0x28, array step: 0x1000 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x28, array step: 0x1000 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x28, array step: 0x1000 */ + }; + __IO uint32_t SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address Register, array offset: 0x2C, array step: 0x1000 */ + __IO uint32_t DADDR; /**< TCD Destination Address Register, array offset: 0x30, array step: 0x1000 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset Register, array offset: 0x34, array step: 0x1000 */ + union { /* offset: 0x36, array step: 0x1000 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x36, array step: 0x1000 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x36, array step: 0x1000 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x38, array step: 0x1000 */ + __IO uint16_t CSR; /**< TCD Control and Status Register, array offset: 0x3C, array step: 0x1000 */ + union { /* offset: 0x3E, array step: 0x1000 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x3E, array step: 0x1000 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x3E, array step: 0x1000 */ + }; + uint8_t RESERVED_1[4032]; + } TCD[64]; +} DMA4_TCD_Type; + +/* ---------------------------------------------------------------------------- + -- DMA4_TCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_TCD_Register_Masks DMA4_TCD Register Masks + * @{ + */ + +/*! @name CH_CSR - Channel Control and Status Register */ +/*! @{ */ + +#define DMA4_TCD_CH_CSR_ERQ_MASK (0x1U) +#define DMA4_TCD_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..The DMA hardware request signal for the corresponding channel is disabled. + * 0b1..The DMA hardware request signal for the corresponding channel is enabled. + */ +#define DMA4_TCD_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_ERQ_SHIFT)) & DMA4_TCD_CH_CSR_ERQ_MASK) + +#define DMA4_TCD_CH_CSR_EARQ_MASK (0x2U) +#define DMA4_TCD_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel. + * 0b1..Enable asynchronous DMA request for the channel. + */ +#define DMA4_TCD_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_EARQ_SHIFT)) & DMA4_TCD_CH_CSR_EARQ_MASK) + +#define DMA4_TCD_CH_CSR_EEI_MASK (0x4U) +#define DMA4_TCD_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA4_TCD_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_EEI_SHIFT)) & DMA4_TCD_CH_CSR_EEI_MASK) + +#define DMA4_TCD_CH_CSR_SWAP_MASK (0xF000U) +#define DMA4_TCD_CH_CSR_SWAP_SHIFT (12U) +/*! SWAP - Swap size + * 0b0000..disabled + * 0b0001..read with 8-bit swap + * 0b0010..read with 16-bit swap + * 0b0011..read with 32-bit swap + * 0b0100-0b1000..reserved + * 0b1001..write with 8-bit swap + * 0b1010..write with 16-bit swap + * 0b1011..write with 32-bit swap + * 0b1100-0b1111..reserved + */ +#define DMA4_TCD_CH_CSR_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_SWAP_SHIFT)) & DMA4_TCD_CH_CSR_SWAP_MASK) + +#define DMA4_TCD_CH_CSR_SIGNEXT_MASK (0x3F0000U) +#define DMA4_TCD_CH_CSR_SIGNEXT_SHIFT (16U) +/*! SIGNEXT - Sign Extension + * 0b000000..disabled + * 0b000001..A non-zero value specifying the sign extend bit position + */ +#define DMA4_TCD_CH_CSR_SIGNEXT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_SIGNEXT_SHIFT)) & DMA4_TCD_CH_CSR_SIGNEXT_MASK) + +#define DMA4_TCD_CH_CSR_DONE_MASK (0x40000000U) +#define DMA4_TCD_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA4_TCD_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_DONE_SHIFT)) & DMA4_TCD_CH_CSR_DONE_MASK) + +#define DMA4_TCD_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA4_TCD_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA4_TCD_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_ACTIVE_SHIFT)) & DMA4_TCD_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_CSR */ +#define DMA4_TCD_CH_CSR_COUNT (64U) + +/*! @name CH_ES - Channel Error Status Register */ +/*! @{ */ + +#define DMA4_TCD_CH_ES_DBE_MASK (0x1U) +#define DMA4_TCD_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA4_TCD_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_DBE_SHIFT)) & DMA4_TCD_CH_ES_DBE_MASK) + +#define DMA4_TCD_CH_ES_SBE_MASK (0x2U) +#define DMA4_TCD_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA4_TCD_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SBE_SHIFT)) & DMA4_TCD_CH_ES_SBE_MASK) + +#define DMA4_TCD_CH_ES_SGE_MASK (0x4U) +#define DMA4_TCD_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is + * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is + * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA4_TCD_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SGE_SHIFT)) & DMA4_TCD_CH_ES_SGE_MASK) + +#define DMA4_TCD_CH_ES_NCE_MASK (0x8U) +#define DMA4_TCD_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. + * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, + * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ +#define DMA4_TCD_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_NCE_SHIFT)) & DMA4_TCD_CH_ES_NCE_MASK) + +#define DMA4_TCD_CH_ES_DOE_MASK (0x10U) +#define DMA4_TCD_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_TCD_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_DOE_SHIFT)) & DMA4_TCD_CH_ES_DOE_MASK) + +#define DMA4_TCD_CH_ES_DAE_MASK (0x20U) +#define DMA4_TCD_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_TCD_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_DAE_SHIFT)) & DMA4_TCD_CH_ES_DAE_MASK) + +#define DMA4_TCD_CH_ES_SOE_MASK (0x40U) +#define DMA4_TCD_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_TCD_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SOE_SHIFT)) & DMA4_TCD_CH_ES_SOE_MASK) + +#define DMA4_TCD_CH_ES_SAE_MASK (0x80U) +#define DMA4_TCD_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_TCD_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SAE_SHIFT)) & DMA4_TCD_CH_ES_SAE_MASK) + +#define DMA4_TCD_CH_ES_ERR_MASK (0x80000000U) +#define DMA4_TCD_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA4_TCD_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_ERR_SHIFT)) & DMA4_TCD_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_ES */ +#define DMA4_TCD_CH_ES_COUNT (64U) + +/*! @name CH_INT - Channel Interrupt Status Register */ +/*! @{ */ + +#define DMA4_TCD_CH_INT_INT_MASK (0x1U) +#define DMA4_TCD_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA4_TCD_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_INT_INT_SHIFT)) & DMA4_TCD_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_INT */ +#define DMA4_TCD_CH_INT_COUNT (64U) + +/*! @name CH_SBR - Channel System Bus Register */ +/*! @{ */ + +#define DMA4_TCD_CH_SBR_MID_MASK (0xFU) +#define DMA4_TCD_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define DMA4_TCD_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_MID_SHIFT)) & DMA4_TCD_CH_SBR_MID_MASK) + +#define DMA4_TCD_CH_SBR_INSTR_MASK (0x2000U) +#define DMA4_TCD_CH_SBR_INSTR_SHIFT (13U) +/*! INSTR - Instruction/Data Access + * 0b0..Data access for DMA transfers + * 0b1..Instruction access for DMA transfers + */ +#define DMA4_TCD_CH_SBR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_INSTR_SHIFT)) & DMA4_TCD_CH_SBR_INSTR_MASK) + +#define DMA4_TCD_CH_SBR_SEC_MASK (0x4000U) +#define DMA4_TCD_CH_SBR_SEC_SHIFT (14U) +/*! SEC - Security Level + * 0b0..Nonsecure protection level for DMA transfers + * 0b1..Secure protection level for DMA transfers + */ +#define DMA4_TCD_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_SEC_SHIFT)) & DMA4_TCD_CH_SBR_SEC_MASK) + +#define DMA4_TCD_CH_SBR_PAL_MASK (0x8000U) +#define DMA4_TCD_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA4_TCD_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_PAL_SHIFT)) & DMA4_TCD_CH_SBR_PAL_MASK) + +#define DMA4_TCD_CH_SBR_EMI_MASK (0x10000U) +#define DMA4_TCD_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define DMA4_TCD_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_EMI_SHIFT)) & DMA4_TCD_CH_SBR_EMI_MASK) + +#define DMA4_TCD_CH_SBR_ATTR_MASK (0x7E0000U) +#define DMA4_TCD_CH_SBR_ATTR_SHIFT (17U) +/*! ATTR - Attribute Output */ +#define DMA4_TCD_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_ATTR_SHIFT)) & DMA4_TCD_CH_SBR_ATTR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_SBR */ +#define DMA4_TCD_CH_SBR_COUNT (64U) + +/*! @name CH_PRI - Channel Priority Register */ +/*! @{ */ + +#define DMA4_TCD_CH_PRI_APL_MASK (0x7U) +#define DMA4_TCD_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA4_TCD_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_PRI_APL_SHIFT)) & DMA4_TCD_CH_PRI_APL_MASK) + +#define DMA4_TCD_CH_PRI_DPA_MASK (0x40000000U) +#define DMA4_TCD_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability. + * 0b0..The channel can suspend a lower priority channel. + * 0b1..The channel cannot suspend any other channel, regardless of channel priority. + */ +#define DMA4_TCD_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_PRI_DPA_SHIFT)) & DMA4_TCD_CH_PRI_DPA_MASK) + +#define DMA4_TCD_CH_PRI_ECP_MASK (0x80000000U) +#define DMA4_TCD_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption. + * 0b0..The channel cannot be suspended by a higher priority channel's service request. + * 0b1..The channel can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA4_TCD_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_PRI_ECP_SHIFT)) & DMA4_TCD_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_PRI */ +#define DMA4_TCD_CH_PRI_COUNT (64U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA4_TCD_CH_MUX_SRC_MASK (0x7FU) +#define DMA4_TCD_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA4_TCD_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_MUX_SRC_SHIFT)) & DMA4_TCD_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_MUX */ +#define DMA4_TCD_CH_MUX_COUNT (64U) + +/*! @name CH_MATTR - Memory Attributes Register */ +/*! @{ */ + +#define DMA4_TCD_CH_MATTR_RCACHE_MASK (0xFU) +#define DMA4_TCD_CH_MATTR_RCACHE_SHIFT (0U) +/*! RCACHE - Read Cache Attributes */ +#define DMA4_TCD_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CH_MATTR_RCACHE_SHIFT)) & DMA4_TCD_CH_MATTR_RCACHE_MASK) + +#define DMA4_TCD_CH_MATTR_WCACHE_MASK (0xF0U) +#define DMA4_TCD_CH_MATTR_WCACHE_SHIFT (4U) +/*! WCACHE - Write Cache Attributes */ +#define DMA4_TCD_CH_MATTR_WCACHE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CH_MATTR_WCACHE_SHIFT)) & DMA4_TCD_CH_MATTR_WCACHE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_MATTR */ +#define DMA4_TCD_CH_MATTR_COUNT (64U) + +/*! @name SADDR - TCD Source Address Register */ +/*! @{ */ + +#define DMA4_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA4_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA4_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_SADDR_SADDR_SHIFT)) & DMA4_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_SADDR */ +#define DMA4_TCD_SADDR_COUNT (64U) + +/*! @name SOFF - TCD Signed Source Address Offset Register */ +/*! @{ */ + +#define DMA4_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA4_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source address signed offset */ +#define DMA4_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_SOFF_SOFF_SHIFT)) & DMA4_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA4_TCD_SOFF */ +#define DMA4_TCD_SOFF_COUNT (64U) + +/*! @name ATTR - TCD Transfer Attributes Register */ +/*! @{ */ + +#define DMA4_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA4_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110..64-byte + * 0b111..128-byte + */ +#define DMA4_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_DSIZE_SHIFT)) & DMA4_TCD_ATTR_DSIZE_MASK) + +#define DMA4_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA4_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination address modulo */ +#define DMA4_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_DMOD_SHIFT)) & DMA4_TCD_ATTR_DMOD_MASK) + +#define DMA4_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA4_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110..64-byte + * 0b111..128-byte + */ +#define DMA4_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_SSIZE_SHIFT)) & DMA4_TCD_ATTR_SSIZE_MASK) + +#define DMA4_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA4_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source address modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001..Source address modulo feature is enabled for any non-zero value [1-31] + */ +#define DMA4_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_SMOD_SHIFT)) & DMA4_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA4_TCD_ATTR */ +#define DMA4_TCD_ATTR_COUNT (64U) + +/*! @name NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets Register */ +/*! @{ */ + +#define DMA4_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA4_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes to transfer per service request */ +#define DMA4_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA4_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA4_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA4_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA4_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA4_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA4_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA4_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_NBYTES_MLOFFNO */ +#define DMA4_TCD_NBYTES_MLOFFNO_COUNT (64U) + +/*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets Register */ +/*! @{ */ + +#define DMA4_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA4_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes to transfer per service request */ +#define DMA4_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA4_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA4_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA4_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA4_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA4_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA4_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA4_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA4_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA4_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_NBYTES_MLOFFYES */ +#define DMA4_TCD_NBYTES_MLOFFYES_COUNT (64U) + +/*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address Register */ +/*! @{ */ + +#define DMA4_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA4_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA4_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA4_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA4_TCD_SLAST_SDA */ +#define DMA4_TCD_SLAST_SDA_COUNT (64U) + +/*! @name DADDR - TCD Destination Address Register */ +/*! @{ */ + +#define DMA4_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA4_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA4_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_DADDR_DADDR_SHIFT)) & DMA4_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_DADDR */ +#define DMA4_TCD_DADDR_COUNT (64U) + +/*! @name DOFF - TCD Signed Destination Address Offset Register */ +/*! @{ */ + +#define DMA4_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA4_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA4_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_DOFF_DOFF_SHIFT)) & DMA4_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA4_TCD_DOFF */ +#define DMA4_TCD_DOFF_COUNT (64U) + +/*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register */ +/*! @{ */ + +#define DMA4_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA4_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA4_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA4_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA4_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA4_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA4_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CITER_ELINKNO */ +#define DMA4_TCD_CITER_ELINKNO_COUNT (64U) + +/*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register */ +/*! @{ */ + +#define DMA4_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA4_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA4_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA4_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA4_TCD_CITER_ELINKYES_LINKCH_MASK (0x7E00U) +#define DMA4_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA4_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA4_TCD_CITER_ELINKYES_LINKCH_MASK) + +#define DMA4_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA4_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA4_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CITER_ELINKYES */ +#define DMA4_TCD_CITER_ELINKYES_COUNT (64U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */ +/*! @{ */ + +#define DMA4_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA4_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Final Destination Address Adjustment / Scatter Gather Address */ +#define DMA4_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA4_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA4_TCD_DLAST_SGA */ +#define DMA4_TCD_DLAST_SGA_COUNT (64U) + +/*! @name CSR - TCD Control and Status Register */ +/*! @{ */ + +#define DMA4_TCD_CSR_START_MASK (0x1U) +#define DMA4_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ +#define DMA4_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_START_SHIFT)) & DMA4_TCD_CSR_START_MASK) + +#define DMA4_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA4_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ +#define DMA4_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_INTMAJOR_SHIFT)) & DMA4_TCD_CSR_INTMAJOR_MASK) + +#define DMA4_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA4_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ +#define DMA4_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_INTHALF_SHIFT)) & DMA4_TCD_CSR_INTHALF_MASK) + +#define DMA4_TCD_CSR_DREQ_MASK (0x8U) +#define DMA4_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable request + * 0b0..No operation + * 0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests. + */ +#define DMA4_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_DREQ_SHIFT)) & DMA4_TCD_CSR_DREQ_MASK) + +#define DMA4_TCD_CSR_ESG_MASK (0x10U) +#define DMA4_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer + * to the next TCD to be loaded into this channel after the major loop completes its execution. + */ +#define DMA4_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_ESG_SHIFT)) & DMA4_TCD_CSR_ESG_MASK) + +#define DMA4_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA4_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ +#define DMA4_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_MAJORELINK_SHIFT)) & DMA4_TCD_CSR_MAJORELINK_MASK) + +#define DMA4_TCD_CSR_EEOP_MASK (0x40U) +#define DMA4_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable end-of-packet processing + * 0b0..The end-of-packet operation is disabled. + * 0b1..The end-of-packet hardware input signal is enabled. + */ +#define DMA4_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_EEOP_SHIFT)) & DMA4_TCD_CSR_EEOP_MASK) + +#define DMA4_TCD_CSR_ESDA_MASK (0x80U) +#define DMA4_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable store destination address + * 0b0..The store destination address to system memory operation is disabled. + * 0b1..The store destination address to system memory operation is enabled. + */ +#define DMA4_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_ESDA_SHIFT)) & DMA4_TCD_CSR_ESDA_MASK) + +#define DMA4_TCD_CSR_MAJORLINKCH_MASK (0x3F00U) +#define DMA4_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major loop link channel number */ +#define DMA4_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA4_TCD_CSR_MAJORLINKCH_MASK) + +#define DMA4_TCD_CSR_TMC_MASK (0xC000U) +#define DMA4_TCD_CSR_TMC_SHIFT (14U) +/*! TMC - Transfer Mode Control + * 0b00..Read/Write + * 0b01..Read Only + * 0b10..Write Only + * 0b11..Reserved + */ +#define DMA4_TCD_CSR_TMC(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_TMC_SHIFT)) & DMA4_TCD_CSR_TMC_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CSR */ +#define DMA4_TCD_CSR_COUNT (64U) + +/*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register */ +/*! @{ */ + +#define DMA4_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA4_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA4_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA4_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA4_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA4_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA4_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_BITER_ELINKNO */ +#define DMA4_TCD_BITER_ELINKNO_COUNT (64U) + +/*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register */ +/*! @{ */ + +#define DMA4_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA4_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting major iteration count */ +#define DMA4_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA4_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA4_TCD_BITER_ELINKYES_LINKCH_MASK (0x7E00U) +#define DMA4_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA4_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA4_TCD_BITER_ELINKYES_LINKCH_MASK) + +#define DMA4_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA4_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA4_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_BITER_ELINKYES */ +#define DMA4_TCD_BITER_ELINKYES_COUNT (64U) + + +/*! + * @} + */ /* end of group DMA4_TCD_Register_Masks */ + + +/* DMA4_TCD - Peripheral instance base addresses */ +/** Peripheral EDMA4_2__TCD base address */ +#define EDMA4_2__TCD_BASE (0u) +/** Peripheral EDMA4_2__TCD base pointer */ +#define EDMA4_2__TCD ((DMA4_TCD_Type *)EDMA4_2__TCD_BASE) +/** Array initializer of DMA4_TCD peripheral base addresses */ +#define DMA4_TCD_BASE_ADDRS { EDMA4_2__TCD_BASE } +/** Array initializer of DMA4_TCD peripheral base pointers */ +#define DMA4_TCD_BASE_PTRS { EDMA4_2__TCD } + +/*! + * @} + */ /* end of group DMA4_TCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ + uint8_t RESERVED_8[4]; + __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_9[12]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[24]; + __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ + __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ + __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ + __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ + __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ + __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ + uint8_t RESERVED_12[8]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ + uint8_t RESERVED_13[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ + uint8_t RESERVED_15[8]; + __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ + __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ + __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ + __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ + __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ + __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ + uint8_t RESERVED_16[16]; + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint8_t RESERVED_17[4]; + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_18[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint8_t RESERVED_19[4]; + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_20[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_21[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +/*! @{ */ + +#define ENET_EIR_RXB1_MASK (0x1U) +#define ENET_EIR_RXB1_SHIFT (0U) +/*! RXB1 - Receive buffer interrupt, class 1 */ +#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) + +#define ENET_EIR_RXF1_MASK (0x2U) +#define ENET_EIR_RXF1_SHIFT (1U) +/*! RXF1 - Receive frame interrupt, class 1 */ +#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) + +#define ENET_EIR_TXB1_MASK (0x4U) +#define ENET_EIR_TXB1_SHIFT (2U) +/*! TXB1 - Transmit buffer interrupt, class 1 */ +#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) + +#define ENET_EIR_TXF1_MASK (0x8U) +#define ENET_EIR_TXF1_SHIFT (3U) +/*! TXF1 - Transmit frame interrupt, class 1 */ +#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) + +#define ENET_EIR_RXB2_MASK (0x10U) +#define ENET_EIR_RXB2_SHIFT (4U) +/*! RXB2 - Receive buffer interrupt, class 2 */ +#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) + +#define ENET_EIR_RXF2_MASK (0x20U) +#define ENET_EIR_RXF2_SHIFT (5U) +/*! RXF2 - Receive frame interrupt, class 2 */ +#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) + +#define ENET_EIR_TXB2_MASK (0x40U) +#define ENET_EIR_TXB2_SHIFT (6U) +/*! TXB2 - Transmit buffer interrupt, class 2 */ +#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) + +#define ENET_EIR_TXF2_MASK (0x80U) +#define ENET_EIR_TXF2_SHIFT (7U) +/*! TXF2 - Transmit frame interrupt, class 2 */ +#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) + +#define ENET_EIR_RXFLUSH_0_MASK (0x1000U) +#define ENET_EIR_RXFLUSH_0_SHIFT (12U) +#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) + +#define ENET_EIR_RXFLUSH_1_MASK (0x2000U) +#define ENET_EIR_RXFLUSH_1_SHIFT (13U) +#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) + +#define ENET_EIR_RXFLUSH_2_MASK (0x4000U) +#define ENET_EIR_RXFLUSH_2_SHIFT (14U) +#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) + +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - Timestamp Timer */ +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) + +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - Transmit Timestamp Available */ +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) + +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +/*! WAKEUP - Node Wakeup Request Indication */ +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) + +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +/*! PLR - Payload Receive Error */ +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) + +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +/*! UN - Transmit FIFO Underrun */ +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) + +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +/*! RL - Collision Retry Limit */ +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) + +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +/*! LC - Late Collision */ +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) + +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +/*! EBERR - Ethernet Bus Error */ +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) + +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +/*! MII - MII Interrupt. */ +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) + +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +/*! RXB - Receive Buffer Interrupt */ +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) + +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +/*! RXF - Receive Frame Interrupt */ +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) + +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +/*! TXB - Transmit Buffer Interrupt */ +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) + +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +/*! TXF - Transmit Frame Interrupt */ +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) + +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +/*! GRA - Graceful Stop Complete */ +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) + +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +/*! BABT - Babbling Transmit Error */ +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) + +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +/*! BABR - Babbling Receive Error */ +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ + +/*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ + +#define ENET_EIMR_RXB1_MASK (0x1U) +#define ENET_EIMR_RXB1_SHIFT (0U) +/*! RXB1 - Receive buffer interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) + +#define ENET_EIMR_RXF1_MASK (0x2U) +#define ENET_EIMR_RXF1_SHIFT (1U) +/*! RXF1 - Receive frame interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) + +#define ENET_EIMR_TXB1_MASK (0x4U) +#define ENET_EIMR_TXB1_SHIFT (2U) +/*! TXB1 - Transmit buffer interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) + +#define ENET_EIMR_TXF1_MASK (0x8U) +#define ENET_EIMR_TXF1_SHIFT (3U) +/*! TXF1 - Transmit frame interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) + +#define ENET_EIMR_RXB2_MASK (0x10U) +#define ENET_EIMR_RXB2_SHIFT (4U) +/*! RXB2 - Receive buffer interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) + +#define ENET_EIMR_RXF2_MASK (0x20U) +#define ENET_EIMR_RXF2_SHIFT (5U) +/*! RXF2 - Receive frame interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) + +#define ENET_EIMR_TXB2_MASK (0x40U) +#define ENET_EIMR_TXB2_SHIFT (6U) +/*! TXB2 - Transmit buffer interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) + +#define ENET_EIMR_TXF2_MASK (0x80U) +#define ENET_EIMR_TXF2_SHIFT (7U) +/*! TXF2 - Transmit frame interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) + +#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U) +#define ENET_EIMR_RXFLUSH_0_SHIFT (12U) +/*! RXFLUSH_0 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) + +#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U) +#define ENET_EIMR_RXFLUSH_1_SHIFT (13U) +/*! RXFLUSH_1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) + +#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U) +#define ENET_EIMR_RXFLUSH_2_SHIFT (14U) +/*! RXFLUSH_2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) + +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - TS_TIMER Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) + +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - TS_AVAIL Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) + +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +/*! WAKEUP - WAKEUP Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) + +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +/*! PLR - PLR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) + +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +/*! UN - UN Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) + +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +/*! RL - RL Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) + +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +/*! LC - LC Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) + +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +/*! EBERR - EBERR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) + +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +/*! MII - MII Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) + +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +/*! RXB - RXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) + +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +/*! RXF - RXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) + +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) + +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) + +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) + +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) + +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ + +/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */ +/*! @{ */ + +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active */ +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ + +/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */ +/*! @{ */ + +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active */ +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ + +/*! @name ECR - Ethernet Control Register */ +/*! @{ */ + +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +/*! RESET - Ethernet MAC Reset */ +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) + +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) + +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) + +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) + +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588. + */ +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) + +#define ENET_ECR_SPEED_MASK (0x20U) +#define ENET_ECR_SPEED_SHIFT (5U) +/*! SPEED + * 0b0..10/100-Mbit/s mode + * 0b1..1000-Mbit/s mode + */ +#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) + +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) + +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +#define ENET_ECR_SVLANEN_MASK (0x200U) +#define ENET_ECR_SVLANEN_SHIFT (9U) +/*! SVLANEN - S-VLAN enable + * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. + * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in + * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the + * classification match comparators, RCMRn. + */ +#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) + +#define ENET_ECR_VLANUSE2ND_MASK (0x400U) +#define ENET_ECR_VLANUSE2ND_SHIFT (10U) +/*! VLANUSE2ND - VLAN use second tag + * 0b0..Always extract data from the first VLAN tag if it exists. + * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A + * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The + * second tag must be a C-VLAN + */ +#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) + +#define ENET_ECR_SVLANDBL_MASK (0x800U) +#define ENET_ECR_SVLANDBL_SHIFT (11U) +/*! SVLANDBL - S-VLAN double tag + * 0b0..Disable S-VLAN double tag + * 0b1..Enable S-VLAN double tag + */ +#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) + +#define ENET_ECR_TXC_DLY_MASK (0x10000U) +#define ENET_ECR_TXC_DLY_SHIFT (16U) +/*! TXC_DLY - Transmit clock delay + * 0b0..RGMII_TXC is not delayed. + * 0b1..Generate delayed version of RGMII_TXC. + */ +#define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK) + +#define ENET_ECR_RXC_DLY_MASK (0x20000U) +#define ENET_ECR_RXC_DLY_SHIFT (17U) +/*! RXC_DLY - Receive clock delay + * 0b0..Use non-delayed version of RGMII_RXC. + * 0b1..Use delayed version of RGMII_RXC. + */ +#define ENET_ECR_RXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK) +/*! @} */ + +/*! @name MMFR - MII Management Frame Register */ +/*! @{ */ + +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +/*! DATA - Management Frame Data */ +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) + +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +/*! TA - Turn Around */ +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) + +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +/*! RA - Register Address */ +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) + +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +/*! PA - PHY Address */ +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) + +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +/*! OP - Operation Code */ +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) + +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +/*! ST - Start Of Frame Delimiter */ +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ + +/*! @name MSCR - MII Speed Control Register */ +/*! @{ */ + +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +/*! MII_SPEED - MII Speed */ +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) + +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) + +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ + +/*! @name MIBC - MIB Control Register */ +/*! @{ */ + +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) + +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) + +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ + +/*! @name RCR - Receive Control Register */ +/*! @{ */ + +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) + +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) + +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) + +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) + +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +/*! BC_REJ - Broadcast Frame Reject + * 0b0..Will not reject frames as described above + * 0b1..Will reject frames as described above + */ +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) + +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +/*! FCE - Flow Control Enable + * 0b0..Disable flow control + * 0b1..Enable flow control + */ +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) + +#define ENET_RCR_RGMII_EN_MASK (0x40U) +#define ENET_RCR_RGMII_EN_SHIFT (6U) +/*! RGMII_EN - RGMII Mode Enable + * 0b0..MAC configured for non-RGMII operation + * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If + * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. + */ +#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) + +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) + +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s or 1-Gbit/s operation. + * 0b1..10-Mbit/s operation. + */ +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) + +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) + +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) + +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) + +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) + +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +/*! MAX_FL - Maximum Frame Length */ +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) + +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) + +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +/*! GRS - Graceful Receive Stopped + * 0b0..Receive not stopped + * 0b1..Receive stopped + */ +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control Register */ +/*! @{ */ + +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +/*! GTS - Graceful Transmit Stop + * 0b0..Disable graceful transmit stop + * 0b1..Enable graceful transmit stop + */ +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) + +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +/*! FDEN - Full-Duplex Enable + * 0b0..Disable full-duplex + * 0b1..Enable full-duplex + */ +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) + +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) + +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +/*! RFC_PAUSE - Receive Frame Control Pause */ +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) + +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) + +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) + +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ + +/*! @name PALR - Physical Address Lower Register */ +/*! @{ */ + +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +/*! PADDR1 - Pause Address */ +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ + +/*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ + +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +/*! TYPE - Type Field In PAUSE Frames */ +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) + +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ + +/*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ + +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +/*! PAUSE_DUR - Pause Duration */ +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) + +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +/*! OPCODE - Opcode Field In PAUSE Frames */ +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ + +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold */ +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) + +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold */ +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) + +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) + +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ + +/* The count of ENET_TXIC */ +#define ENET_TXIC_COUNT (3U) + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ + +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold */ +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) + +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold */ +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) + +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) + +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ + +/* The count of ENET_RXIC */ +#define ENET_RXIC_COUNT (3U) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ + +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ + +/*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ + +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ + +/*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ + +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ + +/*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ + +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ + +/*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ + +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b111111..4032 bytes written. + */ +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) + +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ + +/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */ +/*! @{ */ + +#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR1_R_DES_START_SHIFT (3U) +#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */ +/*! @{ */ + +#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR1_X_DES_START_SHIFT (3U) +#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */ +/*! @{ */ + +#define ENET_MRBR1_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */ +/*! @{ */ + +#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR2_R_DES_START_SHIFT (3U) +#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */ +/*! @{ */ + +#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR2_X_DES_START_SHIFT (3U) +#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */ +/*! @{ */ + +#define ENET_MRBR2_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RDSR - Receive Descriptor Ring 0 Start Register */ +/*! @{ */ + +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */ +/*! @{ */ + +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */ +/*! @{ */ + +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ + +#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold */ +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ + +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */ +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) + +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold */ +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ + +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold */ +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ + +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold */ +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ + +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold */ +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ + +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold */ +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ + +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold */ +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ + +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +/*! IPG - Transmit Inter-Packet Gap */ +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ + +/*! @name FTRL - Frame Truncation Length */ +/*! @{ */ + +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +/*! TRUNC_FL - Frame Truncation Length */ +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ + +/*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ + +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the + * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This + * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is + * extended to a 16-byte header. + */ +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) + +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must + * be cleared. If a non-IP frame is transmitted the frame is not modified. + */ +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) + +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the + * frame. The checksum field must be cleared. The other frames are not modified. + */ +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ + +/*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ + +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) + +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no + * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in + * store and forward mode (RSFL cleared). + */ +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) + +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame + * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL + * cleared). + */ +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) + +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) + +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ + +/*! @name RCMR - Receive Classification Match Register for Class n */ +/*! @{ */ + +#define ENET_RCMR_CMP0_MASK (0x7U) +#define ENET_RCMR_CMP0_SHIFT (0U) +/*! CMP0 - Compare 0 */ +#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) + +#define ENET_RCMR_CMP1_MASK (0x70U) +#define ENET_RCMR_CMP1_SHIFT (4U) +/*! CMP1 - Compare 1 */ +#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) + +#define ENET_RCMR_CMP2_MASK (0x700U) +#define ENET_RCMR_CMP2_SHIFT (8U) +/*! CMP2 - Compare 2 */ +#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) + +#define ENET_RCMR_CMP3_MASK (0x7000U) +#define ENET_RCMR_CMP3_SHIFT (12U) +/*! CMP3 - Compare 3 */ +#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) + +#define ENET_RCMR_MATCHEN_MASK (0x10000U) +#define ENET_RCMR_MATCHEN_SHIFT (16U) +/*! MATCHEN - Match Enable + * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. + * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. + */ +#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK) +/*! @} */ + +/* The count of ENET_RCMR */ +#define ENET_RCMR_COUNT (2U) + +/*! @name DMACFG - DMA Class Based Configuration */ +/*! @{ */ + +#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) +#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) +/*! IDLE_SLOPE - Idle slope */ +#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) + +#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) +#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) +/*! DMA_CLASS_EN - DMA class enable + * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also + * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 + * queues are disabled then their frames will be placed in queue 0. + * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. + */ +#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) + +#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) +#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U) +/*! CALC_NOIPG - Calculate no IPG + * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred + * for a frame when doing bandwidth calculations. This is the default. + * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, + * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every + * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames + * will become more bandwidth than large frames due to the relation of data to IPG overhead). + */ +#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK) +/*! @} */ + +/* The count of ENET_DMACFG */ +#define ENET_DMACFG_COUNT (2U) + +/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */ +/*! @{ */ + +#define ENET_RDAR1_RDAR_MASK (0x1000000U) +#define ENET_RDAR1_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active */ +#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK) +/*! @} */ + +/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */ +/*! @{ */ + +#define ENET_TDAR1_TDAR_MASK (0x1000000U) +#define ENET_TDAR1_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active */ +#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK) +/*! @} */ + +/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */ +/*! @{ */ + +#define ENET_RDAR2_RDAR_MASK (0x1000000U) +#define ENET_RDAR2_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active */ +#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK) +/*! @} */ + +/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */ +/*! @{ */ + +#define ENET_TDAR2_TDAR_MASK (0x1000000U) +#define ENET_TDAR2_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active */ +#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK) +/*! @} */ + +/*! @name QOS - QOS Scheme */ +/*! @{ */ + +#define ENET_QOS_TX_SCHEME_MASK (0x7U) +#define ENET_QOS_TX_SCHEME_SHIFT (0U) +/*! TX_SCHEME - TX scheme configuration + * 0b000..Credit-based scheme + * 0b001..Round-robin scheme + * 0b010-0b111..Reserved + */ +#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) + +#define ENET_QOS_RX_FLUSH0_MASK (0x8U) +#define ENET_QOS_RX_FLUSH0_SHIFT (3U) +/*! RX_FLUSH0 - RX Flush Ring 0 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) + +#define ENET_QOS_RX_FLUSH1_MASK (0x10U) +#define ENET_QOS_RX_FLUSH1_SHIFT (4U) +/*! RX_FLUSH1 - RX Flush Ring 1 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) + +#define ENET_QOS_RX_FLUSH2_MASK (0x20U) +#define ENET_QOS_RX_FLUSH2_SHIFT (5U) +/*! RX_FLUSH2 - RX Flush Ring 2 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK) +/*! @} */ + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +/*! TXPKTS - Packet count */ +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of broadcast packets */ +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of multicast packets */ +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of packets with CRC/align error */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC */ +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of packets less than 64 bytes with bad CRC */ +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC */ +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit collisions */ +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 64-byte transmit packets */ +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 65- to 127-byte transmit packets */ +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 128- to 255-byte transmit packets */ +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 256- to 511-byte transmit packets */ +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 512- to 1023-byte transmit packets */ +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 1024- to 2047-byte transmit packets */ +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than 2048 bytes */ +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +/*! TXOCTS - Number of transmit octets */ +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted OK */ +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with one collision */ +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with multiple collisions */ +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with deferral delay */ +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with late collision */ +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with excessive collisions */ +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with transmit FIFO underrun */ +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with carrier sense error */ +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +/*! COUNT - This read-only field is reserved and always has the value 0 */ +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames transmitted */ +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). */ +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +/*! COUNT - Number of packets received */ +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive broadcast packets */ +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive multicast packets */ +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with CRC or align error */ +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and good CRC */ +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and good CRC */ +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC */ +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC */ +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +/*! COUNT - Number of 64-byte receive packets */ +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +/*! COUNT - Number of 65- to 127-byte receive packets */ +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +/*! COUNT - Number of 128- to 255-byte receive packets */ +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +/*! COUNT - Number of 256- to 511-byte receive packets */ +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +/*! COUNT - Number of 512- to 1023-byte receive packets */ +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +/*! COUNT - Number of 1024- to 2047-byte receive packets */ +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +/*! COUNT - Number of greater-than-2048-byte receive packets */ +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +/*! COUNT - Number of receive octets */ +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +/*! COUNT - Frame count */ +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received OK */ +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with CRC error */ +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with alignment error */ +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Receive FIFO overflow count */ +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames received */ +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of octets for frames received without error */ +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ + +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) + +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared + * when the offset event is reached, so no further event occurs until the field is set again. The timer + * offset value must be set before setting this field. + */ +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) + +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) + +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when + * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before + * setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) + +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event + * 0b0..Disable. + * 0b1..Enable. + */ +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) + +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +/*! RESTART - Reset Timer */ +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) + +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) + +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except + * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ + +/*! @name ATVR - Timer Value Register */ +/*! @{ */ + +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ + +/*! @name ATOFF - Timer Offset Register */ +/*! @{ */ + +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ + +/*! @name ATPER - Timer Period Register */ +/*! @{ */ + +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +/*! PERIOD - Value for generating periodic events */ +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ + +/*! @name ATCOR - Timer Correction Register */ +/*! @{ */ + +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +/*! COR - Correction Counter Wrap-Around Value */ +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ + +/*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ + +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */ +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) + +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +/*! INC_CORR - Correction Increment Value */ +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ + +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +/*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the + * ff_tx_ts_frm signal asserted from the user application + */ +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ + +/*! @name TGSR - Timer Global Status Register */ +/*! @{ */ + +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) + +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) + +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) + +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ + +/*! @name TCSR - Timer Control Status Register */ +/*! @{ */ + +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) + +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. + */ +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) + +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) + +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +/*! @} */ + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ + +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +/*! TCC - Timer Capture Compare */ +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x42890000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { 0u, 0u, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { (ENET_Type *)0u, (ENET_Type *)0u, ENET2 } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET_QOS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer + * @{ + */ + +/** ENET_QOS - Register Layout Typedef */ +typedef struct { + __IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration Register, offset: 0x0 */ + __IO uint32_t MAC_EXT_CONFIGURATION; /**< MAC Extended Configuration Register, offset: 0x4 */ + __IO uint32_t MAC_PACKET_FILTER; /**< MAC Packet Filter, offset: 0x8 */ + __IO uint32_t MAC_WATCHDOG_TIMEOUT; /**< Watchdog Timeout, offset: 0xC */ + __IO uint32_t MAC_HASH_TABLE_REG0; /**< MAC Hash Table Register 0, offset: 0x10 */ + __IO uint32_t MAC_HASH_TABLE_REG1; /**< MAC Hash Table Register 1, offset: 0x14 */ + uint8_t RESERVED_0[56]; + __IO uint32_t MAC_VLAN_TAG_CTRL; /**< MAC VLAN Tag Control, offset: 0x50 */ + __IO uint32_t MAC_VLAN_TAG_DATA; /**< MAC VLAN Tag Data, offset: 0x54 */ + __IO uint32_t MAC_VLAN_HASH_TABLE; /**< MAC VLAN Hash Table, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MAC_VLAN_INCL; /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */ + __IO uint32_t MAC_INNER_VLAN_INCL; /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MAC_TX_FLOW_CTRL_Q[5]; /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Rx Flow Control, offset: 0x90 */ + __IO uint32_t MAC_RXQ_CTRL4; /**< Receive Queue Control 4, offset: 0x94 */ + __IO uint32_t MAC_TXQ_PRTY_MAP0; /**< Transmit Queue Priority Mapping 0, offset: 0x98 */ + __IO uint32_t MAC_TXQ_PRTY_MAP1; /**< Transmit Queue Priority Mapping 1, offset: 0x9C */ + __IO uint32_t MAC_RXQ_CTRL[4]; /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */ + __I uint32_t MAC_INTERRUPT_STATUS; /**< Interrupt Status, offset: 0xB0 */ + __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ + __I uint32_t MAC_RX_TX_STATUS; /**< Receive Transmit Status, offset: 0xB8 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MAC_PMT_CONTROL_STATUS; /**< PMT Control and Status, offset: 0xC0 */ + __IO uint32_t MAC_RWK_PACKET_FILTER; /**< Remote Wakeup Filter, offset: 0xC4 */ + uint8_t RESERVED_5[8]; + __IO uint32_t MAC_LPI_CONTROL_STATUS; /**< LPI Control and Status, offset: 0xD0 */ + __IO uint32_t MAC_LPI_TIMERS_CONTROL; /**< LPI Timers Control, offset: 0xD4 */ + __IO uint32_t MAC_LPI_ENTRY_TIMER; /**< Tx LPI Entry Timer Control, offset: 0xD8 */ + __IO uint32_t MAC_ONEUS_TIC_COUNTER; /**< One-microsecond Reference Timer, offset: 0xDC */ + uint8_t RESERVED_6[24]; + __IO uint32_t MAC_PHYIF_CONTROL_STATUS; /**< PHY Interface Control and Status, offset: 0xF8 */ + uint8_t RESERVED_7[20]; + __I uint32_t MAC_VERSION; /**< MAC Version, offset: 0x110 */ + __I uint32_t MAC_DEBUG; /**< MAC Debug, offset: 0x114 */ + uint8_t RESERVED_8[4]; + __I uint32_t MAC_HW_FEAT[4]; /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */ + uint8_t RESERVED_9[212]; + __IO uint32_t MAC_MDIO_ADDRESS; /**< MDIO Address, offset: 0x200 */ + __IO uint32_t MAC_MDIO_DATA; /**< MAC MDIO Data, offset: 0x204 */ + uint8_t RESERVED_10[40]; + __IO uint32_t MAC_CSR_SW_CTRL; /**< CSR Software Control, offset: 0x230 */ + __IO uint32_t MAC_FPE_CTRL_STS; /**< Frame Preemption Control, offset: 0x234 */ + uint8_t RESERVED_11[8]; + __I uint32_t MAC_PRESN_TIME_NS; /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */ + __IO uint32_t MAC_PRESN_TIME_UPDT; /**< MAC 1722 Presentation Time, offset: 0x244 */ + uint8_t RESERVED_12[184]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t HIGH; /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */ + __IO uint32_t LOW; /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */ + } MAC_ADDRESS[64]; + uint8_t RESERVED_13[512]; + __IO uint32_t MAC_MMC_CONTROL; /**< MMC Control, offset: 0x700 */ + __I uint32_t MAC_MMC_RX_INTERRUPT; /**< MMC Rx Interrupt, offset: 0x704 */ + __I uint32_t MAC_MMC_TX_INTERRUPT; /**< MMC Tx Interrupt, offset: 0x708 */ + __IO uint32_t MAC_MMC_RX_INTERRUPT_MASK; /**< MMC Rx Interrupt Mask, offset: 0x70C */ + __IO uint32_t MAC_MMC_TX_INTERRUPT_MASK; /**< MMC Tx Interrupt Mask, offset: 0x710 */ + __I uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD; /**< Tx Octet Count Good and Bad, offset: 0x714 */ + __I uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD; /**< Tx Packet Count Good and Bad, offset: 0x718 */ + __I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD; /**< Tx Broadcast Packets Good, offset: 0x71C */ + __I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD; /**< Tx Multicast Packets Good, offset: 0x720 */ + __I uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */ + __I uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */ + __I uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */ + __I uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */ + __I uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */ + __I uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */ + __I uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD; /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */ + __I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */ + __I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */ + __I uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS; /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */ + __I uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */ + __I uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */ + __I uint32_t MAC_TX_DEFERRED_PACKETS; /**< Deferred Packets Transmitted, offset: 0x754 */ + __I uint32_t MAC_TX_LATE_COLLISION_PACKETS; /**< Late Collision Packets Transmitted, offset: 0x758 */ + __I uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */ + __I uint32_t MAC_TX_CARRIER_ERROR_PACKETS; /**< Carrier Error Packets Transmitted, offset: 0x760 */ + __I uint32_t MAC_TX_OCTET_COUNT_GOOD; /**< Bytes Transmitted in Good Packets, offset: 0x764 */ + __I uint32_t MAC_TX_PACKET_COUNT_GOOD; /**< Good Packets Transmitted, offset: 0x768 */ + __I uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR; /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */ + __I uint32_t MAC_TX_PAUSE_PACKETS; /**< Pause Packets Transmitted, offset: 0x770 */ + __I uint32_t MAC_TX_VLAN_PACKETS_GOOD; /**< Good VLAN Packets Transmitted, offset: 0x774 */ + __I uint32_t MAC_TX_OSIZE_PACKETS_GOOD; /**< Good Oversize Packets Transmitted, offset: 0x778 */ + uint8_t RESERVED_14[4]; + __I uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD; /**< Good and Bad Packets Received, offset: 0x780 */ + __I uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD; /**< Bytes in Good and Bad Packets Received, offset: 0x784 */ + __I uint32_t MAC_RX_OCTET_COUNT_GOOD; /**< Bytes in Good Packets Received, offset: 0x788 */ + __I uint32_t MAC_RX_BROADCAST_PACKETS_GOOD; /**< Good Broadcast Packets Received, offset: 0x78C */ + __I uint32_t MAC_RX_MULTICAST_PACKETS_GOOD; /**< Good Multicast Packets Received, offset: 0x790 */ + __I uint32_t MAC_RX_CRC_ERROR_PACKETS; /**< CRC Error Packets Received, offset: 0x794 */ + __I uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS; /**< Alignment Error Packets Received, offset: 0x798 */ + __I uint32_t MAC_RX_RUNT_ERROR_PACKETS; /**< Runt Error Packets Received, offset: 0x79C */ + __I uint32_t MAC_RX_JABBER_ERROR_PACKETS; /**< Jabber Error Packets Received, offset: 0x7A0 */ + __I uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD; /**< Good Undersize Packets Received, offset: 0x7A4 */ + __I uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD; /**< Good Oversize Packets Received, offset: 0x7A8 */ + __I uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */ + __I uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */ + __I uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */ + __I uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */ + __I uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */ + __I uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */ + __I uint32_t MAC_RX_UNICAST_PACKETS_GOOD; /**< Good Unicast Packets Received, offset: 0x7C4 */ + __I uint32_t MAC_RX_LENGTH_ERROR_PACKETS; /**< Length Error Packets Received, offset: 0x7C8 */ + __I uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS; /**< Out-of-range Type Packets Received, offset: 0x7CC */ + __I uint32_t MAC_RX_PAUSE_PACKETS; /**< Pause Packets Received, offset: 0x7D0 */ + __I uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS; /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */ + __I uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD; /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */ + __I uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS; /**< Watchdog Error Packets Received, offset: 0x7DC */ + __I uint32_t MAC_RX_RECEIVE_ERROR_PACKETS; /**< Receive Error Packets Received, offset: 0x7E0 */ + __I uint32_t MAC_RX_CONTROL_PACKETS_GOOD; /**< Good Control Packets Received, offset: 0x7E4 */ + uint8_t RESERVED_15[4]; + __I uint32_t MAC_TX_LPI_USEC_CNTR; /**< Microseconds Tx LPI Asserted, offset: 0x7EC */ + __I uint32_t MAC_TX_LPI_TRAN_CNTR; /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */ + __I uint32_t MAC_RX_LPI_USEC_CNTR; /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */ + __I uint32_t MAC_RX_LPI_TRAN_CNTR; /**< Number of Times Rx LPI Entered, offset: 0x7F8 */ + uint8_t RESERVED_16[4]; + __IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK; /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */ + uint8_t RESERVED_17[4]; + __I uint32_t MAC_MMC_IPC_RX_INTERRUPT; /**< MMC IPC Receive Interrupt, offset: 0x808 */ + uint8_t RESERVED_18[4]; + __I uint32_t MAC_RXIPV4_GOOD_PACKETS; /**< Good IPv4 Datagrams Received, offset: 0x810 */ + __I uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS; /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */ + __I uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS; /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */ + __I uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS; /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */ + __I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */ + __I uint32_t MAC_RXIPV6_GOOD_PACKETS; /**< Good IPv6 Datagrams Received, offset: 0x824 */ + __I uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS; /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */ + __I uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS; /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */ + __I uint32_t MAC_RXUDP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */ + __I uint32_t MAC_RXUDP_ERROR_PACKETS; /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */ + __I uint32_t MAC_RXTCP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */ + __I uint32_t MAC_RXTCP_ERROR_PACKETS; /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */ + __I uint32_t MAC_RXICMP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */ + __I uint32_t MAC_RXICMP_ERROR_PACKETS; /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */ + uint8_t RESERVED_19[8]; + __I uint32_t MAC_RXIPV4_GOOD_OCTETS; /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */ + __I uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */ + __I uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */ + __I uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS; /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */ + __I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */ + __I uint32_t MAC_RXIPV6_GOOD_OCTETS; /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */ + __I uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */ + __I uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */ + __I uint32_t MAC_RXUDP_GOOD_OCTETS; /**< Bytes Received in Good UDP Segment, offset: 0x870 */ + __I uint32_t MAC_RXUDP_ERROR_OCTETS; /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */ + __I uint32_t MAC_RXTCP_GOOD_OCTETS; /**< Bytes Received in Good TCP Segment, offset: 0x878 */ + __I uint32_t MAC_RXTCP_ERROR_OCTETS; /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */ + __I uint32_t MAC_RXICMP_GOOD_OCTETS; /**< Bytes Received in Good ICMP Segment, offset: 0x880 */ + __I uint32_t MAC_RXICMP_ERROR_OCTETS; /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */ + uint8_t RESERVED_20[24]; + __I uint32_t MAC_MMC_FPE_TX_INTERRUPT; /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */ + __IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK; /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */ + __I uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR; /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */ + __I uint32_t MAC_MMC_TX_HOLD_REQ_CNTR; /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */ + uint8_t RESERVED_21[16]; + __I uint32_t MAC_MMC_FPE_RX_INTERRUPT; /**< MMC FPE Receive Interrupt, offset: 0x8C0 */ + __IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK; /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */ + __I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */ + __I uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR; /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */ + __I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */ + __I uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR; /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */ + uint8_t RESERVED_22[40]; + __IO uint32_t MAC_L3_L4_CONTROL0; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */ + __IO uint32_t MAC_LAYER4_ADDRESS0; /**< Layer 4 Address 0, offset: 0x904 */ + uint8_t RESERVED_23[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG0; /**< Layer 3 Address 0 Register 0, offset: 0x910 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG0; /**< Layer 3 Address 1 Register 0, offset: 0x914 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG0; /**< Layer 3 Address 2 Register 0, offset: 0x918 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG0; /**< Layer 3 Address 3 Register 0, offset: 0x91C */ + uint8_t RESERVED_24[16]; + __IO uint32_t MAC_L3_L4_CONTROL1; /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */ + __IO uint32_t MAC_LAYER4_ADDRESS1; /**< Layer 4 Address 0, offset: 0x934 */ + uint8_t RESERVED_25[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG1; /**< Layer 3 Address 0 Register 1, offset: 0x940 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG1; /**< Layer 3 Address 1 Register 1, offset: 0x944 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG1; /**< Layer 3 Address 2 Register 1, offset: 0x948 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG1; /**< Layer 3 Address 3 Register 1, offset: 0x94C */ + uint8_t RESERVED_26[16]; + __IO uint32_t MAC_L3_L4_CONTROL2; /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */ + __IO uint32_t MAC_LAYER4_ADDRESS2; /**< Layer 4 Address 2, offset: 0x964 */ + uint8_t RESERVED_27[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x970 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x974 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG2; /**< Layer 3 Address 2 Register 2, offset: 0x978 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG2; /**< Layer 3 Address 3 Register 2, offset: 0x97C */ + uint8_t RESERVED_28[16]; + __IO uint32_t MAC_L3_L4_CONTROL3; /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */ + __IO uint32_t MAC_LAYER4_ADDRESS3; /**< Layer 4 Address 3, offset: 0x994 */ + uint8_t RESERVED_29[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG3; /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG3; /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG3; /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG3; /**< Layer 3 Address 3 Register 3, offset: 0x9AC */ + uint8_t RESERVED_30[16]; + __IO uint32_t MAC_L3_L4_CONTROL4; /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */ + __IO uint32_t MAC_LAYER4_ADDRESS4; /**< Layer 4 Address 4, offset: 0x9C4 */ + uint8_t RESERVED_31[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG4; /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG4; /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG4; /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG4; /**< Layer 3 Address 3 Register 4, offset: 0x9DC */ + uint8_t RESERVED_32[16]; + __IO uint32_t MAC_L3_L4_CONTROL5; /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */ + __IO uint32_t MAC_LAYER4_ADDRESS5; /**< Layer 4 Address 5, offset: 0x9F4 */ + uint8_t RESERVED_33[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG5; /**< Layer 3 Address 0 Register 5, offset: 0xA00 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG5; /**< Layer 3 Address 1 Register 5, offset: 0xA04 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG5; /**< Layer 3 Address 2 Register 5, offset: 0xA08 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG5; /**< Layer 3 Address 3 Register 5, offset: 0xA0C */ + uint8_t RESERVED_34[16]; + __IO uint32_t MAC_L3_L4_CONTROL6; /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */ + __IO uint32_t MAC_LAYER4_ADDRESS6; /**< Layer 4 Address 6, offset: 0xA24 */ + uint8_t RESERVED_35[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG6; /**< Layer 3 Address 0 Register 6, offset: 0xA30 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG6; /**< Layer 3 Address 1 Register 6, offset: 0xA34 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG6; /**< Layer 3 Address 2 Register 6, offset: 0xA38 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG6; /**< Layer 3 Address 3 Register 6, offset: 0xA3C */ + uint8_t RESERVED_36[16]; + __IO uint32_t MAC_L3_L4_CONTROL7; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */ + __IO uint32_t MAC_LAYER4_ADDRESS7; /**< Layer 4 Address 7, offset: 0xA54 */ + uint8_t RESERVED_37[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG7; /**< Layer 3 Address 0 Register 7, offset: 0xA60 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG7; /**< Layer 3 Address 1 Register 7, offset: 0xA64 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG7; /**< Layer 3 Address 2 Register 7, offset: 0xA68 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG7; /**< Layer 3 Address 3 Register 7, offset: 0xA6C */ + __IO uint32_t MAC_INDIR_ACCESS_CTRL; /**< MAC_INDIR_ACCESS_CTRL, offset: 0xA70 */ + __IO uint32_t MAC_INDIR_ACCESS_DATA; /**< MAC_INDIR_ACCESS_DATA, offset: 0xA74 */ + uint8_t RESERVED_38[136]; + __IO uint32_t MAC_TIMESTAMP_CONTROL; /**< Timestamp Control, offset: 0xB00 */ + __IO uint32_t MAC_SUB_SECOND_INCREMENT; /**< Subsecond Increment, offset: 0xB04 */ + __I uint32_t MAC_SYSTEM_TIME_SECONDS; /**< System Time Seconds, offset: 0xB08 */ + __I uint32_t MAC_SYSTEM_TIME_NANOSECONDS; /**< System Time Nanoseconds, offset: 0xB0C */ + __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE; /**< System Time Seconds Update, offset: 0xB10 */ + __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */ + __IO uint32_t MAC_TIMESTAMP_ADDEND; /**< Timestamp Addend, offset: 0xB18 */ + __IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */ + __I uint32_t MAC_TIMESTAMP_STATUS; /**< Timestamp Status, offset: 0xB20 */ + uint8_t RESERVED_39[12]; + __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */ + __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Transmit Timestamp Status Seconds, offset: 0xB34 */ + uint8_t RESERVED_40[8]; + __IO uint32_t MAC_AUXILIARY_CONTROL; /**< Auxiliary Timestamp Control, offset: 0xB40 */ + uint8_t RESERVED_41[4]; + __I uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */ + __I uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS; /**< Auxiliary Timestamp Seconds, offset: 0xB4C */ + __IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR; /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */ + __IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR; /**< Timestamp Egress Asymmetry Correction, offset: 0xB54 */ + __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */ + __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */ + __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */ + __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */ + __I uint32_t MAC_TIMESTAMP_INGRESS_LATENCY; /**< Timestamp Ingress Latency, offset: 0xB68 */ + __I uint32_t MAC_TIMESTAMP_EGRESS_LATENCY; /**< Timestamp Egress Latency, offset: 0xB6C */ + __IO uint32_t MAC_PPS_CONTROL; /**< PPS Control, offset: 0xB70 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS; /**< PPS0 Target Time Seconds, offset: 0xB80 */ + __IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS; /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */ + __IO uint32_t MAC_PPS0_INTERVAL; /**< PPS0 Interval, offset: 0xB88 */ + __IO uint32_t MAC_PPS0_WIDTH; /**< PPS0 Width, offset: 0xB8C */ + __IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS; /**< PPS1 Target Time Seconds, offset: 0xB90 */ + __IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS; /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */ + __IO uint32_t MAC_PPS1_INTERVAL; /**< PPS1 Interval, offset: 0xB98 */ + __IO uint32_t MAC_PPS1_WIDTH; /**< PPS1 Width, offset: 0xB9C */ + __IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS; /**< PPS2 Target Time Seconds, offset: 0xBA0 */ + __IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS; /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */ + __IO uint32_t MAC_PPS2_INTERVAL; /**< PPS2 Interval, offset: 0xBA8 */ + __IO uint32_t MAC_PPS2_WIDTH; /**< PPS2 Width, offset: 0xBAC */ + __IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS; /**< PPS3 Target Time Seconds, offset: 0xBB0 */ + __IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS; /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */ + __IO uint32_t MAC_PPS3_INTERVAL; /**< PPS3 Interval, offset: 0xBB8 */ + __IO uint32_t MAC_PPS3_WIDTH; /**< PPS3 Width, offset: 0xBBC */ + __IO uint32_t MAC_PTO_CONTROL; /**< PTP Offload Engine Control, offset: 0xBC0 */ + __IO uint32_t MAC_SOURCE_PORT_IDENTITY0; /**< Source Port Identity 0, offset: 0xBC4 */ + __IO uint32_t MAC_SOURCE_PORT_IDENTITY1; /**< Source Port Identity 1, offset: 0xBC8 */ + __IO uint32_t MAC_SOURCE_PORT_IDENTITY2; /**< Source Port Identity 2, offset: 0xBCC */ + __IO uint32_t MAC_LOG_MESSAGE_INTERVAL; /**< Log Message Interval, offset: 0xBD0 */ + uint8_t RESERVED_43[44]; + __IO uint32_t MTL_OPERATION_MODE; /**< MTL Operation Mode, offset: 0xC00 */ + uint8_t RESERVED_44[4]; + __IO uint32_t MTL_DBG_CTL; /**< FIFO Debug Access Control and Status, offset: 0xC08 */ + __IO uint32_t MTL_DBG_STS; /**< FIFO Debug Status, offset: 0xC0C */ + __IO uint32_t MTL_FIFO_DEBUG_DATA; /**< FIFO Debug Data, offset: 0xC10 */ + uint8_t RESERVED_45[12]; + __I uint32_t MTL_INTERRUPT_STATUS; /**< MTL Interrupt Status, offset: 0xC20 */ + uint8_t RESERVED_46[12]; + __IO uint32_t MTL_RXQ_DMA_MAP0; /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */ + __IO uint32_t MTL_RXQ_DMA_MAP1; /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */ + uint8_t RESERVED_47[8]; + __IO uint32_t MTL_TBS_CTRL; /**< Time Based Scheduling Control, offset: 0xC40 */ + uint8_t RESERVED_48[12]; + __IO uint32_t MTL_EST_CONTROL; /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */ + __IO uint32_t MTL_EST_EXT_CONTROL; /**< MTL_EST_EXT_CONTROL, offset: 0xC54 */ + __IO uint32_t MTL_EST_STATUS; /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */ + uint8_t RESERVED_49[4]; + __IO uint32_t MTL_EST_SCH_ERROR; /**< EST Scheduling Error, offset: 0xC60 */ + __IO uint32_t MTL_EST_FRM_SIZE_ERROR; /**< EST Frame Size Error, offset: 0xC64 */ + __I uint32_t MTL_EST_FRM_SIZE_CAPTURE; /**< EST Frame Size Capture, offset: 0xC68 */ + uint8_t RESERVED_50[4]; + __IO uint32_t MTL_EST_INTR_ENABLE; /**< EST Interrupt Enable, offset: 0xC70 */ + uint8_t RESERVED_51[12]; + __IO uint32_t MTL_EST_GCL_CONTROL; /**< EST GCL Control, offset: 0xC80 */ + __IO uint32_t MTL_EST_GCL_DATA; /**< EST GCL Data, offset: 0xC84 */ + uint8_t RESERVED_52[8]; + __IO uint32_t MTL_FPE_CTRL_STS; /**< Frame Preemption Control and Status, offset: 0xC90 */ + __IO uint32_t MTL_FPE_ADVANCE; /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */ + uint8_t RESERVED_53[8]; + __IO uint32_t MTL_RXP_CONTROL_STATUS; /**< RXP Control Status, offset: 0xCA0 */ + __IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS; /**< RXP Interrupt Control Status, offset: 0xCA4 */ + __I uint32_t MTL_RXP_DROP_CNT; /**< RXP Drop Count, offset: 0xCA8 */ + __I uint32_t MTL_RXP_ERROR_CNT; /**< RXP Error Count, offset: 0xCAC */ + __IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */ + __IO uint32_t MTL_RXP_INDIRECT_ACC_DATA; /**< RXP Indirect Access Data, offset: 0xCB4 */ + __I uint32_t MTL_RXP_BYPASS_CNT; /**< MTL_RXP_BYPASS_CNT, offset: 0xCB8 */ + uint8_t RESERVED_54[68]; + struct { /* offset: 0xD00, array step: 0x40 */ + __IO uint32_t MTL_TXQX_OP_MODE; /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */ + __I uint32_t MTL_TXQX_UNDRFLW; /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */ + __I uint32_t MTL_TXQX_DBG; /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t MTL_TXQX_ETS_CTRL; /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40, valid indices: [1-4] */ + __I uint32_t MTL_TXQX_ETS_STAT; /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */ + __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */ + __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40, valid indices: [1-4] */ + __IO uint32_t MTL_TXQX_HI_CRDT; /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40, valid indices: [1-4] */ + __IO uint32_t MTL_TXQX_LO_CRDT; /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40, valid indices: [1-4] */ + uint8_t RESERVED_1[4]; + __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */ + __IO uint32_t MTL_RXQX_OP_MODE; /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */ + __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */ + __I uint32_t MTL_RXQX_DBG; /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */ + __IO uint32_t MTL_RXQX_CTRL; /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */ + } MTL_QUEUE[5]; + uint8_t RESERVED_55[448]; + __IO uint32_t DMA_MODE; /**< DMA Bus Mode, offset: 0x1000 */ + __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus Mode, offset: 0x1004 */ + __I uint32_t DMA_INTERRUPT_STATUS; /**< DMA Interrupt Status, offset: 0x1008 */ + __I uint32_t DMA_DEBUG_STATUS0; /**< DMA Debug Status 0, offset: 0x100C */ + __I uint32_t DMA_DEBUG_STATUS1; /**< DMA Debug Status 1, offset: 0x1010 */ + uint8_t RESERVED_56[44]; + __IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL; /**< AXI LPI Entry Interval Control, offset: 0x1040 */ + uint8_t RESERVED_57[12]; + __IO uint32_t DMA_TBS_CTRL0; /**< DMA_TBS_CTRL0, offset: 0x1050 */ + __IO uint32_t DMA_TBS_CTRL1; /**< DMA_TBS_CTRL1, offset: 0x1054 */ + __IO uint32_t DMA_TBS_CTRL2; /**< DMA_TBS_CTRL2, offset: 0x1058 */ + __IO uint32_t DMA_TBS_CTRL3; /**< DMA_TBS_CTRL3, offset: 0x105C */ + uint8_t RESERVED_58[160]; + struct { /* offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_CTRL; /**< DMA Channel 0 Control..Channel 4 Control, array offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */ + uint8_t RESERVED_0[8]; + __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_CONTROL2; /**< Channel 0 Receive Control 2 register..DMA Channel 4 Receive Control 2 register, array offset: 0x1130, array step: 0x80 */ + __IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ + __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ + uint8_t RESERVED_3[4]; + __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */ + uint8_t RESERVED_4[4]; + __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */ + uint8_t RESERVED_5[4]; + __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */ + uint8_t RESERVED_6[4]; + __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */ + __IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */ + __I uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */ + __I uint32_t DMA_CHX_RXP_ACCEPT_CNT; /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */ + uint8_t RESERVED_7[20]; + } DMA_CH[5]; +} ENET_QOS_Type; + +/* ---------------------------------------------------------------------------- + -- ENET_QOS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks + * @{ + */ + +/*! @name MAC_CONFIGURATION - MAC Configuration Register */ +/*! @{ */ + +#define ENET_QOS_MAC_CONFIGURATION_RE_MASK (0x1U) +#define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT (0U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled + * 0b1..Receiver is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_TE_MASK (0x2U) +#define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT (1U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled + * 0b1..Transmitter is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK (0xCU) +#define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT (2U) +/*! PRELEN - Preamble Length for Transmit packets + * 0b00..7 bytes of preamble + * 0b01..5 bytes of preamble + * 0b10..3 bytes of preamble + * 0b11..Reserved + */ +#define ENET_QOS_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DC_MASK (0x10U) +#define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT (4U) +/*! DC - Deferral Check + * 0b0..Deferral check function is disabled + * 0b1..Deferral check function is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_BL_MASK (0x60U) +#define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT (5U) +/*! BL - Back-Off Limit + * 0b00..k = min(n,10) + * 0b01..k = min(n,8) + * 0b10..k = min(n,4) + * 0b11..k = min(n,1) + */ +#define ENET_QOS_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DR_MASK (0x100U) +#define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT (8U) +/*! DR - Disable Retry + * 0b0..Enable Retry + * 0b1..Disable Retry + */ +#define ENET_QOS_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK (0x200U) +#define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT (9U) +/*! DCRS - Disable Carrier Sense During Transmission + * 0b0..Enable Carrier Sense During Transmission + * 0b1..Disable Carrier Sense During Transmission + */ +#define ENET_QOS_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DO_MASK (0x400U) +#define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT (10U) +/*! DO - Disable Receive Own + * 0b0..Enable Receive Own + * 0b1..Disable Receive Own + */ +#define ENET_QOS_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK (0x800U) +#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT (11U) +/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode + * 0b0..ECRSFD is disabled + * 0b1..ECRSFD is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_LM_MASK (0x1000U) +#define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT (12U) +/*! LM - Loopback Mode + * 0b0..Loopback is disabled + * 0b1..Loopback is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DM_MASK (0x2000U) +#define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT (13U) +/*! DM - Duplex Mode + * 0b0..Half-duplex mode + * 0b1..Full-duplex mode + */ +#define ENET_QOS_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_FES_MASK (0x4000U) +#define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT (14U) +/*! FES - Speed + * 0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0 + * 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 + */ +#define ENET_QOS_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_PS_MASK (0x8000U) +#define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT (15U) +/*! PS - Port Select + * 0b0..For 1000 or 2500 Mbps operations + * 0b1..For 10 or 100 Mbps operations + */ +#define ENET_QOS_MAC_CONFIGURATION_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_JE_MASK (0x10000U) +#define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT (16U) +/*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes + * (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet + * status. + * 0b0..Jumbo packet is disabled + * 0b1..Jumbo packet is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_JD_MASK (0x20000U) +#define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT (17U) +/*! JD - Jabber Disable + * 0b0..Jabber is enabled + * 0b1..Jabber is disabled + */ +#define ENET_QOS_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_BE_MASK (0x40000U) +#define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT (18U) +/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during + * transmission in the GMII half-duplex mode. + * 0b0..Packet Burst is disabled + * 0b1..Packet Burst is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_WD_MASK (0x80000U) +#define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT (19U) +/*! WD - Watchdog Disable + * 0b0..Watchdog is enabled + * 0b1..Watchdog is disabled + */ +#define ENET_QOS_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_ACS_MASK (0x100000U) +#define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT (20U) +/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field + * on the incoming packets only if the value of the length field is less than 1,536 bytes. + * 0b0..Automatic Pad or CRC Stripping is disabled + * 0b1..Automatic Pad or CRC Stripping is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_CST_MASK (0x200000U) +#define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT (21U) +/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all + * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding + * the packet to the application. + * 0b0..CRC stripping for Type packets is disabled + * 0b1..CRC stripping for Type packets is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK (0x400000U) +#define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT (22U) +/*! S2KP - IEEE 802. + * 0b0..Support upto 2K packet is disabled + * 0b1..Support upto 2K packet is Enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK (0x800000U) +#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT (23U) +/*! GPSLCE - Giant Packet Size Limit Control Enable + * 0b0..Giant Packet Size Limit Control is disabled + * 0b1..Giant Packet Size Limit Control is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_IPG_MASK (0x7000000U) +#define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT (24U) +/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission. + * 0b000..96 bit times IPG + * 0b001..88 bit times IPG + * 0b010..80 bit times IPG + * 0b011..72 bit times IPG + * 0b100..64 bit times IPG + * 0b101..56 bit times IPG + * 0b110..48 bit times IPG + * 0b111..40 bit times IPG + */ +#define ENET_QOS_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_IPC_MASK (0x8000000U) +#define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT (27U) +/*! IPC - Checksum Offload + * 0b0..IP header/payload checksum checking is disabled + * 0b1..IP header/payload checksum checking is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_SARC_MASK (0x70000000U) +#define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT (28U) +/*! SARC - Source Address Insertion or Replacement Control + * 0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation + * 0b010..Contents of MAC Addr-0 inserted in SA field + * 0b011..Contents of MAC Addr-0 replaces SA field + * 0b110..Contents of MAC Addr-1 inserted in SA field + * 0b111..Contents of MAC Addr-1 replaces SA field + */ +#define ENET_QOS_MAC_CONFIGURATION_SARC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK) +/*! @} */ + +/*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */ +/*! @{ */ + +#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU) +#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U) +/*! GPSL - Giant Packet Size Limit */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U) +/*! DCRCC - Disable CRC Checking for Received Packets + * 0b0..CRC Checking is enabled + * 0b1..CRC Checking is disabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U) +/*! SPEN - Slow Protocol Detection Enable + * 0b0..Slow Protocol Detection is disabled + * 0b1..Slow Protocol Detection is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK (0x40000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U) +/*! USP - Unicast Slow Protocol Packet Detect + * 0b0..Unicast Slow Protocol Packet Detection is disabled + * 0b1..Unicast Slow Protocol Packet Detection is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK (0x80000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U) +/*! PDC - Packet Duplication Control + * 0b0..Packet Duplication Control is disabled + * 0b1..Packet Duplication Control is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U) +/*! EIPGEN - Extended Inter-Packet Gap Enable + * 0b0..Extended Inter-Packet Gap is disabled + * 0b1..Extended Inter-Packet Gap is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U) +/*! EIPG - Extended Inter-Packet Gap */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK) +/*! @} */ + +/*! @name MAC_PACKET_FILTER - MAC Packet Filter */ +/*! @{ */ + +#define ENET_QOS_MAC_PACKET_FILTER_PR_MASK (0x1U) +#define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT (0U) +/*! PR - Promiscuous Mode + * 0b0..Promiscuous Mode is disabled + * 0b1..Promiscuous Mode is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK (0x2U) +#define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT (1U) +/*! HUC - Hash Unicast + * 0b0..Hash Unicast is disabled + * 0b1..Hash Unicast is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_HUC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK (0x4U) +#define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT (2U) +/*! HMC - Hash Multicast + * 0b0..Hash Multicast is disabled + * 0b1..Hash Multicast is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_HMC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK (0x8U) +#define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT (3U) +/*! DAIF - DA Inverse Filtering + * 0b0..DA Inverse Filtering is disabled + * 0b1..DA Inverse Filtering is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_PM_MASK (0x10U) +#define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT (4U) +/*! PM - Pass All Multicast + * 0b0..Pass All Multicast is disabled + * 0b1..Pass All Multicast is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK (0x20U) +#define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT (5U) +/*! DBF - Disable Broadcast Packets + * 0b0..Enable Broadcast Packets + * 0b1..Disable Broadcast Packets + */ +#define ENET_QOS_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK (0xC0U) +#define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT (6U) +/*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including + * unicast and multicast Pause packets). + * 0b00..MAC filters all control packets from reaching the application + * 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter + * 0b10..MAC forwards all control packets to the application even if they fail the Address filter + * 0b11..MAC forwards the control packets that pass the Address filter + */ +#define ENET_QOS_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK (0x100U) +#define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT (8U) +/*! SAIF - SA Inverse Filtering + * 0b0..SA Inverse Filtering is disabled + * 0b1..SA Inverse Filtering is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK (0x200U) +#define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT (9U) +/*! SAF - Source Address Filter Enable + * 0b0..SA Filtering is disabled + * 0b1..SA Filtering is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK (0x400U) +#define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT (10U) +/*! HPF - Hash or Perfect Filter + * 0b0..Hash or Perfect Filter is disabled + * 0b1..Hash or Perfect Filter is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_HPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK (0x10000U) +#define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT (16U) +/*! VTFE - VLAN Tag Filter Enable + * 0b0..VLAN Tag Filter is disabled + * 0b1..VLAN Tag Filter is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_VTFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK (0x100000U) +#define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT (20U) +/*! IPFE - Layer 3 and Layer 4 Filter Enable + * 0b0..Layer 3 and Layer 4 Filters are disabled + * 0b1..Layer 3 and Layer 4 Filters are enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_IPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK (0x200000U) +#define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT (21U) +/*! DNTU - Drop Non-TCP/UDP over IP Packets + * 0b0..Forward Non-TCP/UDP over IP Packets + * 0b1..Drop Non-TCP/UDP over IP Packets + */ +#define ENET_QOS_MAC_PACKET_FILTER_DNTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_RA_MASK (0x80000000U) +#define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT (31U) +/*! RA - Receive All + * 0b0..Receive All is disabled + * 0b1..Receive All is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK) +/*! @} */ + +/*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */ +/*! @{ */ + +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU) +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U) +/*! WTO - Watchdog Timeout + * 0b0000..2 KB + * 0b0001..3 KB + * 0b0010..4 KB + * 0b0011..5 KB + * 0b0100..6 KB + * 0b0101..7 KB + * 0b0110..8 KB + * 0b0111..9 KB + * 0b1000..10 KB + * 0b1001..11 KB + * 0b1010..12 KB + * 0b1011..13 KB + * 0b1100..14 KB + * 0b1101..15 KB + * 0b1110..16383 Bytes + * 0b1111..Reserved + */ +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK) + +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x100U) +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U) +/*! PWE - Programmable Watchdog Enable + * 0b0..Programmable Watchdog is disabled + * 0b1..Programmable Watchdog is enabled + */ +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK) +/*! @} */ + +/*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U) +/*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. */ +#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK) +/*! @} */ + +/*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U) +/*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. */ +#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK) +/*! @} */ + +/*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK (0x1U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT (0U) +/*! OB - Operation Busy + * 0b0..Operation Busy is disabled + * 0b1..Operation Busy is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK (0x2U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT (1U) +/*! CT - Command Type + * 0b0..Write operation + * 0b1..Read operation + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK (0x7CU) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2U) +/*! OFS - Offset */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK (0x20000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT (17U) +/*! VTIM - VLAN Tag Inverse Match Enable + * 0b0..VLAN Tag Inverse Match is disabled + * 0b1..VLAN Tag Inverse Match is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK (0x40000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT (18U) +/*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN + * packets (Type = 0x88A8) as valid VLAN tagged packets. + * 0b0..S-VLAN is disabled + * 0b1..S-VLAN is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x600000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U) +/*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the + * outer VLAN Tag in received packet. + * 0b00..Do not strip + * 0b01..Strip if VLAN filter passes + * 0b10..Strip if VLAN filter fails + * 0b11..Always strip + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK (0x1000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT (24U) +/*! EVLRXS - Enable VLAN Tag in Rx status + * 0b0..VLAN Tag in Rx status is disabled + * 0b1..VLAN Tag in Rx status is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK (0x2000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT (25U) +/*! VTHM - VLAN Tag Hash Table Match Enable + * 0b0..VLAN Tag Hash Table Match is disabled + * 0b1..VLAN Tag Hash Table Match is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK (0x4000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT (26U) +/*! EDVLP - Enable Double VLAN Processing + * 0b0..Double VLAN Processing is disabled + * 0b1..Double VLAN Processing is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK (0x8000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT (27U) +/*! ERIVLT - ERIVLT + * 0b0..Inner VLAN tag is disabled + * 0b1..Inner VLAN tag is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x30000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U) +/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation + * on inner VLAN Tag in received packet. + * 0b00..Do not strip + * 0b01..Strip if VLAN filter passes + * 0b10..Strip if VLAN filter fails + * 0b11..Always strip + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK (0x80000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U) +/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status + * 0b0..Inner VLAN Tag in Rx status is disabled + * 0b1..Inner VLAN Tag in Rx status is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK) +/*! @} */ + +/*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFFU) +#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT (0U) +/*! VID - VLAN Tag ID */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK (0x10000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT (16U) +/*! VEN - VLAN Tag Enable + * 0b0..VLAN Tag is disabled + * 0b1..VLAN Tag is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK (0x20000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT (17U) +/*! ETV - 12bits or 16bits VLAN comparison + * 0b0..16 bit VLAN comparison + * 0b1..12 bit VLAN comparison + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK (0x40000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT (18U) +/*! DOVLTC - Disable VLAN Type Comparison + * 0b0..VLAN type comparison is enabled + * 0b1..VLAN type comparison is disabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK (0x80000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT (19U) +/*! ERSVLM - Enable S-VLAN Match for received Frames + * 0b0..Receive S-VLAN Match is disabled + * 0b1..Receive S-VLAN Match is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK (0x100000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT (20U) +/*! ERIVLT - Enable Inner VLAN Tag Comparison + * 0b0..Inner VLAN tag comparison is disabled + * 0b1..Inner VLAN tag comparison is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK (0x1000000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U) +/*! DMACHEN - DMA Channel Number Enable + * 0b0..DMA Channel Number is disabled + * 0b1..DMA Channel Number is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK (0xE000000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT (25U) +/*! DMACHN - DMA Channel Number */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK) +/*! @} */ + +/*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFFU) +#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0U) +/*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table. */ +#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK) +/*! @} */ + +/*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_INCL_VLT_MASK (0xFFFFU) +#define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT (0U) +/*! VLT - VLAN Tag for Transmit Packets */ +#define ENET_QOS_MAC_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_VLC_MASK (0x30000U) +#define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT (16U) +/*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or + * replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag + * (bytes 15 and 16) of all transmitted packets with VLAN tags. + * 0b00..No VLAN tag deletion, insertion, or replacement + * 0b01..VLAN tag deletion + * 0b10..VLAN tag insertion + * 0b11..VLAN tag replacement + */ +#define ENET_QOS_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_VLP_MASK (0x40000U) +#define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT (18U) +/*! VLP - VLAN Priority Control + * 0b0..VLAN Priority Control is disabled + * 0b1..VLAN Priority Control is enabled + */ +#define ENET_QOS_MAC_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK (0x80000U) +#define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT (19U) +/*! CSVL - C-VLAN or S-VLAN + * 0b0..C-VLAN type (0x8100) is inserted or replaced + * 0b1..S-VLAN type (0x88A8) is inserted or replaced + */ +#define ENET_QOS_MAC_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK (0x100000U) +#define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT (20U) +/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or + * replaced in Tx packet should be taken from: - The Tx descriptor + * 0b0..VLAN Tag Input is disabled + * 0b1..VLAN Tag Input is enabled + */ +#define ENET_QOS_MAC_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK (0x200000U) +#define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT (21U) +/*! CBTI - Channel based tag insertion + * 0b0..Channel based tag insertion is disabled + * 0b1..Channel based tag insertion is enabled + */ +#define ENET_QOS_MAC_VLAN_INCL_CBTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK (0x7000000U) +#define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT (24U) +/*! ADDR - Address */ +#define ENET_QOS_MAC_VLAN_INCL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK (0x40000000U) +#define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT (30U) +/*! RDWR - Read write control + * 0b0..Read operation of indirect access + * 0b1..Write operation of indirect access + */ +#define ENET_QOS_MAC_VLAN_INCL_RDWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK (0x80000000U) +#define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT (31U) +/*! BUSY - Busy + * 0b0..Busy status not detected + * 0b1..Busy status detected + */ +#define ENET_QOS_MAC_VLAN_INCL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK) +/*! @} */ + +/*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */ +/*! @{ */ + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFFU) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT (0U) +/*! VLT - VLAN Tag for Transmit Packets */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U) +/*! VLC - VLAN Tag Control in Transmit Packets + * 0b00..No VLAN tag deletion, insertion, or replacement + * 0b01..VLAN tag deletion + * 0b10..VLAN tag insertion + * 0b11..VLAN tag replacement + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK (0x40000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT (18U) +/*! VLP - VLAN Priority Control + * 0b0..VLAN Priority Control is disabled + * 0b1..VLAN Priority Control is enabled + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK (0x80000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT (19U) +/*! CSVL - C-VLAN or S-VLAN + * 0b0..C-VLAN type (0x8100) is inserted + * 0b1..S-VLAN type (0x88A8) is inserted + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK (0x100000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT (20U) +/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or + * replaced in Tx packet should be taken from: - The Tx descriptor + * 0b0..VLAN Tag Input is disabled + * 0b1..VLAN Tag Input is enabled + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK) +/*! @} */ + +/*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U) +/*! FCB_BPA - Flow Control Busy or Backpressure Activate + * 0b0..Flow Control Busy or Backpressure Activate is disabled + * 0b1..Flow Control Busy or Backpressure Activate is enabled + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) +/*! TFE - Transmit Flow Control Enable + * 0b0..Transmit Flow Control is disabled + * 0b1..Transmit Flow Control is enabled + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) +/*! PLT - Pause Low Threshold + * 0b000..Pause Time minus 4 Slot Times (PT -4 slot times) + * 0b001..Pause Time minus 28 Slot Times (PT -28 slot times) + * 0b010..Pause Time minus 36 Slot Times (PT -36 slot times) + * 0b011..Pause Time minus 144 Slot Times (PT -144 slot times) + * 0b100..Pause Time minus 256 Slot Times (PT -256 slot times) + * 0b101..Pause Time minus 512 Slot Times (PT -512 slot times) + * 0b110..Reserved + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) +/*! DZPQ - Disable Zero-Quanta Pause + * 0b0..Zero-Quanta Pause packet generation is enabled + * 0b1..Zero-Quanta Pause packet generation is disabled + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) +/*! PT - Pause Time */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK) +/*! @} */ + +/* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT (5U) + +/*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) +#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) +/*! RFE - Receive Flow Control Enable + * 0b0..Receive Flow Control is disabled + * 0b1..Receive Flow Control is enabled + */ +#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK) + +#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) +#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) +/*! UP - Unicast Pause Packet Detect + * 0b0..Unicast Pause Packet Detect disabled + * 0b1..Unicast Pause Packet Detect enabled + */ +#define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK) + +#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK (0x100U) +#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT (8U) +/*! PFCE - Priority Based Flow Control Enable + * 0b0..Priority Based Flow Control is disabled + * 0b1..Priority Based Flow Control is enabled + */ +#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK) +/*! @} */ + +/*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK (0x1U) +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT (0U) +/*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable. + * 0b0..Unicast Address Filter Fail Packets Queuing is disabled + * 0b1..Unicast Address Filter Fail Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK (0xEU) +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT (1U) +/*! UFFQ - Unicast Address Filter Fail Packets Queue. */ +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK (0x100U) +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT (8U) +/*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable. + * 0b0..Multicast Address Filter Fail Packets Queuing is disabled + * 0b1..Multicast Address Filter Fail Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK (0xE00U) +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT (9U) +/*! MFFQ - Multicast Address Filter Fail Packets Queue. */ +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK (0x10000U) +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT (16U) +/*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable + * 0b0..VLAN tag Filter Fail Packets Queuing is disabled + * 0b1..VLAN tag Filter Fail Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK (0xE0000U) +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT (17U) +/*! VFFQ - VLAN Tag Filter Fail Packets Queue */ +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK) +/*! @} */ + +/*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK (0xFFU) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT (0U) +/*! PSTQ0 - Priorities Selected in Transmit Queue 0 */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK) + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK (0xFF00U) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT (8U) +/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK) + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK (0xFF0000U) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT (16U) +/*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit. */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK) + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK (0xFF000000U) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT (24U) +/*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit. */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK) +/*! @} */ + +/*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK (0xFFU) +#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT (0U) +/*! PSTQ4 - Priorities Selected in Transmit Queue 4 */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK) +/*! @} */ + +/*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) +/*! AVCPQ - AV Untagged Control Packets Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) +/*! PSRQ0 - Priorities Selected in the Receive Queue 0 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK (0xFFU) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT (0U) +/*! PSRQ4 - Priorities Selected in the Receive Queue 4 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) +/*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) +/*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK (0x70U) +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT (4U) +/*! PTPQ - PTP Packets Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK (0x30U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT (4U) +/*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK (0xC0U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT (6U) +/*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK (0x700U) +#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT (8U) +/*! DCBCPQ - DCB Control Packets Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) +/*! PSRQ1 - Priorities Selected in the Receive Queue 1 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK (0x300U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT (8U) +/*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) +#define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT (12U) +/*! UPQ - Untagged Packet Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) +/*! MCBCQ - Multicast and Broadcast Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U) +/*! PSRQ2 - Priorities Selected in the Receive Queue 2 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) +/*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast + * packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed + * to Rx Queue specified in MCBCQ field. + * 0b0..Multicast and Broadcast Queue is disabled + * 0b1..Multicast and Broadcast Queue is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK (0x200000U) +#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT (21U) +/*! TACPQE - Tagged AV Control Packets Queuing Enable. + * 0b0..Tagged AV Control Packets Queuing is disabled + * 0b1..Tagged AV Control Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK (0xC00000U) +#define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT (22U) +/*! TPQC - Tagged PTP over Ethernet Packets Queuing Control. */ +#define ENET_QOS_MAC_RXQ_CTRL_TPQC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK (0x7000000U) +#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT (24U) +/*! FPRQ - Frame Preemption Residue Queue */ +#define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U) +/*! PSRQ3 - Priorities Selected in the Receive Queue 3 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK) +/*! @} */ + +/* The count of ENET_QOS_MAC_RXQ_CTRL */ +#define ENET_QOS_MAC_RXQ_CTRL_COUNT (4U) + +/*! @name MAC_INTERRUPT_STATUS - Interrupt Status */ +/*! @{ */ + +#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U) +/*! RGSMIIIS - RGMII or SMII Interrupt Status + * 0b0..RGMII or SMII Interrupt Status is not active + * 0b1..RGMII or SMII Interrupt Status is active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U) +/*! PHYIS - PHY Interrupt + * 0b0..PHY Interrupt not detected + * 0b1..PHY Interrupt detected + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U) +/*! PMTIS - PMT Interrupt Status + * 0b0..PMT Interrupt status not active + * 0b1..PMT Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U) +/*! LPIIS - LPI Interrupt Status + * 0b0..LPI Interrupt status not active + * 0b1..LPI Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U) +/*! MMCIS - MMC Interrupt Status + * 0b0..MMC Interrupt status not active + * 0b1..MMC Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U) +/*! MMCRXIS - MMC Receive Interrupt Status + * 0b0..MMC Receive Interrupt status not active + * 0b1..MMC Receive Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U) +/*! MMCTXIS - MMC Transmit Interrupt Status + * 0b0..MMC Transmit Interrupt status not active + * 0b1..MMC Transmit Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U) +/*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status + * 0b0..MMC Receive Checksum Offload Interrupt status not active + * 0b1..MMC Receive Checksum Offload Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U) +/*! TSIS - Timestamp Interrupt Status + * 0b0..Timestamp Interrupt status not active + * 0b1..Timestamp Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U) +/*! TXSTSIS - Transmit Status Interrupt + * 0b0..Transmit Interrupt status not active + * 0b1..Transmit Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U) +/*! RXSTSIS - Receive Status Interrupt + * 0b0..Receive Interrupt status not active + * 0b1..Receive Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U) +/*! FPEIS - Frame Preemption Interrupt Status + * 0b0..Frame Preemption Interrupt status not active + * 0b1..Frame Preemption Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U) +/*! MDIOIS - MDIO Interrupt Status + * 0b0..MDIO Interrupt status not active + * 0b1..MDIO Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U) +/*! MFTIS - MMC FPE Transmit Interrupt Status + * 0b0..MMC FPE Transmit Interrupt status not active + * 0b1..MMC FPE Transmit Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U) +/*! MFRIS - MMC FPE Receive Interrupt Status + * 0b0..MMC FPE Receive Interrupt status not active + * 0b1..MMC FPE Receive Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK) +/*! @} */ + +/*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U) +/*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register. + * 0b0..RGMII or SMII Interrupt is disabled + * 0b1..RGMII or SMII Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U) +/*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS]. + * 0b0..PHY Interrupt is disabled + * 0b1..PHY Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U) +/*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS]. + * 0b0..PMT Interrupt is disabled + * 0b1..PMT Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U) +/*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS]. + * 0b0..LPI Interrupt is disabled + * 0b1..LPI Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U) +/*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS]. + * 0b0..Timestamp Interrupt is disabled + * 0b1..Timestamp Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U) +/*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS]. + * 0b0..Timestamp Status Interrupt is disabled + * 0b1..Timestamp Status Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U) +/*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS]. + * 0b0..Receive Status Interrupt is disabled + * 0b1..Receive Status Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U) +/*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS. + * 0b0..Frame Preemption Interrupt is disabled + * 0b1..Frame Preemption Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U) +/*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * when MDIOIS field is set in the MAC_INTERRUPT_STATUS register. + * 0b0..MDIO Interrupt is disabled + * 0b1..MDIO Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK) +/*! @} */ + +/*! @name MAC_RX_TX_STATUS - Receive Transmit Status */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK (0x1U) +#define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT (0U) +/*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which + * happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) + * and JD bit is reset in the MAC_CONFIGURATION register. + * 0b0..No Transmit Jabber Timeout + * 0b1..Transmit Jabber Timeout occurred + */ +#define ENET_QOS_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK (0x2U) +#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT (1U) +/*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit + * indicates that the carrier signal from the PHY is not present at the end of preamble transmission. + * 0b0..Carrier is present + * 0b1..No carrier + */ +#define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK (0x4U) +#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT (2U) +/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit + * indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i + * signal was inactive for one or more transmission clock periods during packet transmission. + * 0b0..Carrier is present + * 0b1..Loss of carrier + */ +#define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK (0x8U) +#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U) +/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the + * DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission + * ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or + * when Jumbo packet is enabled). + * 0b0..No Excessive deferral + * 0b1..Excessive deferral + */ +#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK (0x10U) +#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT (4U) +/*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit + * indicates that the packet transmission aborted because a collision occurred after the collision + * window (512 bytes including Preamble and Carrier Extension in GMII mode). + * 0b0..No collision + * 0b1..Late collision is sensed + */ +#define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK (0x20U) +#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U) +/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this + * bit indicates that the transmission aborted after 16 successive collisions while attempting + * to transmit the current packet. + * 0b0..No collision + * 0b1..Excessive collision is sensed + */ +#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK (0x100U) +#define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT (8U) +/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 + * bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the + * MAC_CONFIGURATION register. + * 0b0..No receive watchdog timeout + * 0b1..Receive watchdog timed out + */ +#define ENET_QOS_MAC_RX_TX_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK) +/*! @} */ + +/*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */ +/*! @{ */ + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U) +/*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it + * receives the expected magic packet or remote wake-up packet. + * 0b0..Power down is disabled + * 0b1..Power down is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U) +/*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet. + * 0b0..Magic Packet is disabled + * 0b1..Magic Packet is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U) +/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is + * generated when the MAC receives a remote wake-up packet. + * 0b0..Remote wake-up packet is disabled + * 0b1..Remote wake-up packet is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U) +/*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management + * event is generated because of the reception of a magic packet. + * 0b0..No Magic packet is received + * 0b1..Magic packet is received + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U) +/*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power + * management event is generated because of the reception of a remote wake-up packet. + * 0b0..Remote wake-up packet is received + * 0b1..Remote wake-up packet is received + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U) +/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) + * address recognition is detected as a remote wake-up packet. + * 0b0..Global unicast is disabled + * 0b1..Global unicast is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U) +/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the + * MAC receiver drops all received frames until it receives the expected Wake-up frame. + * 0b0..Remote Wake-up Packet Forwarding is disabled + * 0b1..Remote Wake-up Packet Forwarding is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U) +/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when + * 4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter + * register pointer. + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U) +/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the + * remote wake-up packet filter register pointer is reset to 3'b000. + * 0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset + * 0b1..Remote Wake-Up Packet Filter Register Pointer is Reset + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK) +/*! @} */ + +/*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */ +/*! @{ */ + +#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U) +/*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter. */ +#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK) +/*! @} */ + +/*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */ +/*! @{ */ + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U) +/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has + * entered the LPI state because of the setting of the LPIEN bit. + * 0b0..Transmit LPI entry not detected + * 0b1..Transmit LPI entry detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U) +/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited + * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. + * 0b0..Transmit LPI exit not detected + * 0b1..Transmit LPI exit detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U) +/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received + * an LPI pattern and entered the LPI state. + * 0b0..Receive LPI entry not detected + * 0b1..Receive LPI entry detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U) +/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped + * receiving the LPI pattern on the GMII interface, exited the LPI state, and resumed the normal + * reception. + * 0b0..Receive LPI exit not detected + * 0b1..Receive LPI exit detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U) +/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the + * LPI pattern on the GMII interface. + * 0b0..Transmit LPI state not detected + * 0b1..Transmit LPI state detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U) +/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the GMII interface. + * 0b0..Receive LPI state not detected + * 0b1..Receive LPI state detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U) +/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. + * 0b0..LPI state is disabled + * 0b1..LPI state is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U) +/*! PLS - PHY Link Status This bit indicates the link status of the PHY. + * 0b0..link is down + * 0b1..link is okay (UP) + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U) +/*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or + * SMII Receive paths to be used for activating the LPI LS TIMER. + * 0b0..PHY Link Status is disabled + * 0b1..PHY Link Status is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U) +/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming + * out of the LPI mode on the Transmit side. + * 0b0..LPI Tx Automate is disabled + * 0b1..LPI Tx Automate is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U) +/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. + * 0b0..LPI Timer is disabled + * 0b1..LPI Timer is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U) +/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts + * sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. + * 0b0..LPI Tx Clock Stop is disabled + * 0b1..LPI Tx Clock Stop is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK) +/*! @} */ + +/*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */ +/*! @{ */ + +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU) +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U) +/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC + * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal + * transmission. + */ +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK) + +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U) +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U) +/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link + * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. + */ +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK) +/*! @} */ + +/*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */ +/*! @{ */ + +#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0xFFFF8U) +#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U) +/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI + * mode, after it has transmitted all the frames. + */ +#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK) +/*! @} */ + +/*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */ +/*! @{ */ + +#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU) +#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U) +/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. */ +#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK) +/*! @} */ + +/*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */ +/*! @{ */ + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U) +/*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission + * of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or + * SGMII port. + * 0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII + * 0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U) +/*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of + * configuration in the RGMII, SGMII, or SMII interface. + * 0b0..Link down + * 0b1..Link up + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U) +/*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link. + * 0b0..Half-duplex mode + * 0b1..Full-duplex mode + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U) +/*! LNKSPEED - Link Speed This bit indicates the current speed of the link. + * 0b00..2.5 MHz + * 0b01..25 MHz + * 0b10..125 MHz + * 0b11..Reserved + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U) +/*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0). + * 0b0..Link down + * 0b1..Link up + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK) +/*! @} */ + +/*! @name MAC_VERSION - MAC Version */ +/*! @{ */ + +#define ENET_QOS_MAC_VERSION_SNPSVER_MASK (0xFFU) +#define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT (0U) +/*! SNPSVER - Synopsys-defined Version */ +#define ENET_QOS_MAC_VERSION_SNPSVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK) + +#define ENET_QOS_MAC_VERSION_USERVER_MASK (0xFF00U) +#define ENET_QOS_MAC_VERSION_USERVER_SHIFT (8U) +/*! USERVER - User-defined Version (8'h10) */ +#define ENET_QOS_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK) +/*! @} */ + +/*! @name MAC_DEBUG - MAC Debug */ +/*! @{ */ + +#define ENET_QOS_MAC_DEBUG_RPESTS_MASK (0x1U) +#define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT (0U) +/*! RPESTS - MAC GMII Receive Protocol Engine Status When this bit is set, it indicates that the MAC + * GMII receive protocol engine is actively receiving data, and it is not in the Idle state. + * 0b0..MAC GMII Receive Protocol Engine Status not detected + * 0b1..MAC GMII Receive Protocol Engine Status detected + */ +#define ENET_QOS_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK) + +#define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK (0x6U) +#define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT (1U) +/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates + * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet + * Controller module. + */ +#define ENET_QOS_MAC_DEBUG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK) + +#define ENET_QOS_MAC_DEBUG_TPESTS_MASK (0x10000U) +#define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT (16U) +/*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that + * the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in + * the Idle state. + * 0b0..MAC GMII Transmit Protocol Engine Status not detected + * 0b1..MAC GMII Transmit Protocol Engine Status detected + */ +#define ENET_QOS_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK) + +#define ENET_QOS_MAC_DEBUG_TFCSTS_MASK (0x60000U) +#define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT (17U) +/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. + * 0b00..Idle state + * 0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over + * 0b10..Generating and transmitting a Pause control packet (in full-duplex mode) + * 0b11..Transferring input packet for transmission + */ +#define ENET_QOS_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK) +/*! @} */ + +/*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK (0x1U) +#define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT (0U) +/*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation + * 0b0..No 10 or 100 Mbps support + * 0b1..10 or 100 Mbps support + */ +#define ENET_QOS_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_NRVF_MASK (0x7U) +#define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT (0U) +/*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: + * 0b000..No Extended Rx VLAN Filters + * 0b001..4 Extended Rx VLAN Filters + * 0b010..8 Extended Rx VLAN Filters + * 0b011..16 Extended Rx VLAN Filters + * 0b100..24 Extended Rx VLAN Filters + * 0b101..32 Extended Rx VLAN Filters + * 0b110..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) +#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in + * bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: + * 0b00000..128 bytes + * 0b00001..256 bytes + * 0b00010..512 bytes + * 0b00011..1024 bytes + * 0b00100..2048 bytes + * 0b00101..4096 bytes + * 0b00110..8192 bytes + * 0b00111..16384 bytes + * 0b01000..32 KB + * 0b01001..64 KB + * 0b01010..128 KB + * 0b01011..256 KB + * 0b01100..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK (0xFU) +#define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT (0U) +/*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues: + * 0b0000..1 MTL Rx Queue + * 0b0001..2 MTL Rx Queues + * 0b0010..3 MTL Rx Queues + * 0b0011..4 MTL Rx Queues + * 0b0100..5 MTL Rx Queues + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK (0x2U) +#define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT (1U) +/*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation + * 0b0..No 1000 Mbps support + * 0b1..1000 Mbps support + */ +#define ENET_QOS_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK (0x4U) +#define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT (2U) +/*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected + * 0b0..No Half-duplex support + * 0b1..Half-duplex support + */ +#define ENET_QOS_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK (0x8U) +#define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT (3U) +/*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI, + * SGMII, or RTBI PHY interface option is selected + * 0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface) + * 0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface) + */ +#define ENET_QOS_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK (0x10U) +#define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT (4U) +/*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the + * Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected. + * 0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected + * 0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK (0x10U) +#define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT (4U) +/*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected + * 0b0..VLAN Hash Filter not selected + * 0b1..VLAN Hash Filter selected + */ +#define ENET_QOS_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK) + +#define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK (0x20U) +#define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT (5U) +/*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected. + * 0b0..Double VLAN option is not selected + * 0b1..Double VLAN option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK (0x20U) +#define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT (5U) +/*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected + * 0b0..SMA (MDIO) Interface not selected + * 0b1..SMA (MDIO) Interface selected + */ +#define ENET_QOS_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK (0x20U) +#define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT (5U) +/*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected. + * 0b0..Single Port RAM feature is not selected + * 0b1..Single Port RAM feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK (0x40U) +#define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT (6U) +/*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected + * 0b0..PMT Remote Wake-up Packet Enable option is not selected + * 0b1..PMT Remote Wake-up Packet Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) +#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) +/*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in + * bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: + * 0b00000..128 bytes + * 0b00001..256 bytes + * 0b00010..512 bytes + * 0b00011..1024 bytes + * 0b00100..2048 bytes + * 0b00101..4096 bytes + * 0b00110..8192 bytes + * 0b00111..16384 bytes + * 0b01000..32 KB + * 0b01001..64 KB + * 0b01010..128 KB + * 0b01011..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) +#define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT (6U) +/*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: + * 0b0000..1 MTL Tx Queue + * 0b0001..2 MTL Tx Queues + * 0b0010..3 MTL Tx Queues + * 0b0011..4 MTL Tx Queues + * 0b0100..5 MTL Tx Queues + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK (0x80U) +#define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT (7U) +/*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected + * 0b0..PMT Magic Packet Enable option is not selected + * 0b1..PMT Magic Packet Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK (0x100U) +#define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT (8U) +/*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected + * 0b0..RMON Module Enable option is not selected + * 0b1..RMON Module Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) +#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) +/*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected + * 0b0..ARP Offload Enable option is not selected + * 0b1..ARP Offload Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK (0x200U) +#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT (9U) +/*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the + * Broadcast/Multicast Packet Duplication feature is selected. + * 0b0..Broadcast/Multicast Packet Duplication feature is not selected + * 0b1..Broadcast/Multicast Packet Duplication feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK (0x400U) +#define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT (10U) +/*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible + * Programmable Receive Parser option is selected. + * 0b0..Flexible Receive Parser feature is not selected + * 0b1..Flexible Receive Parser feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK (0x1800U) +#define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT (11U) +/*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of + * bytes of the packet data to be Parsed by Flexible Receive Parser. + * 0b00..64 Bytes + * 0b01..128 Bytes + * 0b10..256 Bytes + * 0b11..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK) + +#define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK (0x800U) +#define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT (11U) +/*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. + * 0b0..One-Step Timestamping feature is not selected + * 0b1..One-Step Timestamping feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK (0x1000U) +#define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT (12U) +/*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. + * 0b0..PTP Offload feature is not selected + * 0b1..PTP Offload feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) +#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) +/*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels: + * 0b0000..1 MTL Rx Channel + * 0b0001..2 MTL Rx Channels + * 0b0010..3 MTL Rx Channels + * 0b0011..4 MTL Rx Channels + * 0b0100..5 MTL Rx Channels + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK (0x1000U) +#define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT (12U) +/*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected + * 0b0..IEEE 1588-2008 Timestamp Enable option is not selected + * 0b1..IEEE 1588-2008 Timestamp Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) +#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) +/*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected + * 0b0..IEEE 1588 High Word Register option is not selected + * 0b1..IEEE 1588 High Word Register option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK) + +#define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK (0x2000U) +#define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT (13U) +/*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient + * Ethernet (EEE) option is selected + * 0b0..Energy Efficient Ethernet Enable option is not selected + * 0b1..Energy Efficient Ethernet Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FRPES_MASK (0x6000U) +#define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT (13U) +/*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser + * Entries supported by Flexible Receive Parser. + * 0b00..64 Entries + * 0b01..128 Entries + * 0b10..256 Entries + * 0b11..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK (0xC000U) +#define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT (14U) +/*! ADDR64 - Address Width. + * 0b00..32 + * 0b01..40 + * 0b10..48 + * 0b11..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) +#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) +/*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit + * TCP/IP Checksum Insertion option is selected + * 0b0..Transmit Checksum Offload Enable option is not selected + * 0b1..Transmit Checksum Offload Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK (0x10000U) +#define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT (16U) +/*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected + * 0b0..DCB Feature is not selected + * 0b1..DCB Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK (0x10000U) +#define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT (16U) +/*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable + * Enhancements to Scheduling Traffic feature is selected. + * 0b0..Enable Enhancements to Scheduling Traffic feature is not selected + * 0b1..Enable Enhancements to Scheduling Traffic feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) +#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) +/*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected + * 0b0..Receive Checksum Offload Enable option is not selected + * 0b1..Receive Checksum Offload Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U) +#define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT (17U) +/*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5 + * 0b000..No Depth configured + * 0b001..64 + * 0b010..128 + * 0b011..256 + * 0b100..512 + * 0b101..1024 + * 0b110..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK (0x20000U) +#define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT (17U) +/*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected + * 0b0..Split Header Feature is not selected + * 0b1..Split Header Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK (0x7C0000U) +#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT (18U) +/*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is + * selected for Enable Additional 1-31 MAC Address Registers option + */ +#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK (0x40000U) +#define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT (18U) +/*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation + * Offloading for TCP/IP Packets option is selected + * 0b0..TCP Segmentation Offload Feature is not selected + * 0b1..TCP Segmentation Offload Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) +#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) +/*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: + * 0b0000..1 MTL Tx Channel + * 0b0001..2 MTL Tx Channels + * 0b0010..3 MTL Tx Channels + * 0b0011..4 MTL Tx Channels + * 0b0100..5 MTL Tx Channels + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) +#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) +/*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected + * 0b0..DMA Debug Registers option is not selected + * 0b1..DMA Debug Registers option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK) + +#define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK (0x100000U) +#define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT (20U) +/*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. + * 0b0..AV Feature is not selected + * 0b1..AV Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK (0x300000U) +#define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT (20U) +/*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the + * width of the Configured Time Interval Field + * 0b00..Width not configured + * 0b01..16 + * 0b10..20 + * 0b11..24 + */ +#define ENET_QOS_MAC_HW_FEAT_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK (0x200000U) +#define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT (21U) +/*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video + * Bridging option on Rx Side Only is selected. + * 0b0..Rx Side Only AV Feature is not selected + * 0b1..Rx Side Only AV Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK (0x800000U) +#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U) +/*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 + * MAC Address Registers (32-63) option is selected + * 0b0..MAC Addresses 32-63 Select option is not selected + * 0b1..MAC Addresses 32-63 Select option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_POUOST_MASK (0x800000U) +#define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT (23U) +/*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One + * step timestamp for PTP over UDP/IP feature is selected. + * 0b0..One Step for PTP over UDP/IP Feature is not selected + * 0b1..One Step for PTP over UDP/IP Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK) + +#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) +#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) +/*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table: + * 0b00..No hash table + * 0b01..64 + * 0b10..128 + * 0b11..256 + */ +#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK (0x1000000U) +#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U) +/*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 + * MAC Address Registers (64-127) option is selected + * 0b0..MAC Addresses 64-127 Select option is not selected + * 0b1..MAC Addresses 64-127 Select option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) +#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) +/*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs: + * 0b000..No PPS output + * 0b001..1 PPS output + * 0b010..2 PPS output + * 0b011..3 PPS output + * 0b100..4 PPS output + * 0b101..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) +#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) +/*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system + * time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected + * 0b00..Reserved + * 0b01..Internal + * 0b10..External + * 0b11..Both + */ +#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK (0x4000000U) +#define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT (26U) +/*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected. + * 0b0..Frame Preemption Enable feature is not selected + * 0b1..Frame Preemption Enable feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U) +#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U) +/*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: + * 0b0000..No L3 or L4 Filter + * 0b0001..1 L3 or L4 Filter + * 0b0010..2 L3 or L4 Filters + * 0b0011..3 L3 or L4 Filters + * 0b0100..4 L3 or L4 Filters + * 0b0101..5 L3 or L4 Filters + * 0b0110..6 L3 or L4 Filters + * 0b0111..7 L3 or L4 Filters + * 0b1000..8 L3 or L4 Filters + */ +#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK (0x8000000U) +#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT (27U) +/*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and + * VLAN Insertion on Tx option is selected + * 0b0..Source Address or VLAN Insertion Enable option is not selected + * 0b1..Source Address or VLAN Insertion Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U) +#define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT (27U) +/*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected. + * 0b0..Time Based Scheduling Enable feature is not selected + * 0b1..Time Based Scheduling Enable feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) +#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) +/*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration, + * this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. + * 0b000..GMII + * 0b001..RGMII + * 0b010..SGMII + * 0b011..TBI + * 0b100..RMII + * 0b101..RTBI + * 0b110..SMII + * 0b111..RevMII + */ +#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ASP_MASK (0x30000000U) +#define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT (28U) +/*! ASP - Automotive Safety Package Following are the encoding for the different Safety features + * 0b00..No Safety features selected + * 0b01..Only "ECC protection for external memory" feature is selected + * 0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature + * 0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature + */ +#define ENET_QOS_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK) + +#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) +#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) +/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: + * 0b000..No auxiliary input + * 0b001..1 auxiliary input + * 0b010..2 auxiliary input + * 0b011..3 auxiliary input + * 0b100..4 auxiliary input + * 0b101..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK) +/*! @} */ + +/* The count of ENET_QOS_MAC_HW_FEAT */ +#define ENET_QOS_MAC_HW_FEAT_COUNT (4U) + +/*! @name MAC_MDIO_ADDRESS - MDIO Address */ +/*! @{ */ + +#define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK (0x1U) +#define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT (0U) +/*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave. + * 0b0..GMII Busy is disabled + * 0b1..GMII Busy is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_GB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK (0x2U) +#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT (1U) +/*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. + * 0b0..Clause 45 PHY is disabled + * 0b1..Clause 45 PHY is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK (0x4U) +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U) +/*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII. + * 0b0..GMII Operation Command 0 is disabled + * 0b1..GMII Operation Command 0 is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK (0x8U) +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U) +/*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or + * RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read + * Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write + * and Read commands are valid. + * 0b0..GMII Operation Command 1 is disabled + * 0b1..GMII Operation Command 1 is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK (0x10U) +#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U) +/*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets + * before read, write, or post-read increment address packets. + * 0b0..Skip Address Packet is disabled + * 0b1..Skip Address Packet is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) +#define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT (8U) +/*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock + * according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC + * clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock + * = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26 + * - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz; + * MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR + * clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency + * applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1. + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK (0x7000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT (12U) +/*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles + * generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK (0x1F0000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT (16U) +/*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. */ +#define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK (0x3E00000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT (21U) +/*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. */ +#define ENET_QOS_MAC_MDIO_ADDRESS_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK (0x4000000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT (26U) +/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then + * the MAC informs the completion of a read or write command at the end of frame transfer (before + * the trailing clocks are transmitted). + * 0b0..Back to Back transactions disabled + * 0b1..Back to Back transactions enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK (0x8000000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT (27U) +/*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble + * and transmits MDIO frames with only 1 preamble bit. + * 0b0..Preamble Suppression disabled + * 0b1..Preamble Suppression enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK) +/*! @} */ + +/*! @name MAC_MDIO_DATA - MAC MDIO Data */ +/*! @{ */ + +#define ENET_QOS_MAC_MDIO_DATA_GD_MASK (0xFFFFU) +#define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT (0U) +/*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a + * Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a + * Management Write operation. + */ +#define ENET_QOS_MAC_MDIO_DATA_GD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK) + +#define ENET_QOS_MAC_MDIO_DATA_RA_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT (16U) +/*! RA - Register Address This field is valid only when C45E is set. */ +#define ENET_QOS_MAC_MDIO_DATA_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK) +/*! @} */ + +/*! @name MAC_CSR_SW_CTRL - CSR Software Control */ +/*! @{ */ + +#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U) +#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U) +/*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register + * fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to + * clear it. + * 0b0..Register Clear on Write 1 is disabled + * 0b1..Register Clear on Write 1 is enabled + */ +#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK) +/*! @} */ + +/*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */ +/*! @{ */ + +#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK (0x1U) +#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT (0U) +/*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled. + * 0b0..Tx Frame Preemption is disabled + * 0b1..Tx Frame Preemption is enabled + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK (0x2U) +#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT (1U) +/*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket. + * 0b0..Send Verify mPacket is disabled + * 0b1..Send Verify mPacket is enabled + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK (0x4U) +#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT (2U) +/*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket. + * 0b0..Send Respond mPacket is disabled + * 0b1..Send Respond mPacket is enabled + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK (0x8U) +#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U) +/*! S1_SET_0 - Reserved, Must be set to "0". */ +#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK (0x10000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT (16U) +/*! RVER - Received Verify Frame Set when a Verify mPacket is received. + * 0b0..Not received Verify Frame + * 0b1..Received Verify Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK (0x20000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT (17U) +/*! RRSP - Received Respond Frame Set when a Respond mPacket is received. + * 0b0..Not received Respond Frame + * 0b1..Received Respond Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK (0x40000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT (18U) +/*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field). + * 0b0..Not transmitted Verify Frame + * 0b1..transmitted Verify Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK (0x80000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT (19U) +/*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field). + * 0b0..Not transmitted Respond Frame + * 0b1..transmitted Respond Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK) +/*! @} */ + +/*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */ +/*! @{ */ + +#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT (0U) +/*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary + * rollover equivalent time of the PTP System Time in ns + */ +#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK) +/*! @} */ + +/*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */ +/*! @{ */ + +#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0U) +/*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. */ +#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK) +/*! @} */ + +/*! @name HIGH - MAC Address0 High..MAC Address63 High */ +/*! @{ */ + +#define ENET_QOS_HIGH_ADDRHI_MASK (0xFFFFU) +#define ENET_QOS_HIGH_ADDRHI_SHIFT (0U) +/*! ADDRHI - MAC ADDRESS12 [47:32] This field contains the upper 16 bits[47:32] of the thirteenth 6-byte MAC address. */ +#define ENET_QOS_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK) + +#define ENET_QOS_HIGH_DCS_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ +#define ENET_QOS_HIGH_DCS_SHIFT (16U) +/*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field + * contains the binary representation of the DMA Channel number to which an Rx packet whose DA + * matches the MAC Address(#i) content is routed. + */ +#define ENET_QOS_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ + +#define ENET_QOS_HIGH_MBC_MASK (0x3F000000U) +#define ENET_QOS_HIGH_MBC_SHIFT (24U) +/*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. */ +#define ENET_QOS_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK) + +#define ENET_QOS_HIGH_SA_MASK (0x40000000U) +#define ENET_QOS_HIGH_SA_SHIFT (30U) +/*! SA - Source Address When this bit is set, the MAC ADDRESS31[47:0] is used to compare with the SA + * fields of the received packet. + * 0b0..Compare with Destination Address + * 0b1..Compare with Source Address + */ +#define ENET_QOS_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK) + +#define ENET_QOS_HIGH_AE_MASK (0x80000000U) +#define ENET_QOS_HIGH_AE_SHIFT (31U) +/*! AE - Address Enable When this bit is set, the address filter module uses the thirteenth MAC address for perfect filtering. + * 0b0..INVALID : This bit must be always set to 1 + * 0b1..This bit is always set to 1 + */ +#define ENET_QOS_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK) +/*! @} */ + +/* The count of ENET_QOS_HIGH */ +#define ENET_QOS_HIGH_COUNT (64U) + +/*! @name LOW - MAC Address0 Low..MAC Address63 Low */ +/*! @{ */ + +#define ENET_QOS_LOW_ADDRLO_MASK (0xFFFFFFFFU) +#define ENET_QOS_LOW_ADDRLO_SHIFT (0U) +/*! ADDRLO - MAC ADDRESS12 [31:0] This field contains the lower 32 bits of thirteenth 6-byte MAC address. */ +#define ENET_QOS_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK) +/*! @} */ + +/* The count of ENET_QOS_LOW */ +#define ENET_QOS_LOW_COUNT (64U) + +/*! @name MAC_MMC_CONTROL - MMC Control */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK (0x1U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT (0U) +/*! CNTRST - Counters Reset When this bit is set, all counters are reset. + * 0b0..Counters are not reset + * 0b1..All counters are reset + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK (0x2U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U) +/*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. + * 0b0..Counter Stop Rollover is disabled + * 0b1..Counter Stop Rollover is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK (0x4U) +#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT (2U) +/*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). + * 0b0..Reset on Read is disabled + * 0b1..Reset on Read is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK (0x8U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U) +/*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. + * 0b0..MMC Counter Freeze is disabled + * 0b1..MMC Counter Freeze is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK (0x10U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT (4U) +/*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost + * full or almost half according to the CNTPRSTLVL bit. + * 0b0..Counters Preset is disabled + * 0b1..Counters Preset is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U) +/*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. + * 0b0..Full-Half Preset is disabled + * 0b1..Full-Half Preset is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK (0x100U) +#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT (8U) +/*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit. + * 0b0..Update MMC Counters for Dropped Broadcast Packets is disabled + * 0b1..Update MMC Counters for Dropped Broadcast Packets is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U) +/*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the + * rxpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U) +/*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the + * rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U) +/*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the + * rxoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U) +/*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the + * rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U) +/*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the + * rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U) +/*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the + * rxcrcerror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U) +/*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when + * the rxalignmenterror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U) +/*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the + * rxrunterror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Runt Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Runt Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U) +/*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the + * rxjabbererror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U) +/*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when + * the rxundersize_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U) +/*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the + * rxoversize_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U) +/*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set + * when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U) +/*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit + * is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U) +/*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U) +/*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U) +/*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U) +/*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status + * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U) +/*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the + * rxunicastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U) +/*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the + * rxlengtherror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Length Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U) +/*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status. + * 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U) +/*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the + * rxpausepackets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Pause Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Pause Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U) +/*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the + * rxfifooverflow counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected + * 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U) +/*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the + * rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U) +/*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the + * rxwatchdog error counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U) +/*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the + * rxrcverror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U) +/*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the + * rxctrlpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Control Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Control Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U) +/*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the + * Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected + * 0b1..MMC Receive LPI microsecond Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U) +/*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the + * Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI transition Counter Interrupt Status not detected + * 0b1..MMC Receive LPI transition Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U) +/*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the + * txoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U) +/*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the + * txpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U) +/*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the + * txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U) +/*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the + * txmulticastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U) +/*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set + * when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U) +/*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it + * reaches the maximum value. + * 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U) +/*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U) +/*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U) +/*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status + * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U) +/*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status + * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or + * the maximum value. + * 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U) +/*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when + * the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U) +/*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when + * the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U) +/*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when + * the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U) +/*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when + * the txunderflowerror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U) +/*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set + * when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U) +/*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is + * set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U) +/*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the + * txdeferred counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U) +/*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when + * the txlatecol counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U) +/*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set + * when the txexesscol counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U) +/*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the + * txcarriererror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U) +/*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the + * txoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Octet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U) +/*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the + * txpacketcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U) +/*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set + * when the txexcessdef counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U) +/*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the + * txpausepacketserror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Pause Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U) +/*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the + * txvlanpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U) +/*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when + * the txoversize_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U) +/*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the + * Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected + * 0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U) +/*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the + * Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI transition Counter Interrupt Status not detected + * 0b1..MMC Transmit LPI transition Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U) +/*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U) +/*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U) +/*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt + * when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U) +/*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U) +/*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U) +/*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U) +/*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxalignmenterror counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U) +/*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt + * when the rxrunterror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U) +/*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U) +/*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U) +/*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U) +/*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U) +/*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U) +/*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U) +/*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U) +/*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the + * maximum value or the maximum value. + * 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U) +/*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask. + * 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U) +/*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U) +/*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U) +/*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U) +/*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt + * when the rxpausepackets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U) +/*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U) +/*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U) +/*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U) +/*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U) +/*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U) +/*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the + * interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled + * 0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U) +/*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the + * interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI transition counter interrupt Mask is disabled + * 0b1..MMC Receive LPI transition counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U) +/*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U) +/*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U) +/*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U) +/*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U) +/*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U) +/*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U) +/*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U) +/*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U) +/*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the + * maximum value or the maximum value. + * 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U) +/*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the + * maximum value or the maximum value. + * 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U) +/*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U) +/*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U) +/*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U) +/*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txunderflowerror counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U) +/*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U) +/*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U) +/*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U) +/*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U) +/*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U) +/*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txcarriererror counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U) +/*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt + * when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U) +/*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt + * when the txpacketcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U) +/*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U) +/*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U) +/*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U) +/*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U) +/*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the + * interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled + * 0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U) +/*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the + * interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI transition counter interrupt Mask is disabled + * 0b1..MMC Transmit LPI transition counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK) +/*! @} */ + +/*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U) +/*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted, + * exclusive of preamble and retried bytes, in good and bad packets. + */ +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U) +/*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets + * transmitted, exclusive of retried packets. + */ +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U) +/*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted. */ +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK) +/*! @} */ + +/*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U) +/*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted. */ +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK) +/*! @} */ + +/*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U) +/*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets + * transmitted with length 64 bytes, exclusive of preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U) +/*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and + * bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble + * and retried packets. + */ +#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U) +/*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and + * bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U) +/*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and + * bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U) +/*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good + * and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U) +/*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good + * and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U) +/*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted. */ +#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U) +/*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted. */ +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U) +/*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted. */ +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U) +/*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error. */ +#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK) +/*! @} */ + +/*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U) +/*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully + * transmitted packets after a single collision in the half-duplex mode. + */ +#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK) +/*! @} */ + +/*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U) +/*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully + * transmitted packets after multiple collisions in the half-duplex mode. + */ +#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK) +/*! @} */ + +/*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U) +/*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after + * a deferral in the half-duplex mode. + */ +#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK) +/*! @} */ + +/*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U) +/*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error. */ +#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK) +/*! @} */ + +/*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U) +/*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted + * because of excessive (16) collision errors. + */ +#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK) +/*! @} */ + +/*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U) +/*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of + * carrier sense error (no carrier or loss of carrier). + */ +#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK) +/*! @} */ + +/*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U) +/*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets. */ +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK) +/*! @} */ + +/*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U) +/*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted. */ +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK) +/*! @} */ + +/*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U) +/*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted + * because of excessive deferral error (deferred for more than two max-sized packet times). + */ +#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK) +/*! @} */ + +/*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U) +/*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted. */ +#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK) +/*! @} */ + +/*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U) +/*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted. */ +#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK) +/*! @} */ + +/*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U) +/*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without + * errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets; + * 2000 bytes if enabled in S2KP bit of the CONFIGURATION register). + */ +#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK) +/*! @} */ + +/*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U) +/*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received. */ +#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U) +/*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive + * of preamble, in good and bad packets. + */ +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U) +/*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets. */ +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK) +/*! @} */ + +/*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U) +/*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received. */ +#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK) +/*! @} */ + +/*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U) +/*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received. */ +#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK) +/*! @} */ + +/*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U) +/*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error. */ +#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK) +/*! @} */ + +/*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U) +/*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. */ +#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK) +/*! @} */ + +/*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U) +/*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt + * (length less than 64 bytes and CRC error) error. + */ +#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK) +/*! @} */ + +/*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U) +/*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received + * with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC + * error. + */ +#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK) +/*! @} */ + +/*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U) +/*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with + * length less than 64 bytes, without any errors. + */ +#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK) +/*! @} */ + +/*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U) +/*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without + * errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged + * packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register). + */ +#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK) +/*! @} */ + +/*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U) +/*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad + * packets received with length 64 bytes, exclusive of the preamble. + */ +#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U) +/*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and + * bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble. + */ +#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U) +/*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and + * bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U) +/*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and + * bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U) +/*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good + * and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U) +/*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad + * packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U) +/*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received. */ +#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK) +/*! @} */ + +/*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U) +/*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with + * length error (Length Type field not equal to packet size), for all packets with valid length field. + */ +#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK) +/*! @} */ + +/*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U) +/*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received + * with length field not equal to the valid packet size (greater than 1,500 but less than 1,536). + */ +#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK) +/*! @} */ + +/*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U) +/*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received. */ +#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK) +/*! @} */ + +/*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U) +/*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow. */ +#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK) +/*! @} */ + +/*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U) +/*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received. */ +#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U) +/*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with + * error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when + * JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and + * WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in + * MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register). + */ +#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK) +/*! @} */ + +/*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U) +/*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with + * Receive error or Packet Extension error on the GMII interface. + */ +#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK) +/*! @} */ + +/*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U) +/*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received. */ +#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK) +/*! @} */ + +/*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U) +/*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. */ +#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK) +/*! @} */ + +/*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U) +/*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. */ +#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK) +/*! @} */ + +/*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U) +/*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. */ +#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK) +/*! @} */ + +/*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U) +/*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. */ +#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK) +/*! @} */ + +/*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U) +/*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U) +/*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U) +/*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U) +/*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U) +/*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U) +/*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U) +/*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U) +/*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U) +/*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U) +/*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U) +/*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U) +/*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U) +/*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U) +/*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U) +/*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U) +/*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U) +/*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U) +/*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U) +/*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U) +/*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U) +/*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U) +/*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U) +/*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U) +/*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U) +/*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U) +/*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U) +/*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U) +/*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U) +/*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the + * rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U) +/*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set + * when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U) +/*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set + * when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U) +/*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when + * the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U) +/*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit + * is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U) +/*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the + * rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U) +/*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set + * when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U) +/*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set + * when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U) +/*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the + * rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U) +/*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the + * rxudp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U) +/*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the + * rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U) +/*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the + * rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U) +/*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the + * rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U) +/*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the + * rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U) +/*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the + * rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U) +/*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when + * the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U) +/*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when + * the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U) +/*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when + * the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U) +/*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit + * is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U) +/*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the + * rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U) +/*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when + * the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U) +/*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when + * the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U) +/*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the + * rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U) +/*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the + * rxudp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U) +/*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the + * rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U) +/*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the + * rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U) +/*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the + * rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U) +/*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the + * rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U) +/*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. */ +#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U) +/*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams + * received with header (checksum, length, or version mismatch) errors. + */ +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U) +/*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets + * received that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U) +/*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation. */ +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U) +/*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good + * IPv4 datagrams received that had a UDP payload with checksum disabled. + */ +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U) +/*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload. */ +#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U) +/*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams + * received with header (length or version mismatch) errors. + */ +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U) +/*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets + * received that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U) +/*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. */ +#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U) +/*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received + * whose UDP payload has a checksum error. + */ +#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U) +/*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload. */ +#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U) +/*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received + * whose TCP payload has a checksum error. + */ +#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U) +/*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload. */ +#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U) +/*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams + * received whose ICMP payload has a checksum error. + */ +#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U) +/*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 + * datagrams encapsulating TCP, UDP, or ICMP data. + */ +#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U) +/*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received + * in IPv4 datagrams with header errors (checksum, length, version mismatch). + */ +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U) +/*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 + * datagrams that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U) +/*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. */ +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U) +/*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes + * received in a UDP segment that had the UDP checksum disabled. + */ +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U) +/*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 + * datagrams encapsulating TCP, UDP, or ICMP data. + */ +#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U) +/*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received + * in IPv6 datagrams with header errors (length, version mismatch). + */ +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U) +/*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 + * datagrams that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U) +/*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. */ +#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U) +/*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. */ +#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U) +/*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. */ +#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U) +/*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. */ +#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U) +/*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. */ +#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U) +/*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. */ +#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U) +/*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the + * Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Tx FPE Fragment Counter Interrupt status not detected + * 0b1..MMC Tx FPE Fragment Counter Interrupt status detected + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U) +/*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr + * counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Tx Hold Request Counter Interrupt Status not detected + * 0b1..MMC Tx Hold Request Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U) +/*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when + * the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U) +/*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt + * when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U) +/*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has + * been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled + * during FPE Enabled configuration. + */ +#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U) +/*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. */ +#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U) +/*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the + * Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected + * 0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U) +/*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the + * Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected + * 0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U) +/*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the + * Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected + * 0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U) +/*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the + * Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected + * 0b1..MMC Rx FPE Fragment Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U) +/*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the + * interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled + * 0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U) +/*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt + * when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled + * 0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U) +/*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt + * when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled + * 0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U) +/*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the + * Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled + * 0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U) +/*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with + * reassembly errors on the Receiver, due to mismatch in the Fragment Count value. + */ +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U) +/*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to + * unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there + * was no preceding preempted frame. + */ +#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U) +/*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were + * successfully reassembled and delivered to MAC. + */ +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U) +/*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received + * due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE + * Enabled configuration. + */ +#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U) +/*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U) +/*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U) +/*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U) +/*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U) +/*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U) +/*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U) +/*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U) +/*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U) +/*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U) +/*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U) +/*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U) +/*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U) +/*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U) +/*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U) +/*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U) +/*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U) +/*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U) +/*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U) +/*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U) +/*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U) +/*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U) +/*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U) +/*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U) +/*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U) +/*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U) +/*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U) +/*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U) +/*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U) +/*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U) +/*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U) +/*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U) +/*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U) +/*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U) +/*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U) +/*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN1 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U) +/*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM1 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U) +/*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U) +/*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U) +/*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U) +/*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U) +/*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U) +/*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U) +/*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U) +/*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U) +/*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U) +/*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U) +/*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U) +/*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U) +/*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U) +/*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U) +/*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U) +/*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U) +/*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U) +/*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U) +/*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN2 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U) +/*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN2 bit is reset and the L4DPM2 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U) +/*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U) +/*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U) +/*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U) +/*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U) +/*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U) +/*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U) +/*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U) +/*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U) +/*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U) +/*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U) +/*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U) +/*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U) +/*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U) +/*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U) +/*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U) +/*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U) +/*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U) +/*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U) +/*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN3 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U) +/*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN3 bit is reset and the L4DPM3 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U) +/*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U) +/*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U) +/*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U) +/*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U) +/*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U) +/*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U) +/*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U) +/*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U) +/*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U) +/*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U) +/*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U) +/*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U) +/*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U) +/*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U) +/*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U) +/*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U) +/*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U) +/*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U) +/*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN4 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U) +/*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN4 bit is reset and the L4DPM4 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U) +/*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U) +/*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U) +/*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U) +/*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U) +/*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U) +/*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U) +/*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U) +/*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U) +/*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U) +/*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U) +/*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U) +/*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U) +/*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U) +/*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U) +/*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U) +/*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U) +/*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U) +/*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U) +/*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN5 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U) +/*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN5 bit is reset and the L4DPM5 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U) +/*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U) +/*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U) +/*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U) +/*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U) +/*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U) +/*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U) +/*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U) +/*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U) +/*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U) +/*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U) +/*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U) +/*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U) +/*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U) +/*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U) +/*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U) +/*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U) +/*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U) +/*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U) +/*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN6 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U) +/*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN6 bit is reset and the L4DPM6 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U) +/*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U) +/*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U) +/*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U) +/*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U) +/*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U) +/*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U) +/*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U) +/*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U) +/*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U) +/*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U) +/*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U) +/*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U) +/*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U) +/*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U) +/*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U) +/*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U) +/*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U) +/*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U) +/*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN7 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U) +/*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN7 bit is reset and the L4DPM7 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U) +/*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U) +/*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U) +/*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U) +/*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK) +/*! @} */ + +/*! @name MAC_INDIR_ACCESS_CTRL - MAC_INDIR_ACCESS_CTRL */ +/*! @{ */ + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_MASK (0x1U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_SHIFT (0U) +/*! OB - Operation Busy */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_MASK (0x2U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_SHIFT (1U) +/*! COM - Command type. Indicates the register access type. + * 0b0..Indicates a write operation + * 0b1..Indicates a read operation + */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_MASK (0x20U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_SHIFT (5U) +/*! AUTO - Auto increment enable + * 0b0..AOFF is not incremented automatically. Software should program the correct Address Offset for each access. + * 0b1..AOFF is incremented by 1. Software should ensure not to cause a wrap condition. Byte wise read/write is + * not supported when auto increment is enabled. + */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_MASK (0xFF00U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_SHIFT (8U) +/*! AOFF - Address Offset */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_MASK (0xF0000U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_SHIFT (16U) +/*! MSEL - Mode Select */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_MASK) +/*! @} */ + +/*! @name MAC_INDIR_ACCESS_DATA - MAC_INDIR_ACCESS_DATA */ +/*! @{ */ + +#define ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_SHIFT (0U) +/*! DATA - This field contains data to read/write for Indirect address access associated with MAC_INDIR_ACCESS_CTRL register. */ +#define ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U) +/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. + * 0b0..Timestamp is disabled + * 0b1..Timestamp is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U) +/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. + * 0b0..Coarse method is used to update system timestamp + * 0b1..Fine method is used to update system timestamp + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U) +/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten) + * with the value specified in the MAC_System_Time_Seconds_Update and + * MAC_System_Time_Nanoseconds_Update registers. + * 0b0..Timestamp is not initialized + * 0b1..Timestamp is initialized + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U) +/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted) + * with the value specified in MAC_System_Time_Seconds_Update and + * MAC_System_Time_Nanoseconds_Update registers. + * 0b0..Timestamp is not updated + * 0b1..Timestamp is updated + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U) +/*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend + * register is updated in the PTP block for fine correction. + * 0b0..Addend Register is not updated + * 0b1..Addend Register is updated + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U) +/*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled. + * 0b0..Presentation Time Generation is disabled + * 0b1..Presentation Time Generation is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U) +/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is + * enabled for all packets received by the MAC. + * 0b0..Timestamp for All Packets disabled + * 0b1..Timestamp for All Packets enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) +/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low + * register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments + * the timestamp (High) seconds. + * 0b0..Timestamp Digital or Binary Rollover Control is disabled + * 0b1..Timestamp Digital or Binary Rollover Control is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U) +/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE + * 1588 version 2 format is used to process the PTP packets. + * 0b0..PTP Packet Processing for Version 2 Format is disabled + * 0b1..PTP Packet Processing for Version 2 Format is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U) +/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver + * processes the PTP packets encapsulated directly in the Ethernet packets. + * 0b0..Processing of PTP over Ethernet Packets is disabled + * 0b1..Processing of PTP over Ethernet Packets is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U) +/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC + * receiver processes the PTP packets encapsulated in IPv6-UDP packets. + * 0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled + * 0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U) +/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC + * receiver processes the PTP packets encapsulated in IPv4-UDP packets. + * 0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled + * 0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U) +/*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp + * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). + * 0b0..Timestamp Snapshot for Event Messages is disabled + * 0b1..Timestamp Snapshot for Event Messages is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U) +/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot + * is taken only for the messages that are relevant to the master node. + * 0b0..Snapshot for Messages Relevant to Master is disabled + * 0b1..Snapshot for Messages Relevant to Master is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U) +/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, + * decide the set of PTP packet types for which snapshot needs to be taken. + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U) +/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC + * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is + * directly sent over Ethernet. + * 0b0..MAC Address for PTP Packet Filtering is disabled + * 0b1..MAC Address for PTP Packet Filtering is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK (0x80000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U) +/*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set, + * the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum + * correct, for changes made to origin timestamp and/or correction field as part of one step timestamp + * operation. + * 0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled + * 0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U) +/*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit + * reference System Time input for the following: - To take the timestamp provided as status - To insert + * the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is + * enabled. + * 0b0..External System Time Input is disabled + * 0b1..External System Time Input is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U) +/*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier + * transmit timestamp status even if it is not read by the software. + * 0b0..Transmit Timestamp Status Mode is disabled + * 0b1..Transmit Timestamp Status Mode is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U) +/*! AV8021ASMEN - AV 802. + * 0b0..AV 802.1AS Mode is disabled + * 0b1..AV 802.1AS Mode is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK) +/*! @} */ + +/*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */ +/*! @{ */ + +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U) +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U) +/*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value, + * represented in nanoseconds multiplied by 2^8. + */ +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) + +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U) +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U) +/*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock + * cycle (of clk_ptp_i) with the contents of the sub-second register. + */ +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U) +/*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the + * System Time maintained by the MAC. + */ +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U) +/*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0. */ +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U) +/*! TSS - Timestamp Seconds The value in this field is the seconds part of the update. */ +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U) +/*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. */ +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) + +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U) +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U) +/*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. + * 0b0..Add time + * 0b1..Subtract time + */ +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U) +/*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the + * Accumulator register to achieve time synchronization. + */ +#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U) +/*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. */ +#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U) +/*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of + * the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. + * 0b0..Timestamp Seconds Overflow status not detected + * 0b1..Timestamp Seconds Overflow status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U) +/*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system + * time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and + * MAC_PPS0_Target_Time_Nanoseconds registers. + * 0b0..Timestamp Target Time Reached status not detected + * 0b1..Timestamp Target Time Reached status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U) +/*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. + * 0b0..Auxiliary Timestamp Trigger Snapshot status not detected + * 0b1..Auxiliary Timestamp Trigger Snapshot status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U) +/*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U) +/*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that + * the value of system time is greater than or equal to the value specified in the + * MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers. + * 0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS1 status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U) +/*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U) +/*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that + * the value of system time is greater than or equal to the value specified in the + * MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers. + * 0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS2 status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U) +/*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U) +/*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates + * that the value of system time is greater than or equal to the value specified in the + * MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers. + * 0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS3 status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U) +/*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U) +/*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop + * transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in + * the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers. + * 0b0..Tx Timestamp Status Interrupt status not detected + * 0b1..Tx Timestamp Status Interrupt status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U) +/*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary + * trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U) +/*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary + * timestamp snapshot FIFO is full and external trigger was set. + * 0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected + * 0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U) +/*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK) +/*! @} */ + +/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U) +/*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field + * of the Transmit packet's captured timestamp. + */ +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) + +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U) +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U) +/*! TXTSSMIS - Transmit Timestamp Status Missed + * 0b0..Transmit Timestamp Status Missed status not detected + * 0b1..Transmit Timestamp Status Missed status detected + */ +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK) +/*! @} */ + +/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U) +/*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds + * field of Transmit packet's captured timestamp. + */ +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK) +/*! @} */ + +/*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */ +/*! @{ */ + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U) +/*! ATSFC - Auxiliary Snapshot FIFO Clear + * 0b0..Auxiliary Snapshot FIFO Clear is disabled + * 0b1..Auxiliary Snapshot FIFO Clear is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U) +/*! ATSEN0 - Auxiliary Snapshot 0 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U) +/*! ATSEN1 - Auxiliary Snapshot 1 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U) +/*! ATSEN2 - Auxiliary Snapshot 2 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U) +/*! ATSEN3 - Auxiliary Snapshot 3 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK) +/*! @} */ + +/*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U) +/*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. */ +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK) +/*! @} */ + +/*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U) +/*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */ +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U) +/*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - Timestamp Egress Asymmetry Correction */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U) +/*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) +/*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as + * defined by the Ingress Correction expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) +/*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path + * correction value as defined by the Egress Correction expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U) +/*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds + * part of the ingress path correction value as defined by the "Ingress Correction" expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U) +/*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds + * part of the egress path correction value as defined by the "Egress Correction" expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U) +/*! ITLSNS - Ingress Timestamp Latency, in nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U) +/*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U) +/*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U) +/*! ETLNS - Egress Timestamp Latency, in nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) +/*! @} */ + +/*! @name MAC_PPS_CONTROL - PPS Control */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U) +/*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK (0x10U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT (4U) +/*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD. + * 0b0..Flexible PPS Output Mode is disabled + * 0b1..Flexible PPS Output Mode is enabled + */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U) +/*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time + * registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0 + * output signal: + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK (0x80U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT (7U) +/*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode. + * 0b0..0th PPS instance is enabled to operate in PPS mode + * 0b1..0th PPS instance is enabled to operate in MCGR mode + */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF00U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8U) +/*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U) +/*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time + * registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1 + * output signal. + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK (0x8000U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT (15U) +/*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode. + * 0b0..1st PPS instance is disabled to operate in PPS or MCGR mode + * 0b1..1st PPS instance is enabled to operate in PPS or MCGR mode + */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF0000U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16U) +/*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U) +/*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time + * registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2 + * output signal. + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK (0x800000U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT (23U) +/*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode. + * 0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode + * 0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode + */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF000000U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24U) +/*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U) +/*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time + * registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3 + * output signal. + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT (31U) +/*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK) +/*! @} */ + +/*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U) +/*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK) +/*! @} */ + +/*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U) +/*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) + +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U) +/*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK) +/*! @} */ + +/*! @name MAC_PPS0_INTERVAL - PPS0 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U) +/*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */ +#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK) +/*! @} */ + +/*! @name MAC_PPS0_WIDTH - PPS0 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0U) +/*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK) +/*! @} */ + +/*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U) +/*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK) +/*! @} */ + +/*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U) +/*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK) + +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U) +/*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK) +/*! @} */ + +/*! @name MAC_PPS1_INTERVAL - PPS1 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U) +/*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS1 signal output. */ +#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK) +/*! @} */ + +/*! @name MAC_PPS1_WIDTH - PPS1 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0U) +/*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK) +/*! @} */ + +/*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U) +/*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK) +/*! @} */ + +/*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U) +/*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK) + +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U) +/*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK) +/*! @} */ + +/*! @name MAC_PPS2_INTERVAL - PPS2 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U) +/*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS2 signal output. */ +#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK) +/*! @} */ + +/*! @name MAC_PPS2_WIDTH - PPS2 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0U) +/*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK) +/*! @} */ + +/*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U) +/*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK) +/*! @} */ + +/*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U) +/*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK) + +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U) +/*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK) +/*! @} */ + +/*! @name MAC_PPS3_INTERVAL - PPS3 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U) +/*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS3 signal output. */ +#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK) +/*! @} */ + +/*! @name MAC_PPS3_WIDTH - PPS3 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0U) +/*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK) +/*! @} */ + +/*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */ +/*! @{ */ + +#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK (0x1U) +#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT (0U) +/*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled. + * 0b0..PTP Offload feature is disabled + * 0b1..PTP Offload feature is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK (0x2U) +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT (1U) +/*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated + * periodically based on interval programmed or trigger from application, when the MAC is + * programmed to be in Clock Master mode. + * 0b0..Automatic PTP SYNC message is disabled + * 0b1..Automatic PTP SYNC message is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK (0x4U) +#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT (2U) +/*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message + * is generated periodically based on interval programmed or trigger from application, when the + * MAC is programmed to be in Peer-to-Peer Transparent mode. + * 0b0..Automatic PTP Pdelay_Req message is disabled + * 0b1..Automatic PTP Pdelay_Req message is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK (0x10U) +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U) +/*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted. + * 0b0..Automatic PTP SYNC message Trigger is disabled + * 0b1..Automatic PTP SYNC message Trigger is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U) +#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U) +/*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted. + * 0b0..Automatic PTP Pdelay_Req message Trigger is disabled + * 0b1..Automatic PTP Pdelay_Req message Trigger is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK (0x40U) +#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT (6U) +/*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay + * Request and Delay response is not generated for received SYNC and Delay request packet + * respectively, as required by the programmed mode. + * 0b0..PTO Delay Request/Response response generation is enabled + * 0b1..PTO Delay Request/Response response generation is disabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK (0x80U) +#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT (7U) +/*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay + * Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) + * request packet, as required by the programmed mode. + * 0b0..Peer Delay Response response generation is enabled + * 0b1..Peer Delay Response response generation is disabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_DN_MASK (0xFF00U) +#define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT (8U) +/*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating. */ +#define ENET_QOS_MAC_PTO_CONTROL_DN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK) +/*! @} */ + +/*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U) +/*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. */ +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK) +/*! @} */ + +/*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U) +/*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. */ +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK) +/*! @} */ + +/*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU) +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U) +/*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. */ +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK) +/*! @} */ + +/*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU) +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U) +/*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC + * message when the PTP node is Master. + */ +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK) + +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U) +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U) +/*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. + * 0b000..DelayReq generated for every received SYNC + * 0b001..DelayReq generated every alternate reception of SYNC + * 0b010..for every 4 SYNC messages + * 0b011..for every 8 SYNC messages + * 0b100..for every 16 SYNC messages + * 0b101..for every 32 SYNC messages + * 0b110..Reserved + */ +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK) + +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U) +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U) +/*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. */ +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK) +/*! @} */ + +/*! @name MTL_OPERATION_MODE - MTL Operation Mode */ +/*! @{ */ + +#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK (0x2U) +#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U) +/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. + * 0b0..Drop Transmit Status is disabled + * 0b1..Drop Transmit Status is enabled + */ +#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK (0x4U) +#define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT (2U) +/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. + * 0b0..Strict priority (SP) + * 0b1..Weighted Strict Priority (WSP) + */ +#define ENET_QOS_MTL_OPERATION_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK (0x60U) +#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U) +/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: + * 0b00..WRR algorithm + * 0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved + * 0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved + * 0b11..Strict priority algorithm + */ +#define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U) +#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U) +/*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0. + * 0b0..Counters Preset is disabled + * 0b1..Counters Preset is enabled + */ +#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK (0x200U) +#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U) +/*! CNTCLR - Counters Reset When this bit is set, all counters are reset. + * 0b0..Counters are not reset + * 0b1..All counters are reset + */ +#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK (0x8000U) +#define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT (15U) +/*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled. + * 0b0..Flexible Rx parser is disabled + * 0b1..Flexible Rx parser is enabled + */ +#define ENET_QOS_MTL_OPERATION_MODE_FRPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK) +/*! @} */ + +/*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */ +/*! @{ */ + +#define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK (0x1U) +#define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT (0U) +/*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled. + * 0b0..FIFO Debug Access is disabled + * 0b1..FIFO Debug Access is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_FDBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK (0x2U) +#define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT (1U) +/*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to + * the FIFO is read, write, and debug access. + * 0b0..Debug Mode Access to FIFO is disabled + * 0b1..Debug Mode Access to FIFO is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_DBGMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK) + +#define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK (0xCU) +#define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT (2U) +/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. + * 0b00..Byte 0 valid + * 0b01..Byte 0 and Byte 1 are valid + * 0b10..Byte 0, Byte 1, and Byte 2 are valid + * 0b11..All four bytes are valid + */ +#define ENET_QOS_MTL_DBG_CTL_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK (0x60U) +#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT (5U) +/*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. + * 0b00..Packet Data + * 0b01..Control Word/Normal Status + * 0b10..SOP Data/Last Status + * 0b11..EOP Data/EOP + */ +#define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK) + +#define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK (0x100U) +#define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT (8U) +/*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled. + * 0b0..Reset All Pointers is disabled + * 0b1..Reset All Pointers is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_RSTALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK) + +#define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK (0x200U) +#define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT (9U) +/*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the + * currently-selected FIFO are reset when FIFO Debug Access is enabled. + * 0b0..Reset Pointers of Selected FIFO is disabled + * 0b1..Reset Pointers of Selected FIFO is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_RSTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK) + +#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK (0x400U) +#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT (10U) +/*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled. + * 0b0..FIFO Read is disabled + * 0b1..FIFO Read is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK (0x800U) +#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT (11U) +/*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected + * FIFO when FIFO Debug Access is enabled. + * 0b0..FIFO Write is disabled + * 0b1..FIFO Write is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK (0x3000U) +#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT (12U) +/*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access: + * 0b00..Tx FIFO + * 0b01..Tx Status FIFO (only read access when SLVMOD is set) + * 0b10..TSO FIFO (cannot be accessed when SLVMOD is set) + * 0b11..Rx FIFO + */ +#define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK) + +#define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK (0x4000U) +#define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT (14U) +/*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is + * generated when EOP of received packet is written to the Rx FIFO. + * 0b0..Receive Packet Available Interrupt Status is disabled + * 0b1..Receive Packet Available Interrupt Status is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_PKTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK) + +#define ENET_QOS_MTL_DBG_CTL_STSIE_MASK (0x8000U) +#define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT (15U) +/*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is + * generated when Transmit status is available in slave mode. + * 0b0..Transmit Packet Available Interrupt Status is disabled + * 0b1..Transmit Packet Available Interrupt Status is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_STSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK) +/*! @} */ + +/*! @name MTL_DBG_STS - FIFO Debug Status */ +/*! @{ */ + +#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK (0x1U) +#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT (0U) +/*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the + * MAC and content of the following fields is not valid: - All other fields of this register - All + * fields of the MTL_FIFO_DEBUG_DATA register + * 0b0..FIFO Busy not detected + * 0b1..FIFO Busy detected + */ +#define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK) + +#define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK (0x6U) +#define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT (1U) +/*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO. + * 0b00..Packet Data + * 0b01..Control Word/Normal Status + * 0b10..SOP Data/Last Status + * 0b11..EOP Data/EOP + */ +#define ENET_QOS_MTL_DBG_STS_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK) + +#define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK (0x18U) +#define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT (3U) +/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. + * 0b00..Byte 0 valid + * 0b01..Byte 0 and Byte 1 are valid + * 0b10..Byte 0, Byte 1, and Byte 2 are valid + * 0b11..All four bytes are valid + */ +#define ENET_QOS_MTL_DBG_STS_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK) + +#define ENET_QOS_MTL_DBG_STS_PKTI_MASK (0x100U) +#define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT (8U) +/*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has + * written the EOP of received packet to the Rx FIFO. + * 0b0..Receive Packet Available Interrupt Status not detected + * 0b1..Receive Packet Available Interrupt Status detected + */ +#define ENET_QOS_MTL_DBG_STS_PKTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK) + +#define ENET_QOS_MTL_DBG_STS_STSI_MASK (0x200U) +#define ENET_QOS_MTL_DBG_STS_STSI_SHIFT (9U) +/*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave + * mode Tx packet is transmitted, and the status is available in Tx Status FIFO. + * 0b0..Transmit Status Available Interrupt Status not detected + * 0b1..Transmit Status Available Interrupt Status detected + */ +#define ENET_QOS_MTL_DBG_STS_STSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK) + +#define ENET_QOS_MTL_DBG_STS_LOCR_MASK (0xFFFF8000U) +#define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT (15U) +/*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. */ +#define ENET_QOS_MTL_DBG_STS_LOCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK) +/*! @} */ + +/*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */ +/*! @{ */ + +#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU) +#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U) +/*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the + * data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO. + */ +#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK) +/*! @} */ + +/*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */ +/*! @{ */ + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U) +/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. + * 0b0..Queue 0 Interrupt status not detected + * 0b1..Queue 0 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U) +/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. + * 0b0..Queue 1 Interrupt status not detected + * 0b1..Queue 1 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK (0x4U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U) +/*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2. + * 0b0..Queue 2 Interrupt status not detected + * 0b1..Queue 2 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK (0x8U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U) +/*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3. + * 0b0..Queue 3 Interrupt status not detected + * 0b1..Queue 3 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK (0x10U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U) +/*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4. + * 0b0..Queue 4 Interrupt status not detected + * 0b1..Queue 4 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U) +/*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access. + * 0b0..Debug Interrupt status not detected + * 0b1..Debug Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U) +/*! ESTIS - EST (TAS- 802. + * 0b0..EST (TAS- 802.1Qbv) Interrupt status not detected + * 0b1..EST (TAS- 802.1Qbv) Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U) +/*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block. + * 0b0..MTL Rx Parser Interrupt status not detected + * 0b1..MTL Rx Parser Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK) +/*! @} */ + +/*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK (0x7U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U) +/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received + * in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q0DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK (0x10U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U) +/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 0 disabled for DA-based DMA Channel Selection + * 0b1..Queue 0 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK (0x700U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U) +/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet + * in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q1DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK (0x1000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U) +/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 1 disabled for DA-based DMA Channel Selection + * 0b1..Queue 1 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK (0x70000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U) +/*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet + * in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q2DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK (0x100000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U) +/*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 2 disabled for DA-based DMA Channel Selection + * 0b1..Queue 2 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK (0x7000000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U) +/*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet + * in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q3DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK (0x10000000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U) +/*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit + * indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided + * in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, + * or the Ethernet DA address. + * 0b0..Queue 3 disabled for DA-based DMA Channel Selection + * 0b1..Queue 3 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK) +/*! @} */ + +/*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK (0x7U) +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U) +/*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received + * in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q4DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK (0x10U) +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U) +/*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 4 disabled for DA-based DMA Channel Selection + * 0b1..Queue 4 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK) +/*! @} */ + +/*! @name MTL_TBS_CTRL - Time Based Scheduling Control */ +/*! @{ */ + +#define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK (0x1U) +#define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT (0U) +/*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling + * is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the + * current list. + * 0b0..EST offset Mode is disabled + * 0b1..EST offset Mode is enabled + */ +#define ENET_QOS_MTL_TBS_CTRL_ESTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK) + +#define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK (0x2U) +#define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT (1U) +/*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid. + * 0b0..LEOS field is invalid + * 0b1..LEOS field is valid + */ +#define ENET_QOS_MTL_TBS_CTRL_LEOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK) + +#define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK (0x70U) +#define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT (4U) +/*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. */ +#define ENET_QOS_MTL_TBS_CTRL_LEGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK) + +#define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF00U) +#define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT (8U) +/*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the + * Launch time to compute the Launch Expiry time. + */ +#define ENET_QOS_MTL_TBS_CTRL_LEOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK) +/*! @} */ + +/*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_CONTROL_EEST_MASK (0x1U) +#define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT (0U) +/*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state. + * 0b0..EST is disabled + * 0b1..EST is enabled + */ +#define ENET_QOS_MTL_EST_CONTROL_EEST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK (0x2U) +#define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT (1U) +/*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list + * that it currently owns (SWOL) and the hardware should switch to the new list based on the new + * BTR. + * 0b0..Switch to S/W owned list is disabled + * 0b1..Switch to S/W owned list is enabled + */ +#define ENET_QOS_MTL_EST_CONTROL_SSWL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK (0x10U) +#define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT (4U) +/*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during + * Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register). + * 0b0..Drop frames during Frame Size Error + * 0b1..Do not Drop frames during Frame Size Error + */ +#define ENET_QOS_MTL_EST_CONTROL_DDBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK (0x20U) +#define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT (5U) +/*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due + * to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE + * field of this register) GCL iterations are dropped. + * 0b0..Do not Drop Frames causing Scheduling Error + * 0b1..Drop Frames causing Scheduling Error + */ +#define ENET_QOS_MTL_EST_CONTROL_DFBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK (0xC0U) +#define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT (6U) +/*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before + * reporting an HLBS error defined in EST_STATUS register. + * 0b00..4 iterations + * 0b01..8 iterations + * 0b10..16 iterations + * 0b11..32 iterations + */ +#define ENET_QOS_MTL_EST_CONTROL_LCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_TILS_MASK (0x700U) +#define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT (8U) +/*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the + * programmed Time Interval values used in the Gate Control Lists. + */ +#define ENET_QOS_MTL_EST_CONTROL_TILS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK (0xFFF000U) +#define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT (12U) +/*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is + * added to the current time to compensate for all the implementation pipeline delays such as the CDC + * sync delay, buffering delays, data path delays etc. + */ +#define ENET_QOS_MTL_EST_CONTROL_CTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK (0xFF000000U) +#define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT (24U) +/*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. */ +#define ENET_QOS_MTL_EST_CONTROL_PTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK) +/*! @} */ + +/*! @name MTL_EST_EXT_CONTROL - MTL_EST_EXT_CONTROL */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_MASK (0x3FU) +#define ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_SHIFT (0U) +/*! OVHD - Overhead Bytes Value */ +#define ENET_QOS_MTL_EST_EXT_CONTROL_OVHD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_SHIFT)) & ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_MASK) +/*! @} */ + +/*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_STATUS_SWLC_MASK (0x1U) +#define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT (0U) +/*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully + * switched to the SWOL, and the SWOL bit has been updated to that effect. + * 0b0..Switch to S/W owned list Complete not detected + * 0b1..Switch to S/W owned list Complete detected + */ +#define ENET_QOS_MTL_EST_STATUS_SWLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK) + +#define ENET_QOS_MTL_EST_STATUS_BTRE_MASK (0x2U) +#define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT (1U) +/*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed + * value is less than current time. + * 0b0..BTR Error not detected + * 0b1..BTR Error detected + */ +#define ENET_QOS_MTL_EST_STATUS_BTRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK) + +#define ENET_QOS_MTL_EST_STATUS_HLBF_MASK (0x4U) +#define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT (2U) +/*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more + * Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or + * equal to the duration needed for frame size (or frame fragment size when preemption is + * enabled) transmission. + * 0b0..Head-Of-Line Blocking due to Frame Size not detected + * 0b1..Head-Of-Line Blocking due to Frame Size detected + */ +#define ENET_QOS_MTL_EST_STATUS_HLBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK) + +#define ENET_QOS_MTL_EST_STATUS_HLBS_MASK (0x8U) +#define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT (3U) +/*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration + * and get scheduled even after 4 iterations of the GCL. + * 0b0..Head-Of-Line Blocking due to Scheduling not detected + * 0b1..Head-Of-Line Blocking due to Scheduling detected + */ +#define ENET_QOS_MTL_EST_STATUS_HLBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK) + +#define ENET_QOS_MTL_EST_STATUS_CGCE_MASK (0x10U) +#define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT (4U) +/*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the + * programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the + * Cycle Time (CTR). + * 0b0..Constant Gate Control Error not detected + * 0b1..Constant Gate Control Error detected + */ +#define ENET_QOS_MTL_EST_STATUS_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK) + +#define ENET_QOS_MTL_EST_STATUS_SWOL_MASK (0x80U) +#define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT (7U) +/*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and + * when "1" indicates the Gate Control list "1" is owned by the software. + * 0b0..Gate control list number "0" is owned by software + * 0b1..Gate control list number "1" is owned by software + */ +#define ENET_QOS_MTL_EST_STATUS_SWOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK) + +#define ENET_QOS_MTL_EST_STATUS_BTRL_MASK (0xF00U) +#define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT (8U) +/*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time + * =< New BTR + (N * New Cycle Time) becomes true. + */ +#define ENET_QOS_MTL_EST_STATUS_BTRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK) + +#define ENET_QOS_MTL_EST_STATUS_CGSN_MASK (0xF0000U) +#define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT (16U) +/*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list. */ +#define ENET_QOS_MTL_EST_STATUS_CGSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK) +/*! @} */ + +/*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK (0x1FU) +#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT (0U) +/*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced + * error/timeout described in HLBS field of status register. + */ +#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK) +/*! @} */ + +/*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU) +#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U) +/*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced + * error described in HLBF field of status register. + */ +#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK) +/*! @} */ + +/*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU) +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U) +/*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number + * indicated in HBFQ field of this register. + */ +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) + +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U) +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U) +/*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number) + * experiencing HLBF error (see HLBF field of status register). + */ +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK) +/*! @} */ + +/*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK (0x1U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT (0U) +/*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration + * change is successful and the hardware has switched to the new list. + * 0b0..Interrupt for Switch List is disabled + * 0b1..Interrupt for Switch List is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK (0x2U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT (1U) +/*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status. + * 0b0..Interrupt for BTR Error is disabled + * 0b1..Interrupt for BTR Error is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK (0x4U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT (2U) +/*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking + * due to Frame Size error occurs and is indicated in the status. + * 0b0..Interrupt for HLBF is disabled + * 0b1..Interrupt for HLBF is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK (0x8U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT (3U) +/*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking + * due to Scheduling issue and is indicated in the status. + * 0b0..Interrupt for HLBS is disabled + * 0b1..Interrupt for HLBS is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK (0x10U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT (4U) +/*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control + * Error occurs and is indicated in the status. + * 0b0..Interrupt for CGCE is disabled + * 0b1..Interrupt for CGCE is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK) +/*! @} */ + +/*! @name MTL_EST_GCL_CONTROL - EST GCL Control */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK (0x1U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT (0U) +/*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress. + * 0b0..Start Read/Write Op disabled + * 0b1..Start Read/Write Op enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK (0x2U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT (1U) +/*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation. + * 0b0..Write Operation + * 0b1..Read Operation + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK (0x4U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT (2U) +/*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL + * related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA. + * 0b0..Gate Control Related Registers are disabled + * 0b1..Gate Control Related Registers are enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK (0x10U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT (4U) +/*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and + * Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is + * used to determine which bank to use. + * 0b0..Debug Mode is disabled + * 0b1..Debug Mode is enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK (0x20U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT (5U) +/*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to + * Bank 0 (GCL0 and corresponding Time related registers). + * 0b0..R/W in debug mode should be directed to Bank 0 + * 0b1..R/W in debug mode should be directed to Bank 1 + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK (0x1FF00U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8U) +/*! ADDR - Gate Control List Address: (GCLA when GCRR is "0"). */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK (0x100000U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT (20U) +/*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL + * registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set. + * 0b0..ERR0 is disabled + * 0b1..ERR1 is enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U) +/*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register, + * enables the ECC error injection feature. + * 0b0..EST ECC Inject Error is disabled + * 0b1..EST ECC Inject Error is enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U) +/*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set, + * following are the errors inserted based on the value encoded in this field. + * 0b00..Insert 1 bit error + * 0b01..Insert 2 bit errors + * 0b10..Insert 3 bit errors + * 0b11..Insert 1 bit error in address field + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) +/*! @} */ + +/*! @name MTL_EST_GCL_DATA - EST GCL Data */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFFU) +#define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT (0U) +/*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register. */ +#define ENET_QOS_MTL_EST_GCL_DATA_GCD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK) +/*! @} */ + +/*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */ +/*! @{ */ + +#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3U) +#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0U) +/*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of + * bytes over 64 bytes required in non-final fragments of preempted frames. + */ +#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK) + +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK (0x1F00U) +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT (8U) +/*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as + * preemptable, when '0' Queue is classified as express. + */ +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK) + +#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK (0x10000000U) +#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT (28U) +/*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State. + * 0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State + * 0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State + */ +#define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK) +/*! @} */ + +/*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */ +/*! @{ */ + +#define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK (0xFFFFU) +#define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT (0U) +/*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to + * the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of + * transmission or any preemptable frames that are queued for transmission. + */ +#define ENET_QOS_MTL_FPE_ADVANCE_HADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK) + +#define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF0000U) +#define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT (16U) +/*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE + * to the MAC and the MAC being ready to resume transmission of preemptable frames, in the + * absence of there being any express frames available for transmission. + */ +#define ENET_QOS_MTL_FPE_ADVANCE_RADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK) +/*! @} */ + +/*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU) +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U) +/*! NVE - Number of valid entries in the Instruction table This control indicates the number of + * valid entries in the Instruction Memory. + */ +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK) + +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U) +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U) +/*! NPE - Number of parsable entries in the Instruction table This control indicates the number of + * parsable entries in the Instruction Memory. + */ +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK) + +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U) +/*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State + * and waiting for a new packet for processing. + * 0b0..RX Parser not in Idle state + * 0b1..RX Parser in Idle state + */ +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK) +/*! @} */ + +/*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U) +/*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction + * address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then + * this bit is set to 1. + * 0b0..Number of Valid Entries Overflow Interrupt Status not detected + * 0b1..Number of Valid Entries Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U) +/*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the + * number of parsed entries found to be more than NPE[] (Number of Parseable Entries in + * MTL_RXP_CONTROL register),then this bit is set to 1. + * 0b0..Number of Parsable Entries Overflow Interrupt Status not detected + * 0b1..Number of Parsable Entries Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U) +/*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's + * 'Frame Offset' found to be more than EOF offset, then then this bit is set. + * 0b0..Frame Offset Overflow Interrupt Status not detected + * 0b1..Frame Offset Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U) +/*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the + * packet by setting RF=1 in the instruction memory, then this bit is set to 1. + * 0b0..Packet Dropped due to RF Interrupt Status not detected + * 0b1..Packet Dropped due to RF Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U) +/*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled. + * 0b0..Number of Valid Entries Overflow Interrupt is disabled + * 0b1..Number of Valid Entries Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U) +/*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled. + * 0b0..Number of Parsable Entries Overflow Interrupt is disabled + * 0b1..Number of Parsable Entries Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U) +/*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled. + * 0b0..Frame Offset Overflow Interrupt is disabled + * 0b1..Frame Offset Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U) +/*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled. + * 0b0..Packet Drop due to RF Interrupt is disabled + * 0b1..Packet Drop due to RF Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK) +/*! @} */ + +/*! @name MTL_RXP_DROP_CNT - RXP Drop Count */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFFU) +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0U) +/*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. */ +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK) + +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U) +/*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the + * MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit. + * 0b0..Rx Parser Drop count overflow not occurred + * 0b1..Rx Parser Drop count overflow occurred + */ +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK) +/*! @} */ + +/*! @name MTL_RXP_ERROR_CNT - RXP Error Count */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFFU) +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0U) +/*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters + * following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry + * address > EOF data entry address The counter is cleared when the register is read. + */ +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK) + +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U) +/*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the + * MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit. + * 0b0..Rx Parser Error count overflow not occurred + * 0b1..Rx Parser Error count overflow occurred + */ +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK) +/*! @} */ + +/*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U) +/*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK) + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U) +/*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory. + * 0b0..Read operation to the Rx Parser Memory + * 0b1..Write operation to the Rx Parser Memory + */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK) + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U) +/*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it + * indicates to start the Read/Write operation from/to the Rx Parser Memory. + * 0b0..hardware not busy + * 0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory) + */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK) +/*! @} */ + +/*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U) +/*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK) +/*! @} */ + +/*! @name MTL_RXP_BYPASS_CNT - MTL_RXP_BYPASS_CNT */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_MASK (0x7FFFFFFFU) +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_SHIFT (0U) +/*! RXPBC - Rx Parser Bypass Count */ +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_SHIFT)) & ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_MASK) + +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_SHIFT (31U) +/*! RXPBCOF - Rx Parser bypass Counter Overflow Bit. Access restriction applies. Clears on read. Self-set to 1 on internal event. + * 0b0..Indicates that MTL_RXP_BYPASS_CNT[RXPBC] counter field has not crossed the maximum limit + * 0b1..Indicates that MTL_RXP_BYPASS_CNT[RXPBC] counter field has crossed the maximum limit + */ +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_SHIFT)) & ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_MASK) +/*! @} */ + +/*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) +#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) +/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. + * 0b0..Flush Transmit Queue is disabled + * 0b1..Flush Transmit Queue is enabled + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) +#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) +/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. + * 0b0..Transmit Store and Forward is disabled + * 0b1..Transmit Store and Forward is enabled + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) +#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) +/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0. + * 0b00..Not enabled + * 0b01..Enable in AV mode (Reserved in non-AV) + * 0b10..Enabled + * 0b11..Reserved + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) +#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) +/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. + * 0b000..32 + * 0b001..64 + * 0b010..96 + * 0b011..128 + * 0b100..192 + * 0b101..256 + * 0b110..384 + * 0b111..512 + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK (0x1F0000U) +#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) +/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_OP_MODE */ +#define ENET_QOS_MTL_TXQX_OP_MODE_COUNT (5U) + +/*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) +/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the + * controller because of Tx Queue Underflow. + */ +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) + +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) +/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue + * Underflow Packet Counter field overflows, that is, it has crossed the maximum count. + * 0b0..Overflow not detected for Underflow Packet Counter + * 0b1..Overflow detected for Underflow Packet Counter + */ +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_UNDRFLW */ +#define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT (5U) + +/*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) +#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) +/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it + * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because + * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue + * when PFC is enabled - Reception of 802. + * 0b0..Transmit Queue in Pause status is not detected + * 0b1..Transmit Queue in Pause status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) +#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) +/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: + * 0b00..Idle state + * 0b01..Read state (transferring data to the MAC transmitter) + * 0b10..Waiting for pending Tx Status from the MAC transmitter + * 0b11..Flushing the Tx queue because of the Packet Abort request from the MAC + */ +#define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) +#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) +/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx + * Queue Write Controller is active, and it is transferring the data to the Tx Queue. + * 0b0..MTL Tx Queue Write Controller status is not detected + * 0b1..MTL Tx Queue Write Controller status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) +#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) +/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue + * is not empty and some data is left for transmission. + * 0b0..MTL Tx Queue Not Empty status is not detected + * 0b1..MTL Tx Queue Not Empty status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) +#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) +/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. + * 0b0..MTL Tx Status FIFO Full status is not detected + * 0b1..MTL Tx Status FIFO Full status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) +#define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT (16U) +/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. */ +#define ENET_QOS_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U) +#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT (20U) +/*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current + * number of status in the Tx Status FIFO of this queue. + */ +#define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_DBG */ +#define ENET_QOS_MTL_TXQX_DBG_COUNT (5U) + +/*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) +#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) +/*! AVALG - AV Algorithm When Queue 4 is programmed for AV, this field configures the scheduling + * algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is + * selected for Queue 4 traffic. + * 0b0..CBS Algorithm is disabled + * 0b1..CBS Algorithm is enabled + */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK) + +#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) +#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) +/*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based + * shaper algorithm logic is not reset to zero when there is positive credit and no packet to + * transmit in Channel 4. + * 0b0..Credit Control is disabled + * 0b1..Credit Control is enabled + */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK) + +#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) +#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) +/*! SLC - Slot Count + * 0b000..1 slot + * 0b001..2 slots + * 0b010..4 slots + * 0b011..8 slots + * 0b100..16 slots + * 0b101..Reserved + */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT (5U) + +/*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) +#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) +/*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot. */ +#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_ETS_STAT */ +#define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT (5U) + +/*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) +/*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 + * traffic, this field contains the quantum value in bytes to be added to credit during every queue + * scanning cycle. + */ +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */ +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT (5U) + +/*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) +/*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the + * sendSlopeCredit value required for credit-based shaper algorithm for Queue 4. + */ +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */ +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT (5U) + +/*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) +#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) +/*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value + * required for the credit-based shaper algorithm. + */ +#define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_HI_CRDT */ +#define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT (5U) + +/*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) +#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) +/*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value + * required for the credit-based shaper algorithm. + */ +#define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_LO_CRDT */ +#define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT (5U) + +/*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) +/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue + * had an underflow while transmitting the packet. + * 0b0..Transmit Queue Underflow Interrupt Status not detected + * 0b1..Transmit Queue Underflow Interrupt Status detected + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) +/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. + * 0b0..Average Bits Per Slot Interrupt Status not detected + * 0b1..Average Bits Per Slot Interrupt Status detected + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U) +/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. + * 0b0..Transmit Queue Underflow Interrupt Status is disabled + * 0b1..Transmit Queue Underflow Interrupt Status is enabled + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U) +/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the + * sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. + * 0b0..Average Bits Per Slot Interrupt is disabled + * 0b1..Average Bits Per Slot Interrupt is enabled + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) +/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had + * an overflow while receiving the packet. + * 0b0..Receive Queue Overflow Interrupt Status not detected + * 0b1..Receive Queue Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U) +/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. + * 0b0..Receive Queue Overflow Interrupt is disabled + * 0b1..Receive Queue Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT (5U) + +/*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) +/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue + * (in bytes): The received packet is transferred to the application or DMA when the packet size + * within the MTL Rx queue is larger than the threshold. + * 0b00..64 + * 0b01..32 + * 0b10..96 + * 0b11..128 + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) +#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) +/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized + * good packets (packets with no error and length less than 64 bytes), including pad-bytes and + * CRC. + * 0b0..Forward Undersized Good Packets is disabled + * 0b1..Forward Undersized Good Packets is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) +#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) +/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status + * (CRC error, GMII_ER, watchdog timeout, or overflow). + * 0b0..Forward Error Packets is disabled + * 0b1..Forward Error Packets is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) +/*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet + * from the Rx queue only after the complete packet has been written to it, ignoring the RTC field + * of this register. + * 0b0..Receive Queue Store and Forward is disabled + * 0b1..Receive Queue Store and Forward is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) +#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) +/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC + * does not drop the packets which only have the errors detected by the Receive Checksum Offload + * engine. + * 0b0..Dropping of TCP/IP Checksum Error Packets is enabled + * 0b1..Dropping of TCP/IP Checksum Error Packets is disabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK (0x80U) +#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT (7U) +/*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation, + * based on the fill-level of Rx queue, is enabled. + * 0b0..Hardware Flow Control is disabled + * 0b1..Hardware Flow Control is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK (0xF00U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT (8U) +/*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control + * the threshold (fill-level of Rx queue) at which the flow control is activated: For more + * information on encoding for this field, see RFD. + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK (0x3C000U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT (14U) +/*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits + * control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after + * activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK (0x1F00000U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) +/*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_OP_MODE */ +#define ENET_QOS_MTL_RXQX_OP_MODE_COUNT (5U) + +/*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) +/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the + * DWC_ether_qos because of Receive queue overflow. + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) +/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue + * Overflow Packet Counter field crossed the maximum limit. + * 0b0..Overflow Counter overflow not detected + * 0b1..Overflow Counter overflow detected + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U) +/*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the + * DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK) + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U) +/*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue + * Missed Packet Counter crossed the maximum limit. + * 0b0..Missed Packet Counter overflow not detected + * 0b1..Missed Packet Counter overflow detected + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U) + +/*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) +#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) +/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL + * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. + * 0b0..MTL Rx Queue Write Controller Active Status not detected + * 0b1..MTL Rx Queue Write Controller Active Status detected + */ +#define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK) + +#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) +#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) +/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: + * 0b00..Idle state + * 0b01..Reading packet data + * 0b10..Reading packet status (or timestamp) + * 0b11..Flushing the packet data and status + */ +#define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK) + +#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) +#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) +/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: + * 0b00..Rx Queue empty + * 0b01..Rx Queue fill-level below flow-control deactivate threshold + * 0b10..Rx Queue fill-level above flow-control activate threshold + * 0b11..Rx Queue full + */ +#define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK) + +#define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) +#define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT (16U) +/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. */ +#define ENET_QOS_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_DBG */ +#define ENET_QOS_MTL_RXQX_DBG_COUNT (5U) + +/*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) +/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 4. */ +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK) + +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) +/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives + * the packet data to the ARI interface such that the entire packet data of currently-selected + * queue is transmitted before switching to other queue. + * 0b0..Receive Queue Packet Arbitration is disabled + * 0b1..Receive Queue Packet Arbitration is enabled + */ +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_CTRL */ +#define ENET_QOS_MTL_RXQX_CTRL_COUNT (5U) + +/*! @name DMA_MODE - DMA Bus Mode */ +/*! @{ */ + +#define ENET_QOS_DMA_MODE_SWR_MASK (0x1U) +#define ENET_QOS_DMA_MODE_SWR_SHIFT (0U) +/*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and + * all internal registers of the DMA, MTL, and MAC. + * 0b0..Software Reset is disabled + * 0b1..Software Reset is enabled + */ +#define ENET_QOS_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK) + +#define ENET_QOS_DMA_MODE_DSPW_MASK (0x100U) +#define ENET_QOS_DMA_MODE_DSPW_SHIFT (8U) +/*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted. + * 0b0..Descriptor Posted Write is disabled + * 0b1..Descriptor Posted Write is enabled + */ +#define ENET_QOS_DMA_MODE_DSPW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK) + +#define ENET_QOS_DMA_MODE_INTM_MASK (0x30000U) +#define ENET_QOS_DMA_MODE_INTM_SHIFT (16U) +/*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos. + * 0b00..See above description + * 0b01..See above description + * 0b10..See above description + * 0b11..Reserved + */ +#define ENET_QOS_DMA_MODE_INTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK) +/*! @} */ + +/*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */ +/*! @{ */ + +#define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK (0x1U) +#define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT (0U) +/*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers + * of specified lengths as given below. + * 0b0..Fixed Burst Length is disabled + * 0b1..Fixed Burst Length is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK (0x2U) +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT (1U) +/*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI + * master can select a burst length of 4 on the AXI interface. + * 0b0..No effect + * 0b1..AXI Burst Length 4 + */ +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK (0x4U) +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT (2U) +/*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI + * master can select a burst length of 8 on the AXI interface. + * 0b0..No effect + * 0b1..AXI Burst Length 8 + */ +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK (0x8U) +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT (3U) +/*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI + * master can select a burst length of 16 on the AXI interface. + * 0b0..No effect + * 0b1..AXI Burst Length 16 + */ +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK (0x400U) +#define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT (10U) +/*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state + * when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in + * the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register. + * 0b0..Automatic AXI LPI is disabled + * 0b1..Automatic AXI LPI is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_AALE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) +#define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT (12U) +/*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs + * address-aligned burst transfers on Read and Write channels. + * 0b0..Address-Aligned Beats is disabled + * 0b1..Address-Aligned Beats is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK (0x2000U) +#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT (13U) +/*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers + * performed by the EQOS-AXI master do not cross 1 KB boundary. + * 0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled + * 0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U) +#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U) +/*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. */ +#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U) +#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U) +/*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum + * outstanding request on the AXI write interface. + */ +#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U) +#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U) +/*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables + * the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet + * is received. + * 0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled + * 0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK (0x80000000U) +#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT (31U) +/*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported + * by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock + * controller. + * 0b0..Low Power Interface (LPI) is disabled + * 0b1..Low Power Interface (LPI) is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK) +/*! @} */ + +/*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */ +/*! @{ */ + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) +/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. + * 0b0..DMA Channel 0 Interrupt Status not detected + * 0b1..DMA Channel 0 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) +/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. + * 0b0..DMA Channel 1 Interrupt Status not detected + * 0b1..DMA Channel 1 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U) +/*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. + * 0b0..DMA Channel 2 Interrupt Status not detected + * 0b1..DMA Channel 2 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U) +/*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. + * 0b0..DMA Channel 3 Interrupt Status not detected + * 0b1..DMA Channel 3 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U) +/*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. + * 0b0..DMA Channel 4 Interrupt Status not detected + * 0b1..DMA Channel 4 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) +/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL. + * 0b0..MTL Interrupt Status not detected + * 0b1..MTL Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) +/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC. + * 0b0..MAC Interrupt Status not detected + * 0b1..MAC Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK) +/*! @} */ + +/*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */ +/*! @{ */ + +#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U) +#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) +/*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the + * AXI master is active, and it is transferring data. + * 0b0..AXI Master Write Channel or AHB Master Status not detected + * 0b1..AXI Master Write Channel or AHB Master Status detected + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK (0x2U) +#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U) +/*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of + * the AXI master is active, and it is transferring the data. + * 0b0..AXI Master Read Channel Status not detected + * 0b1..AXI Master Read Channel Status detected + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) +/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) +/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) +/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) +/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK (0xF000000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT (24U) +/*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK (0xF0000000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT (28U) +/*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK) +/*! @} */ + +/*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */ +/*! @{ */ + +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK (0xFU) +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT (0U) +/*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK (0xF0U) +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT (4U) +/*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK (0xF00U) +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT (8U) +/*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK (0xF000U) +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT (12U) +/*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK) +/*! @} */ + +/*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */ +/*! @{ */ + +#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU) +#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U) +/*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait + * for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 + * clock cycles + */ +#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL0 - DMA_TBS_CTRL0 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL0_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL0_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL0_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL0_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL0_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL0_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL0_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL0_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL0_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL0_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL0_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL0_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL0_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL0_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL0_FTOS_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL1 - DMA_TBS_CTRL1 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL1_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL1_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL1_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL1_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL1_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL1_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL1_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL1_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL1_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL1_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL1_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL1_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL1_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL1_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL1_FTOS_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL2 - DMA_TBS_CTRL2 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL2_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL2_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL2_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL2_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL2_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL2_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL2_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL2_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL2_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL2_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL2_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL2_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL2_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL2_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL2_FTOS_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL3 - DMA_TBS_CTRL3 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL3_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL3_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL3_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL3_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL3_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL3_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL3_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL3_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL3_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL3_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL3_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL3_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL3_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL3_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL3_FTOS_MASK) +/*! @} */ + +/*! @name DMA_CHX_CTRL - DMA Channel 0 Control..Channel 4 Control */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) +#define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT (16U) +/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in + * DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times. + * 0b0..8xPBL mode is disabled + * 0b1..8xPBL mode is enabled + */ +#define ENET_QOS_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK) + +#define ENET_QOS_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) +#define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT (18U) +/*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on + * the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. + */ +#define ENET_QOS_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CTRL */ +#define ENET_QOS_DMA_CHX_CTRL_COUNT (5U) + +/*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK (0x1U) +#define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT (0U) +/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. + * 0b0..Stop Transmission Command + * 0b1..Start Transmission Command + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) +#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) +/*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second + * packet of the Transmit data even before the status for the first packet is obtained. + * 0b0..Operate on Second Packet disabled + * 0b1..Operate on Second Packet enabled + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT (15U) +/*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of + * locations in the MTL before initiating a transfer. + * 0b0..Ignore PBL Requirement is disabled + * 0b1..Ignore PBL Requirement is enabled + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) +/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be + * transferred in one DMA block data transfer. + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK (0x10000000U) +#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT (28U) +/*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced + * Descriptors that are 32 Bytes for both Normal and Context Descriptors. + * 0b0..Enhanced Descriptor is disabled + * 0b1..Enhanced Descriptor is enabled + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TX_CTRL */ +#define ENET_QOS_DMA_CHX_TX_CTRL_COUNT (5U) + +/*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK (0x1U) +#define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT (0U) +/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from + * the Receive list and processes the incoming packets. + * 0b0..Stop Receive + * 0b1..Start Receive + */ +#define ENET_QOS_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK (0xEU) +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT (1U) +/*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK (0x7FF0U) +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U) +/*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) +/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be + * transferred in one DMA block data transfer. + */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) +#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) +/*! RPF - Rx Packet Flush. + * 0b0..Rx Packet Flush is disabled + * 0b1..Rx Packet Flush is enabled + */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RX_CTRL */ +#define ENET_QOS_DMA_CHX_RX_CTRL_COUNT (5U) + +/*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U) +/*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. */ +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */ +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT (5U) + +/*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U) +/*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. */ +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */ +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT (5U) + +/*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U) +/*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. */ +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */ +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT (5U) + +/*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U) +/*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. */ +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */ +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT (5U) + +/*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) +/*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. */ +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */ +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U) + +/*! @name DMA_CHX_RX_CONTROL2 - Channel 0 Receive Control 2 register..DMA Channel 4 Receive Control 2 register */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_MASK (0x3FFU) +#define ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_SHIFT (0U) +/*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. */ +#define ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_MASK) + +#define ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_MASK (0xFE0000U) +#define ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_SHIFT (17U) +/*! ARBS - Alternate Receive Buffer Size */ +#define ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_SHIFT)) & ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RX_CONTROL2 */ +#define ENET_QOS_DMA_CHX_RX_CONTROL2_COUNT (5U) + +/*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK (0x1U) +#define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT (0U) +/*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. + * 0b0..Transmit Interrupt is disabled + * 0b1..Transmit Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK (0x2U) +#define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT (1U) +/*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. + * 0b0..Transmit Stopped is disabled + * 0b1..Transmit Stopped is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_TXSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK (0x4U) +#define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT (2U) +/*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the + * Transmit Buffer Unavailable interrupt is enabled. + * 0b0..Transmit Buffer Unavailable is disabled + * 0b1..Transmit Buffer Unavailable is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK (0x40U) +#define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT (6U) +/*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. + * 0b0..Receive Interrupt is disabled + * 0b1..Receive Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK (0x80U) +#define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT (7U) +/*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the + * Receive Buffer Unavailable interrupt is enabled. + * 0b0..Receive Buffer Unavailable is disabled + * 0b1..Receive Buffer Unavailable is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK (0x100U) +#define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT (8U) +/*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. + * 0b0..Receive Stopped is disabled + * 0b1..Receive Stopped is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK (0x200U) +#define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT (9U) +/*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive + * Watchdog Timeout interrupt is enabled. + * 0b0..Receive Watchdog Timeout is disabled + * 0b1..Receive Watchdog Timeout is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK (0x400U) +#define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT (10U) +/*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. + * 0b0..Early Transmit Interrupt is disabled + * 0b1..Early Transmit Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK (0x800U) +#define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT (11U) +/*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. + * 0b0..Early Receive Interrupt is disabled + * 0b1..Early Receive Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) +#define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT (12U) +/*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. + * 0b0..Fatal Bus Error is disabled + * 0b1..Fatal Bus Error is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK (0x2000U) +#define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT (13U) +/*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. + * 0b0..Context Descriptor Error is disabled + * 0b1..Context Descriptor Error is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_CDEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK (0x4000U) +#define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT (14U) +/*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. + * 0b0..Abnormal Interrupt Summary is disabled + * 0b1..Abnormal Interrupt Summary is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT (15U) +/*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. + * 0b0..Normal Interrupt Summary is disabled + * 0b1..Normal Interrupt Summary is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_INT_EN */ +#define ENET_QOS_DMA_CHX_INT_EN_COUNT (5U) + +/*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU) +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U) +/*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock + * cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. + */ +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK) + +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U) +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U) +/*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system + * clock cycles corresponding to one unit in RWT field. + */ +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */ +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT (5U) + +/*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) +/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers + * programmed in the Tx descriptor with the current reference given in the RSN field. + * 0b0..Slot Comparison is disabled + * 0b1..Slot Comparison is enabled + */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) +/*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer + * when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot + * number given in the RSN field or - ahead of the reference slot number by up to two slots This + * bit is applicable only when the ESC bit is set. + * 0b0..Advance Slot Check is disabled + * 0b1..Advance Slot Check is enabled + */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U) +/*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA + * fetches the scheduled packets. + */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK) + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) +/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA. */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U) +/*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U) +/*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U) +/*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U) +/*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT (5U) + +/*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_STAT_TI_MASK (0x1U) +#define ENET_QOS_DMA_CHX_STAT_TI_SHIFT (0U) +/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete. + * 0b0..Transmit Interrupt status not detected + * 0b1..Transmit Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_TPS_MASK (0x2U) +#define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT (1U) +/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped. + * 0b0..Transmit Process Stopped status not detected + * 0b1..Transmit Process Stopped status detected + */ +#define ENET_QOS_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_TBU_MASK (0x4U) +#define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT (2U) +/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next + * descriptor in the Transmit list, and the DMA cannot acquire it. + * 0b0..Transmit Buffer Unavailable status not detected + * 0b1..Transmit Buffer Unavailable status detected + */ +#define ENET_QOS_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RI_MASK (0x40U) +#define ENET_QOS_DMA_CHX_STAT_RI_SHIFT (6U) +/*! RI - Receive Interrupt This bit indicates that the packet reception is complete. + * 0b0..Receive Interrupt status not detected + * 0b1..Receive Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RBU_MASK (0x80U) +#define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT (7U) +/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next + * descriptor in the Receive list, and the DMA cannot acquire it. + * 0b0..Receive Buffer Unavailable status not detected + * 0b1..Receive Buffer Unavailable status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RPS_MASK (0x100U) +#define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT (8U) +/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. + * 0b0..Receive Process Stopped status not detected + * 0b1..Receive Process Stopped status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RWT_MASK (0x200U) +#define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT (9U) +/*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 + * bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. + * 0b0..Receive Watchdog Timeout status not detected + * 0b1..Receive Watchdog Timeout status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK) + +#define ENET_QOS_DMA_CHX_STAT_ETI_MASK (0x400U) +#define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT (10U) +/*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the + * transfer of packet data to the MTL TXFIFO memory. + * 0b0..Early Transmit Interrupt status not detected + * 0b1..Early Transmit Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_ERI_MASK (0x800U) +#define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT (11U) +/*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the + * transfer of packet data to the memory. + * 0b0..Early Receive Interrupt status not detected + * 0b1..Early Receive Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_FBE_MASK (0x1000U) +#define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT (12U) +/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). + * 0b0..Fatal Bus Error status not detected + * 0b1..Fatal Bus Error status detected + */ +#define ENET_QOS_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK) + +#define ENET_QOS_DMA_CHX_STAT_CDE_MASK (0x2000U) +#define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT (13U) +/*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a + * descriptor error, which indicates invalid context in the middle of packet flow ( intermediate + * descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor + * with either of the buffer address as ones which is considered to be invalid. + * 0b0..Context Descriptor Error status not detected + * 0b1..Context Descriptor Error status detected + */ +#define ENET_QOS_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK) + +#define ENET_QOS_DMA_CHX_STAT_AIS_MASK (0x4000U) +#define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT (14U) +/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the + * following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE + * register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive + * Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context + * Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. + * 0b0..Abnormal Interrupt Summary status not detected + * 0b1..Abnormal Interrupt Summary status detected + */ +#define ENET_QOS_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_NIS_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT (15U) +/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the + * following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE + * register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive + * Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt + * enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. + * 0b0..Normal Interrupt Summary status not detected + * 0b1..Normal Interrupt Summary status detected + */ +#define ENET_QOS_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_TEB_MASK (0x70000U) +#define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT (16U) +/*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. */ +#define ENET_QOS_DMA_CHX_STAT_TEB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK) + +#define ENET_QOS_DMA_CHX_STAT_REB_MASK (0x380000U) +#define ENET_QOS_DMA_CHX_STAT_REB_SHIFT (19U) +/*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. */ +#define ENET_QOS_DMA_CHX_STAT_REB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_STAT */ +#define ENET_QOS_DMA_CHX_STAT_COUNT (5U) + +/*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU) +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U) +/*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are + * dropped by the DMA either because of bus error or because of programming RPF field in + * DMA_CH2_RX_CONTROL register. + */ +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK) + +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U) +/*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. + * 0b0..Miss Frame Counter overflow not occurred + * 0b1..Miss Frame Counter overflow occurred + */ +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */ +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT (5U) + +/*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) +/*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. */ +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK) + +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) +/*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC + * Counter field crossed the maximum limit. + * 0b0..Rx Parser Accept Counter overflow not occurred + * 0b1..Rx Parser Accept Counter overflow occurred + */ +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */ +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT (5U) + + +/*! + * @} + */ /* end of group ENET_QOS_Register_Masks */ + + +/* ENET_QOS - Peripheral instance base addresses */ +/** Peripheral ENET_QOS base address */ +#define ENET_QOS_BASE (0x428A0000u) +/** Peripheral ENET_QOS base pointer */ +#define ENET_QOS ((ENET_QOS_Type *)ENET_QOS_BASE) +/** Array initializer of ENET_QOS peripheral base addresses */ +#define ENET_QOS_BASE_ADDRS { ENET_QOS_BASE } +/** Array initializer of ENET_QOS peripheral base pointers */ +#define ENET_QOS_BASE_PTRS { ENET_QOS } + +/*! + * @} + */ /* end of group ENET_QOS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ + uint8_t RESERVED_4[4]; + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __IO uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __IO uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __IO uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __IO uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_6[96]; + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_7[224]; + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[96]; + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[96]; + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_10[96]; + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_11[96]; + __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[96]; + __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_13[96]; + __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_14[352]; + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_15[96]; + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_16[96]; + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ + uint8_t RESERVED_17[96]; + __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_18[96]; + __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_19[96]; + __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FLEXIO Control */ +/*! @{ */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FLEXIO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Normal + * 0b1..Fast + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State */ +/*! @{ */ + +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status */ +/*! @{ */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + * 0b00000000..Clear + * 0b00000000..No effect + * 0b00000001..Set + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error */ +/*! @{ */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flag + * 0b00000000..Clear + * 0b00000000..No effect + * 0b00000001..Set + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Flag */ +/*! @{ */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flag + * 0b00000000..Clear + * 0b00000000..No effect + * 0b00000001..Set + * 0b00000001..Clear the flag + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name TIMERSDEN - Timer Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) +/*! TSDE - Timer Status DMA Enable */ +#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State */ +/*! @{ */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name TRGSTAT - Trigger Status */ +/*! @{ */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xFU) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) +/*! ETSF - External Trigger Status Flag + * 0b0000..Clear + * 0b0000..No effect + * 0b0001..Set + * 0b0001..Clear the flag + */ +#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) +/*! @} */ + +/*! @name TRIGIEN - External Trigger Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xFU) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) +/*! TRIE - External Trigger Interrupt Enable */ +#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) +/*! @} */ + +/*! @name PINSTAT - Pin Status */ +/*! @{ */ + +#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) +#define FLEXIO_PINSTAT_PSF_SHIFT (0U) +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000001..Clear the flag + */ +#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) +/*! @} */ + +/*! @name PINIEN - Pin Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINIEN_PSIE_SHIFT (0U) +/*! PSIE - Pin Status Interrupt Enable */ +#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) +/*! @} */ + +/*! @name PINREN - Pin Rising Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINREN_PRE_SHIFT (0U) +/*! PRE - Pin Rising Edge */ +#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) +/*! @} */ + +/*! @name PINFEN - Pin Falling Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINFEN_PFE_SHIFT (0U) +/*! PFE - Pin Falling Edge */ +#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) +/*! @} */ + +/*! @name PINOUTD - Pin Output Data */ +/*! @{ */ + +#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTD_OUTD_SHIFT (0U) +/*! OUTD - Output Data */ +#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) +/*! @} */ + +/*! @name PINOUTE - Pin Output Enable */ +/*! @{ */ + +#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTE_OUTE_SHIFT (0U) +/*! OUTE - Output Enable */ +#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) +/*! @} */ + +/*! @name PINOUTDIS - Pin Output Disable */ +/*! @{ */ + +#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) +/*! OUTDIS - Output Disable */ +#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) +/*! @} */ + +/*! @name PINOUTCLR - Pin Output Clear */ +/*! @{ */ + +#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) +/*! OUTCLR - Output Clear */ +#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) +/*! @} */ + +/*! @name PINOUTSET - Pin Output Set */ +/*! @{ */ + +#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) +/*! OUTSET - Output Set */ +#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) +/*! @} */ + +/*! @name PINOUTTOG - Pin Output Toggle */ +/*! @{ */ + +#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) +/*! OUTTOG - Output Toggle */ +#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control */ +/*! @{ */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open-drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Positive edge + * 0b1..Negative edge + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (8U) + +/*! @name SHIFTCFG - Shifter Configuration */ +/*! @{ */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter n+1 output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) +/*! LATST - Late Store + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state + */ +#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) +/*! SSIZE - Shifter Size + * 0b0..32-bit + * 0b1..24-bit + */ +#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (8U) + +/*! @name SHIFTBUF - Shifter Buffer */ +/*! @{ */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (8U) + +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (8U) + +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (8U) + +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (8U) + +/*! @name TIMCTL - Timer Control */ +/*! @{ */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) +#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) +/*! ONETIM - Timer One Time Operation + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear + */ +#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + +#define FLEXIO_TIMCTL_PININS_MASK (0x40U) +#define FLEXIO_TIMCTL_PININS_SHIFT (6U) +/*! PININS - Timer Pin Input Select + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL + */ +#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open-drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (8U) + +/*! @name TIMCFG - Timer Configuration */ +/*! @{ */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low + * 0b100..Timer disabled on pin rising or falling edge + * 0b101..Timer disabled on pin rising or falling edge provided trigger is high + * 0b110..Timer disabled on trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Never reset timer + * 0b001..Timer reset on timer output high. + * 0b010..Timer reset on timer pin equal to timer output + * 0b011..Timer reset on timer trigger equal to timer output + * 0b100..Timer reset on timer pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on trigger rising edge + * 0b111..Timer reset on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (8U) + +/*! @name TIMCMP - Timer Compare */ +/*! @{ */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (8U) + +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (8U) + +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (8U) + +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (8U) + +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) +/*! SHIFTBUFOES - Shift Buffer */ +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFOES */ +#define FLEXIO_SHIFTBUFOES_COUNT (8U) + +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) +/*! SHIFTBUFEOS - Shift Buffer */ +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFEOS */ +#define FLEXIO_SHIFTBUFEOS_COUNT (8U) + +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) +/*! SHIFTBUFHBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHBS */ +#define FLEXIO_SHIFTBUFHBS_COUNT (8U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO1 base address */ +#define FLEXIO1_BASE (0x425C0000u) +/** Peripheral FLEXIO1 base pointer */ +#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) +/** Peripheral FLEXIO2 base address */ +#define FLEXIO2_BASE (0x425D0000u) +/** Peripheral FLEXIO2 base pointer */ +#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO1_BASE, FLEXIO2_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO1, FLEXIO2 } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[8]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[32]; + __IO uint32_t FLSHCR0[4]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FLSHCR4; /**< Flash Control 4, offset: 0x94 */ + uint8_t RESERVED_2[8]; + __IO uint32_t IPCR0; /**< IP Control 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ + __IO uint32_t IPCR2; /**< IP Control 2, offset: 0xA8 */ + uint8_t RESERVED_3[4]; + __IO uint32_t IPCMD; /**< IP Command, offset: 0xB0 */ + __IO uint32_t DLPR; /**< Data Learning Pattern, offset: 0xB4 */ + __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[24]; + __I uint32_t STS0; /**< Status 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP Receive FIFO Status, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP Transmit FIFO Status, offset: 0xF4 */ + uint8_t RESERVED_5[8]; + __I uint32_t RFDR[32]; /**< IP Receive FIFO Data 0..IP Receive FIFO Data 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data 0..IP TX FIFO Data 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[128]; /**< Lookup Table 0..Lookup Table 127, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[64]; + __IO uint32_t AHBBUFREGIONSTART0; /**< Receive Buffer Start Address of Region 0, offset: 0x440 */ + __IO uint32_t AHBBUFREGIONEND0; /**< Receive Buffer Region 0 End Address, offset: 0x444 */ + __IO uint32_t AHBBUFREGIONSTART1; /**< Receive Buffer Start Address of Region 1, offset: 0x448 */ + __IO uint32_t AHBBUFREGIONEND1; /**< Receive Buffer Region 1 End Address, offset: 0x44C */ + __IO uint32_t AHBBUFREGIONSTART2; /**< Receive Buffer Start Address of Region 2, offset: 0x450 */ + __IO uint32_t AHBBUFREGIONEND2; /**< Receive Buffer Region 2 End Address, offset: 0x454 */ + __IO uint32_t AHBBUFREGIONSTART3; /**< Receive Buffer Start Address of Region 3, offset: 0x458 */ + __IO uint32_t AHBBUFREGIONEND3; /**< Receive Buffer Region 3 End Address, offset: 0x45C */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control 0 */ +/*! @{ */ + +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +/*! SWRESET - Software Reset + * 0b0..No impact + * 0b1..Software reset + */ +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) + +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + * 0b0..No impact + * 0b1..Module disable + */ +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) + +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock Source for Flash Reading + * 0b00..Dummy Read strobe that FlexSPI generates, looped back internally + * 0b01..Dummy Read strobe that FlexSPI generates, looped back from DQS pad + * 0b10..SCLK output clock and looped back from SCLK pad + * 0b11..Flash-memory-provided read strobe and input from DQS pad + */ +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) + +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - AHB Read Access to IP Receive FIFO Enable + * 0b0..AHB read access disabled. IP bus reads IP receive FIFO. AHB Bus read access to IP receive FIFO memory space produces bus error. + * 0b1..AHB read access enabled. AHB bus reads IP receive FIFO. IP Bus read access to IP receive FIFO memory + * space returns data zero and causes no bus error. + */ +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) + +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - AHB Write Access to IP Transmit FIFO Enable + * 0b0..AHB write access disabled. IP bus writes to IP transmit FIFO. AHB bus write access to IP transmit FIFO memory space produces bus error. + * 0b1..AHB write access enabled. AHB bus writes to IP transmit FIFO. IP Bus write access to IP transmit FIFO + * memory space is ignored and causes no bus error. + */ +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) + +#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) +/*! SERCLKDIV - Serial Root Clock Divider + * 0b000..Divided by 1 + * 0b001..Divided by 2 + * 0b010..Divided by 3 + * 0b011..Divided by 4 + * 0b100..Divided by 5 + * 0b101..Divided by 6 + * 0b110..Divided by 7 + * 0b111..Divided by 8 + */ +#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) + +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash Memory Access Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) + +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) + +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - SCLK Free-running Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) + +#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) +#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) +/*! LEARNEN - Data Learning Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) + +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +/*! IPGRANTWAIT - Timeout Wait Cycle for IP Command Grant */ +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) + +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +/*! AHBGRANTWAIT - Timeouts Wait Cycle for AHB command Grant */ +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control 1 */ +/*! @{ */ + +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +/*! AHBBUSWAIT - AHB Bus Wait */ +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) + +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +/*! SEQWAIT - Command Sequence Wait */ +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control 2 */ +/*! @{ */ + +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - Clear AHB Buffer + * 0b0..Not cleared automatically + * 0b1..Cleared automatically + */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) + +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +/*! CLRLEARNPHASE - Clear Learn Phase Selection + * 0b0..No impact + * 0b1..Reset sample clock phase selection to 0 + */ +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) + +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - Same Device Enable + * 0b0..In Individual mode, FLSHA1CRx and FLSHA2CRx, FLSHB1CRx and FLSHB2CRx settings are applied to Flash A1, A2, B1, B2 separately. + * 0b1..FLSHA1CR0, FLSHA1CR1, and FLSHA1CR2 register settings are applied to Flash A1, A2, B1, B2. FLSHA2CRx, + * FLSHB1CRx, and FLSHB2CRx settings are ignored. + */ +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) + +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +/*! RESUMEWAIT - Resume Wait Duration */ +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control */ +/*! @{ */ + +#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) +#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) +/*! CLRAHBTXBUF - Clear AHB Transmit Buffer + * 0b0..No impact. + * 0b1..Enable clear operation. + */ +#define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) + +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Cacheable Read Access Enable + * 0b0..Disabled. When an AHB bus cacheable read access occurs, FlexSPI does not check whether it hit the AHB transmit buffer. + * 0b1..Enabled. When an AHB bus cacheable read access occurs, FlexSPI first checks whether the access hit the AHB transmit buffer. + */ +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) + +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Bufferable Write Access Enable + * 0b0..Disabled. For all AHB write accesses (bufferable or nonbufferable), FlexSPI returns AHB Bus Ready after + * transmitting all data and finishing command. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI returns AHB Bus Ready when the arbitrator grants the + * AHB command. FlexSPI does not wait for the AHB command to finish. + */ +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) + +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +/*! PREFETCHEN - AHB Read Prefetch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) + +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address Option + * 0b0..AHB read burst start address alignment is limited when flash memory is accessed in flash is word-addressable. + * 0b1..AHB read burst start address alignment is not limited. FlexSPI fetches more data than the AHB burst requires for address alignment. + */ +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) + +#define FLEXSPI_AHBCR_RESUMEDISABLE_MASK (0x80U) +#define FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT (7U) +/*! RESUMEDISABLE - AHB Read Resume Disable + * 0b0..Suspended AHB read prefetch resumes when AHB is IDLE. + * 0b1..Suspended AHB read prefetch does not resume once aborted. + */ +#define FLEXSPI_AHBCR_RESUMEDISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT)) & FLEXSPI_AHBCR_RESUMEDISABLE_MASK) + +#define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) +#define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) +/*! READSZALIGN - AHB Read Size Alignment + * 0b0..Register settings such as PREFETCH_EN and OTFAD_EN determine AHB read size. + * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching + */ +#define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) + +#define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) +#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) +/*! ALIGNMENT - AHB Boundary Alignment + * 0b00..No limit + * 0b01..1 KB + * 0b10..512 bytes + * 0b11..256 bytes + */ +#define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) + +#define FLEXSPI_AHBCR_AFLASHBASE_MASK (0xF8000000U) +#define FLEXSPI_AHBCR_AFLASHBASE_SHIFT (27U) +/*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */ +#define FLEXSPI_AHBCR_AFLASHBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable */ +/*! @{ */ + +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +/*! IPCMDDONEEN - IP-Triggered Command Sequences Execution Finished Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) + +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +/*! IPCMDGEEN - IP-Triggered Command Sequences Grant Timeout Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) + +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +/*! AHBCMDGEEN - AHB-Triggered Command Sequences Grant Timeout Interrupt Enable. + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) + +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +/*! IPCMDERREN - IP-Triggered Command Sequences Error Detected Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) + +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +/*! AHBCMDERREN - AHB-Triggered Command Sequences Error Detected Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) + +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +/*! IPRXWAEN - IP Receive FIFO Watermark Available Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) + +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +/*! IPTXWEEN - IP Transmit FIFO Watermark Empty Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) + +#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) +/*! DATALEARNFAILEN - Data Learning Failed Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) + +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +/*! SCKSTOPBYRDEN - SCLK Stopped By Read Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) + +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +/*! SCKSTOPBYWREN - SCLK Stopped By Write Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) + +#define FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U) +/*! AHBBUSERROREN - AHB Bus Error Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) + +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +/*! SEQTIMEOUTEN - Sequence execution Timeout Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) + +#define FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U) +#define FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U) +/*! KEYDONEEN - OTFAD Key Blob Processing Done Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) + +#define FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U) +#define FLEXSPI_INTEN_KEYERROREN_SHIFT (13U) +/*! KEYERROREN - OTFAD Key Blob Processing Error Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt */ +/*! @{ */ + +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +/*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) + +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +/*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) + +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +/*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) + +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +/*! IPCMDERR - IP-Triggered Command Sequences Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) + +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +/*! AHBCMDERR - AHB-Triggered Command Sequences Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) + +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +/*! IPRXWA - IP Receive FIFO Watermark Available + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) + +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +/*! IPTXWE - IP Transmit FIFO Watermark Empty + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) + +#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) +#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) +/*! DATALEARNFAIL - Data Learning Failed + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) + +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +/*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) + +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +/*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) + +#define FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) +/*! AHBBUSERROR - AHB Bus Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) + +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +/*! SEQTIMEOUT - Sequence Execution Timeout + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) + +#define FLEXSPI_INTR_KEYDONE_MASK (0x1000U) +#define FLEXSPI_INTR_KEYDONE_SHIFT (12U) +/*! KEYDONE - OTFAD key blob processing done interrupt. */ +#define FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) + +#define FLEXSPI_INTR_KEYERROR_MASK (0x2000U) +#define FLEXSPI_INTR_KEYERROR_SHIFT (13U) +/*! KEYERROR - OTFAD Key Blob Processing Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key */ +/*! @{ */ + +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +/*! KEY - LUT Key */ +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control */ +/*! @{ */ + +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +/*! LOCK - Lock LUT + * 0b0..LUT is unlocked (LUTCR[UNLOCK] must be 1) + * 0b1..LUT is locked and cannot be written + */ +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) + +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +/*! UNLOCK - Unlock LUT + * 0b0..LUT is locked (LUTCR[LOCK] must be 1) + * 0b1..LUT is unlocked and can be written + */ +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0 */ +/*! @{ */ + +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +/*! BUFSZ - AHB Receive Buffer Size */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) + +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +/*! MSTRID - AHB Controller ID */ +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) + +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +/*! PRIORITY - AHB Controller Read Priority */ +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) + +#define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) +#define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) +/*! REGIONEN - AHB Receive Buffer Address Region Enable + * 0b0..Disabled. The buffer hit is based on the value of MSTRID only. + * 0b1..Enabled. The buffer hit is based on the value of MSTRID and the address within AHBBUFREGIONSTARTn and AHBREGIONENDn. + */ +#define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) + +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +/*! PREFETCHEN - AHB Read Prefetch Enable + * 0b0..Disabled + * 0b1..Enabled when is enabled. + */ +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) + +/*! @name FLSHCR0 - Flash Control 0 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +/*! FLSHSZ - Flash Size in KB */ +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) + +#define FLEXSPI_FLSHCR0_ADDRSHIFT_MASK (0x20000000U) +#define FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT (29U) +/*! ADDRSHIFT - AHB Address Shift Function control + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXSPI_FLSHCR0_ADDRSHIFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash Control 1 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +/*! TCSS - Serial Flash CS Setup Time */ +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) + +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +/*! TCSH - Serial Flash CS Hold Time */ +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) + +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +/*! WA - Word-Addressable + * 0b0..Byte-addressable + * 0b1..Word-addressable + */ +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) + +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +/*! CAS - Column Address Size */ +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) + +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - Chip Select Interval Unit + * 0b0..1 serial clock cycle + * 0b1..256 serial clock cycles + */ +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) + +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +/*! CSINTERVAL - Chip Select Interval */ +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash Control 2 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +/*! ARDSEQID - Sequence Index for AHB Read-Triggered Command in LUT */ +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) + +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +/*! ARDSEQNUM - Sequence Number for AHB Read-Triggered Command */ +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) + +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +/*! AWRSEQID - Sequence Index for AHB Write-Triggered Command */ +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) + +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +/*! AWRSEQNUM - Sequence Number for AHB Write-Triggered Command */ +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) + +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +/*! AWRWAIT - AHB Write Wait */ +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) + +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT Unit + * 0b000..2 + * 0b001..8 + * 0b010..32 + * 0b011..128 + * 0b100..512 + * 0b101..2048 + * 0b110..8192 + * 0b111..32768 + */ +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) + +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +/*! CLRINSTRPTR - Clear Instruction Pointer */ +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR4 - Flash Control 4 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write Mask Option 1 + * 0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst start address alignment is not limited. + * 0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst start address alignment is limited. + */ +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) + +#define FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U) +#define FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U) +/*! WMOPT2 - Write Mask Option 2 + * 0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst length is not limited. + * 0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst length is limited. The minimum write burst length should be 4. + */ +#define FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) + +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write Mask Enable for Port A + * 0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven. + * 0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output. + */ +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control 0 */ +/*! @{ */ + +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +/*! SFAR - Serial Flash Address */ +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control 1 */ +/*! @{ */ + +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +/*! IDATSZ - Flash Read/Program Data Size (in bytes) for IP command. */ +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) + +#define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +/*! ISEQID - Sequence Index in LUT for IP command. */ +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) + +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +/*! @} */ + +/*! @name IPCR2 - IP Control 2 */ +/*! @{ */ + +#define FLEXSPI_IPCR2_IPBLKAHBREQ_MASK (0x1U) +#define FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT (0U) +/*! IPBLKAHBREQ - IP Command Blocking AHB Command Request Enable + * 0b0..IP commands do not block AHB command requests. + * 0b1..IP commands block AHB command requests. + */ +#define FLEXSPI_IPCR2_IPBLKAHBREQ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBREQ_MASK) + +#define FLEXSPI_IPCR2_IPBLKAHBACK_MASK (0x2U) +#define FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT (1U) +/*! IPBLKAHBACK - IP Command Blocking AHB Command Acknowledgment Enable + * 0b0..IP commands do not block AHB command acknowledgment. + * 0b1..IP commands block AHB command acknowledgment. + */ +#define FLEXSPI_IPCR2_IPBLKAHBACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBACK_MASK) + +#define FLEXSPI_IPCR2_IPBLKALLAHB_MASK (0x4U) +#define FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT (2U) +/*! IPBLKALLAHB - IP Command Blocking All AHB Command Enable + * 0b0.. + * 0b1..IP commands block all AHB commands. + */ +#define FLEXSPI_IPCR2_IPBLKALLAHB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT)) & FLEXSPI_IPCR2_IPBLKALLAHB_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command */ +/*! @{ */ + +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +/*! TRG - Command Trigger + * 0b0..No action + * 0b1..Start the IP command that the IPCR0 and IPCR1 registers define. + */ +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name DLPR - Data Learning Pattern */ +/*! @{ */ + +#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) +#define FLEXSPI_DLPR_DLP_SHIFT (0U) +/*! DLP - Data Learning Pattern */ +#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP Receive FIFO Control */ +/*! @{ */ + +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +/*! CLRIPRXF - Clear IP Receive FIFO + * 0b0..No function + * 0b1..A clock cycle pulse clears all valid data entries in IP receive FIFO. + */ +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) + +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP Receive FIFO Reading by DMA Enable + * 0b0..Disabled. The processor reads the FIFO. + * 0b1..Enabled. DMA reads the FIFO. + */ +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) + +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +/*! RXWMRK - IP Receive FIFO Watermark Level */ +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP Transmit FIFO Control */ +/*! @{ */ + +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +/*! CLRIPTXF - Clear IP Transmit FIFO + * 0b0..No function + * 0b1..A clock cycle pulse clears all valid data entries in the IP transmit FIFO. + */ +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) + +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - Transmit FIFO DMA Enable + * 0b0..Processor + * 0b1..DMA + */ +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) + +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +/*! TXWMRK - Transmit Watermark Level */ +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control 0 */ +/*! @{ */ + +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +/*! DLLEN - DLL Calibration Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) + +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +/*! DLLRESET - DLL reset + * 0b0..No function + * 0b1..Force DLL reset. + */ +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) + +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +/*! SLVDLYTARGET - Target Delay Line */ +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) + +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +/*! OVRDEN - Target Clock Delay Line Override Value Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) + +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +/*! OVRDVAL - Target Clock Delay Line Override Value */ +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) + +#define FLEXSPI_DLLCR_REFPHASEGAP_MASK (0x18000U) +#define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT (15U) +/*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */ +#define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) + +#define FLEXSPI_DLLCR_REFPHASESTART_MASK (0xE0000U) +#define FLEXSPI_DLLCR_REFPHASESTART_SHIFT (17U) +/*! REFPHASESTART - Reference Clock Delay Line Start Phase */ +#define FLEXSPI_DLLCR_REFPHASESTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASESTART_SHIFT)) & FLEXSPI_DLLCR_REFPHASESTART_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status 0 */ +/*! @{ */ + +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +/*! SEQIDLE - SEQ_CTL State Machine Idle + * 0b0..Not idle + * 0b1..Idle + */ +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) + +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +/*! ARBIDLE - ARB_CTL State Machine Idle + * 0b0..Not idle + * 0b1..Idle + */ +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) + +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - ARB Command Source + * 0b00..Trigger source is AHB read command. + * 0b01..Trigger source is AHB write command. + * 0b10..Trigger source is IP command (by writing 1 to IPCMD[TRG]). + * 0b11..Trigger source is a suspended command that has resumed. + */ +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) + +#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) +#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) +/*! DATALEARNPHASEA - Data Learning Phase Selection on Port A */ +#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) +/*! @} */ + +/*! @name STS1 - Status 1 */ +/*! @{ */ + +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +/*! AHBCMDERRID - AHB Command Error ID */ +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) + +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - AHB Command Error Code + * 0b0000..No error + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence + * 0b0011..Unknown instruction opcode in the sequence + * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence + * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence + * 0b1110..Sequence execution timeout + */ +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) + +#define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +/*! IPCMDERRID - IP Command Error ID */ +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) + +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - IP Command Error Code + * 0b0000..No error + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence + * 0b0011..Unknown instruction opcode in the sequence + * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence + * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence + * 0b0110..Flash memory access start address exceeds entire flash address range (A1, A2, B1, and B2) + * 0b1110..Sequence execution timeout + * 0b1111..Flash boundary crossed + */ +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status 2 */ +/*! @{ */ + +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +/*! ASLVLOCK - Flash A Sample Target Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) + +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +/*! AREFLOCK - Flash A Sample Clock Reference Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) + +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +/*! ASLVSEL - Flash A Sample Clock Target Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) + +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +/*! AREFSEL - Flash A Sample Clock Reference Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) + +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +/*! BSLVLOCK - Flash B Sample Target Reference Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) + +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +/*! BREFLOCK - Flash B Sample Clock Reference Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) + +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +/*! BSLVSEL - Flash B Sample Clock Target Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) + +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +/*! BREFSEL - Flash B Sample Clock Reference Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status */ +/*! @{ */ + +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +/*! ACTIVE - Active AHB Read Prefetch Suspended + * 0b0..No suspended AHB read prefetch command. + * 0b1..An AHB read prefetch command sequence has been suspended. + */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) + +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +/*! BUFID - AHB Receive Buffer ID for Suspended Command Sequence */ +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) + +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +/*! DATLFT - Data Left */ +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP Receive FIFO Status */ +/*! @{ */ + +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill Level of IP Receive FIFO */ +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) + +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +/*! RDCNTR - Read Data Counter */ +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP Transmit FIFO Status */ +/*! @{ */ + +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill Level of IP Transmit FIFO */ +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) + +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +/*! WRCNTR - Write Data Counter */ +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP Receive FIFO Data 0..IP Receive FIFO Data 31 */ +/*! @{ */ + +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +/*! RXDATA - Receive Data */ +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data 0..IP TX FIFO Data 31 */ +/*! @{ */ + +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit Data */ +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - Lookup Table 0..Lookup Table 127 */ +/*! @{ */ + +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +/*! OPERAND0 - OPERAND0 */ +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) + +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +/*! NUM_PADS0 - NUM_PADS0 */ +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) + +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +/*! OPCODE0 - OPCODE */ +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) + +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +/*! OPERAND1 - OPERAND1 */ +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) + +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +/*! NUM_PADS1 - NUM_PADS1 */ +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) + +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +/*! OPCODE1 - OPCODE1 */ +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (128U) + +/*! @name AHBBUFREGIONSTART0 - Receive Buffer Start Address of Region 0 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND0 - Receive Buffer Region 0 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART1 - Receive Buffer Start Address of Region 1 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND1 - Receive Buffer Region 1 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART2 - Receive Buffer Start Address of Region 2 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND2 - Receive Buffer Region 2 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART3 - Receive Buffer Start Address of Region 3 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND3 - Receive Buffer Region 3 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FLEXSPI1 base address */ +#define FLEXSPI1_BASE (0x425E0000u) +/** Peripheral FLEXSPI1 base pointer */ +#define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1 } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) +/* FlexSPI1 AMBA address. */ +#define FlexSPI1_AMBA_BASE (0x38000000u) +/* FlexSPI1 ASFM address. */ +#define FlexSPI1_ASFM_BASE (0x38000000u) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI1_ARDF_BASE (0x57420000u) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI1_ATDF_BASE (0x57430000u) + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FSB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FSB_Peripheral_Access_Layer FSB Peripheral Access Layer + * @{ + */ + +/** FSB - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< FSB Version ID Register, offset: 0x0 */ + uint8_t RESERVED_0[24]; + __I uint32_t FSB_STATUS; /**< FSB Status Register, offset: 0x1C */ + uint8_t RESERVED_1[68]; + __IO uint32_t ACCESS_COUNT; /**< Access Count Register, offset: 0x64 */ + uint8_t RESERVED_2[3992]; + __IO uint32_t FUSE_STAT; /**< Fuse Status Register, offset: 0x1000 */ + __IO uint32_t FUSE_EVNT; /**< Fuse Event Register, offset: 0x1004 */ + __IO uint32_t FUSE_INT_EN; /**< Fuse Interrupt Enable Register, offset: 0x1008 */ + __I uint32_t FUSE_INT; /**< Fuse Interrupt Register, offset: 0x100C */ + uint8_t RESERVED_3[28656]; + __I uint32_t FUSE[512]; /**< Fuse Value Registers, array offset: 0x8000, array step: 0x4 */ +} FSB_Type; + +/* ---------------------------------------------------------------------------- + -- FSB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FSB_Register_Masks FSB Register Masks + * @{ + */ + +/*! @name VERID - FSB Version ID Register */ +/*! @{ */ + +#define FSB_VERID_MISC_MASK (0xFFU) +#define FSB_VERID_MISC_SHIFT (0U) +/*! MISC - Feature Specification + * 0bxxxxxx1x..MU IRQ steering is enabled. + * 0bxxxxxxx1..Support for aborted transfers to OCOTP fuse space on the FSB slave APB is enabled. + */ +#define FSB_VERID_MISC(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_MISC_SHIFT)) & FSB_VERID_MISC_MASK) + +#define FSB_VERID_ECO_MASK (0xFF00U) +#define FSB_VERID_ECO_SHIFT (8U) +/*! ECO - ECO Version Number */ +#define FSB_VERID_ECO(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_ECO_SHIFT)) & FSB_VERID_ECO_MASK) + +#define FSB_VERID_MINOR_MASK (0xFF0000U) +#define FSB_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FSB_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_MINOR_SHIFT)) & FSB_VERID_MINOR_MASK) + +#define FSB_VERID_MAJOR_MASK (0xFF000000U) +#define FSB_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FSB_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_MAJOR_SHIFT)) & FSB_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name FSB_STATUS - FSB Status Register */ +/*! @{ */ + +#define FSB_FSB_STATUS_VMTR_MASK (0x1U) +#define FSB_FSB_STATUS_VMTR_SHIFT (0U) +/*! VMTR - MTR Trim fuses valid. */ +#define FSB_FSB_STATUS_VMTR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VMTR_SHIFT)) & FSB_FSB_STATUS_VMTR_MASK) + +#define FSB_FSB_STATUS_VERL_MASK (0x2U) +#define FSB_FSB_STATUS_VERL_SHIFT (1U) +/*! VERL - Early fuses valid. */ +#define FSB_FSB_STATUS_VERL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VERL_SHIFT)) & FSB_FSB_STATUS_VERL_MASK) + +#define FSB_FSB_STATUS_VMED_MASK (0x4U) +#define FSB_FSB_STATUS_VMED_SHIFT (2U) +/*! VMED - Medium fuses valid. */ +#define FSB_FSB_STATUS_VMED(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VMED_SHIFT)) & FSB_FSB_STATUS_VMED_MASK) + +#define FSB_FSB_STATUS_VALL_MASK (0x8U) +#define FSB_FSB_STATUS_VALL_SHIFT (3U) +/*! VALL - All fuses valid. */ +#define FSB_FSB_STATUS_VALL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VALL_SHIFT)) & FSB_FSB_STATUS_VALL_MASK) + +#define FSB_FSB_STATUS_LMTR_MASK (0x10U) +#define FSB_FSB_STATUS_LMTR_SHIFT (4U) +/*! LMTR - MTR Trim fuses loaded. */ +#define FSB_FSB_STATUS_LMTR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LMTR_SHIFT)) & FSB_FSB_STATUS_LMTR_MASK) + +#define FSB_FSB_STATUS_LERL_MASK (0x20U) +#define FSB_FSB_STATUS_LERL_SHIFT (5U) +/*! LERL - Early fuses loaded. */ +#define FSB_FSB_STATUS_LERL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LERL_SHIFT)) & FSB_FSB_STATUS_LERL_MASK) + +#define FSB_FSB_STATUS_LMED_MASK (0x40U) +#define FSB_FSB_STATUS_LMED_SHIFT (6U) +/*! LMED - Medium fuses loaded. */ +#define FSB_FSB_STATUS_LMED(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LMED_SHIFT)) & FSB_FSB_STATUS_LMED_MASK) + +#define FSB_FSB_STATUS_LALL_MASK (0x80U) +#define FSB_FSB_STATUS_LALL_SHIFT (7U) +/*! LALL - All fuses loaded. */ +#define FSB_FSB_STATUS_LALL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LALL_SHIFT)) & FSB_FSB_STATUS_LALL_MASK) +/*! @} */ + +/*! @name ACCESS_COUNT - Access Count Register */ +/*! @{ */ + +#define FSB_ACCESS_COUNT_COUNT_MASK (0xFFFFFFFFU) +#define FSB_ACCESS_COUNT_COUNT_SHIFT (0U) +/*! COUNT - Access Count Register. */ +#define FSB_ACCESS_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FSB_ACCESS_COUNT_COUNT_SHIFT)) & FSB_ACCESS_COUNT_COUNT_MASK) +/*! @} */ + +/*! @name FUSE_STAT - Fuse Status Register */ +/*! @{ */ + +#define FSB_FUSE_STAT_FUSE_ADDR_MASK (0xFFFFU) +#define FSB_FUSE_STAT_FUSE_ADDR_SHIFT (0U) +/*! FUSE_ADDR - Fuse address */ +#define FSB_FUSE_STAT_FUSE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_FUSE_ADDR_SHIFT)) & FSB_FUSE_STAT_FUSE_ADDR_MASK) + +#define FSB_FUSE_STAT_SHDW_ZERO_MASK (0x1000000U) +#define FSB_FUSE_STAT_SHDW_ZERO_SHIFT (24U) +/*! SHDW_ZERO - Shadow zeroized */ +#define FSB_FUSE_STAT_SHDW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_SHDW_ZERO_SHIFT)) & FSB_FUSE_STAT_SHDW_ZERO_MASK) + +#define FSB_FUSE_STAT_SHDW_UNPROG_MASK (0x2000000U) +#define FSB_FUSE_STAT_SHDW_UNPROG_SHIFT (25U) +/*! SHDW_UNPROG - Shadow unprogrammed */ +#define FSB_FUSE_STAT_SHDW_UNPROG(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_SHDW_UNPROG_SHIFT)) & FSB_FUSE_STAT_SHDW_UNPROG_MASK) + +#define FSB_FUSE_STAT_FUSE_ERR_MASK (0x4000000U) +#define FSB_FUSE_STAT_FUSE_ERR_SHIFT (26U) +/*! FUSE_ERR - Fuse error */ +#define FSB_FUSE_STAT_FUSE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_FUSE_ERR_SHIFT)) & FSB_FUSE_STAT_FUSE_ERR_MASK) + +#define FSB_FUSE_STAT_LOADING_MASK (0x8000000U) +#define FSB_FUSE_STAT_LOADING_SHIFT (27U) +/*! LOADING - Shadow loading */ +#define FSB_FUSE_STAT_LOADING(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_LOADING_SHIFT)) & FSB_FUSE_STAT_LOADING_MASK) + +#define FSB_FUSE_STAT_RLD_ERR_MASK (0x10000000U) +#define FSB_FUSE_STAT_RLD_ERR_SHIFT (28U) +/*! RLD_ERR - Reload error */ +#define FSB_FUSE_STAT_RLD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_RLD_ERR_SHIFT)) & FSB_FUSE_STAT_RLD_ERR_MASK) + +#define FSB_FUSE_STAT_RD_ERR_MASK (0x20000000U) +#define FSB_FUSE_STAT_RD_ERR_SHIFT (29U) +/*! RD_ERR - Read error */ +#define FSB_FUSE_STAT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_RD_ERR_SHIFT)) & FSB_FUSE_STAT_RD_ERR_MASK) + +#define FSB_FUSE_STAT_ADDR_ERR_MASK (0x80000000U) +#define FSB_FUSE_STAT_ADDR_ERR_SHIFT (31U) +/*! ADDR_ERR - Address error */ +#define FSB_FUSE_STAT_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_ADDR_ERR_SHIFT)) & FSB_FUSE_STAT_ADDR_ERR_MASK) +/*! @} */ + +/*! @name FUSE_EVNT - Fuse Event Register */ +/*! @{ */ + +#define FSB_FUSE_EVNT_SHDW_ZERO_MASK (0x1000000U) +#define FSB_FUSE_EVNT_SHDW_ZERO_SHIFT (24U) +/*! SHDW_ZERO - Shadow zeroized */ +#define FSB_FUSE_EVNT_SHDW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_SHDW_ZERO_SHIFT)) & FSB_FUSE_EVNT_SHDW_ZERO_MASK) + +#define FSB_FUSE_EVNT_SHDW_UNPROG_MASK (0x2000000U) +#define FSB_FUSE_EVNT_SHDW_UNPROG_SHIFT (25U) +/*! SHDW_UNPROG - Shadow unprogrammed */ +#define FSB_FUSE_EVNT_SHDW_UNPROG(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_SHDW_UNPROG_SHIFT)) & FSB_FUSE_EVNT_SHDW_UNPROG_MASK) + +#define FSB_FUSE_EVNT_FUSE_ERR_MASK (0x4000000U) +#define FSB_FUSE_EVNT_FUSE_ERR_SHIFT (26U) +/*! FUSE_ERR - Fuse error */ +#define FSB_FUSE_EVNT_FUSE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_FUSE_ERR_SHIFT)) & FSB_FUSE_EVNT_FUSE_ERR_MASK) + +#define FSB_FUSE_EVNT_LOADING_MASK (0x8000000U) +#define FSB_FUSE_EVNT_LOADING_SHIFT (27U) +/*! LOADING - Shadow loading */ +#define FSB_FUSE_EVNT_LOADING(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_LOADING_SHIFT)) & FSB_FUSE_EVNT_LOADING_MASK) + +#define FSB_FUSE_EVNT_RLD_ERR_MASK (0x10000000U) +#define FSB_FUSE_EVNT_RLD_ERR_SHIFT (28U) +/*! RLD_ERR - Reload error */ +#define FSB_FUSE_EVNT_RLD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_RLD_ERR_SHIFT)) & FSB_FUSE_EVNT_RLD_ERR_MASK) + +#define FSB_FUSE_EVNT_RD_ERR_MASK (0x20000000U) +#define FSB_FUSE_EVNT_RD_ERR_SHIFT (29U) +/*! RD_ERR - Read error */ +#define FSB_FUSE_EVNT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_RD_ERR_SHIFT)) & FSB_FUSE_EVNT_RD_ERR_MASK) + +#define FSB_FUSE_EVNT_ADDR_ERR_MASK (0x80000000U) +#define FSB_FUSE_EVNT_ADDR_ERR_SHIFT (31U) +/*! ADDR_ERR - Address error */ +#define FSB_FUSE_EVNT_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_ADDR_ERR_SHIFT)) & FSB_FUSE_EVNT_ADDR_ERR_MASK) +/*! @} */ + +/*! @name FUSE_INT_EN - Fuse Interrupt Enable Register */ +/*! @{ */ + +#define FSB_FUSE_INT_EN_INT_EN_MASK (0xFF000000U) +#define FSB_FUSE_INT_EN_INT_EN_SHIFT (24U) +/*! INT_EN - Interrupt Enables */ +#define FSB_FUSE_INT_EN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_INT_EN_INT_EN_SHIFT)) & FSB_FUSE_INT_EN_INT_EN_MASK) +/*! @} */ + +/*! @name FUSE_INT - Fuse Interrupt Register */ +/*! @{ */ + +#define FSB_FUSE_INT_INT_MASK (0xFF000000U) +#define FSB_FUSE_INT_INT_SHIFT (24U) +/*! INT - Interrupts */ +#define FSB_FUSE_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_INT_INT_SHIFT)) & FSB_FUSE_INT_INT_MASK) +/*! @} */ + +/*! @name FUSE - Fuse Value Registers */ +/*! @{ */ + +#define FSB_FUSE_FUSE_MASK (0xFFFFFFFFU) +#define FSB_FUSE_FUSE_SHIFT (0U) +/*! FUSE - Fuse Values */ +#define FSB_FUSE_FUSE(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_FUSE_SHIFT)) & FSB_FUSE_FUSE_MASK) +/*! @} */ + +/* The count of FSB_FUSE */ +#define FSB_FUSE_COUNT (512U) + + +/*! + * @} + */ /* end of group FSB_Register_Masks */ + + +/* FSB - Peripheral instance base addresses */ +/** Peripheral FSB1 base address */ +#define FSB1_BASE (0x47510000u) +/** Peripheral FSB1 base pointer */ +#define FSB1 ((FSB_Type *)FSB1_BASE) +/** Array initializer of FSB peripheral base addresses */ +#define FSB_BASE_ADDRS { FSB1_BASE } +/** Array initializer of FSB peripheral base pointers */ +#define FSB_BASE_PTRS { FSB1 } + +/*! + * @} + */ /* end of group FSB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC_CPU_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_CPU_CTRL_Peripheral_Access_Layer GPC_CPU_CTRL Peripheral Access Layer + * @{ + */ + +/** GPC_CPU_CTRL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t CM_AUTHEN_CTRL; /**< CM Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CM_MISC; /**< Miscellaneous, offset: 0xC */ + __IO uint32_t CM_MODE_CTRL; /**< CPU mode control, offset: 0x10 */ + __I uint32_t CM_MODE_STAT; /**< CM CPU mode Status, offset: 0x14 */ + __I uint32_t CM_PIN_STAT; /**< CM pin Status, offset: 0x18 */ + uint8_t RESERVED_2[228]; + __IO uint32_t CM_IRQ_WAKEUP_MASK_0; /**< CM IRQ0~31 wakeup mask, offset: 0x100 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_1; /**< CM IRQ32~63 wakeup mask, offset: 0x104 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_2; /**< CM IRQ64~95 wakeup mask, offset: 0x108 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_3; /**< CM IRQ96~127 wakeup mask, offset: 0x10C */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_4; /**< CM IRQ128~159 wakeup mask, offset: 0x110 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_5; /**< CM IRQ160~191 wakeup mask, offset: 0x114 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_6; /**< CM IRQ192~223 wakeup mask, offset: 0x118 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_7; /**< CM IRQ224~255 wakeup mask, offset: 0x11C */ + uint8_t RESERVED_3[32]; + __IO uint32_t CM_NON_IRQ_WAKEUP_MASK; /**< CM non-IRQ wakeup mask, offset: 0x140 */ + uint8_t RESERVED_4[12]; + __I uint32_t CM_IRQ_WAKEUP_STAT_0; /**< CM IRQ0~31 wakeup status, offset: 0x150 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_1; /**< CM IRQ32~63 wakeup status, offset: 0x154 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_2; /**< CM IRQ64~95 wakeup status, offset: 0x158 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_3; /**< CM IRQ96~127 wakeup status, offset: 0x15C */ + __I uint32_t CM_IRQ_WAKEUP_STAT_4; /**< CM IRQ128~159 wakeup status, offset: 0x160 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_5; /**< CM IRQ160~191 wakeup status, offset: 0x164 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_6; /**< CM IRQ192~223 wakeup status, offset: 0x168 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_7; /**< CM IRQ224~255 wakeup status, offset: 0x16C */ + uint8_t RESERVED_5[32]; + __I uint32_t CM_NON_IRQ_WAKEUP_STAT; /**< CM non-IRQ wakeup status, offset: 0x190 */ + uint8_t RESERVED_6[108]; + __IO uint32_t CM_SLEEP_A55_HDSK_CTRL; /**< CM sleep A55_HDSK control, offset: 0x200 */ + uint8_t RESERVED_7[4]; + __IO uint32_t CM_SLEEP_SSAR_CTRL; /**< CM sleep SSAR control, offset: 0x208 */ + uint8_t RESERVED_8[4]; + __IO uint32_t CM_SLEEP_LPCG_CTRL; /**< CM sleep LPCG control, offset: 0x210 */ + uint8_t RESERVED_9[4]; + __IO uint32_t CM_SLEEP_PLL_CTRL; /**< CM sleep PLL control, offset: 0x218 */ + uint8_t RESERVED_10[4]; + __IO uint32_t CM_SLEEP_ISO_CTRL; /**< CM sleep isolation control, offset: 0x220 */ + uint8_t RESERVED_11[4]; + __IO uint32_t CM_SLEEP_MEM_CTRL; /**< CM sleep memory control, offset: 0x228 */ + uint8_t RESERVED_12[4]; + __IO uint32_t CM_SLEEP_RESET_CTRL; /**< CM sleep reset control, offset: 0x230 */ + uint8_t RESERVED_13[4]; + __IO uint32_t CM_SLEEP_POWER_CTRL; /**< CM sleep power control, offset: 0x238 */ + uint8_t RESERVED_14[4]; + __IO uint32_t CM_SLEEP_RSV2_CTRL; /**< CM sleep rsv2 control, offset: 0x240 */ + uint8_t RESERVED_15[68]; + __IO uint32_t CM_WAKEUP_RSV2_CTRL; /**< CM wakeup rsv2 control, offset: 0x288 */ + uint8_t RESERVED_16[4]; + __IO uint32_t CM_WAKEUP_POWER_CTRL; /**< CM wakeup power control, offset: 0x290 */ + uint8_t RESERVED_17[4]; + __IO uint32_t CM_WAKEUP_MEM_CTRL; /**< CM wakeup memory control, offset: 0x298 */ + uint8_t RESERVED_18[4]; + __IO uint32_t CM_WAKEUP_RESET_CTRL; /**< CM wakeup reset control, offset: 0x2A0 */ + uint8_t RESERVED_19[4]; + __IO uint32_t CM_WAKEUP_ISO_CTRL; /**< CM wakeup isolation control, offset: 0x2A8 */ + uint8_t RESERVED_20[4]; + __IO uint32_t CM_WAKEUP_PLL_CTRL; /**< CM wakeup PLL control, offset: 0x2B0 */ + uint8_t RESERVED_21[4]; + __IO uint32_t CM_WAKEUP_LPCG_CTRL; /**< CM wakeup LPCG control, offset: 0x2B8 */ + uint8_t RESERVED_22[4]; + __IO uint32_t CM_WAKEUP_MTR_CTRL; /**< CM wakeup MTR control, offset: 0x2C0 */ + uint8_t RESERVED_23[4]; + __IO uint32_t CM_WAKEUP_SSAR_CTRL; /**< CM wakeup SSAR control, offset: 0x2C8 */ + uint8_t RESERVED_24[4]; + __IO uint32_t CM_WAKEUP_A55_HDSK_CTRL; /**< CM wakeup A55_HDSK control, offset: 0x2D0 */ + uint8_t RESERVED_25[172]; + __IO uint32_t CM_SYS_SLEEP_CTRL; /**< CM system sleep control, offset: 0x380 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CM_DEBUG; /**< CM debug, offset: 0x390 */ +} GPC_CPU_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- GPC_CPU_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_CPU_CTRL_Register_Masks GPC_CPU_CTRL Register Masks + * @{ + */ + +/*! @name CM_AUTHEN_CTRL - CM Authentication Control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..The value of low power configuration fields are not locked. + * 0b1..The value of low power configuration fields are locked. It locks the CPUx_CM registers which are marked + * as "Locked by LOCK_CFG field" in the function field. + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x100U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (8U) +/*! USER - Allow user mode access + * 0b0..Allow only privilege mode to access CPU mode control registers + * 0b1..Allow both privilege and user mode to access CPU mode control registers + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x200U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (9U) +/*! NONSECURE - Allow non-secure mode access + * 0b0..Allow only secure mode to access CPU mode control + * 0b1..Allow both secure and non-secure mode to access CPU mode control registers + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U) +/*! LOCK_SETTING - Lock NONSECURE and USER + * 0b0..NONSECURE and USER fields are not locked + * 0b1..NONSECURE and USER fields are locked + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST is not locked + * 0b1..WHITE_LIST is locked + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name CM_MISC - Miscellaneous */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_MISC_NMI_STAT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_MISC_NMI_STAT_SHIFT (0U) +/*! NMI_STAT - Non-masked interrupt status + * 0b0..NMI is not asserted + * 0b1..NMI is asserted + */ +#define GPC_CPU_CTRL_CM_MISC_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_NMI_STAT_MASK) + +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U) +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U) +/*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status + * 0b0..Disable cpu_sleep_hold_req + * 0b1..Allow cpu_sleep_hold_req to assert during CPU low power status + */ +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK) + +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U) +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U) +/*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b + * 0b0..CPU sleep hold is acknowledged + * 0b1..CPU is not in sleep hold + */ +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK) + +#define GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_MASK (0x10U) +#define GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_SHIFT (4U) +/*! GIC_WAKEUP_STAT - GIC wakeup request status */ +#define GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_MASK) + +#define GPC_CPU_CTRL_CM_MISC_IRQ_MUX_MASK (0x20U) +#define GPC_CPU_CTRL_CM_MISC_IRQ_MUX_SHIFT (5U) +/*! IRQ_MUX - IRQ select + * 0b0..From raw IRQ + * 0b1..From GIC + */ +#define GPC_CPU_CTRL_CM_MISC_IRQ_MUX(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_IRQ_MUX_SHIFT)) & GPC_CPU_CTRL_CM_MISC_IRQ_MUX_MASK) + +#define GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_MASK (0x40U) +#define GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_SHIFT (6U) +/*! SW_WAKEUP - software wakeup. Used for CPU hotplug. */ +#define GPC_CPU_CTRL_CM_MISC_SW_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_MASK) +/*! @} */ + +/*! @name CM_MODE_CTRL - CPU mode control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U) +#define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U) +/*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event + * 0b00..Stay in RUN mode + * 0b01..Transit to WAIT mode + * 0b10..Transit to STOP mode + * 0b11..Transit to SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK) +/*! @} */ + +/*! @name CM_MODE_STAT - CM CPU mode Status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U) +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U) +/*! CPU_MODE_CURRENT - Current CPU mode + * 0b00..CPU is currently in RUN mode + * 0b01..CPU is currently in WAIT mode + * 0b10..CPU is currently in STOP mode + * 0b11..CPU is currently in SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU) +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U) +/*! CPU_MODE_PREVIOUS - Previous CPU mode + * 0b00..CPU was previously in RUN mode + * 0b01..CPU was previously in WAIT mode + * 0b10..CPU was previously in STOP mode + * 0b11..CPU was previously in SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_MASK (0x100U) +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT (8U) +/*! SLEEP_TRANS_BUSY - Busy on CPU mode transition of sleep, not include set point trans busy. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_MASK (0x200U) +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT (9U) +/*! WAKEUP_TRANS_BUSY - Busy on CPU mode transition of wakeup, not include set point trans busy. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_MASK (0x400U) +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_SHIFT (10U) +/*! SLEEPING_IDLE - Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_MASK (0x10000U) +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_SHIFT (16U) +/*! SLEEP_REQUEST - Status of sleep_request input port */ +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_MASK (0x40000U) +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_SHIFT (18U) +/*! WAKEUP_REQUEST - "ORed" of all unmasked IRQ in. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_MASK (0x1F000000U) +#define GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_SHIFT (24U) +/*! FSM_STATE - CPU mode trans FSM state. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_MASK) +/*! @} */ + +/*! @name CM_PIN_STAT - CM pin Status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT (0U) +/*! A55_HDSK_REQUEST_STAT - cpu_mode_trans_a55_hdsk_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_MASK (0x2U) +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_SHIFT (1U) +/*! SSAR_REQUEST_STAT - cpu_mode_trans_ssar_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_MASK (0x4U) +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_SHIFT (2U) +/*! LPCG_REQUEST_STAT - cpu_mode_trans_lpcg_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_MASK (0x8U) +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_SHIFT (3U) +/*! PLL_REQUEST_STAT - cpu_mode_trans_pll_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_MASK (0x10U) +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_SHIFT (4U) +/*! ISO_REQUEST_STAT - cpu_mode_trans_iso_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_MASK (0x20U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_SHIFT (5U) +/*! MEM_REQUEST_STAT - cpu_mode_trans_mem_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_MASK (0x40U) +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_SHIFT (6U) +/*! RESET_REQUEST_STAT - cpu_mode_trans_reset_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_MASK (0x80U) +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_SHIFT (7U) +/*! POWER_REQUEST_STAT - cpu_mode_trans_power_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_MASK (0x100U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_SHIFT (8U) +/*! MTR_REQUEST_STAT - cpu_mode_trans_mtr_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_MASK (0x10000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT (16U) +/*! A55_HDSK_DONE_STAT - cpu_mode_trans_a55_hdsk_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_MASK (0x20000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_SHIFT (17U) +/*! SSAR_DONE_STAT - cpu_mode_trans_ssar_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_MASK (0x40000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_SHIFT (18U) +/*! LPCG_DONE_STAT - cpu_mode_trans_lpcg_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_MASK (0x80000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_SHIFT (19U) +/*! PLL_DONE_STAT - cpu_mode_trans_pll_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_MASK (0x100000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_SHIFT (20U) +/*! ISO_DONE_STAT - cpu_mode_trans_iso_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_MASK (0x200000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_SHIFT (21U) +/*! MEM_DONE_STAT - cpu_mode_trans_mem_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_MASK (0x400000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_SHIFT (22U) +/*! RESET_DONE_STAT - cpu_mode_trans_reset_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_MASK (0x800000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_SHIFT (23U) +/*! POWER_DONE_STAT - cpu_mode_trans_power_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_MASK (0x1000000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_SHIFT (24U) +/*! MTR_DONE_STAT - cpu_mode_trans_mtr_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_MASK (0x60000000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_SHIFT (29U) +/*! CPU_MODE_STAT - cpu_power_mode pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT (31U) +/*! DEBUG_WAKEUP_ACK_STAT - debug wakeup acknowledge pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_0 - CM IRQ0~31 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_1 - CM IRQ32~63 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_2 - CM IRQ64~95 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_3 - CM IRQ96~127 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_4 - CM IRQ128~159 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_5 - CM IRQ160~191 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_6 - CM IRQ192~223 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_7 - CM IRQ224~255 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_MASK) +/*! @} */ + +/*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-IRQ wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U) +/*! EVENT_WAKEUP_MASK - "1" means the event cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK) + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U) +/*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_0 - CM IRQ0~31 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_0_31 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_1 - CM IRQ32~63 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_32_63 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_2 - CM IRQ64~95 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_64_95 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_3 - CM IRQ96~127 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_96_127 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_4 - CM IRQ128~159 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_128_159 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_5 - CM IRQ160~191 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_160_191 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_6 - CM IRQ192~223 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_192_223 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_7 - CM IRQ224~255 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_224_255 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_MASK) +/*! @} */ + +/*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-IRQ wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U) +/*! EVENT_WAKEUP_STAT - Event wakeup status + * 0b0..No event wakeup is requested + * 0b1..Event wakeup is requested + */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK) + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U) +/*! DEBUG_WAKEUP_STAT - Debug wakeup status + * 0b0..No debug wakeup is requested + * 0b1..Debug wakeup is requested + */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK) +/*! @} */ + +/*! @name CM_SLEEP_A55_HDSK_CTRL - CM sleep A55_HDSK control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE. */ +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE. */ +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_MEM_CTRL - CM sleep memory control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_RSV2_CTRL - CM sleep rsv2 control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_RSV2_CTRL - CM wakeup rsv2 control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_MEM_CTRL - CM wakeup memory control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_MTR_CTRL - CM wakeup MTR control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_A55_HDSK_CTRL - CM wakeup A55_HDSK control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SYS_SLEEP_CTRL - CM system sleep control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_SHIFT (0U) +/*! SS_WAIT - Request system sleep when CPU is in WAIT mode + * 0b0..Do not request system sleep when CPU is in WAIT mode + * 0b1..Request system sleep when CPU is in WAIT mode + */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_MASK (0x2U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_SHIFT (1U) +/*! SS_STOP - Request system sleep when CPU is in STOP mode + * 0b0..Do not request system sleep when CPU is in STOP mode + * 0b1..Request system sleep when CPU is in STOP mode + */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_MASK (0x4U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT (2U) +/*! SS_SUSPEND - Request system sleep when CPU is in SUSPEND mode + * 0b0..Do not request system sleep when CPU is in SUSPEND mode + * 0b1..Request system sleep when CPU is in SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_MASK (0x10000U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT (16U) +/*! SYS_SLEEP_BUSY - Indicates the CPU is busy entering system sleep mode. */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_MASK (0x20000U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT (17U) +/*! SYS_WAKEUP_BUSY - Indicates the CPU is busy exiting system sleep mode. */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_MASK) +/*! @} */ + +/*! @name CM_DEBUG - CM debug */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_MASK (0x1U) +#define GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_SHIFT (0U) +/*! PRETEND_SLEEP - Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */ +#define GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_SHIFT)) & GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_CPU_CTRL_Register_Masks */ + + +/* GPC_CPU_CTRL - Peripheral instance base addresses */ +/** Peripheral GPC__GPC_CTRL_CA55_0 base address */ +#define GPC__GPC_CTRL_CA55_0_BASE (0x44470800u) +/** Peripheral GPC__GPC_CTRL_CA55_0 base pointer */ +#define GPC__GPC_CTRL_CA55_0 ((GPC_CPU_CTRL_Type *)GPC__GPC_CTRL_CA55_0_BASE) +/** Peripheral GPC__GPC_CTRL_CA55_CLUSTER base address */ +#define GPC__GPC_CTRL_CA55_CLUSTER_BASE (0x44471800u) +/** Peripheral GPC__GPC_CTRL_CA55_CLUSTER base pointer */ +#define GPC__GPC_CTRL_CA55_CLUSTER ((GPC_CPU_CTRL_Type *)GPC__GPC_CTRL_CA55_CLUSTER_BASE) +/** Array initializer of GPC_CPU_CTRL peripheral base addresses */ +#define GPC_CPU_CTRL_BASE_ADDRS { GPC__GPC_CTRL_CA55_0_BASE, GPC__GPC_CTRL_CA55_CLUSTER_BASE } +/** Array initializer of GPC_CPU_CTRL peripheral base pointers */ +#define GPC_CPU_CTRL_BASE_PTRS { GPC__GPC_CTRL_CA55_0, GPC__GPC_CTRL_CA55_CLUSTER } + +/*! + * @} + */ /* end of group GPC_CPU_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC_GLOBAL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_GLOBAL_Peripheral_Access_Layer GPC_GLOBAL Peripheral Access Layer + * @{ + */ + +/** GPC_GLOBAL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t AUTHEN_CTRL; /**< GPC Global Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t GPC_DOMAIN; /**< GPC domain assignment, offset: 0x10 */ + uint8_t RESERVED_2[8]; + __IO uint32_t GPC_MASTER; /**< GPC master CPU configuration, offset: 0x1C */ + uint8_t RESERVED_3[32]; + __IO uint32_t GPC_SYS_SLEEP; /**< GPC system sleep control, offset: 0x40 */ + uint8_t RESERVED_4[188]; + __IO uint32_t PMIC_CTRL; /**< PMIC standby control, offset: 0x100 */ + __IO uint32_t PMIC_PRE_DLY_CTRL; /**< PMIC standby pre delay control, offset: 0x104 */ + __IO uint32_t PMIC_STBY_ACK_CTRL; /**< PMIC standby acknowledge control, offset: 0x108 */ + uint8_t RESERVED_5[244]; + __IO uint32_t GPC_ROSC_CTRL; /**< RCOSC control, offset: 0x200 */ + __IO uint32_t GPC_AON_MEM_CTRL; /**< AON Memory control, offset: 0x204 */ + __IO uint32_t GPC_EFUSE_CTRL; /**< eFUSE control, offset: 0x208 */ +} GPC_GLOBAL_Type; + +/* ---------------------------------------------------------------------------- + -- GPC_GLOBAL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_GLOBAL_Register_Masks GPC_GLOBAL Register Masks + * @{ + */ + +/*! @name AUTHEN_CTRL - GPC Global Authentication Control */ +/*! @{ */ + +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..The value of low power configuration fields are not locked. + * 0b1..The value of low power configuration fields are locked. Refer to the function field of each gpc_global registers. + */ +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_USER_MASK (0x100U) +#define GPC_GLOBAL_AUTHEN_CTRL_USER_SHIFT (8U) +/*! USER - Allow user mode access + * 0b0..Allow only privilege mode to access CPU mode control registers + * 0b1..Allow both privilege and user mode to access CPU mode control registers + */ +#define GPC_GLOBAL_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_USER_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_USER_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_MASK (0x200U) +#define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_SHIFT (9U) +/*! NONSECURE - Allow non-secure mode access + * 0b0..Allow only secure mode to access CPU mode registers + * 0b1..Allow both secure and non-secure mode to access CPU mode control registers. + */ +#define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U) +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U) +/*! LOCK_SETTING - Lock NONSECURE and USER + * 0b0..NONSECURE and USER fields are not locked + * 0b1..NONSECURE and USER fields are locked + */ +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST is not locked + * 0b1..WHITE_LIST is locked + */ +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list */ +#define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPC_DOMAIN - GPC domain assignment */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_MASK (0xFU) +#define GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_SHIFT (0U) +/*! CPU0_DOMAIN - CPU0 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_MASK) + +#define GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_MASK (0xF0U) +#define GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_SHIFT (4U) +/*! CPU1_DOMAIN - CPU1 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_MASK) + +#define GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_MASK (0xF00U) +#define GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_SHIFT (8U) +/*! CPU2_DOMAIN - CPU2 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_MASK) + +#define GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_MASK (0xF000U) +#define GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_SHIFT (12U) +/*! CPU3_DOMAIN - CPU3 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_MASK) +/*! @} */ + +/*! @name GPC_MASTER - GPC master CPU configuration */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_MASK (0x1U) +#define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_SHIFT (0U) +/*! CPU0_MASTER - Setting to 1 means CPU0 is the master CPU of its domain + * 0b0..CPU0 is not the master CPU of its domain + * 0b1..CPU0 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_MASK) + +#define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_MASK (0x2U) +#define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_SHIFT (1U) +/*! CPU1_MASTER - Setting to 1 means CPU1 is the master CPU of its domain + * 0b0..CPU1 is not the master CPU of its domain + * 0b1..CPU1 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_MASK) + +#define GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_MASK (0x4U) +#define GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_SHIFT (2U) +/*! CPU2_MASTER - Setting to 1 means CPU2 is the master CPU of its domain + * 0b0..CPU2 is not the master CPU of its domain + * 0b1..CPU2 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU2_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_MASK) + +#define GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_MASK (0x8U) +#define GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_SHIFT (3U) +/*! CPU3_MASTER - Setting to 1 means CPU3 is the master CPU of its domain + * 0b0..CPU3 is not the master CPU of its domain + * 0b1..CPU3 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU3_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_MASK) +/*! @} */ + +/*! @name GPC_SYS_SLEEP - GPC system sleep control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_MASK (0x10000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_SHIFT (16U) +/*! FORCE_CPU0_DISABLE - Force CPU0 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_MASK) + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_MASK (0x20000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_SHIFT (17U) +/*! FORCE_CPU1_DISABLE - Force CPU1 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_MASK) + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_MASK (0x40000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_SHIFT (18U) +/*! FORCE_CPU2_DISABLE - Force CPU2 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_MASK) + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_MASK (0x80000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_SHIFT (19U) +/*! FORCE_CPU3_DISABLE - Force CPU3 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_MASK) +/*! @} */ + +/*! @name PMIC_CTRL - PMIC standby control */ +/*! @{ */ + +#define GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_MASK (0x1U) +#define GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_SHIFT (0U) +/*! PMIC_STBY_EN - Assert the PMIC_STBY_REQ when system sleep */ +#define GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_SHIFT)) & GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_MASK) +/*! @} */ + +/*! @name PMIC_PRE_DLY_CTRL - PMIC standby pre delay control */ +/*! @{ */ + +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_MASK (0xFFFFU) +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_SHIFT (0U) +/*! DLY_PRE_STBY_ON - Delay before pmic_standby on. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_SHIFT)) & GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_MASK) + +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_MASK (0xFFFF0000U) +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_SHIFT (16U) +/*! DLY_PRE_STBY_OFF - Delay before pmic_standby off. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_SHIFT)) & GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_MASK) +/*! @} */ + +/*! @name PMIC_STBY_ACK_CTRL - PMIC standby acknowledge control */ +/*! @{ */ + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK (0xFFFU) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT (0U) +/*! STBY_ON_CNT_CFG - PMIC standby on acknowledge count configure. Usage depends on STBY_ON_CNT_MODE. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK) + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK (0xC000U) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT (14U) +/*! STBY_ON_CNT_MODE - PMIC standby on acknowledge count mode. Locked by LOCK_CFG field. + * 0b00..Finish the process once pmic_standby signal changes + * 0b01..Finish the process once getting acknowledge from PMIC + * 0b10..Ignore PMIC acknowledge, the delay counter starts to count once pmic_standby changes + * 0b11..Time out mode, the counter starts to count once pmic_standby changes, then finishes the process when + * either acknowledge received or counting to CNT_CFG value + */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK) + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK (0xFFF0000U) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT (16U) +/*! STBY_OFF_CNT_CFG - PMIC standby off acknowledge count configure. Usage depends on STBY_OFF_CNT_MODE. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK) + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK (0xC0000000U) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT (30U) +/*! STBY_OFF_CNT_MODE - PMIC standby off acknowledge count mode. Locked by LOCK_CFG field. + * 0b00..Finish the process once pmic_standby signal changes + * 0b01..Finish the process once getting acknowledge from PMIC + * 0b10..Ignore PMIC acknowledge, the delay counter starts to count once pmic_standby changes + * 0b11..Time out mode, the counter starts to count once pmic_standby changes, then finishes the process when + * either acknowledge received or counting to CNT_CFG value + */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK) +/*! @} */ + +/*! @name GPC_ROSC_CTRL - RCOSC control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK (0x1U) +#define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT (0U) +/*! ROSC_OFF_EN - Shut off the 24 MHz RCOSC clock when system sleep */ +#define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT)) & GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK) +/*! @} */ + +/*! @name GPC_AON_MEM_CTRL - AON Memory control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_MASK (0x1U) +#define GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_SHIFT (0U) +/*! AON_MEM_LP_EN - AON memory enter LP enable */ +#define GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_SHIFT)) & GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_MASK) +/*! @} */ + +/*! @name GPC_EFUSE_CTRL - eFUSE control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_MASK (0x1U) +#define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_SHIFT (0U) +/*! EFUSE_PD_EN - eFUSE power down enable */ +#define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_SHIFT)) & GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_GLOBAL_Register_Masks */ + + +/* GPC_GLOBAL - Peripheral instance base addresses */ +/** Peripheral GPC__GPC_GLOBAL base address */ +#define GPC__GPC_GLOBAL_BASE (0x44474000u) +/** Peripheral GPC__GPC_GLOBAL base pointer */ +#define GPC__GPC_GLOBAL ((GPC_GLOBAL_Type *)GPC__GPC_GLOBAL_BASE) +/** Array initializer of GPC_GLOBAL peripheral base addresses */ +#define GPC_GLOBAL_BASE_ADDRS { GPC__GPC_GLOBAL_BASE } +/** Array initializer of GPC_GLOBAL peripheral base pointers */ +#define GPC_GLOBAL_BASE_PTRS { GPC__GPC_GLOBAL } + +/*! + * @} + */ /* end of group GPC_GLOBAL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ + __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ + __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ + __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ + __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ + __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ + __IO uint32_t TDR[2]; /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_0[24]; + __I uint32_t TFR[2]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[24]; + __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TTCR; /**< Transmit Timestamp Control, offset: 0x70 */ + __I uint32_t TTSR; /**< Transmit Timestamp, offset: 0x74 */ + __I uint32_t TBCR; /**< Transmit Bit Count, offset: 0x78 */ + __I uint32_t TBCTR; /**< Transmit Bit Count Timestamp, offset: 0x7C */ + uint8_t RESERVED_3[8]; + __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ + __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ + __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ + __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ + __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ + __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ + __I uint32_t RDR[2]; /**< Receive Data, array offset: 0xA0, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_4[24]; + __I uint32_t RFR[2]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_5[24]; + __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t RTCR; /**< Receive Timestamp Control, offset: 0xF0 */ + __I uint32_t RTSR; /**< Receive Timestamp, offset: 0xF4 */ + __I uint32_t RBCR; /**< Receive Bit Count, offset: 0xF8 */ + __I uint32_t RBCTR; /**< Receive Bit Count Timestamp, offset: 0xFC */ + __IO uint32_t MCR; /**< MCLK Control, offset: 0x100 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + * 0b0000000000000010..Standard feature set with timestamp registers + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) + +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) + +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +/*! DATALINE - Number of Data Lines */ +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) + +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +/*! FIFO - FIFO Size */ +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) + +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +/*! FRAME - Frame Size */ +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - Transmit Control */ +/*! @{ */ + +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) + +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) + +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) + +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) + +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) + +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) + +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) + +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) + +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) + +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) + +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) + +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) + +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) + +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) + +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) + +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) + +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) + +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - Transmit Configuration 1 */ +/*! @{ */ + +#define I2S_TCR1_TFW_MASK (0x7FU) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +#define I2S_TCR1_TFW_SHIFT (0U) +/*! TFW - Transmit FIFO Watermark + * 0b0000000..1 + * 0b0000001..2 + * 0b0000010-0b1111110..(TFW +1) + * 0b1111111..128 + */ +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +/*! @} */ + +/*! @name TCR2 - Transmit Configuration 2 */ +/*! @{ */ + +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) + +#define I2S_TCR2_BYP_MASK (0x800000U) +#define I2S_TCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) + +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generate externally in Target mode + * 0b1..Generate internally in Controller mode + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) + +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) + +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) + +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) + +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) + +#define I2S_TCR2_SYNC_MASK (0x40000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b0..Asynchronous mode + * 0b1..Synchronous with receiver + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - Transmit Configuration 3 */ +/*! @{ */ + +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration */ +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) + +#define I2S_TCR3_TCE_MASK (0x30000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable */ +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ + +#define I2S_TCR3_CFR_MASK (0x3000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - Transmit Configuration 4 */ +/*! @{ */ + +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) + +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) + +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated after the FIFO warning flag is cleared + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) + +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) + +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) + +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode + * 0b1..Output mode + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) + +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width */ +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) + +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size */ +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable FIFO packing + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) + +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO reads (from transmit shift registers) + * 0b10..Enable on FIFO writes (by software) + * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) + +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..Continue from the start of the next frame + * 0b1..Continue from the same word that caused the FIFO error + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - Transmit Configuration 5 */ +/*! @{ */ + +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT + * 0b11111..31 + */ +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) + +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) + +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +/*! TDR - Transmit Data */ +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (2U) + +/*! @name TFR - Transmit FIFO */ +/*! @{ */ + +#define I2S_TFR_RFP_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_TFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ + +#define I2S_TFR_WFP_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_TFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ + +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be written + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (2U) + +/*! @name TMR - Transmit Mask */ +/*! @{ */ + +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name TTCR - Transmit Timestamp Control */ +/*! @{ */ + +#define I2S_TTCR_TSEN_MASK (0x1U) +#define I2S_TTCR_TSEN_SHIFT (0U) +/*! TSEN - Timestamp Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK) + +#define I2S_TTCR_TSINC_MASK (0x2U) +#define I2S_TTCR_TSINC_SHIFT (1U) +/*! TSINC - Timestamp Increment + * 0b0..When enabled and after the bit counter has incremented + * 0b1..When enabled + */ +#define I2S_TTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK) + +#define I2S_TTCR_TSSEL_MASK (0xCU) +#define I2S_TTCR_TSSEL_SHIFT (2U) +/*! TSSEL - Timestamp Select + * 0b00..Increment when enabled + * 0b01..Increment when the receive timestamp counter is enabled + * 0b10..Increment when the transmit timestamp counter on another instance is enabled + * 0b11..Increment when the receive timestamp counter on another instance is enabled + */ +#define I2S_TTCR_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSSEL_SHIFT)) & I2S_TTCR_TSSEL_MASK) + +#define I2S_TTCR_RTSC_MASK (0x100U) +#define I2S_TTCR_RTSC_SHIFT (8U) +/*! RTSC - Reset Timestamp Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_TTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK) + +#define I2S_TTCR_RBC_MASK (0x200U) +#define I2S_TTCR_RBC_SHIFT (9U) +/*! RBC - Reset Bit Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_TTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK) +/*! @} */ + +/*! @name TTSR - Transmit Timestamp */ +/*! @{ */ + +#define I2S_TTSR_TSC_MASK (0xFFFFFFFFU) +#define I2S_TTSR_TSC_SHIFT (0U) +/*! TSC - Timestamp Counter */ +#define I2S_TTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK) +/*! @} */ + +/*! @name TBCR - Transmit Bit Count */ +/*! @{ */ + +#define I2S_TBCR_BCNT_MASK (0xFFFFFFFFU) +#define I2S_TBCR_BCNT_SHIFT (0U) +/*! BCNT - Bit Counter */ +#define I2S_TBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK) +/*! @} */ + +/*! @name TBCTR - Transmit Bit Count Timestamp */ +/*! @{ */ + +#define I2S_TBCTR_BCTS_MASK (0xFFFFFFFFU) +#define I2S_TBCTR_BCTS_SHIFT (0U) +/*! BCTS - Bit Timestamp */ +#define I2S_TBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK) +/*! @} */ + +/*! @name RCSR - Receive Control */ +/*! @{ */ + +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) + +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) + +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) + +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) + +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) + +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) + +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) + +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) + +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not full + * 0b1..Full + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) + +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Receive overflow detected + * 0b1..Clear the flag + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) + +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) + +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) + +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) + +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) + +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) + +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable after completing the current frame + * 0b1..Enable + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) + +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) + +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable (or receiver disabled and not yet reached end of frame) + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - Receive Configuration 1 */ +/*! @{ */ + +#define I2S_RCR1_RFW_MASK (0x7FU) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +#define I2S_RCR1_RFW_SHIFT (0U) +/*! RFW - Receive FIFO Watermark + * 0b0000000..1 + * 0b0000001..2 + * 0b0000010-0b1111110..(RFW value + 1) + * 0b1111111..128 + */ +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +/*! @} */ + +/*! @name RCR2 - Receive Configuration 2 */ +/*! @{ */ + +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) + +#define I2S_RCR2_BYP_MASK (0x800000U) +#define I2S_RCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) + +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) + +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) + +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) + +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) + +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) + +#define I2S_RCR2_SYNC_MASK (0x40000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b0..Asynchronous mode + * 0b1..Synchronous with transmitter + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - Receive Configuration 3 */ +/*! @{ */ + +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + * 0b00000..Word 1 + * 0b00001..Word 2 + * 0b00010-0b11110..Word (WDFL value + 1) + * 0b11111..Word 32 + */ +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) + +#define I2S_RCR3_RCE_MASK (0x30000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable */ +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ + +#define I2S_RCR3_CFR_MASK (0x3000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - Receive Configuration 4 */ +/*! @{ */ + +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) + +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) + +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated when the FIFO warning flag is 0 + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) + +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) + +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) + +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(SYWD value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) + +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(FRSZ value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) + +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO writes (from receive shift registers) + * 0b10..Enable on FIFO reads (by software) + * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) + +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..From the start of the next frame after the FIFO error flag is cleared + * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - Receive Configuration 5 */ +/*! @{ */ + +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT value + * 0b11111..31 + */ +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) + +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) + +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +/*! RDR - Receive Data */ +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (2U) + +/*! @name RFR - Receive FIFO */ +/*! @{ */ + +#define I2S_RFR_RFP_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_RFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ + +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Read Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be read + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) + +#define I2S_RFR_WFP_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_RFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (2U) + +/*! @name RMR - Receive Mask */ +/*! @{ */ + +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + +/*! @name RTCR - Receive Timestamp Control */ +/*! @{ */ + +#define I2S_RTCR_TSEN_MASK (0x1U) +#define I2S_RTCR_TSEN_SHIFT (0U) +/*! TSEN - Timestamp Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK) + +#define I2S_RTCR_TSINC_MASK (0x2U) +#define I2S_RTCR_TSINC_SHIFT (1U) +/*! TSINC - Timestamp Increment + * 0b0..When enabled and after the bit counter has incremented + * 0b1..When enabled + */ +#define I2S_RTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK) + +#define I2S_RTCR_TSSEL_MASK (0xCU) +#define I2S_RTCR_TSSEL_SHIFT (2U) +/*! TSSEL - Timestamp Select + * 0b00..Increment when enabled + * 0b01..Increment when the transmit timestamp counter is enabled + * 0b10..Increment when the receive timestamp counter on another instance is enabled + * 0b11..Increment when the transmit timestamp counter on another instance is enabled + */ +#define I2S_RTCR_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSSEL_SHIFT)) & I2S_RTCR_TSSEL_MASK) + +#define I2S_RTCR_RTSC_MASK (0x100U) +#define I2S_RTCR_RTSC_SHIFT (8U) +/*! RTSC - Reset Timestamp Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK) + +#define I2S_RTCR_RBC_MASK (0x200U) +#define I2S_RTCR_RBC_SHIFT (9U) +/*! RBC - Reset Bit Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK) +/*! @} */ + +/*! @name RTSR - Receive Timestamp */ +/*! @{ */ + +#define I2S_RTSR_TSC_MASK (0xFFFFFFFFU) +#define I2S_RTSR_TSC_SHIFT (0U) +/*! TSC - Timestamp Counter */ +#define I2S_RTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK) +/*! @} */ + +/*! @name RBCR - Receive Bit Count */ +/*! @{ */ + +#define I2S_RBCR_BCNT_MASK (0xFFFFFFFFU) +#define I2S_RBCR_BCNT_SHIFT (0U) +/*! BCNT - Bit Counter */ +#define I2S_RBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK) +/*! @} */ + +/*! @name RBCTR - Receive Bit Count Timestamp */ +/*! @{ */ + +#define I2S_RBCTR_BCTS_MASK (0xFFFFFFFFU) +#define I2S_RBCTR_BCTS_SHIFT (0U) +/*! BCTS - Bit Timestamp */ +#define I2S_RBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK) +/*! @} */ + +/*! @name MCR - MCLK Control */ +/*! @{ */ + +#define I2S_MCR_DIV_MASK (0xFFU) +#define I2S_MCR_DIV_SHIFT (0U) +/*! DIV - MCLK Post Divide */ +#define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) + +#define I2S_MCR_DIVEN_MASK (0x800000U) +#define I2S_MCR_DIVEN_SHIFT (23U) +/*! DIVEN - MCLK Post Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) + +#define I2S_MCR_MSEL_MASK (0x3000000U) +#define I2S_MCR_MSEL_SHIFT (24U) +/*! MSEL - MCLK Select + * 0b00..Controller clock (MCLK) option 1 + * 0b01..Reserved + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) + +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +/*! MOE - MCLK Output Enable + * 0b0..Input + * 0b1..Output + */ +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral SAI1 base address */ +#define SAI1_BASE (0x443B0000u) +/** Peripheral SAI1 base pointer */ +#define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x42650000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) +/** Peripheral SAI3 base address */ +#define SAI3_BASE (0x42660000u) +/** Peripheral SAI3 base pointer */ +#define SAI3 ((I2S_Type *)SAI3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ + uint8_t RESERVED_2[8]; + union { /* offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ + }; + uint8_t RESERVED_3[4]; + __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ + uint8_t RESERVED_4[4]; + __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ + __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ + __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ + uint8_t RESERVED_5[8]; + __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ + union { /* offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ + __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ + }; + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_7[4]; + __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_8[24]; + __IO uint32_t SRSTACTTIME; /**< Timing Rules for Target Reset Recovery, offset: 0x100 */ + uint8_t RESERVED_9[8]; + __IO uint32_t SCCCMASK; /**< CCC Mask for Unhandled CCCs, offset: 0x10C */ + __IO uint32_t SERRWARNMASK; /**< Target Errors and Warnings Mask, offset: 0x110 */ + uint8_t RESERVED_10[8]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + __IO uint32_t SMAPCTRL1; /**< Map Feature Control 1, offset: 0x120 */ + uint8_t RESERVED_11[28]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_12[3752]; + __IO uint32_t SELFRESET; /**< Self Reset, offset: 0xFF0 */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Controller Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Controller Enable + * 0b00..CONTROLLER_OFF + * 0b01..CONTROLLER_ON + * 0b10..CONTROLLER_CAPABLE + * 0b11..I2C_CONTROLLER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + * 0b0..Enabled + * 0b1..Disabled, if configured + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..None + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open Drain Stop + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-Pull Baud Rate */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull Low */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open Drain Baud Rate */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open Drain High Push-Pull + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C Baud Rate */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Target Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not Acknowledge + * 0b0..Always disable NACK mode + * 0b1..Always enable NACK mode (works normally) + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match Start or Stop + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b0..Do not ignore TE0 or TE1 errors + * 0b1..Ignore TE0 or TE1 errors + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_HDROK_MASK (0x10U) +#define I3C_SCONFIG_HDROK_SHIFT (4U) +/*! HDROK - HDR OK + * 0b0..Disable HDR OK + * 0b1..Enable HDR OK + */ +#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0x3F0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus Available Match */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static Address */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Target Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not Stop + * 0b0..In STOP condition + * 0b1..Busy + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status Message + * 0b0..Idle + * 0b1..Busy + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + * 0b0..No CCC message handled + * 0b1..Handled automatically + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status Request Read + * 0b0..Not an SDR read + * 0b1..SDR read from this target or an IBI is being pushed out + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status Request Write + * 0b0..Not an SDR write + * 0b1..SDR write data from the controller, but not in ENTDAA mode + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + * 0b0..Not in ENTDAA mode + * 0b1..In ENTDAA mode + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + * 0b0..I3C bus not in HDR-DDR mode + * 0b1..I3C bus in HDR-DDR mode + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Flag + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Header matched + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop Flag + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Stopped state detected + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received Message Pending + * 0b0..No received message pending + * 0b1..Received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer Not Full + * 0b0..Transmit buffer full + * 0b1..Transmit buffer not full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Flag + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..DA change detected + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code Flag + * 0b0..CCC not received + * 0b0..No effect + * 0b1..CCC received + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error Warning */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate Command Match Flag + * 0b0..Did not match + * 0b0..No effect + * 0b1..Matched the I3C dynamic address + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code Handled Flag + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..CCC handling in progress + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event Flag + * 0b0..No event occurred + * 0b0..No effect + * 0b1..IBI, CR, or HJ occurred + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_SLVRST_MASK (0x80000U) +#define I3C_SSTATUS_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset Flag */ +#define I3C_SSTATUS_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_SLVRST_SHIFT)) & I3C_SSTATUS_SLVRST_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event Details + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Controller Requests Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join Disabled + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity State from Common Command Codes (CCC) + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time Control + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Target Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - Event + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..CONTROLLER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_MAPIDX_MASK (0x10U) +#define I3C_SCTRL_MAPIDX_SHIFT (4U) +/*! MAPIDX - Map Index */ +#define I3C_SCTRL_MAPIDX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_MAPIDX_SHIFT)) & I3C_SCTRL_MAPIDX_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt Data */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending Interrupt */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity State of Target */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor Information */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Target Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) + +#define I3C_SINTSET_SLVRST_MASK (0x80000U) +#define I3C_SINTSET_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_SLVRST_SHIFT)) & I3C_SINTSET_SLVRST_MASK) +/*! @} */ + +/*! @name SINTCLR - Target Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) + +#define I3C_SINTCLR_SLVRST_MASK (0x80000U) +#define I3C_SINTCLR_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset Flag (SLVRST Interrupt Enable Clear) */ +#define I3C_SINTCLR_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_SLVRST_SHIFT)) & I3C_SINTCLR_SLVRST_MASK) +/*! @} */ + +/*! @name SINTMASKED - Target Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START Interrupt Mask */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED Interrupt Mask */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Mask */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Mask */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Mask */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Mask */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Mask */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Mask */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Mask */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) + +#define I3C_SINTMASKED_SLVRST_MASK (0x80000U) +#define I3C_SINTMASKED_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset Interrupt Mask */ +#define I3C_SINTMASKED_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_SLVRST_SHIFT)) & I3C_SINTMASKED_SLVRST_MASK) +/*! @} */ + +/*! @name SERRWARN - Target Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun Error Flag + * 0b0..No overrun error + * 0b0..No effect + * 0b1..Overrun error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error Flag + * 0b0..No underrun error + * 0b0..No effect + * 0b1..Underrun error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error Flag + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Underrun; not acknowledged error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated Error Flag + * 0b0..No terminated error + * 0b0..No effect + * 0b1..Terminated error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid Start Error Flag + * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Invalid start error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR Parity Error Flag + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..SDR parity error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR Parity Error Flag + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..HDR parity error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC Error Flag + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..HDR-DDR CRC error occurred + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - TE0 or TE1 Error Flag + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..TE0 or TE1 error occurred + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-Read Error Flag + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Over-read error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-Write Error Flag + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Overwrite error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Target DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA Operations + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) + +#define I3C_SDMACTRL_BULKFB_MASK (0x40U) +#define I3C_SDMACTRL_BULKFB_SHIFT (6U) +/*! BULKFB - Bulk Transfer from Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SDMACTRL_BULKFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_BULKFB_SHIFT)) & I3C_SDMACTRL_BULKFB_MASK) + +#define I3C_SDMACTRL_BULKTB_MASK (0x80U) +#define I3C_SDMACTRL_BULKTB_SHIFT (7U) +/*! BULKTB - Bulk Transfer to Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SDMACTRL_BULKTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_BULKTB_SHIFT)) & I3C_SDMACTRL_BULKTB_MASK) +/*! @} */ + +/*! @name SDATACTRL - Target Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Cannot be changed + * 0b1..Can be changed + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Default (trigger when 1 less than full or less) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty (default) + * 0b01..Trigger when 1/4 or more full + * 0b10..Trigger when 1/2 or more full + * 0b11..Trigger when 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of Bytes in Transmit */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of Bytes in Receive */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End Also + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Target Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Target Write Data Halfword End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Target Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Target Read Data Halfword */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SWDATAB1 - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB1_DATA_MASK (0xFFU) +#define I3C_SWDATAB1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH1 - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH1_DATA_MASK (0xFFFFU) +#define I3C_SWDATAH1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Target Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_V1_1_MASK (0x10000U) +#define I3C_SCAPABILITIES2_V1_1_SHIFT (16U) +/*! V1_1 - Version 1.1 + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_V1_1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_V1_1_SHIFT)) & I3C_SCAPABILITIES2_V1_1_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Target Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - Group + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - SETAASA + * 0b0..SETAASA not supported + * 0b1..SETAASA supported + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable + * 0b0..Not subscriber capable + * 0b1..Subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Target-Target(s)-Tunnel Write Capable + * 0b0..Not write capable + * 0b1..Write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Target Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b Handler + * 0b00..Application + * 0b01..Hardware + * 0b10..Hardware, but the I3C module instance handles ID 48b + * 0b11..A part number register (PARTNO) + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID Register + * 0b0000..All ID register features disabled + * 0b1xxx..A Bus Characteristics Register (BCR) is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0bxx1x..An ID Random field is available + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - High Data Rate Support + * 0b00..No HDR modes supported + * 0b01..DDR mode supported + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Controller + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static Address + * 0b00..No static address + * 0b01..Static address is fixed in hardware + * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) + * 0b11..SCONFIG register supplies the static address + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes Handling + * 0b0000..All handling features disabled + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing + * 0bx1xxx..Application can generate a Hot-Join event + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxxxx1..Application can generate an IBI + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time Control + * 0b0..No time control supported + * 0b1..At least one time-control type supported + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..No external FIFO available + * 0b001..Standard available or free external FIFO + * 0b010..Request track external FIFO + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO Transmit + * 0b00..Two + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO Receive + * 0b00..Two or three + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - Interrupts + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - Direct Memory Access + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Target Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum Read Length */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum Write Length */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Target ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part Number */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Target ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Target Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Target Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock Accuracy */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock Frequency */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Target Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + * 0b0..I3C dynamic address + * 0b1..I2C static address + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCONFIG_EXT - Controller Extended Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_EXT_I2CBLOW_MASK (0xFU) +#define I3C_MCONFIG_EXT_I2CBLOW_SHIFT (0U) +/*! I2CBLOW - I2C Baud Low */ +#define I3C_MCONFIG_EXT_I2CBLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2CBLOW_SHIFT)) & I3C_MCONFIG_EXT_I2CBLOW_MASK) + +#define I3C_MCONFIG_EXT_I2CHS_MASK (0x10U) +#define I3C_MCONFIG_EXT_I2CHS_SHIFT (4U) +/*! I2CHS - I2C HS */ +#define I3C_MCONFIG_EXT_I2CHS(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2CHS_SHIFT)) & I3C_MCONFIG_EXT_I2CHS_MASK) + +#define I3C_MCONFIG_EXT_I2C_A10B_MASK (0x100U) +#define I3C_MCONFIG_EXT_I2C_A10B_SHIFT (8U) +/*! I2C_A10B - I2C_A10B + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_EXT_I2C_A10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2C_A10B_SHIFT)) & I3C_MCONFIG_EXT_I2C_A10B_MASK) + +#define I3C_MCONFIG_EXT_I2C_A10BEXT_MASK (0xE00U) +#define I3C_MCONFIG_EXT_I2C_A10BEXT_SHIFT (9U) +/*! I2C_A10BEXT - I2C_A10BEXT */ +#define I3C_MCONFIG_EXT_I2C_A10BEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2C_A10BEXT_SHIFT)) & I3C_MCONFIG_EXT_I2C_A10BEXT_MASK) + +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) +/*! I3C_CAS_DEL - I3C CAS Delay After START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 3/2 + */ +#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) + +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) +/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 1 1/2 + */ +#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) +/*! @} */ + +/*! @name MCTRL - Controller Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..Force Exit and Target Reset + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus Type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt Response + * 0b00..ACK (acknowledge) + * 0b01..NACK (reject) + * 0b10..Acknowledge with mandatory byte + * 0b11..Manual + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read Terminate Counter */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Controller Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive (for other cases) + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not Acknowledged + * 0b0..Not NACKed + * 0b1..NACKed (not acknowledged) + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) Type + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Flag + * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Target requesting START + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Flag + * 0b0..Not done + * 0b0..No effect + * 0b1..Done + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + * 0b0..No receive message pending + * 0b1..Receive message pending + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX Buffer or FIFO Not Full + * 0b0..Receive buffer or FIFO full + * 0b1..Receive buffer or FIFO not full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) Won Flag + * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..IBI arbitration won + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning + * 0b0..No error or warning + * 0b1..Error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Module is now Controller Flag + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Controller + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI Address */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Most Significant Address Bit is 0 + * 0b0..MSB is not 0 + * 0b1..MSB is 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + * 0b0..With mandatory IBI byte + * 0b1..Without mandatory IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Controller Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed Message Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Pending Interrupt Enable */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - IBI Won Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now Controller Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Controller Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Controller Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Controller Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_URUN_MASK (0x2U) +#define I3C_MERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not Acknowledge Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - Write Abort Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_TERM_MASK (0x10U) +#define I3C_MERRWARN_TERM_SHIFT (4U) +/*! TERM - Terminate Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High Data Rate Parity Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High Data Rate CRC Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Overread Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Overwrite Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid Request Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - Timeout Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Controller DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA Width + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) + +#define I3C_MDMACTRL_BULKFB_MASK (0x40U) +#define I3C_MDMACTRL_BULKFB_SHIFT (6U) +/*! BULKFB - Bulk Transfer from Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MDMACTRL_BULKFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_BULKFB_SHIFT)) & I3C_MDMACTRL_BULKFB_MASK) + +#define I3C_MDMACTRL_BULKTB_MASK (0x80U) +#define I3C_MDMACTRL_BULKTB_SHIFT (7U) +/*! BULKTB - Bulk Transfer to Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MDMACTRL_BULKTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_BULKTB_SHIFT)) & I3C_MDMACTRL_BULKTB_MASK) +/*! @} */ + +/*! @name MDATACTRL - Controller Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Locked + * 0b1..Unlocked + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Trigger when 1 less than full or less (default) + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty (default) + * 0b01..Trigger when 1/4 full or more + * 0b10..Trigger when 1/2 full or more + * 0b11..Trigger when 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Transmit Byte Count */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Byte Count */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Controller Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data Byte */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Controller Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Controller Write Data Halfword */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Controller Write Data Halfword End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Controller Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Controller Read Data Halfword */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) +#define I3C_MWDATAH1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Controller Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) +/*! ADDRCMD - Address Command */ +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) +/*! LEN - Length of Message */ +#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Controller Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Controller Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..No valid DA assigned + * 0b1..Valid DA assigned + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SRSTACTTIME - Timing Rules for Target Reset Recovery */ +/*! @{ */ + +#define I3C_SRSTACTTIME_PERRSTTIM_MASK (0xFFU) +#define I3C_SRSTACTTIME_PERRSTTIM_SHIFT (0U) +/*! PERRSTTIM - Time to Recover from the I3C Peripheral */ +#define I3C_SRSTACTTIME_PERRSTTIM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_PERRSTTIM_SHIFT)) & I3C_SRSTACTTIME_PERRSTTIM_MASK) + +#define I3C_SRSTACTTIME_SYSRSTTIM_MASK (0xFF00U) +#define I3C_SRSTACTTIME_SYSRSTTIM_SHIFT (8U) +/*! SYSRSTTIM - Time to Recover from Chip Reset */ +#define I3C_SRSTACTTIME_SYSRSTTIM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_SYSRSTTIM_SHIFT)) & I3C_SRSTACTTIME_SYSRSTTIM_MASK) +/*! @} */ + +/*! @name SCCCMASK - CCC Mask for Unhandled CCCs */ +/*! @{ */ + +#define I3C_SCCCMASK_BASE_MASK (0x1U) +#define I3C_SCCCMASK_BASE_SHIFT (0U) +/*! BASE - Base + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_BASE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASE_SHIFT)) & I3C_SCCCMASK_BASE_MASK) + +#define I3C_SCCCMASK_BASEBX_MASK (0x2U) +#define I3C_SCCCMASK_BASEBX_SHIFT (1U) +/*! BASEBX - BASEBX + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_BASEBX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEBX_SHIFT)) & I3C_SCCCMASK_BASEBX_MASK) + +#define I3C_SCCCMASK_BASEDX_MASK (0x4U) +#define I3C_SCCCMASK_BASEDX_SHIFT (2U) +/*! BASEDX - BASEDX + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_BASEDX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEDX_SHIFT)) & I3C_SCCCMASK_BASEDX_MASK) + +#define I3C_SCCCMASK_MEXTB_MASK (0x8U) +#define I3C_SCCCMASK_MEXTB_SHIFT (3U) +/*! MEXTB - MEXTB + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_MEXTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTB_SHIFT)) & I3C_SCCCMASK_MEXTB_MASK) + +#define I3C_SCCCMASK_MEXTD_MASK (0x10U) +#define I3C_SCCCMASK_MEXTD_SHIFT (4U) +/*! MEXTD - MEXTD + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_MEXTD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTD_SHIFT)) & I3C_SCCCMASK_MEXTD_MASK) + +#define I3C_SCCCMASK_VENDB_MASK (0x20U) +#define I3C_SCCCMASK_VENDB_SHIFT (5U) +/*! VENDB - VENDB + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_VENDB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDB_SHIFT)) & I3C_SCCCMASK_VENDB_MASK) + +#define I3C_SCCCMASK_VENDD_MASK (0x40U) +#define I3C_SCCCMASK_VENDD_SHIFT (6U) +/*! VENDD - VENDD + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_VENDD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDD_SHIFT)) & I3C_SCCCMASK_VENDD_MASK) +/*! @} */ + +/*! @name SERRWARNMASK - Target Errors and Warnings Mask */ +/*! @{ */ + +#define I3C_SERRWARNMASK_ORUN_MASK (0x1U) +#define I3C_SERRWARNMASK_ORUN_SHIFT (0U) +/*! ORUN - ORUN Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_ORUN_SHIFT)) & I3C_SERRWARNMASK_ORUN_MASK) + +#define I3C_SERRWARNMASK_URUN_MASK (0x2U) +#define I3C_SERRWARNMASK_URUN_SHIFT (1U) +/*! URUN - URUN Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUN_SHIFT)) & I3C_SERRWARNMASK_URUN_MASK) + +#define I3C_SERRWARNMASK_URUNNACK_MASK (0x4U) +#define I3C_SERRWARNMASK_URUNNACK_SHIFT (2U) +/*! URUNNACK - URUNNACK Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUNNACK_SHIFT)) & I3C_SERRWARNMASK_URUNNACK_MASK) + +#define I3C_SERRWARNMASK_TERM_MASK (0x8U) +#define I3C_SERRWARNMASK_TERM_SHIFT (3U) +/*! TERM - TERM Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_TERM_SHIFT)) & I3C_SERRWARNMASK_TERM_MASK) + +#define I3C_SERRWARNMASK_INVSTART_MASK (0x10U) +#define I3C_SERRWARNMASK_INVSTART_SHIFT (4U) +/*! INVSTART - INVSTART Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_INVSTART_SHIFT)) & I3C_SERRWARNMASK_INVSTART_MASK) + +#define I3C_SERRWARNMASK_SPAR_MASK (0x100U) +#define I3C_SERRWARNMASK_SPAR_SHIFT (8U) +/*! SPAR - SPAR Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_SPAR_SHIFT)) & I3C_SERRWARNMASK_SPAR_MASK) + +#define I3C_SERRWARNMASK_HPAR_MASK (0x200U) +#define I3C_SERRWARNMASK_HPAR_SHIFT (9U) +/*! HPAR - HPAR Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HPAR_SHIFT)) & I3C_SERRWARNMASK_HPAR_MASK) + +#define I3C_SERRWARNMASK_HCRC_MASK (0x400U) +#define I3C_SERRWARNMASK_HCRC_SHIFT (10U) +/*! HCRC - HCRC Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HCRC_SHIFT)) & I3C_SERRWARNMASK_HCRC_MASK) + +#define I3C_SERRWARNMASK_S0S1_MASK (0x800U) +#define I3C_SERRWARNMASK_S0S1_SHIFT (11U) +/*! S0S1 - S0S1 Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_S0S1_SHIFT)) & I3C_SERRWARNMASK_S0S1_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable Primary Dynamic Address + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + * 0b000..No information (this value occurs when not configured to write DA) + * 0b001..Set using ENTDAA + * 0b010..Set using SETDASA, SETAASA, or SETNEWDA + * 0b011..Cleared using RSTDAA + * 0b100..Auto MAP change happened last + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name SMAPCTRL1 - Map Feature Control 1 */ +/*! @{ */ + +#define I3C_SMAPCTRL1_ENA_MASK (0x1U) +#define I3C_SMAPCTRL1_ENA_SHIFT (0U) +/*! ENA - Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SMAPCTRL1_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ENA_SHIFT)) & I3C_SMAPCTRL1_ENA_MASK) + +#define I3C_SMAPCTRL1_ADDR_MASK (0xFEU) +#define I3C_SMAPCTRL1_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_SMAPCTRL1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ADDR_SHIFT)) & I3C_SMAPCTRL1_ADDR_MASK) + +#define I3C_SMAPCTRL1_MAPSA_MASK (0x100U) +#define I3C_SMAPCTRL1_MAPSA_SHIFT (8U) +/*! MAPSA - MAP Static Address + * 0b0..I3C dynamic address + * 0b1..Static address (I2C style) + */ +#define I3C_SMAPCTRL1_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_MAPSA_SHIFT)) & I3C_SMAPCTRL1_MAPSA_MASK) + +#define I3C_SMAPCTRL1_SA10B_MASK (0xE00U) +#define I3C_SMAPCTRL1_SA10B_SHIFT (9U) +/*! SA10B - Static Address 10-Bit Extension */ +#define I3C_SMAPCTRL1_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_SA10B_SHIFT)) & I3C_SMAPCTRL1_SA10B_MASK) + +#define I3C_SMAPCTRL1_NACK_MASK (0x1000U) +#define I3C_SMAPCTRL1_NACK_SHIFT (12U) +/*! NACK - Not Acknowledged + * 0b0..Do not always NACK messages + * 0b1..Always NACK messages + */ +#define I3C_SMAPCTRL1_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_NACK_SHIFT)) & I3C_SMAPCTRL1_NACK_MASK) + +#define I3C_SMAPCTRL1_AUTO_MASK (0x2000U) +#define I3C_SMAPCTRL1_AUTO_SHIFT (13U) +/*! AUTO - Auto DAA + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL1_AUTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_AUTO_SHIFT)) & I3C_SMAPCTRL1_AUTO_MASK) + +#define I3C_SMAPCTRL1_DCR_MASK (0xFF000000U) +#define I3C_SMAPCTRL1_DCR_SHIFT (24U) +/*! DCR - DCR */ +#define I3C_SMAPCTRL1_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_DCR_SHIFT)) & I3C_SMAPCTRL1_DCR_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra Byte 1 */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra Byte 2 */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra Byte 3 */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra Byte 4 */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra Byte 5 */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra Byte 6 */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra Byte 7 */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SELFRESET - Self Reset */ +/*! @{ */ + +#define I3C_SELFRESET_RST_MASK (0x1U) +#define I3C_SELFRESET_RST_SHIFT (0U) +/*! RST - Reset + * 0b0..No reset + * 0b1..Reset + */ +#define I3C_SELFRESET_RST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_RST_SHIFT)) & I3C_SELFRESET_RST_MASK) + +#define I3C_SELFRESET_KEY_MASK (0xFFFFFF00U) +#define I3C_SELFRESET_KEY_SHIFT (8U) +/*! KEY - Key */ +#define I3C_SELFRESET_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_KEY_SHIFT)) & I3C_SELFRESET_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C1 base address */ +#define I3C1_BASE (0x44330000u) +/** Peripheral I3C1 base pointer */ +#define I3C1 ((I3C_Type *)I3C1_BASE) +/** Peripheral I3C2 base address */ +#define I3C2_BASE (0x42520000u) +/** Peripheral I3C2 base pointer */ +#define I3C2 ((I3C_Type *)I3C2_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { 0u, I3C1_BASE, I3C2_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { (I3C_Type *)0u, I3C1, I3C2 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { NotAvail_IRQn, I3C1_IRQn, I3C2_IRQn } + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC1 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC1_Peripheral_Access_Layer IOMUXC1 Peripheral Access Layer + * @{ + */ + +/** IOMUXC1 - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD[108]; /**< SW_MUX_CTL_PAD_DAP_TDI SW MUX Control Register..SW_MUX_CTL_PAD_WDOG_ANY SW MUX Control Register, array offset: 0x0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[108]; /**< SW_PAD_CTL_PAD_DAP_TDI SW PAD Control Register..SW_PAD_CTL_PAD_WDOG_ANY SW PAD Control Register, array offset: 0x1B0, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[104]; /**< CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..USDHC3_IPP_DAT3_IN_SELECT_INPUT DAISY Register, array offset: 0x360, array step: 0x4 */ +} IOMUXC1_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC1 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC1_Register_Masks IOMUXC1 Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_DAP_TDI SW MUX Control Register..SW_MUX_CTL_PAD_WDOG_ANY SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: GPIO2_IO14 of instance: gpio2 + * 0b001..Select mux mode: ALT1 mux port: LPUART3_TX of instance: lpuart3 + * 0b010..Select mux mode: ALT2 mux port: MEDIAMIX_CAM_DATA06 of instance: mediamix + * 0b011..Select mux mode: ALT3 mux port: MEDIAMIX_DISP_DATA10 of instance: mediamix + * 0b100..Select mux mode: ALT4 mux port: LPSPI8_SOUT of instance: lpspi8 + * 0b101..Select mux mode: ALT5 mux port: LPUART8_CTS_B of instance: lpuart8 + * 0b110..Select mux mode: ALT6 mux port: LPUART4_TX of instance: lpuart4 + * 0b111..Select mux mode: ALT7 mux port: FLEXIO1_FLEXIO14 of instance: flexio1 + */ +#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK) + +#define IOMUXC1_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC1_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b0..Input Path is determined by functionality + * 0b1..Force input path of pad DAP_TDO_TRACESWO + */ +#define IOMUXC1_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC1_SW_MUX_CTL_PAD */ +#define IOMUXC1_SW_MUX_CTL_PAD_COUNT (108U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_DAP_TDI SW PAD Control Register..SW_PAD_CTL_PAD_WDOG_ANY SW PAD Control Register */ +/*! @{ */ + +#define IOMUXC1_SW_PAD_CTL_PAD_DSE_MASK (0x7EU) +#define IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT (1U) +/*! DSE - Drive Strength Field + * 0b000000.. + * 0b000001.. + * 0b000010.. + * 0b000011.. + * 0b000100.. + * 0b000101.. + * 0b000110.. + * 0b000111.. + * 0b001000.. + * 0b001001.. + * 0b001010.. + * 0b001011.. + * 0b001100.. + * 0b001101.. + * 0b001110.. + * 0b001111.. + * 0b010000.. + * 0b010001.. + * 0b010010.. + * 0b010011.. + * 0b010100.. + * 0b010101.. + * 0b010110.. + * 0b010111.. + * 0b011000.. + * 0b011001.. + * 0b011010.. + * 0b011011.. + * 0b011100.. + * 0b011101.. + * 0b011110.. + * 0b011111.. + * 0b100000.. + * 0b100001.. + * 0b100010.. + * 0b100011.. + * 0b100100.. + * 0b100101.. + * 0b100110.. + * 0b100111.. + * 0b101000.. + * 0b101001.. + * 0b101010.. + * 0b101011.. + * 0b101100.. + * 0b101101.. + * 0b101110.. + * 0b101111.. + * 0b110000.. + * 0b110001.. + * 0b110010.. + * 0b110011.. + * 0b110100.. + * 0b110101.. + * 0b110110.. + * 0b110111.. + * 0b111000.. + * 0b111001.. + * 0b111010.. + * 0b111011.. + * 0b111100.. + * 0b111101.. + * 0b111110.. + * 0b111111..X6 + */ +#define IOMUXC1_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_DSE_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_FSEL1_MASK (0x180U) +#define IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT (7U) +/*! FSEL1 - Slew Rate Field + * 0b00.. + * 0b01.. + * 0b10..Slight Fast Slew Rate + * 0b11..Fast Slew Rate + */ +#define IOMUXC1_SW_PAD_CTL_PAD_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_FSEL1_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_PU_MASK (0x200U) +#define IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT (9U) +/*! PU - Pull Up Field + * 0b0..No pull up + * 0b1..Pull up + */ +#define IOMUXC1_SW_PAD_CTL_PAD_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_PU_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_PD_MASK (0x400U) +#define IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT (10U) +/*! PD - Pull Down Field + * 0b0..Not pull down + * 0b1..Pull down + */ +#define IOMUXC1_SW_PAD_CTL_PAD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_PD_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_OD_MASK (0x800U) +#define IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT (11U) +/*! OD - Open Drain Field + * 0b0..Open Drain Disable + * 0b1..Open Drain Enable + */ +#define IOMUXC1_SW_PAD_CTL_PAD_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_OD_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_HYS_MASK (0x1000U) +#define IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT (12U) +/*! HYS - Schmitt trigger Field + * 0b0..No Schmitt input + * 0b1..Schmitt input + */ +#define IOMUXC1_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_HYS_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_APC_MASK (0xFF000000U) +#define IOMUXC1_SW_PAD_CTL_PAD_APC_SHIFT (24U) +/*! APC - Domain Access Field + * 0b00000000.. + * 0b00000001.. + * 0b00000010.. + * 0b00000011.. + * 0b00000100.. + * 0b00000101.. + * 0b00000110.. + * 0b00000111.. + * 0b00001000.. + * 0b00001001.. + * 0b00001010.. + * 0b00001011.. + * 0b00001100.. + * 0b00001101.. + * 0b00001110.. + * 0b00001111.. + * 0b00010000.. + * 0b00010001.. + * 0b00010010.. + * 0b00010011.. + * 0b00010100.. + * 0b00010101.. + * 0b00010110.. + * 0b00010111.. + * 0b00011000.. + * 0b00011001.. + * 0b00011010.. + * 0b00011011.. + * 0b00011100.. + * 0b00011101.. + * 0b00011110.. + * 0b00011111.. + * 0b00100000.. + * 0b00100001.. + * 0b00100010.. + * 0b00100011.. + * 0b00100100.. + * 0b00100101.. + * 0b00100110.. + * 0b00100111.. + * 0b00101000.. + * 0b00101001.. + * 0b00101010.. + * 0b00101011.. + * 0b00101100.. + * 0b00101101.. + * 0b00101110.. + * 0b00101111.. + * 0b00110000.. + * 0b00110001.. + * 0b00110010.. + * 0b00110011.. + * 0b00110100.. + * 0b00110101.. + * 0b00110110.. + * 0b00110111.. + * 0b00111000.. + * 0b00111001.. + * 0b00111010.. + * 0b00111011.. + * 0b00111100.. + * 0b00111101.. + * 0b00111110.. + * 0b00111111.. + * 0b01000000.. + * 0b01000001.. + * 0b01000010.. + * 0b01000011.. + * 0b01000100.. + * 0b01000101.. + * 0b01000110.. + * 0b01000111.. + * 0b01001000.. + * 0b01001001.. + * 0b01001010.. + * 0b01001011.. + * 0b01001100.. + * 0b01001101.. + * 0b01001110.. + * 0b01001111.. + * 0b01010000.. + * 0b01010001.. + * 0b01010010.. + * 0b01010011.. + * 0b01010100.. + * 0b01010101.. + * 0b01010110.. + * 0b01010111.. + * 0b01011000.. + * 0b01011001.. + * 0b01011010.. + * 0b01011011.. + * 0b01011100.. + * 0b01011101.. + * 0b01011110.. + * 0b01011111.. + * 0b01100000.. + * 0b01100001.. + * 0b01100010.. + * 0b01100011.. + * 0b01100100.. + * 0b01100101.. + * 0b01100110.. + * 0b01100111.. + * 0b01101000.. + * 0b01101001.. + * 0b01101010.. + * 0b01101011.. + * 0b01101100.. + * 0b01101101.. + * 0b01101110.. + * 0b01101111.. + * 0b01110000.. + * 0b01110001.. + * 0b01110010.. + * 0b01110011.. + * 0b01110100.. + * 0b01110101.. + * 0b01110110.. + * 0b01110111.. + * 0b01111000.. + * 0b01111001.. + * 0b01111010.. + * 0b01111011.. + * 0b01111100.. + * 0b01111101.. + * 0b01111110.. + * 0b01111111.. + * 0b10000000.. + * 0b10000001.. + * 0b10000010.. + * 0b10000011.. + * 0b10000100.. + * 0b10000101.. + * 0b10000110.. + * 0b10000111.. + * 0b10001000.. + * 0b10001001.. + * 0b10001010.. + * 0b10001011.. + * 0b10001100.. + * 0b10001101.. + * 0b10001110.. + * 0b10001111.. + * 0b10010000.. + * 0b10010001.. + * 0b10010010.. + * 0b10010011.. + * 0b10010100.. + * 0b10010101.. + * 0b10010110.. + * 0b10010111.. + * 0b10011000.. + * 0b10011001.. + * 0b10011010.. + * 0b10011011.. + * 0b10011100.. + * 0b10011101.. + * 0b10011110.. + * 0b10011111.. + * 0b10100000.. + * 0b10100001.. + * 0b10100010.. + * 0b10100011.. + * 0b10100100.. + * 0b10100101.. + * 0b10100110.. + * 0b10100111.. + * 0b10101000.. + * 0b10101001.. + * 0b10101010.. + * 0b10101011.. + * 0b10101100.. + * 0b10101101.. + * 0b10101110.. + * 0b10101111.. + * 0b10110000.. + * 0b10110001.. + * 0b10110010.. + * 0b10110011.. + * 0b10110100.. + * 0b10110101.. + * 0b10110110.. + * 0b10110111.. + * 0b10111000.. + * 0b10111001.. + * 0b10111010.. + * 0b10111011.. + * 0b10111100.. + * 0b10111101.. + * 0b10111110.. + * 0b10111111.. + * 0b11000000.. + * 0b11000001.. + * 0b11000010.. + * 0b11000011.. + * 0b11000100.. + * 0b11000101.. + * 0b11000110.. + * 0b11000111.. + * 0b11001000.. + * 0b11001001.. + * 0b11001010.. + * 0b11001011.. + * 0b11001100.. + * 0b11001101.. + * 0b11001110.. + * 0b11001111.. + * 0b11010000.. + * 0b11010001.. + * 0b11010010.. + * 0b11010011.. + * 0b11010100.. + * 0b11010101.. + * 0b11010110.. + * 0b11010111.. + * 0b11011000.. + * 0b11011001.. + * 0b11011010.. + * 0b11011011.. + * 0b11011100.. + * 0b11011101.. + * 0b11011110.. + * 0b11011111.. + * 0b11100000.. + * 0b11100001.. + * 0b11100010.. + * 0b11100011.. + * 0b11100100.. + * 0b11100101.. + * 0b11100110.. + * 0b11100111.. + * 0b11101000.. + * 0b11101001.. + * 0b11101010.. + * 0b11101011.. + * 0b11101100.. + * 0b11101101.. + * 0b11101110.. + * 0b11101111.. + * 0b11110000.. + * 0b11110001.. + * 0b11110010.. + * 0b11110011.. + * 0b11110100.. + * 0b11110101.. + * 0b11110110.. + * 0b11110111.. + * 0b11111000.. + * 0b11111001.. + * 0b11111010.. + * 0b11111011.. + * 0b11111100.. + * 0b11111101.. + * 0b11111110.. + * 0b11111111.. + */ +#define IOMUXC1_SW_PAD_CTL_PAD_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_APC_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_APC_MASK) +/*! @} */ + +/* The count of IOMUXC1_SW_PAD_CTL_PAD */ +#define IOMUXC1_SW_PAD_CTL_PAD_COUNT (108U) + +/*! @name SELECT_INPUT - CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..USDHC3_IPP_DAT3_IN_SELECT_INPUT DAISY Register */ +/*! @{ */ + +#define IOMUXC1_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define IOMUXC1_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b00..Selecting Pad: DAP_TDO_TRACESWO for Mode: ALT3 + * 0b01..Selecting Pad: GPIO_IO27 for Mode: ALT2 + * 0b10..Selecting Pad: ENET1_TD2 for Mode: ALT2 + * 0b11..Selecting Pad: SD2_DATA1 for Mode: ALT2 + */ +#define IOMUXC1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC1_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +/*! @} */ + +/* The count of IOMUXC1_SELECT_INPUT */ +#define IOMUXC1_SELECT_INPUT_COUNT (104U) + + +/*! + * @} + */ /* end of group IOMUXC1_Register_Masks */ + + +/* IOMUXC1 - Peripheral instance base addresses */ +/** Peripheral IOMUXC1 base address */ +#define IOMUXC1_BASE (0x443C0000u) +/** Peripheral IOMUXC1 base pointer */ +#define IOMUXC1 ((IOMUXC1_Type *)IOMUXC1_BASE) +/** Array initializer of IOMUXC1 peripheral base addresses */ +#define IOMUXC1_BASE_ADDRS { IOMUXC1_BASE } +/** Array initializer of IOMUXC1 peripheral base pointers */ +#define IOMUXC1_BASE_PTRS { IOMUXC1 } + +/*! + * @} + */ /* end of group IOMUXC1_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< IOMUXC GPR Configuration, offset: 0x0 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name CONFIG - IOMUXC GPR Configuration */ +/*! @{ */ + +#define IOMUXC_GPR_CONFIG_MASTERID0_DATA_MASK (0xFU) +#define IOMUXC_GPR_CONFIG_MASTERID0_DATA_SHIFT (0U) +/*! MASTERID0_DATA - Data bits */ +#define IOMUXC_GPR_CONFIG_MASTERID0_DATA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID0_DATA_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID0_DATA_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID1_DATA_MASK (0xF0U) +#define IOMUXC_GPR_CONFIG_MASTERID1_DATA_SHIFT (4U) +/*! MASTERID1_DATA - Data bits */ +#define IOMUXC_GPR_CONFIG_MASTERID1_DATA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID1_DATA_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID1_DATA_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID2_DATA_MASK (0xF00U) +#define IOMUXC_GPR_CONFIG_MASTERID2_DATA_SHIFT (8U) +/*! MASTERID2_DATA - Data bits */ +#define IOMUXC_GPR_CONFIG_MASTERID2_DATA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID2_DATA_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID2_DATA_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID0_LOCK_MASK (0xF0000U) +#define IOMUXC_GPR_CONFIG_MASTERID0_LOCK_SHIFT (16U) +/*! MASTERID0_LOCK - Lock bits */ +#define IOMUXC_GPR_CONFIG_MASTERID0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID0_LOCK_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID0_LOCK_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID1_LOCK_MASK (0xF00000U) +#define IOMUXC_GPR_CONFIG_MASTERID1_LOCK_SHIFT (20U) +/*! MASTERID1_LOCK - Lock bits */ +#define IOMUXC_GPR_CONFIG_MASTERID1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID1_LOCK_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID1_LOCK_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID2_LOCK_MASK (0xF000000U) +#define IOMUXC_GPR_CONFIG_MASTERID2_LOCK_SHIFT (24U) +/*! MASTERID2_LOCK - Lock bits */ +#define IOMUXC_GPR_CONFIG_MASTERID2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID2_LOCK_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID2_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x443D0000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ISI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer + * @{ + */ + +/** ISI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHNL_CTRL; /**< Channel Control, offset: 0x0 */ + __IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control, offset: 0x4 */ + __IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control, offset: 0x8 */ + __IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */ + __IO uint32_t CHNL_IER; /**< Channel Interrupt Enable, offset: 0x10 */ + __IO uint32_t CHNL_STS; /**< Channel Status, offset: 0x14 */ + __IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor, offset: 0x18 */ + __IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset, offset: 0x1C */ + __IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate, offset: 0x20 */ + __IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate, offset: 0x24 */ + __IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient 0, offset: 0x28 */ + __IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient 1, offset: 0x2C */ + __IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient 2, offset: 0x30 */ + __IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient 3, offset: 0x34 */ + __IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient 4, offset: 0x38 */ + __IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient 5, offset: 0x3C */ + __IO uint32_t CHNL_ROI_0_ALPHA; /**< Channel Alpha Value for ROI 0, offset: 0x40 */ + __IO uint32_t CHNL_ROI_0_ULC; /**< Channel Upper Left Coordinate for ROI 0, offset: 0x44 */ + __IO uint32_t CHNL_ROI_0_LRC; /**< Channel Lower Right Coordinate for ROI 0, offset: 0x48 */ + __IO uint32_t CHNL_ROI_1_ALPHA; /**< Channel Alpha Value for ROI 1, offset: 0x4C */ + __IO uint32_t CHNL_ROI_1_ULC; /**< Channel Upper Left Coordinate for ROI 1, offset: 0x50 */ + __IO uint32_t CHNL_ROI_1_LRC; /**< Channel Lower Right Coordinate for ROI 1, offset: 0x54 */ + __IO uint32_t CHNL_ROI_2_ALPHA; /**< Channel Alpha Value for ROI 2, offset: 0x58 */ + __IO uint32_t CHNL_ROI_2_ULC; /**< Channel Upper Left Coordinate for ROI 2, offset: 0x5C */ + __IO uint32_t CHNL_ROI_2_LRC; /**< Channel Lower Right Coordinate for ROI 2, offset: 0x60 */ + __IO uint32_t CHNL_ROI_3_ALPHA; /**< Channel Alpha Value for ROI 3, offset: 0x64 */ + __IO uint32_t CHNL_ROI_3_ULC; /**< Channel Upper Left Coordinate for ROI 3, offset: 0x68 */ + __IO uint32_t CHNL_ROI_3_LRC; /**< Channel Lower Right Coordinate for ROI 3, offset: 0x6C */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */ + __IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */ + __IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */ + __IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */ + __IO uint32_t CHNL_FLOW_CTRL; /**< Channel Flow Control, offset: 0x9C */ +} ISI_Type; + +/* ---------------------------------------------------------------------------- + -- ISI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ISI_Register_Masks ISI Register Masks + * @{ + */ + +/*! @name CHNL_CTRL - Channel Control */ +/*! @{ */ + +#define ISI_CHNL_CTRL_SRC_MASK (0x1U) +#define ISI_CHNL_CTRL_SRC_SHIFT (0U) +/*! SRC - Input Image Source Port Selection + * 0b0..Port 0 + * 0b1..Port 1 + */ +#define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK) + +#define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U) +#define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U) +/*! SRC_TYPE - Type of Selected Input Image Source + * 0b0..Pixel link + * 0b1..Memory + */ +#define ISI_CHNL_CTRL_SRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK) + +#define ISI_CHNL_CTRL_VER_ID_MASK (0x3C0000U) +#define ISI_CHNL_CTRL_VER_ID_SHIFT (18U) +/*! VER_ID - Version ID */ +#define ISI_CHNL_CTRL_VER_ID(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VER_ID_SHIFT)) & ISI_CHNL_CTRL_VER_ID_MASK) + +#define ISI_CHNL_CTRL_RAW_MSB_ALIGN_MASK (0x400000U) +#define ISI_CHNL_CTRL_RAW_MSB_ALIGN_SHIFT (22U) +/*! RAW_MSB_ALIGN - RAW to MSB Align + * 0b0..LSB aligned selection + * 0b1..MSB aligned selection + */ +#define ISI_CHNL_CTRL_RAW_MSB_ALIGN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_RAW_MSB_ALIGN_SHIFT)) & ISI_CHNL_CTRL_RAW_MSB_ALIGN_MASK) + +#define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U) +#define ISI_CHNL_CTRL_SW_RST_SHIFT (24U) +/*! SW_RST - Software Reset + * 0b0..No reset + * 0b1..Software reset + */ +#define ISI_CHNL_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK) + +#define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U) +#define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U) +/*! CHNL_BYPASS - Channel Bypass Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_CTRL_CHNL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK) + +#define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U) +#define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U) +/*! CLK_EN - Channel Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK) + +#define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U) +#define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U) +/*! CHNL_EN - Enable Channel Processing + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_CTRL_CHNL_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK) +/*! @} */ + +/*! @name CHNL_IMG_CTRL - Channel Image Control */ +/*! @{ */ + +#define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U) +#define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U) +/*! CSC_BYP - Color Space Conversion Bypass Control + * 0b0..CSC operational + * 0b1..CSC bypassed + */ +#define ISI_CHNL_IMG_CTRL_CSC_BYP(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK) + +#define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U) +#define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U) +/*! CSC_MODE - Color Space Conversion Operating Mode + * 0b00..Convert from YUV to RGB + * 0b01..Convert from YCbCr to RGB + * 0b10..Convert from RGB to YUV + * 0b11..Convert from RGB to YCbCr + */ +#define ISI_CHNL_IMG_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK) + +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U) +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U) +/*! YCBCR_MODE - YCbCr Mode + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK) + +#define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U) +#define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U) +/*! HFLIP_EN - Horizontal Flip Control + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U) +#define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U) +/*! VFLIP_EN - Vertical Flip Control + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U) +#define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U) +/*! CROP_EN - Output Image Cropping Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U) +#define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U) +/*! DEC_Y - Vertical Pre-Decimation Control + * 0b00..Disabled + * 0b01..Decimate by 2 + * 0b10..Decimate by 4 + * 0b11..Decimate by 8 + */ +#define ISI_CHNL_IMG_CTRL_DEC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK) + +#define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U) +#define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U) +/*! DEC_X - Horizontal Pre-Decimation Control + * 0b00..Disabled + * 0b01..Decimate by 2 + * 0b10..Decimate by 4 + * 0b11..Decimate by 8 + */ +#define ISI_CHNL_IMG_CTRL_DEC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK) + +#define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U) +#define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U) +/*! DEINT - Deinterlace Control + * 0b000, 0b001..No deinterlacing + * 0b010..Weave deinterlacing (odd, even) + * 0b011..Weave deinterlacing (even, odd) + */ +#define ISI_CHNL_IMG_CTRL_DEINT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK) + +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U) +/*! GBL_ALPHA_EN - Global Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U) +/*! GBL_ALPHA_VAL - Global Alpha Value + * 0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels + */ +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK) + +#define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x7F000000U) +#define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U) +/*! FORMAT - Output Image Format + * 0b0000000-0b1000001..See . + */ +#define ISI_CHNL_IMG_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU) +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U) +/*! PANIC_SET_THD_Y - Overflow Panic Set Threshold Value for Y or RGB Output Buffer + * 0b0000..No panic alert + * 0b0001-0b1111..Panic asserts + */ +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U) +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U) +/*! PANIC_SET_THD_U - Overflow Panic Set Threshold Value for U Output Buffer + * 0b0000..No panic alert + * 0b0001-0b1111..Panic asserts + */ +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U) +/*! LOAD_BUF1_ADDR - Load Buffer 1 Address */ +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U) +/*! LOAD_BUF2_ADDR - Load Buffer 2 Address */ +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U) +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U) +/*! PANIC_SET_THD_V - Overflow Panic Set Threshold Value for V Output Buffer + * 0b0000..No panic alert + * 0b0001-0b1111..Panic asserts + */ +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U) +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U) +/*! MAX_WR_BEATS_UV - Maximum AXI Write Beats for U- and V-Buffers + * 0b0..8 beats per write (128 bytes) + * 0b1..16 beats per write (256 bytes) + */ +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U) +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U) +/*! MAX_WR_BEATS_Y - Maximum AXI Write Beats for Y-Buffer + * 0b0..8 beats per write (128 bytes) + * 0b1..16 beats per write (256 bytes) + */ +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK) +/*! @} */ + +/*! @name CHNL_IMG_CFG - Channel Image Configuration */ +/*! @{ */ + +#define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU) +#define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U) +/*! WIDTH - Input Image Width */ +#define ISI_CHNL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK) + +#define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) +#define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U) +/*! HEIGHT - Input Image Height */ +#define ISI_CHNL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK) +/*! @} */ + +/*! @name CHNL_IER - Channel Interrupt Enable */ +/*! @{ */ + +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x10000U) +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (16U) +/*! LATE_VSYNC_ERR_EN - VSYNC Timing (Late) Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK) + +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x20000U) +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (17U) +/*! EARLY_VSYNC_ERR_EN - VSYNC Timing (Early) Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK) + +#define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x40000U) +#define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (18U) +/*! OFLW_Y_BUF_EN - Y Output Buffer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK) + +#define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK (0x80000U) +#define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT (19U) +/*! PANIC_Y_BUF_EN - Y Output Buffer Potential Overflow Panic Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_PANIC_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK) + +#define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x100000U) +#define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (20U) +/*! OFLW_U_BUF_EN - U Output Buffer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK) + +#define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK (0x200000U) +#define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT (21U) +/*! PANIC_U_BUF_EN - U Output Buffer Potential Overflow Panic Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_PANIC_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK) + +#define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x400000U) +#define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (22U) +/*! OFLW_V_BUF_EN - V Output Buffer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK) + +#define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK (0x800000U) +#define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT (23U) +/*! PANIC_V_BUF_EN - V Output Buffer Potential Overflow Panic Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_PANIC_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK) + +#define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U) +#define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U) +/*! AXI_RD_ERR_EN - AXI Bus Read Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK) + +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U) +/*! AXI_WR_ERR_Y_EN - AXI Bus Read Error Interrupt Enable for Y and RGB Data Buffer + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK) + +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U) +/*! AXI_WR_ERR_U_EN - AXI Bus Read Error Interrupt Enable for U Data Buffer + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK) + +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U) +/*! AXI_WR_ERR_V_EN - AXI Bus Read Error Interrupt Enable for V Data Buffer + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK) + +#define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U) +#define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U) +/*! FRM_RCVD_EN - Frame Received Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_FRM_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK) + +#define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U) +#define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U) +/*! LINE_RCVD_EN - Line Received Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_LINE_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK) + +#define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U) +#define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U) +/*! MEM_RD_DONE_EN - Memory Read Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_MEM_RD_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK) +/*! @} */ + +/*! @name CHNL_STS - Channel Status */ +/*! @{ */ + +#define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U) +#define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U) +/*! BUF1_ACTIVE - Current Frame Stored in Buffer 1 Address + * 0b0..Buffer 1 address inactive + * 0b1..Buffer 1 address in use + */ +#define ISI_CHNL_STS_BUF1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK) + +#define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U) +#define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U) +/*! BUF2_ACTIVE - Current Frame Stored in Buffer 2 Address + * 0b0..Buffer 2 address inactive + * 0b1..Buffer 2 address in use + */ +#define ISI_CHNL_STS_BUF2_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK) + +#define ISI_CHNL_STS_MEM_RD_OFLOW_MASK (0x400U) +#define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT (10U) +/*! MEM_RD_OFLOW - Memory Read FIFO Overflow Error Status + * 0b0..No overflow + * 0b1..FIFO overflow + */ +#define ISI_CHNL_STS_MEM_RD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK) + +#define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x10000U) +#define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (16U) +/*! LATE_VSYNC_ERR - VSYNC Timing (Late) Error Interrupt flag + * 0b0..No error + * 0b1..VSYNC detected later + */ +#define ISI_CHNL_STS_LATE_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK) + +#define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x20000U) +#define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (17U) +/*! EARLY_VSYNC_ERR - VSYNC Timing (Early) Error Interrupt flag + * 0b0..No error + * 0b1..VSYNC detected earlier + */ +#define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK) + +#define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x40000U) +#define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (18U) +/*! OFLW_Y_BUF - Overflow in Y or RGB Output Buffer Interrupt Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define ISI_CHNL_STS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK) + +#define ISI_CHNL_STS_PANIC_Y_BUF_MASK (0x80000U) +#define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT (19U) +/*! PANIC_Y_BUF - Y or RGB Output Buffer Potential Overflow Panic Alert Interrupt Flag + * 0b0..Threshold limit not crossed + * 0b1..Threshold limit crossed + */ +#define ISI_CHNL_STS_PANIC_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK) + +#define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x100000U) +#define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (20U) +/*! OFLW_U_BUF - Overflow in U Output Buffer Interrupt Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define ISI_CHNL_STS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK) + +#define ISI_CHNL_STS_PANIC_U_BUF_MASK (0x200000U) +#define ISI_CHNL_STS_PANIC_U_BUF_SHIFT (21U) +/*! PANIC_U_BUF - U Output Buffer Potential Overflow Panic Alert Interrupt Flag + * 0b0..Threshold limit not crossed + * 0b1..Threshold limit crossed + */ +#define ISI_CHNL_STS_PANIC_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK) + +#define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U) +#define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U) +/*! OFLW_V_BUF - Overflow in V Output Buffer Interrupt Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define ISI_CHNL_STS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK) + +#define ISI_CHNL_STS_PANIC_V_BUF_MASK (0x800000U) +#define ISI_CHNL_STS_PANIC_V_BUF_SHIFT (23U) +/*! PANIC_V_BUF - V Output Buffer Potential Overflow Panic Alert Interrupt Flag + * 0b0..Threshold limit not crossed + * 0b1..Threshold limit crossed + */ +#define ISI_CHNL_STS_PANIC_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK) + +#define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U) +#define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U) +/*! AXI_RD_ERR - AXI Bus Read Error Interrupt Flag + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK) + +#define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U) +/*! AXI_WR_ERR_Y - AXI Bus Write Error Interrupt Flag for Y/RGB Data Buffer + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_WR_ERR_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK) + +#define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U) +/*! AXI_WR_ERR_U - AXI Bus Write Error Interrupt Flag for U Data Buffer + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_WR_ERR_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK) + +#define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U) +/*! AXI_WR_ERR_V - AXI Bus Write Error Interrupt Flag for V Data Buffer + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_WR_ERR_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK) + +#define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U) +#define ISI_CHNL_STS_FRM_STRD_SHIFT (29U) +/*! FRM_STRD - Frame Stored Successfully Interrupt Flag + * 0b0..Not received or in progress + * 0b1..Received and stored + */ +#define ISI_CHNL_STS_FRM_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK) + +#define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U) +#define ISI_CHNL_STS_LINE_STRD_SHIFT (30U) +/*! LINE_STRD - Line Received and Stored Interrupt Flag + * 0b0..Not received + * 0b1..Received and stored + */ +#define ISI_CHNL_STS_LINE_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK) + +#define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U) +#define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U) +/*! MEM_RD_DONE - Memory Read Complete Interrupt Flag + * 0b0..Not complete or not started + * 0b1..Completed + */ +#define ISI_CHNL_STS_MEM_RD_DONE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK) +/*! @} */ + +/*! @name CHNL_SCALE_FACTOR - Channel Scale Factor */ +/*! @{ */ + +#define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU) +#define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U) +/*! X_SCALE - Horizontal Scaling Factor */ +#define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK) + +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U) +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U) +/*! Y_SCALE - Vertical Scaling Factor */ +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK) +/*! @} */ + +/*! @name CHNL_SCALE_OFFSET - Channel Scale Offset */ +/*! @{ */ + +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU) +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U) +/*! X_OFFSET - Horizontal Scaling Offset */ +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK) + +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U) +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U) +/*! Y_OFFSET - Vertical Scaling Offset */ +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK) +/*! @} */ + +/*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate */ +/*! @{ */ + +#define ISI_CHNL_CROP_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_CROP_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK) + +#define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_CROP_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate */ +/*! @{ */ + +#define ISI_CHNL_CROP_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_CROP_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK) + +#define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_CROP_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient 0 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U) +/*! A1 - CSC Coefficient A1 Value */ +#define ISI_CHNL_CSC_COEFF0_A1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK) + +#define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U) +/*! A2 - CSC Coefficient A2 Value */ +#define ISI_CHNL_CSC_COEFF0_A2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient 1 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U) +/*! A3 - CSC Coefficient A3 Value */ +#define ISI_CHNL_CSC_COEFF1_A3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK) + +#define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U) +/*! B1 - CSC Coefficient B1 Value */ +#define ISI_CHNL_CSC_COEFF1_B1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient 2 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U) +/*! B2 - CSC Coefficient B2 Value */ +#define ISI_CHNL_CSC_COEFF2_B2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK) + +#define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U) +/*! B3 - CSC Coefficient B3 Value */ +#define ISI_CHNL_CSC_COEFF2_B3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient 3 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U) +/*! C1 - CSC Coefficient C1 Value */ +#define ISI_CHNL_CSC_COEFF3_C1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK) + +#define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U) +/*! C2 - CSC Coefficient C2 Value */ +#define ISI_CHNL_CSC_COEFF3_C2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient 4 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U) +/*! C3 - CSC Coefficient C3 Value */ +#define ISI_CHNL_CSC_COEFF4_C3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK) + +#define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U) +#define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U) +/*! D1 - CSC Coefficient D1 Value */ +#define ISI_CHNL_CSC_COEFF4_D1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient 5 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU) +#define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U) +/*! D2 - CSC Coefficient D2 Value */ +#define ISI_CHNL_CSC_COEFF5_D2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK) + +#define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U) +#define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U) +/*! D3 - CSC Coefficient D3 Value */ +#define ISI_CHNL_CSC_COEFF5_D3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK) +/*! @} */ + +/*! @name CHNL_ROI_0_ALPHA - Channel Alpha Value for ROI 0 */ +/*! @{ */ + +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_0_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_0_ULC - Channel Upper Left Coordinate for ROI 0 */ +/*! @{ */ + +#define ISI_CHNL_ROI_0_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_0_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_0_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_Y_SHIFT)) & ISI_CHNL_ROI_0_ULC_Y_MASK) + +#define ISI_CHNL_ROI_0_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_0_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_0_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_X_SHIFT)) & ISI_CHNL_ROI_0_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_0_LRC - Channel Lower Right Coordinate for ROI 0 */ +/*! @{ */ + +#define ISI_CHNL_ROI_0_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_0_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_0_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_Y_SHIFT)) & ISI_CHNL_ROI_0_LRC_Y_MASK) + +#define ISI_CHNL_ROI_0_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_0_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_0_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_X_SHIFT)) & ISI_CHNL_ROI_0_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_1_ALPHA - Channel Alpha Value for ROI 1 */ +/*! @{ */ + +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_1_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_1_ULC - Channel Upper Left Coordinate for ROI 1 */ +/*! @{ */ + +#define ISI_CHNL_ROI_1_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_1_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_1_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_Y_SHIFT)) & ISI_CHNL_ROI_1_ULC_Y_MASK) + +#define ISI_CHNL_ROI_1_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_1_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_1_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_X_SHIFT)) & ISI_CHNL_ROI_1_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_1_LRC - Channel Lower Right Coordinate for ROI 1 */ +/*! @{ */ + +#define ISI_CHNL_ROI_1_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_1_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_1_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_Y_SHIFT)) & ISI_CHNL_ROI_1_LRC_Y_MASK) + +#define ISI_CHNL_ROI_1_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_1_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_1_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_X_SHIFT)) & ISI_CHNL_ROI_1_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_2_ALPHA - Channel Alpha Value for ROI 2 */ +/*! @{ */ + +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_2_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_2_ULC - Channel Upper Left Coordinate for ROI 2 */ +/*! @{ */ + +#define ISI_CHNL_ROI_2_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_2_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_2_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_Y_SHIFT)) & ISI_CHNL_ROI_2_ULC_Y_MASK) + +#define ISI_CHNL_ROI_2_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_2_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_2_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_X_SHIFT)) & ISI_CHNL_ROI_2_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_2_LRC - Channel Lower Right Coordinate for ROI 2 */ +/*! @{ */ + +#define ISI_CHNL_ROI_2_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_2_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_2_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_Y_SHIFT)) & ISI_CHNL_ROI_2_LRC_Y_MASK) + +#define ISI_CHNL_ROI_2_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_2_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_2_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_X_SHIFT)) & ISI_CHNL_ROI_2_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_3_ALPHA - Channel Alpha Value for ROI 3 */ +/*! @{ */ + +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_3_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_3_ULC - Channel Upper Left Coordinate for ROI 3 */ +/*! @{ */ + +#define ISI_CHNL_ROI_3_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_3_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_3_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_Y_SHIFT)) & ISI_CHNL_ROI_3_ULC_Y_MASK) + +#define ISI_CHNL_ROI_3_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_3_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_3_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_X_SHIFT)) & ISI_CHNL_ROI_3_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_3_LRC - Channel Lower Right Coordinate for ROI 3 */ +/*! @{ */ + +#define ISI_CHNL_ROI_3_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_3_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_3_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_Y_SHIFT)) & ISI_CHNL_ROI_3_LRC_Y_MASK) + +#define ISI_CHNL_ROI_3_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_3_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_3_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_X_SHIFT)) & ISI_CHNL_ROI_3_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U) +/*! ADDR - Address for RGB or Y (Luma) */ +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U) +/*! ADDR - Address for U/Cb/UV/CbCr */ +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U) +/*! ADDR - Address for V or Cr */ +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U) +/*! LINE_PITCH - Output Buffer Line Pitch */ +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK) +/*! @} */ + +/*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */ +/*! @{ */ + +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U) +/*! LINE_PITCH - Line Pitch */ +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK) + +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U) +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U) +/*! FRM_PITCH - Frame Pitch */ +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK) +/*! @} */ + +/*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */ +/*! @{ */ + +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U) +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U) +/*! READ_MEM - Initiate Read from Memory + * 0b0..No reads + * 0b1..Reads initiated + */ +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK) + +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U) +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U) +/*! IMG_TYPE - Input Image Format */ +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U) +/*! ADDR - Starting Address for RGB or Y */ +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U) +/*! ADDR - Starting Address for U/Cb or 2-plane UV/CbCr */ +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U) +/*! ADDR - Starting Address for V or Cr */ +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */ +/*! @{ */ + +#define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU) +#define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U) +/*! WIDTH - Scaled Image Width (Pixels) */ +#define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK) + +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U) +/*! HEIGHT - Scaled Image Height (Lines) */ +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK) +/*! @} */ + +/*! @name CHNL_FLOW_CTRL - Channel Flow Control */ +/*! @{ */ + +#define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK (0xFFU) +#define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT (0U) +/*! FC_DENOM - Denominator Value of Fraction of Usable Bandwidth + * 0b00000000..Invalid value (flow control disabled) + */ +#define ISI_CHNL_FLOW_CTRL_FC_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK) + +#define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK (0xFF0000U) +#define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT (16U) +/*! FC_NUMER - Numerator Value of Fraction of Usable Bandwidth + * 0b00000000..Invalid value (flow control disabled) + */ +#define ISI_CHNL_FLOW_CTRL_FC_NUMER(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ISI_Register_Masks */ + + +/* ISI - Peripheral instance base addresses */ +/** Peripheral ISI base address */ +#define ISI_BASE (0x4AE40000u) +/** Peripheral ISI base pointer */ +#define ISI ((ISI_Type *)ISI_BASE) +/** Array initializer of ISI peripheral base addresses */ +#define ISI_BASE_ADDRS { ISI_BASE } +/** Array initializer of ISI peripheral base pointers */ +#define ISI_BASE_PTRS { ISI } + +/*! + * @} + */ /* end of group ISI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< LCDIF display control Register, offset: 0x0 */ + __IO uint32_t SET; /**< LCDIF display control Register, offset: 0x4 */ + __IO uint32_t CLR; /**< LCDIF display control Register, offset: 0x8 */ + __IO uint32_t TOG; /**< LCDIF display control Register, offset: 0xC */ + } CTRL; + __IO uint32_t DISP_PARA; /**< Display Parameter Register, offset: 0x10 */ + __IO uint32_t DISP_SIZE; /**< Display Size Register, offset: 0x14 */ + __IO uint32_t HSYN_PARA; /**< Horizontal Sync Parameter Register, offset: 0x18 */ + __IO uint32_t VSYN_PARA; /**< Vertical Sync Parameter Register, offset: 0x1C */ + __IO uint32_t VSYN_HSYN_WIDTH; /**< Vertical and Horizontal Pulse Width Parameter Register, offset: 0x20 */ + __IO uint32_t INT_STATUS_D0; /**< Interrupt Status Register for domain 0, offset: 0x24 */ + __IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offset: 0x28 */ + uint8_t RESERVED_0[4]; + __IO uint32_t INT_STATUS_D1; /**< Interrupt Status Register for domain 0, offset: 0x30 */ + __IO uint32_t INT_ENABLE_D1; /**< Interrupt Enable Register for domain 0, offset: 0x34 */ + uint8_t RESERVED_1[456]; + __IO uint32_t CTRLDESCL_1[1]; /**< Control Descriptor Layer Register 1, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CTRLDESCL_3[1]; /**< Control Descriptor Layer Register 3, array offset: 0x208, array step: 0x4 */ + __IO uint32_t CTRLDESCL_LOW_4[1]; /**< Control Descriptor Layer Register 4, array offset: 0x20C, array step: 0x4 */ + __IO uint32_t CTRLDESCL_HIGH_4[1]; /**< Control Descriptor Layer Register 4, array offset: 0x210, array step: 0x4 */ + __IO uint32_t CTRLDESCL_5[1]; /**< Control Descriptor Layer Register 5, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t CSC_CTRL[1]; /**< Color Space Conversion Ctrl Register, array offset: 0x21C, array step: 0x4 */ + __IO uint32_t CSC_COEF0[1]; /**< Color Space Conversion Coefficient Register 0, array offset: 0x220, array step: 0x4 */ + __IO uint32_t CSC_COEF1[1]; /**< Color Space Conversion Coefficient Register 1, array offset: 0x224, array step: 0x4 */ + __IO uint32_t CSC_COEF2[1]; /**< Color Space Conversion Coefficient Register 2, array offset: 0x228, array step: 0x4 */ + __IO uint32_t CSC_COEF3[1]; /**< Color Space Conversion Coefficient Register 3, array offset: 0x22C, array step: 0x4 */ + __IO uint32_t CSC_COEF4[1]; /**< Color Space Conversion Coefficient Register 4, array offset: 0x230, array step: 0x4 */ + __IO uint32_t CSC_COEF5[1]; /**< Color Space Conversion Coefficient Register 0, array offset: 0x234, array step: 0x4 */ + __IO uint32_t PANIC_THRES[1]; /**< Memory request priority threshold register, array offset: 0x238, array step: 0x4 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - LCDIF display control Register */ +/*! @{ */ + +#define LCDIF_CTRL_INV_HS_MASK (0x1U) +#define LCDIF_CTRL_INV_HS_SHIFT (0U) +/*! INV_HS - Invert Horizontal synchronization signal. + * 0b0..HSYNC signal not inverted (active HIGH). + * 0b1..Invert HSYNC signal (active LOW). + */ +#define LCDIF_CTRL_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_HS_SHIFT)) & LCDIF_CTRL_INV_HS_MASK) + +#define LCDIF_CTRL_INV_VS_MASK (0x2U) +#define LCDIF_CTRL_INV_VS_SHIFT (1U) +/*! INV_VS - Invert Vertical synchronization signal. + * 0b0..VSYNC signal not inverted (active HIGH). + * 0b1..Invert VSYNC signal (active LOW). + */ +#define LCDIF_CTRL_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_VS_SHIFT)) & LCDIF_CTRL_INV_VS_MASK) + +#define LCDIF_CTRL_INV_DE_MASK (0x4U) +#define LCDIF_CTRL_INV_DE_SHIFT (2U) +/*! INV_DE - Invert Data Enable polarity + * 0b0..Data enable is active high + * 0b1..Data enable is active low + */ +#define LCDIF_CTRL_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_DE_SHIFT)) & LCDIF_CTRL_INV_DE_MASK) + +#define LCDIF_CTRL_INV_PXCK_MASK (0x8U) +#define LCDIF_CTRL_INV_PXCK_SHIFT (3U) +/*! INV_PXCK - Polarity change of Pixel Clock. + * 0b0..Display samples data on the falling edge + * 0b1..Display samples data on the rising edge + */ +#define LCDIF_CTRL_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_PXCK_SHIFT)) & LCDIF_CTRL_INV_PXCK_MASK) + +#define LCDIF_CTRL_NEG_MASK (0x10U) +#define LCDIF_CTRL_NEG_SHIFT (4U) +/*! NEG - Indicates if value at the output (pixel data output) needs to be negated. + * 0b0..Output is to remain same + * 0b1..Output to be negated + */ +#define LCDIF_CTRL_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_NEG_SHIFT)) & LCDIF_CTRL_NEG_MASK) + +#define LCDIF_CTRL_fetch_start_option_MASK (0x300U) +#define LCDIF_CTRL_fetch_start_option_SHIFT (8U) +/*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time + * 0b00..fetch start as soon as FPV begins(as the end of the data_enable) + * 0b01..fetch start as soon as PWV begins + * 0b10..fetch start as soon as BPV begins + * 0b11..fetch start as soon as RESV begins(still have hsync blanking for margin) + */ +#define LCDIF_CTRL_fetch_start_option(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_fetch_start_option_SHIFT)) & LCDIF_CTRL_fetch_start_option_MASK) + +#define LCDIF_CTRL_SW_RESET_MASK (0x80000000U) +#define LCDIF_CTRL_SW_RESET_SHIFT (31U) +/*! SW_RESET - SW_RESET + * 0b0..No action + * 0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected. + */ +#define LCDIF_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SW_RESET_SHIFT)) & LCDIF_CTRL_SW_RESET_MASK) +/*! @} */ + +/*! @name DISP_PARA - Display Parameter Register */ +/*! @{ */ + +#define LCDIF_DISP_PARA_BGND_B_MASK (0xFFU) +#define LCDIF_DISP_PARA_BGND_B_SHIFT (0U) +/*! BGND_B - Background Blue component value in display Mode 1. */ +#define LCDIF_DISP_PARA_BGND_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_B_SHIFT)) & LCDIF_DISP_PARA_BGND_B_MASK) + +#define LCDIF_DISP_PARA_BGND_G_MASK (0xFF00U) +#define LCDIF_DISP_PARA_BGND_G_SHIFT (8U) +/*! BGND_G - Background Green component value in display Mode 1. */ +#define LCDIF_DISP_PARA_BGND_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_G_SHIFT)) & LCDIF_DISP_PARA_BGND_G_MASK) + +#define LCDIF_DISP_PARA_BGND_R_MASK (0xFF0000U) +#define LCDIF_DISP_PARA_BGND_R_SHIFT (16U) +/*! BGND_R - Background Red component value in display Mode 1. */ +#define LCDIF_DISP_PARA_BGND_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_R_SHIFT)) & LCDIF_DISP_PARA_BGND_R_MASK) + +#define LCDIF_DISP_PARA_DISP_MODE_MASK (0x3000000U) +#define LCDIF_DISP_PARA_DISP_MODE_SHIFT (24U) +/*! DISP_MODE - LCDIF operating mode. + * 0b00..Normal mode. Panel content controlled by layer configuration. + * 0b01..display Mode1.(BGND Color Display) + * 0b10..display Mode2.(Column Color Bar) + * 0b11..display Mode3.(Row Color Bar) + */ +#define LCDIF_DISP_PARA_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_MODE_SHIFT)) & LCDIF_DISP_PARA_DISP_MODE_MASK) + +#define LCDIF_DISP_PARA_LINE_PATTERN_MASK (0x3C000000U) +#define LCDIF_DISP_PARA_LINE_PATTERN_SHIFT (26U) +/*! LINE_PATTERN - LCDIF line output order. + * 0b0000..RGB/YUV. + * 0b0001..RBG. + * 0b0010..GBR. + * 0b0011..GRB/UYV. + * 0b0100..BRG. + * 0b0101..BGR. + * 0b0110..RGB555. + * 0b0111..RGB565. + * 0b1000..YUYV at [15:0]. For line pattern with "1000 - YUYV at [15:0]，Y is [15:8], U is [7:0], and next 16th bit is Y and V. + * 0b1001..UYVY at [15:0]. + * 0b1010..YVYU at [15:0]. + * 0b1011..YUYV at [15:0]. + * 0b1100..YUYV at [23:8]. + * 0b1101..UYVY at [23:8]. + * 0b1110..YVYU at [23:8]. + * 0b1111..YUYV at [23:8]. + */ +#define LCDIF_DISP_PARA_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIF_DISP_PARA_LINE_PATTERN_MASK) + +#define LCDIF_DISP_PARA_SWAP_EN_MASK (0x40000000U) +#define LCDIF_DISP_PARA_SWAP_EN_SHIFT (30U) +/*! SWAP_EN - output data swap enable. + * 0b0..swap disable + * 0b1..swap enbale, output data will swap the high 16bits with the low 16bits. + */ +#define LCDIF_DISP_PARA_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_SWAP_EN_SHIFT)) & LCDIF_DISP_PARA_SWAP_EN_MASK) + +#define LCDIF_DISP_PARA_DISP_ON_MASK (0x80000000U) +#define LCDIF_DISP_PARA_DISP_ON_SHIFT (31U) +/*! DISP_ON - Display panel On/Off mode. + * 0b0..Display Off. + * 0b1..Display On. + */ +#define LCDIF_DISP_PARA_DISP_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_ON_SHIFT)) & LCDIF_DISP_PARA_DISP_ON_MASK) +/*! @} */ + +/*! @name DISP_SIZE - Display Size Register */ +/*! @{ */ + +#define LCDIF_DISP_SIZE_DELTA_X_MASK (0xFFFFU) +#define LCDIF_DISP_SIZE_DELTA_X_SHIFT (0U) +/*! DELTA_X - Sets the display size horizontal resolution in pixels. */ +#define LCDIF_DISP_SIZE_DELTA_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_X_SHIFT)) & LCDIF_DISP_SIZE_DELTA_X_MASK) + +#define LCDIF_DISP_SIZE_DELTA_Y_MASK (0xFFFF0000U) +#define LCDIF_DISP_SIZE_DELTA_Y_SHIFT (16U) +/*! DELTA_Y - Sets the display size vertical resolution in pixels. */ +#define LCDIF_DISP_SIZE_DELTA_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIF_DISP_SIZE_DELTA_Y_MASK) +/*! @} */ + +/*! @name HSYN_PARA - Horizontal Sync Parameter Register */ +/*! @{ */ + +#define LCDIF_HSYN_PARA_FP_H_MASK (0xFFFFU) +#define LCDIF_HSYN_PARA_FP_H_SHIFT (0U) +/*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_HSYN_PARA_FP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_FP_H_SHIFT)) & LCDIF_HSYN_PARA_FP_H_MASK) + +#define LCDIF_HSYN_PARA_BP_H_MASK (0xFFFF0000U) +#define LCDIF_HSYN_PARA_BP_H_SHIFT (16U) +/*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_HSYN_PARA_BP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_BP_H_SHIFT)) & LCDIF_HSYN_PARA_BP_H_MASK) +/*! @} */ + +/*! @name VSYN_PARA - Vertical Sync Parameter Register */ +/*! @{ */ + +#define LCDIF_VSYN_PARA_FP_V_MASK (0xFFFFU) +#define LCDIF_VSYN_PARA_FP_V_SHIFT (0U) +/*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_PARA_FP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_FP_V_SHIFT)) & LCDIF_VSYN_PARA_FP_V_MASK) + +#define LCDIF_VSYN_PARA_BP_V_MASK (0xFFFF0000U) +#define LCDIF_VSYN_PARA_BP_V_SHIFT (16U) +/*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_PARA_BP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_BP_V_SHIFT)) & LCDIF_VSYN_PARA_BP_V_MASK) +/*! @} */ + +/*! @name VSYN_HSYN_WIDTH - Vertical and Horizontal Pulse Width Parameter Register */ +/*! @{ */ + +#define LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK (0xFFFFU) +#define LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT (0U) +/*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_HSYN_WIDTH_PW_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK) + +#define LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK (0xFFFF0000U) +#define LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT (16U) +/*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_HSYN_WIDTH_PW_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK) +/*! @} */ + +/*! @name INT_STATUS_D0 - Interrupt Status Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_STATUS_D0_VSYNC_MASK (0x1U) +#define LCDIF_INT_STATUS_D0_VSYNC_SHIFT (0U) +/*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a + * frame). Write a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VSYNC_SHIFT)) & LCDIF_INT_STATUS_D0_VSYNC_MASK) + +#define LCDIF_INT_STATUS_D0_UNDERRUN_MASK (0x2U) +#define LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT (1U) +/*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition. Write a logic 1 to this field to clear this flag. */ +#define LCDIF_INT_STATUS_D0_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT)) & LCDIF_INT_STATUS_D0_UNDERRUN_MASK) + +#define LCDIF_INT_STATUS_D0_VS_BLANK_MASK (0x4U) +#define LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT (2U) +/*! VS_BLANK - Interrupt flag to indicate vertical blanking period. Write a logic 1 to this field to clear this flag. */ +#define LCDIF_INT_STATUS_D0_VS_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT)) & LCDIF_INT_STATUS_D0_VS_BLANK_MASK) + +#define LCDIF_INT_STATUS_D0_DMA_ERR_MASK (0x100U) +#define LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT (8U) +/*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. Write + * a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_DMA_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_ERR_MASK) + +#define LCDIF_INT_STATUS_D0_DMA_DONE_MASK (0x10000U) +#define LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT (16U) +/*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. + * Write a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_DONE_MASK) + +#define LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK (0x1000000U) +#define LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT (24U) +/*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed. Write + * a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT)) & LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK) +/*! @} */ + +/*! @name INT_ENABLE_D0 - Interrupt Enable Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK (0x1U) +#define LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT (0U) +/*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame). */ +#define LCDIF_INT_ENABLE_D0_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK (0x2U) +#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT (1U) +/*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition. */ +#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK (0x4U) +#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT (2U) +/*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period. */ +#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK (0x100U) +#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT (8U) +/*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. */ +#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK (0x10000U) +#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT (16U) +/*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. */ +#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK (0x1000000U) +#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT (24U) +/*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed. */ +#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK) +/*! @} */ + +/*! @name INT_STATUS_D1 - Interrupt Status Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK (0x1U) +#define LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT (0U) +/*! PLANE_PANIC - Plane panic to indicate that which FIFO reaches the panic threshold. Write a logic 1 to this field to clear this flag. */ +#define LCDIF_INT_STATUS_D1_PLANE_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT)) & LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK) +/*! @} */ + +/*! @name INT_ENABLE_D1 - Interrupt Enable Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK (0x1U) +#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT (0U) +/*! PLANE_PANIC_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed. */ +#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT)) & LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK) +/*! @} */ + +/*! @name CTRLDESCL_1 - Control Descriptor Layer Register 1 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_1_WIDTH_MASK (0xFFFFU) +#define LCDIF_CTRLDESCL_1_WIDTH_SHIFT (0U) +/*! WIDTH - Width of the layer in pixels. */ +#define LCDIF_CTRLDESCL_1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_1_WIDTH_SHIFT)) & LCDIF_CTRLDESCL_1_WIDTH_MASK) + +#define LCDIF_CTRLDESCL_1_HEIGHT_MASK (0xFFFF0000U) +#define LCDIF_CTRLDESCL_1_HEIGHT_SHIFT (16U) +/*! HEIGHT - Height of the layer in pixels. */ +#define LCDIF_CTRLDESCL_1_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_1_HEIGHT_SHIFT)) & LCDIF_CTRLDESCL_1_HEIGHT_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_1 */ +#define LCDIF_CTRLDESCL_1_COUNT (1U) + +/*! @name CTRLDESCL_3 - Control Descriptor Layer Register 3 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_3_PITCH_MASK (0xFFFFU) +#define LCDIF_CTRLDESCL_3_PITCH_SHIFT (0U) +/*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity + * is supported, but SW should align to 64B boundary. + */ +#define LCDIF_CTRLDESCL_3_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_3_PITCH_SHIFT)) & LCDIF_CTRLDESCL_3_PITCH_MASK) + +#define LCDIF_CTRLDESCL_3_T_SIZE_MASK (0x30000U) +#define LCDIF_CTRLDESCL_3_T_SIZE_SHIFT (16U) +/*! T_SIZE - Transaction Size */ +#define LCDIF_CTRLDESCL_3_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_3_T_SIZE_SHIFT)) & LCDIF_CTRLDESCL_3_T_SIZE_MASK) + +#define LCDIF_CTRLDESCL_3_P_SIZE_MASK (0x700000U) +#define LCDIF_CTRLDESCL_3_P_SIZE_SHIFT (20U) +/*! P_SIZE - Payload size. */ +#define LCDIF_CTRLDESCL_3_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_3_P_SIZE_SHIFT)) & LCDIF_CTRLDESCL_3_P_SIZE_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_3 */ +#define LCDIF_CTRLDESCL_3_COUNT (1U) + +/*! @name CTRLDESCL_LOW_4 - Control Descriptor Layer Register 4 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_MASK (0xFFFFFFFFU) +#define LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_SHIFT (0U) +/*! ADDR_LOW - Address of layer data in the memory. The address programmed should be 128-bit aligned. */ +#define LCDIF_CTRLDESCL_LOW_4_ADDR_LOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_SHIFT)) & LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_LOW_4 */ +#define LCDIF_CTRLDESCL_LOW_4_COUNT (1U) + +/*! @name CTRLDESCL_HIGH_4 - Control Descriptor Layer Register 4 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_MASK (0xFU) +#define LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_SHIFT (0U) +/*! ADDR_HIGH - Address of layer data in the memory. */ +#define LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_SHIFT)) & LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_HIGH_4 */ +#define LCDIF_CTRLDESCL_HIGH_4_COUNT (1U) + +/*! @name CTRLDESCL_5 - Control Descriptor Layer Register 5 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_5_YUV_FORMAT_MASK (0xC000U) +#define LCDIF_CTRLDESCL_5_YUV_FORMAT_SHIFT (14U) +/*! YUV_FORMAT - The YUV422 input format selection. + * 0b00..The YUV422 32bit memory is {Y2,V1,Y1,U1} + * 0b01..The YUV422 32bit memory is {Y2,U1,Y1,V1} + * 0b10..The YUV422 32bit memory is {V1,Y2,U1,Y1} + * 0b11..The YUV422 32bit memory is {U1,Y2,V1,Y1} + */ +#define LCDIF_CTRLDESCL_5_YUV_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_YUV_FORMAT_SHIFT)) & LCDIF_CTRLDESCL_5_YUV_FORMAT_MASK) + +#define LCDIF_CTRLDESCL_5_BPP_MASK (0xF000000U) +#define LCDIF_CTRLDESCL_5_BPP_SHIFT (24U) +/*! BPP - Layer encoding format (bit per pixel) + * 0b0100..16 bpp (RGB565) + * 0b0101..16 bpp (ARGB1555) + * 0b0110..16 bpp (ARGB4444) + * 0b0111..YCbCr422 + * 0b1000..24 bpp (RGB888) + * 0b1001..32 bpp (ARGB8888) + * 0b1010..32 bpp (ABGR8888) + */ +#define LCDIF_CTRLDESCL_5_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_BPP_SHIFT)) & LCDIF_CTRLDESCL_5_BPP_MASK) + +#define LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_MASK (0x40000000U) +#define LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_SHIFT (30U) +/*! SHADOW_LOAD_EN - Shadow Load Enable */ +#define LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_SHIFT)) & LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_MASK) + +#define LCDIF_CTRLDESCL_5_EN_MASK (0x80000000U) +#define LCDIF_CTRLDESCL_5_EN_SHIFT (31U) +/*! EN - Enable the layer for DMA. + * 0b0..OFF + * 0b1..ON + */ +#define LCDIF_CTRLDESCL_5_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_EN_SHIFT)) & LCDIF_CTRLDESCL_5_EN_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_5 */ +#define LCDIF_CTRLDESCL_5_COUNT (1U) + +/*! @name CSC_CTRL - Color Space Conversion Ctrl Register */ +/*! @{ */ + +#define LCDIF_CSC_CTRL_BYPASS_MASK (0x1U) +#define LCDIF_CSC_CTRL_BYPASS_SHIFT (0U) +/*! BYPASS - This bit controls whether the pixels entering the CSC2 unit get converted or not. */ +#define LCDIF_CSC_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_CTRL_BYPASS_SHIFT)) & LCDIF_CSC_CTRL_BYPASS_MASK) + +#define LCDIF_CSC_CTRL_CSC_MODE_MASK (0x6U) +#define LCDIF_CSC_CTRL_CSC_MODE_SHIFT (1U) +/*! CSC_MODE - This field controls how the CSC unit operates on pixels when the CSC is not bypassed. + * 0b00..Convert from YUV to RGB. + * 0b01..Convert from YCbCr to RGB. + * 0b10..Reserved + * 0b11..Convert from RGB to YCbCr. + */ +#define LCDIF_CSC_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_CTRL_CSC_MODE_SHIFT)) & LCDIF_CSC_CTRL_CSC_MODE_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_CTRL */ +#define LCDIF_CSC_CTRL_COUNT (1U) + +/*! @name CSC_COEF0 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ + +#define LCDIF_CSC_COEF0_A1_MASK (0x7FFU) +#define LCDIF_CSC_COEF0_A1_SHIFT (0U) +/*! A1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF0_A1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF0_A1_SHIFT)) & LCDIF_CSC_COEF0_A1_MASK) + +#define LCDIF_CSC_COEF0_A2_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF0_A2_SHIFT (16U) +/*! A2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF0_A2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF0_A2_SHIFT)) & LCDIF_CSC_COEF0_A2_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF0 */ +#define LCDIF_CSC_COEF0_COUNT (1U) + +/*! @name CSC_COEF1 - Color Space Conversion Coefficient Register 1 */ +/*! @{ */ + +#define LCDIF_CSC_COEF1_A3_MASK (0x7FFU) +#define LCDIF_CSC_COEF1_A3_SHIFT (0U) +/*! A3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF1_A3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF1_A3_SHIFT)) & LCDIF_CSC_COEF1_A3_MASK) + +#define LCDIF_CSC_COEF1_B1_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF1_B1_SHIFT (16U) +/*! B1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF1_B1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF1_B1_SHIFT)) & LCDIF_CSC_COEF1_B1_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF1 */ +#define LCDIF_CSC_COEF1_COUNT (1U) + +/*! @name CSC_COEF2 - Color Space Conversion Coefficient Register 2 */ +/*! @{ */ + +#define LCDIF_CSC_COEF2_B2_MASK (0x7FFU) +#define LCDIF_CSC_COEF2_B2_SHIFT (0U) +/*! B2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF2_B2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF2_B2_SHIFT)) & LCDIF_CSC_COEF2_B2_MASK) + +#define LCDIF_CSC_COEF2_B3_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF2_B3_SHIFT (16U) +/*! B3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF2_B3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF2_B3_SHIFT)) & LCDIF_CSC_COEF2_B3_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF2 */ +#define LCDIF_CSC_COEF2_COUNT (1U) + +/*! @name CSC_COEF3 - Color Space Conversion Coefficient Register 3 */ +/*! @{ */ + +#define LCDIF_CSC_COEF3_C1_MASK (0x7FFU) +#define LCDIF_CSC_COEF3_C1_SHIFT (0U) +/*! C1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF3_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF3_C1_SHIFT)) & LCDIF_CSC_COEF3_C1_MASK) + +#define LCDIF_CSC_COEF3_C2_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF3_C2_SHIFT (16U) +/*! C2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF3_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF3_C2_SHIFT)) & LCDIF_CSC_COEF3_C2_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF3 */ +#define LCDIF_CSC_COEF3_COUNT (1U) + +/*! @name CSC_COEF4 - Color Space Conversion Coefficient Register 4 */ +/*! @{ */ + +#define LCDIF_CSC_COEF4_C3_MASK (0x7FFU) +#define LCDIF_CSC_COEF4_C3_SHIFT (0U) +/*! C3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF4_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF4_C3_SHIFT)) & LCDIF_CSC_COEF4_C3_MASK) + +#define LCDIF_CSC_COEF4_D1_MASK (0x1FF0000U) +#define LCDIF_CSC_COEF4_D1_SHIFT (16U) +/*! D1 - Two's complement D1 coefficient integer offset to be added. */ +#define LCDIF_CSC_COEF4_D1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF4_D1_SHIFT)) & LCDIF_CSC_COEF4_D1_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF4 */ +#define LCDIF_CSC_COEF4_COUNT (1U) + +/*! @name CSC_COEF5 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ + +#define LCDIF_CSC_COEF5_D2_MASK (0x1FFU) +#define LCDIF_CSC_COEF5_D2_SHIFT (0U) +/*! D2 - Two's complement D2 coefficient integer offset to be added. */ +#define LCDIF_CSC_COEF5_D2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF5_D2_SHIFT)) & LCDIF_CSC_COEF5_D2_MASK) + +#define LCDIF_CSC_COEF5_D3_MASK (0x1FF0000U) +#define LCDIF_CSC_COEF5_D3_SHIFT (16U) +/*! D3 - Two's complement D3 coefficient integer offset to be added. */ +#define LCDIF_CSC_COEF5_D3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF5_D3_SHIFT)) & LCDIF_CSC_COEF5_D3_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF5 */ +#define LCDIF_CSC_COEF5_COUNT (1U) + +/*! @name PANIC_THRES - Memory request priority threshold register */ +/*! @{ */ + +#define LCDIF_PANIC_THRES_PANIC_THRES_HIGH_MASK (0x1FFU) +#define LCDIF_PANIC_THRES_PANIC_THRES_HIGH_SHIFT (0U) +/*! PANIC_THRES_HIGH - Panic Threshold High Value */ +#define LCDIF_PANIC_THRES_PANIC_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC_THRES_PANIC_THRES_HIGH_SHIFT)) & LCDIF_PANIC_THRES_PANIC_THRES_HIGH_MASK) + +#define LCDIF_PANIC_THRES_PANIC_THRES_LOW_MASK (0x1FF0000U) +#define LCDIF_PANIC_THRES_PANIC_THRES_LOW_SHIFT (16U) +/*! PANIC_THRES_LOW - Panic Threshold Low Value */ +#define LCDIF_PANIC_THRES_PANIC_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC_THRES_PANIC_THRES_LOW_SHIFT)) & LCDIF_PANIC_THRES_PANIC_THRES_LOW_MASK) +/*! @} */ + +/* The count of LCDIF_PANIC_THRES */ +#define LCDIF_PANIC_THRES_COUNT (1U) + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x4AE30000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ + uint8_t RESERVED_13[132]; + __O uint32_t MTCBR[128]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t MTDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b0..No effect + * 0b1..Stop or repeated Start generated + * 0b1..Clear the flag + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b0..No effect + * 0b1..Stop condition generated + * 0b1..Clear the flag + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No unexpected NACK detected + * 0b0..No effect + * 0b1..Unexpected NACK detected + * 0b1..Clear the flag + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b0..No effect + * 0b1..Controller lost arbitration + * 0b1..Clear the flag + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..FIFO error + * 0b1..Clear the flag + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout did not occur + * 0b0..No effect + * 0b1..Pin low timeout occurred + * 0b1..Clear the flag + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b0..No effect + * 0b1..Matching data received + * 0b1..Clear the flag + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b0..No effect + * 0b1..Start condition detected + * 0b1..Clear the flag + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0.. + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x7U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x70000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0xFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b0..No effect + * 0b1..Repeated Start detected + * 0b1..Clear the flag + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b0..No effect + * 0b1..Stop detected + * 0b1..Clear the flag + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b0..No effect + * 0b1..Bit error occurred + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..FIFO error + * 0b1..Clear the flag + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + +/*! @name MTCBR - Controller Transmit Command Burst */ +/*! @{ */ + +#define LPI2C_MTCBR_DATA_MASK (0xFFU) +#define LPI2C_MTCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) + +#define LPI2C_MTCBR_CMD_MASK (0x700U) +#define LPI2C_MTCBR_CMD_SHIFT (8U) +/*! CMD - Command */ +#define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) +/*! @} */ + +/* The count of LPI2C_MTCBR */ +#define LPI2C_MTCBR_COUNT (128U) + +/*! @name MTDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPI2C_MTDBR_DATA0_MASK (0xFFU) +#define LPI2C_MTDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data */ +#define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) + +#define LPI2C_MTDBR_DATA1_MASK (0xFF00U) +#define LPI2C_MTDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data */ +#define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) + +#define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) +#define LPI2C_MTDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data */ +#define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) + +#define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) +#define LPI2C_MTDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data */ +#define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPI2C_MTDBR */ +#define LPI2C_MTDBR_COUNT (256U) + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x44340000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x44350000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x42530000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Peripheral LPI2C4 base address */ +#define LPI2C4_BASE (0x42540000u) +/** Peripheral LPI2C4 base pointer */ +#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) +/** Peripheral LPI2C5 base address */ +#define LPI2C5_BASE (0x426B0000u) +/** Peripheral LPI2C5 base pointer */ +#define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) +/** Peripheral LPI2C6 base address */ +#define LPI2C6_BASE (0x426C0000u) +/** Peripheral LPI2C6 base pointer */ +#define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) +/** Peripheral LPI2C7 base address */ +#define LPI2C7_BASE (0x426D0000u) +/** Peripheral LPI2C7 base pointer */ +#define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) +/** Peripheral LPI2C8 base address */ +#define LPI2C8_BASE (0x426E0000u) +/** Peripheral LPI2C8 base pointer */ +#define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn, LPI2C7_IRQn, LPI2C8_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer + * @{ + */ + +/** LPIT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t MCR; /**< Module Control, offset: 0x8 */ + __IO uint32_t MSR; /**< Module Status, offset: 0xC */ + __IO uint32_t MIER; /**< Module Interrupt Enable, offset: 0x10 */ + __IO uint32_t SETTEN; /**< Set Timer Enable, offset: 0x14 */ + __IO uint32_t CLRTEN; /**< Clear Timer Enable, offset: 0x18 */ + uint8_t RESERVED_0[4]; + struct { /* offset: 0x20, array step: 0x10 */ + __IO uint32_t TVAL; /**< Timer Value, array offset: 0x20, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control, array offset: 0x28, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[4]; +} LPIT_Type; + +/* ---------------------------------------------------------------------------- + -- LPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPIT_Register_Masks LPIT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPIT_VERID_FEATURE_MASK (0xFFFFU) +#define LPIT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Number */ +#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) + +#define LPIT_VERID_MINOR_MASK (0xFF0000U) +#define LPIT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) + +#define LPIT_VERID_MAJOR_MASK (0xFF000000U) +#define LPIT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPIT_PARAM_CHANNEL_MASK (0xFFU) +#define LPIT_PARAM_CHANNEL_SHIFT (0U) +/*! CHANNEL - Number of Timer Channels */ +#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) + +#define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) +#define LPIT_PARAM_EXT_TRIG_SHIFT (8U) +/*! EXT_TRIG - Number of External Trigger Inputs */ +#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) +/*! @} */ + +/*! @name MCR - Module Control */ +/*! @{ */ + +#define LPIT_MCR_M_CEN_MASK (0x1U) +#define LPIT_MCR_M_CEN_SHIFT (0U) +/*! M_CEN - Module Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) + +#define LPIT_MCR_SW_RST_MASK (0x2U) +#define LPIT_MCR_SW_RST_SHIFT (1U) +/*! SW_RST - Software Reset + * 0b0..Does not reset + * 0b1..Resets + */ +#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) + +#define LPIT_MCR_DOZE_EN_MASK (0x4U) +#define LPIT_MCR_DOZE_EN_SHIFT (2U) +/*! DOZE_EN - DOZE Mode Enable + * 0b0..Stops timer channels + * 0b1..Allows timer channels to continue running + */ +#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) + +#define LPIT_MCR_DBG_EN_MASK (0x8U) +#define LPIT_MCR_DBG_EN_SHIFT (3U) +/*! DBG_EN - Debug Mode Enable + * 0b0..Stops timer channels + * 0b1..Allows timer channels to continue running + */ +#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) +/*! @} */ + +/*! @name MSR - Module Status */ +/*! @{ */ + +#define LPIT_MSR_TIF0_MASK (0x1U) +#define LPIT_MSR_TIF0_SHIFT (0U) +/*! TIF0 - Channel 0 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) + +#define LPIT_MSR_TIF1_MASK (0x2U) +#define LPIT_MSR_TIF1_SHIFT (1U) +/*! TIF1 - Channel 1 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) + +#define LPIT_MSR_TIF2_MASK (0x4U) +#define LPIT_MSR_TIF2_SHIFT (2U) +/*! TIF2 - Channel 2 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) + +#define LPIT_MSR_TIF3_MASK (0x8U) +#define LPIT_MSR_TIF3_SHIFT (3U) +/*! TIF3 - Channel 3 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) +/*! @} */ + +/*! @name MIER - Module Interrupt Enable */ +/*! @{ */ + +#define LPIT_MIER_TIE0_MASK (0x1U) +#define LPIT_MIER_TIE0_SHIFT (0U) +/*! TIE0 - Channel 0 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) + +#define LPIT_MIER_TIE1_MASK (0x2U) +#define LPIT_MIER_TIE1_SHIFT (1U) +/*! TIE1 - Channel 1 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) + +#define LPIT_MIER_TIE2_MASK (0x4U) +#define LPIT_MIER_TIE2_SHIFT (2U) +/*! TIE2 - Channel 2 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) + +#define LPIT_MIER_TIE3_MASK (0x8U) +#define LPIT_MIER_TIE3_SHIFT (3U) +/*! TIE3 - Channel 3 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) +/*! @} */ + +/*! @name SETTEN - Set Timer Enable */ +/*! @{ */ + +#define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) +#define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) +/*! SET_T_EN_0 - Set Timer 0 Enable + * 0b0..No effect + * 0b1..Enables timer channel 0 + */ +#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) + +#define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) +#define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) +/*! SET_T_EN_1 - Set Timer 1 Enable + * 0b0..No Effect + * 0b1..Enables timer channel 1 + */ +#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) + +#define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) +#define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) +/*! SET_T_EN_2 - Set Timer 2 Enable + * 0b0..No Effect + * 0b1..Enables timer channel 2 + */ +#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) + +#define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) +#define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) +/*! SET_T_EN_3 - Set Timer 3 Enable + * 0b0..No effect + * 0b1..Enables timer channel 3 + */ +#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) +/*! @} */ + +/*! @name CLRTEN - Clear Timer Enable */ +/*! @{ */ + +#define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) +#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) +/*! CLR_T_EN_0 - Clear Timer 0 Enable + * 0b0..No action + * 0b1..Turns TCTRL0[T_EN] = 0 for timer channel 0 + */ +#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) + +#define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) +#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) +/*! CLR_T_EN_1 - Clear Timer 1 Enable + * 0b0..No action + * 0b1..Turns TCTRL1[T_EN] = 0 for timer channel 1 + */ +#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) + +#define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) +#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) +/*! CLR_T_EN_2 - Clear Timer 2 Enable + * 0b0..No action + * 0b1..Turns TCTRL2[T_EN] = 0 for timer channel 2 + */ +#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) + +#define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) +#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) +/*! CLR_T_EN_3 - Clear Timer 3 Enable + * 0b0..No action + * 0b1..Turns TCTRL3[T_EN] = 0 for timer channel 3 + */ +#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) +/*! @} */ + +/*! @name TVAL - Timer Value */ +/*! @{ */ + +#define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) +#define LPIT_TVAL_TMR_VAL_SHIFT (0U) +/*! TMR_VAL - Timer Value + * 0b00000000000000000000000000000000, 0b00000000000000000000000000000001..Invalid load value in Compare mode + * 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In Compare mode: the value to be loaded; in Capture mode, the value of the timer + */ +#define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) +/*! @} */ + +/* The count of LPIT_TVAL */ +#define LPIT_TVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value */ +/*! @{ */ + +#define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) +#define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) +/*! TMR_CUR_VAL - Current Timer Value */ +#define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) +/*! @} */ + +/* The count of LPIT_CVAL */ +#define LPIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control */ +/*! @{ */ + +#define LPIT_TCTRL_T_EN_MASK (0x1U) +#define LPIT_TCTRL_T_EN_SHIFT (0U) +/*! T_EN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) + +#define LPIT_TCTRL_CHAIN_MASK (0x2U) +#define LPIT_TCTRL_CHAIN_SHIFT (1U) +/*! CHAIN - Chain Channel + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) + +#define LPIT_TCTRL_MODE_MASK (0xCU) +#define LPIT_TCTRL_MODE_SHIFT (2U) +/*! MODE - Timer Operation Mode + * 0b00..32-bit periodic counter + * 0b01..Dual 16-bit periodic counter + * 0b10..32-bit trigger accumulator + * 0b11..32-bit trigger input capture + */ +#define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) + +#define LPIT_TCTRL_TSOT_MASK (0x10000U) +#define LPIT_TCTRL_TSOT_SHIFT (16U) +/*! TSOT - Timer Start on Trigger + * 0b0..Immediately + * 0b1..When a rising edge is detected + */ +#define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) + +#define LPIT_TCTRL_TSOI_MASK (0x20000U) +#define LPIT_TCTRL_TSOI_SHIFT (17U) +/*! TSOI - Timer Stop on Interrupt + * 0b0..Does not stop + * 0b1..Stops + */ +#define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) + +#define LPIT_TCTRL_TROT_MASK (0x40000U) +#define LPIT_TCTRL_TROT_SHIFT (18U) +/*! TROT - Timer Reload on Trigger + * 0b0..Does not reload + * 0b1..Reloads + */ +#define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) + +#define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) +#define LPIT_TCTRL_TRG_SRC_SHIFT (23U) +/*! TRG_SRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) + +#define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) +#define LPIT_TCTRL_TRG_SEL_SHIFT (24U) +/*! TRG_SEL - Trigger Select + * 0b0000-0b0011..Timer channel 0-3 trigger source + * 0b0100-0b1111..Reserved + */ +#define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) +/*! @} */ + +/* The count of LPIT_TCTRL */ +#define LPIT_TCTRL_COUNT (4U) + + +/*! + * @} + */ /* end of group LPIT_Register_Masks */ + + +/* LPIT - Peripheral instance base addresses */ +/** Peripheral LPIT1 base address */ +#define LPIT1_BASE (0x442F0000u) +/** Peripheral LPIT1 base pointer */ +#define LPIT1 ((LPIT_Type *)LPIT1_BASE) +/** Peripheral LPIT2 base address */ +#define LPIT2_BASE (0x424C0000u) +/** Peripheral LPIT2 base pointer */ +#define LPIT2 ((LPIT_Type *)LPIT2_BASE) +/** Array initializer of LPIT peripheral base addresses */ +#define LPIT_BASE_ADDRS { 0u, LPIT1_BASE, LPIT2_BASE } +/** Array initializer of LPIT peripheral base pointers */ +#define LPIT_BASE_PTRS { (LPIT_Type *)0u, LPIT1, LPIT2 } + +/*! + * @} + */ /* end of group LPIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No underrun + * 0b0..No effect + * 0b1..Underrun + * 0b1..Clear the flag + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No overflow + * 0b0..No effect + * 0b1..Overflow + * 0b1..Clear the flag + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No match + * 0b0..No effect + * 0b1..Match + * 0b1..Clear the flag + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Controller Mode + * 0b0..Peripheral mode + * 0b1..Controller mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0x700U) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b000..Active low + * 0b001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x7U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x70000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0xFU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0xF0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word or RX FIFO is empty (RXEMPTY=1). + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_TDBR */ +#define LPSPI_TDBR_COUNT (128U) + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_RDBR */ +#define LPSPI_RDBR_COUNT (128U) + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x44360000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE (0x44370000u) +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) +/** Peripheral LPSPI3 base address */ +#define LPSPI3_BASE (0x42550000u) +/** Peripheral LPSPI3 base pointer */ +#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) +/** Peripheral LPSPI4 base address */ +#define LPSPI4_BASE (0x42560000u) +/** Peripheral LPSPI4 base pointer */ +#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) +/** Peripheral LPSPI5 base address */ +#define LPSPI5_BASE (0x426F0000u) +/** Peripheral LPSPI5 base pointer */ +#define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) +/** Peripheral LPSPI6 base address */ +#define LPSPI6_BASE (0x42700000u) +/** Peripheral LPSPI6 base pointer */ +#define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) +/** Peripheral LPSPI7 base address */ +#define LPSPI7_BASE (0x42710000u) +/** Peripheral LPSPI7 base pointer */ +#define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) +/** Peripheral LPSPI8 base address */ +#define LPSPI8_BASE (0x42720000u) +/** Peripheral LPSPI8 base pointer */ +#define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn, LPSPI7_IRQn, LPSPI8_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b0..No effect + * 0b1..CNR = (CMR + 1) + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR1 base address */ +#define LPTMR1_BASE (0x44300000u) +/** Peripheral LPTMR1 base pointer */ +#define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) +/** Peripheral LPTMR2 base address */ +#define LPTMR2_BASE (0x424D0000u) +/** Peripheral LPTMR2 base pointer */ +#define LPTMR2 ((LPTMR_Type *)LPTMR2_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { 0u, LPTMR1_BASE, LPTMR2_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { (LPTMR_Type *)0u, LPTMR1, LPTMR2 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { NotAvail_IRQn, LPTMR1_IRQn, LPTMR2_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MCR; /**< MODEM Control, offset: 0x40 */ + __IO uint32_t MSR; /**< MODEM Status, offset: 0x44 */ + __IO uint32_t REIR; /**< Receiver Extended Idle, offset: 0x48 */ + __IO uint32_t TEIR; /**< Transmitter Extended Idle, offset: 0x4C */ + __IO uint32_t HDCR; /**< Half Duplex Control, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TOCR; /**< Timeout Control, offset: 0x58 */ + __IO uint32_t TOSR; /**< Timeout Status, offset: 0x5C */ + __IO uint32_t TIMEOUT[4]; /**< Timeout N, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_2[400]; + __O uint32_t TCBR[128]; /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t TDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + * 0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MSF_MASK (0x100U) +#define LPUART_STAT_MSF_SHIFT (8U) +/*! MSF - MODEM Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_MSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK) + +#define LPUART_STAT_TSF_MASK (0x200U) +#define LPUART_STAT_TSF_SHIFT (9U) +/*! TSF - Timeout Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Not equal to MA2 + * 0b0..No effect + * 0b1..Equal to MA2 + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Not equal to MA1 + * 0b0..No effect + * 0b1..Equal to MA1 + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error detected + * 0b0..No effect + * 0b1..Parity error detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b0..No effect + * 0b1..Framing error detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected + * 0b0..No effect + * 0b1..Noise detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun + * 0b0..No effect + * 0b1..Receive overrun (new LPUART data is lost) + * 0b1..Clear the flag + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b0..No effect + * 0b1..Idle line not detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..Not occurred + * 0b0..No effect + * 0b1..Occurred + * 0b1..Clear the flag + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0xF00U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No underflow + * 0b0..No effect + * 0b1..Underflow + * 0b1..Clear the flag + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No overflow + * 0b0..No effect + * 0b1..Overflow + * 0b1..Clear the flag + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0xFU) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0x1F00U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0xF0000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0x1F000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + +/*! @name MCR - MODEM Control */ +/*! @{ */ + +#define LPUART_MCR_CTS_MASK (0x1U) +#define LPUART_MCR_CTS_SHIFT (0U) +/*! CTS - Clear To Send + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) + +#define LPUART_MCR_DSR_MASK (0x2U) +#define LPUART_MCR_DSR_SHIFT (1U) +/*! DSR - Data Set Ready + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) + +#define LPUART_MCR_RIN_MASK (0x4U) +#define LPUART_MCR_RIN_SHIFT (2U) +/*! RIN - Ring Indicator + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) + +#define LPUART_MCR_DCD_MASK (0x8U) +#define LPUART_MCR_DCD_SHIFT (3U) +/*! DCD - Data Carrier Detect + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) + +#define LPUART_MCR_DTR_MASK (0x100U) +#define LPUART_MCR_DTR_SHIFT (8U) +/*! DTR - Data Terminal Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) + +#define LPUART_MCR_RTS_MASK (0x200U) +#define LPUART_MCR_RTS_SHIFT (9U) +/*! RTS - Request To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) +/*! @} */ + +/*! @name MSR - MODEM Status */ +/*! @{ */ + +#define LPUART_MSR_DCTS_MASK (0x1U) +#define LPUART_MSR_DCTS_SHIFT (0U) +/*! DCTS - Delta Clear To Send + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) + +#define LPUART_MSR_DDSR_MASK (0x2U) +#define LPUART_MSR_DDSR_SHIFT (1U) +/*! DDSR - Delta Data Set Ready + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) + +#define LPUART_MSR_DRI_MASK (0x4U) +#define LPUART_MSR_DRI_SHIFT (2U) +/*! DRI - Delta Ring Indicator + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) + +#define LPUART_MSR_DDCD_MASK (0x8U) +#define LPUART_MSR_DDCD_SHIFT (3U) +/*! DDCD - Delta Data Carrier Detect + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) + +#define LPUART_MSR_CTS_MASK (0x10U) +#define LPUART_MSR_CTS_SHIFT (4U) +/*! CTS - Clear To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) + +#define LPUART_MSR_DSR_MASK (0x20U) +#define LPUART_MSR_DSR_SHIFT (5U) +/*! DSR - Data Set Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) + +#define LPUART_MSR_RIN_MASK (0x40U) +#define LPUART_MSR_RIN_SHIFT (6U) +/*! RIN - Ring Indicator + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) + +#define LPUART_MSR_DCD_MASK (0x80U) +#define LPUART_MSR_DCD_SHIFT (7U) +/*! DCD - Data Carrier Detect + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) +/*! @} */ + +/*! @name REIR - Receiver Extended Idle */ +/*! @{ */ + +#define LPUART_REIR_IDTIME_MASK (0x3FFFU) +#define LPUART_REIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_REIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK) +/*! @} */ + +/*! @name TEIR - Transmitter Extended Idle */ +/*! @{ */ + +#define LPUART_TEIR_IDTIME_MASK (0x3FFFU) +#define LPUART_TEIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_TEIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK) +/*! @} */ + +/*! @name HDCR - Half Duplex Control */ +/*! @{ */ + +#define LPUART_HDCR_TXSTALL_MASK (0x1U) +#define LPUART_HDCR_TXSTALL_SHIFT (0U) +/*! TXSTALL - Transmit Stall + * 0b0..No effect + * 0b1..Does not become busy + */ +#define LPUART_HDCR_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK) + +#define LPUART_HDCR_RXSEL_MASK (0x2U) +#define LPUART_HDCR_RXSEL_SHIFT (1U) +/*! RXSEL - Receive Select + * 0b0..RXD + * 0b1..TXD + */ +#define LPUART_HDCR_RXSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK) + +#define LPUART_HDCR_RXWRMSK_MASK (0x4U) +#define LPUART_HDCR_RXWRMSK_SHIFT (2U) +/*! RXWRMSK - Receive FIFO Write Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) + +#define LPUART_HDCR_RXMSK_MASK (0x8U) +#define LPUART_HDCR_RXMSK_SHIFT (3U) +/*! RXMSK - Receive Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) + +#define LPUART_HDCR_RTSEXT_MASK (0xFF00U) +#define LPUART_HDCR_RTSEXT_SHIFT (8U) +/*! RTSEXT - RTS Extended */ +#define LPUART_HDCR_RTSEXT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK) +/*! @} */ + +/*! @name TOCR - Timeout Control */ +/*! @{ */ + +#define LPUART_TOCR_TOEN_MASK (0xFU) +#define LPUART_TOCR_TOEN_SHIFT (0U) +/*! TOEN - Timeout Enable */ +#define LPUART_TOCR_TOEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK) + +#define LPUART_TOCR_TOIE_MASK (0xF00U) +#define LPUART_TOCR_TOIE_SHIFT (8U) +/*! TOIE - Timeout Interrupt Enable */ +#define LPUART_TOCR_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK) +/*! @} */ + +/*! @name TOSR - Timeout Status */ +/*! @{ */ + +#define LPUART_TOSR_TOZ_MASK (0xFU) +#define LPUART_TOSR_TOZ_SHIFT (0U) +/*! TOZ - Timeout Zero */ +#define LPUART_TOSR_TOZ(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK) + +#define LPUART_TOSR_TOF_MASK (0xF00U) +#define LPUART_TOSR_TOF_SHIFT (8U) +/*! TOF - Timeout Flag + * 0b0000..Not occurred + * 0b0000..No effect + * 0b0001..Occurred + * 0b0001..Clear the flag + */ +#define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) +/*! @} */ + +/*! @name TIMEOUT - Timeout N */ +/*! @{ */ + +#define LPUART_TIMEOUT_TIMEOUT_MASK (0x3FFFU) +#define LPUART_TIMEOUT_TIMEOUT_SHIFT (0U) +/*! TIMEOUT - Timeout Value */ +#define LPUART_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK) + +#define LPUART_TIMEOUT_CFG_MASK (0xC0000000U) +#define LPUART_TIMEOUT_CFG_SHIFT (30U) +/*! CFG - Idle Configuration + * 0b00..Becomes 1 after timeout characters are received + * 0b01..Becomes 1 when idle for timeout bit clocks + * 0b10..Becomes 1 when idle for timeout bit clocks following the next character + * 0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached + */ +#define LPUART_TIMEOUT_CFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK) +/*! @} */ + +/* The count of LPUART_TIMEOUT */ +#define LPUART_TIMEOUT_COUNT (4U) + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPUART_TCBR_DATA_MASK (0xFFFFU) +#define LPUART_TCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPUART_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK) +/*! @} */ + +/* The count of LPUART_TCBR */ +#define LPUART_TCBR_COUNT (128U) + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPUART_TDBR_DATA0_MASK (0xFFU) +#define LPUART_TDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data0 */ +#define LPUART_TDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK) + +#define LPUART_TDBR_DATA1_MASK (0xFF00U) +#define LPUART_TDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data1 */ +#define LPUART_TDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK) + +#define LPUART_TDBR_DATA2_MASK (0xFF0000U) +#define LPUART_TDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data2 */ +#define LPUART_TDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK) + +#define LPUART_TDBR_DATA3_MASK (0xFF000000U) +#define LPUART_TDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data3 */ +#define LPUART_TDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPUART_TDBR */ +#define LPUART_TDBR_COUNT (256U) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x44380000u) +/** Peripheral LPUART1 base pointer */ +extern LPUART_Type* LPUART1; +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x44390000u) +/** Peripheral LPUART2 base pointer */ +extern LPUART_Type* LPUART2; +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x42570000u) +/** Peripheral LPUART3 base pointer */ +extern LPUART_Type* LPUART3; +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x42580000u) +/** Peripheral LPUART4 base pointer */ +extern LPUART_Type* LPUART4; +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x42590000u) +/** Peripheral LPUART5 base pointer */ +extern LPUART_Type* LPUART5; +/** Peripheral LPUART6 base address */ +#define LPUART6_BASE (0x425A0000u) +/** Peripheral LPUART6 base pointer */ +extern LPUART_Type* LPUART6; +/** Peripheral LPUART7 base address */ +#define LPUART7_BASE (0x42690000u) +/** Peripheral LPUART7 base pointer */ +extern LPUART_Type* LPUART7; +/** Peripheral LPUART8 base address */ +#define LPUART8_BASE (0x426A0000u) +/** Peripheral LPUART8 base pointer */ +extern LPUART_Type* LPUART8; +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { (LPUART_Type **)0u, &LPUART1, &LPUART2, &LPUART3, &LPUART4, &LPUART5, &LPUART6, &LPUART7, &LPUART8 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer + * @{ + */ + +/** MU - Register Layout Typedef */ +typedef struct { + __I uint32_t VER; /**< Version ID, offset: 0x0 */ + __I uint32_t PAR; /**< Parameter, offset: 0x4 */ + __IO uint32_t CR; /**< Control, offset: 0x8 */ + __IO uint32_t SR; /**< Status, offset: 0xC */ + __IO uint32_t CCR0; /**< Core Control 0, offset: 0x10 */ + uint32_t CIER0; /**< Core Interrupt Enable 0, offset: 0x14 */ + __IO uint32_t CSSR0; /**< Core Sticky Status 0, offset: 0x18 */ + uint8_t RESERVED_0[228]; + __IO uint32_t FCR; /**< Flag Control, offset: 0x100 */ + __I uint32_t FSR; /**< Flag Status, offset: 0x104 */ + uint8_t RESERVED_1[8]; + __IO uint32_t GIER; /**< General-Purpose Interrupt Enable, offset: 0x110 */ + __IO uint32_t GCR; /**< General-Purpose Control, offset: 0x114 */ + __IO uint32_t GSR; /**< General-purpose Status, offset: 0x118 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TCR; /**< Transmit Control, offset: 0x120 */ + __I uint32_t TSR; /**< Transmit Status, offset: 0x124 */ + __IO uint32_t RCR; /**< Receive Control, offset: 0x128 */ + __I uint32_t RSR; /**< Receive Status, offset: 0x12C */ + uint8_t RESERVED_3[208]; + __IO uint32_t TR[4]; /**< Transmit, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __I uint32_t RR[4]; /**< Receive, array offset: 0x280, array step: 0x4 */ +} MU_Type; + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/*! @name VER - Version ID */ +/*! @{ */ + +#define MU_VER_FEATURE_MASK (0xFFFFU) +#define MU_VER_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Set Number */ +#define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) + +#define MU_VER_MINOR_MASK (0xFF0000U) +#define MU_VER_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) + +#define MU_VER_MAJOR_MASK (0xFF000000U) +#define MU_VER_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) +/*! @} */ + +/*! @name PAR - Parameter */ +/*! @{ */ + +#define MU_PAR_TR_NUM_MASK (0xFFU) +#define MU_PAR_TR_NUM_SHIFT (0U) +/*! TR_NUM - Transmit Register Number */ +#define MU_PAR_TR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK) + +#define MU_PAR_RR_NUM_MASK (0xFF00U) +#define MU_PAR_RR_NUM_SHIFT (8U) +/*! RR_NUM - Receive Register Number */ +#define MU_PAR_RR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK) + +#define MU_PAR_GIR_NUM_MASK (0xFF0000U) +#define MU_PAR_GIR_NUM_SHIFT (16U) +/*! GIR_NUM - General-Purpose Interrupt Request Number */ +#define MU_PAR_GIR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK) + +#define MU_PAR_FLAG_WIDTH_MASK (0xFF000000U) +#define MU_PAR_FLAG_WIDTH_SHIFT (24U) +/*! FLAG_WIDTH - Flag Width */ +#define MU_PAR_FLAG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define MU_CR_MUR_MASK (0x1U) +#define MU_CR_MUR_SHIFT (0U) +/*! MUR - MU Reset + * 0b0..Idle + * 0b1..Reset + */ +#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) + +#define MU_CR_MURIE_MASK (0x2U) +#define MU_CR_MURIE_SHIFT (1U) +/*! MURIE - MUB Reset Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_CR_MURIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define MU_SR_MURS_MASK (0x1U) +#define MU_SR_MURS_SHIFT (0U) +/*! MURS - MUA and MUB Reset State + * 0b0..Out of reset + * 0b1..In reset + */ +#define MU_SR_MURS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK) + +#define MU_SR_MURIP_MASK (0x2U) +#define MU_SR_MURIP_SHIFT (1U) +/*! MURIP - MU Reset Interrupt Pending Flag + * 0b0..Reset not issued + * 0b0..No effect + * 0b1..Reset issued + * 0b1..Clear the flag + */ +#define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) + +#define MU_SR_EP_MASK (0x4U) +#define MU_SR_EP_SHIFT (2U) +/*! EP - MUB Side Event Pending + * 0b0..Not pending + * 0b1..Pending + */ +#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) + +#define MU_SR_FUP_MASK (0x8U) +#define MU_SR_FUP_SHIFT (3U) +/*! FUP - MUB Flag Update Pending + * 0b0..No pending update flags (initiated by MUA) + * 0b1..Pending update flags (initiated by MUA) + */ +#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) + +#define MU_SR_GIRP_MASK (0x10U) +#define MU_SR_GIRP_SHIFT (4U) +/*! GIRP - MUB General-Purpose Interrupt Pending + * 0b0..No request sent + * 0b1..Request sent + */ +#define MU_SR_GIRP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK) + +#define MU_SR_TEP_MASK (0x20U) +#define MU_SR_TEP_SHIFT (5U) +/*! TEP - MUB Transmit Empty Pending + * 0b0..Not pending; MUA is reading no Receive (RRn) register + * 0b1..Pending; MUA is reading a Receive (RRn) register + */ +#define MU_SR_TEP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK) + +#define MU_SR_RFP_MASK (0x40U) +#define MU_SR_RFP_SHIFT (6U) +/*! RFP - MUB Receive Full Pending + * 0b0..Not pending; MUA is not writing to a Transmit register + * 0b1..Pending; MUA is writing to a Transmit register + */ +#define MU_SR_RFP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK) +/*! @} */ + +/*! @name CCR0 - Core Control 0 */ +/*! @{ */ + +#define MU_CCR0_NMI_MASK (0x1U) +#define MU_CCR0_NMI_SHIFT (0U) +/*! NMI - MUB Nonmaskable Interrupt Request + * 0b0..Nonmaskable interrupt not issued + * 0b1..Nonmaskable interrupt issued + */ +#define MU_CCR0_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR0_NMI_SHIFT)) & MU_CCR0_NMI_MASK) +/*! @} */ + +/*! @name CSSR0 - Core Sticky Status 0 */ +/*! @{ */ + +#define MU_CSSR0_NMIC_MASK (0x1U) +#define MU_CSSR0_NMIC_SHIFT (0U) +/*! NMIC - Processor B Nonmaskable Interrupt Clear + * 0b0..Default + * 0b1..Clear MUA_CCR0[NMI] + */ +#define MU_CSSR0_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_NMIC_SHIFT)) & MU_CSSR0_NMIC_MASK) +/*! @} */ + +/*! @name FCR - Flag Control */ +/*! @{ */ + +#define MU_FCR_F0_MASK (0x1U) +#define MU_FCR_F0_SHIFT (0U) +/*! F0 - MUB to MUA Flag + * 0b0..Clear MUA_FSR[Fn] + * 0b1..Set MUA_FSR[Fn] + */ +#define MU_FCR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK) + +#define MU_FCR_F1_MASK (0x2U) +#define MU_FCR_F1_SHIFT (1U) +/*! F1 - MUB to MUA Flag + * 0b0..Clear MUA_FSR[Fn] + * 0b1..Set MUA_FSR[Fn] + */ +#define MU_FCR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK) + +#define MU_FCR_F2_MASK (0x4U) +#define MU_FCR_F2_SHIFT (2U) +/*! F2 - MUB to MUA Flag + * 0b0..Clear MUA_FSR[Fn] + * 0b1..Set MUA_FSR[Fn] + */ +#define MU_FCR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK) +/*! @} */ + +/*! @name FSR - Flag Status */ +/*! @{ */ + +#define MU_FSR_F0_MASK (0x1U) +#define MU_FSR_F0_SHIFT (0U) +/*! F0 - MUB to MUA-Side Flag + * 0b0..MUA_FCR[Fn] = 0 + * 0b1..MUA_FCR[Fn] = 1 + */ +#define MU_FSR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK) + +#define MU_FSR_F1_MASK (0x2U) +#define MU_FSR_F1_SHIFT (1U) +/*! F1 - MUB to MUA-Side Flag + * 0b0..MUA_FCR[Fn] = 0 + * 0b1..MUA_FCR[Fn] = 1 + */ +#define MU_FSR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK) + +#define MU_FSR_F2_MASK (0x4U) +#define MU_FSR_F2_SHIFT (2U) +/*! F2 - MUB to MUA-Side Flag + * 0b0..MUA_FCR[Fn] = 0 + * 0b1..MUA_FCR[Fn] = 1 + */ +#define MU_FSR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK) +/*! @} */ + +/*! @name GIER - General-Purpose Interrupt Enable */ +/*! @{ */ + +#define MU_GIER_GIE0_MASK (0x1U) +#define MU_GIER_GIE0_SHIFT (0U) +/*! GIE0 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK) + +#define MU_GIER_GIE1_MASK (0x2U) +#define MU_GIER_GIE1_SHIFT (1U) +/*! GIE1 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK) + +#define MU_GIER_GIE2_MASK (0x4U) +#define MU_GIER_GIE2_SHIFT (2U) +/*! GIE2 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK) + +#define MU_GIER_GIE3_MASK (0x8U) +#define MU_GIER_GIE3_SHIFT (3U) +/*! GIE3 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK) +/*! @} */ + +/*! @name GCR - General-Purpose Control */ +/*! @{ */ + +#define MU_GCR_GIR0_MASK (0x1U) +#define MU_GCR_GIR0_SHIFT (0U) +/*! GIR0 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR0(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK) + +#define MU_GCR_GIR1_MASK (0x2U) +#define MU_GCR_GIR1_SHIFT (1U) +/*! GIR1 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR1(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK) + +#define MU_GCR_GIR2_MASK (0x4U) +#define MU_GCR_GIR2_SHIFT (2U) +/*! GIR2 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR2(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK) + +#define MU_GCR_GIR3_MASK (0x8U) +#define MU_GCR_GIR3_SHIFT (3U) +/*! GIR3 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR3(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK) +/*! @} */ + +/*! @name GSR - General-purpose Status */ +/*! @{ */ + +#define MU_GSR_GIP0_MASK (0x1U) +#define MU_GSR_GIP0_SHIFT (0U) +/*! GIP0 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP0(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK) + +#define MU_GSR_GIP1_MASK (0x2U) +#define MU_GSR_GIP1_SHIFT (1U) +/*! GIP1 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP1(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK) + +#define MU_GSR_GIP2_MASK (0x4U) +#define MU_GSR_GIP2_SHIFT (2U) +/*! GIP2 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP2(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK) + +#define MU_GSR_GIP3_MASK (0x8U) +#define MU_GSR_GIP3_SHIFT (3U) +/*! GIP3 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP3(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control */ +/*! @{ */ + +#define MU_TCR_TIE0_MASK (0x1U) +#define MU_TCR_TIE0_SHIFT (0U) +/*! TIE0 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK) + +#define MU_TCR_TIE1_MASK (0x2U) +#define MU_TCR_TIE1_SHIFT (1U) +/*! TIE1 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK) + +#define MU_TCR_TIE2_MASK (0x4U) +#define MU_TCR_TIE2_SHIFT (2U) +/*! TIE2 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK) + +#define MU_TCR_TIE3_MASK (0x8U) +#define MU_TCR_TIE3_SHIFT (3U) +/*! TIE3 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK) +/*! @} */ + +/*! @name TSR - Transmit Status */ +/*! @{ */ + +#define MU_TSR_TE0_MASK (0x1U) +#define MU_TSR_TE0_SHIFT (0U) +/*! TE0 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK) + +#define MU_TSR_TE1_MASK (0x2U) +#define MU_TSR_TE1_SHIFT (1U) +/*! TE1 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK) + +#define MU_TSR_TE2_MASK (0x4U) +#define MU_TSR_TE2_SHIFT (2U) +/*! TE2 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK) + +#define MU_TSR_TE3_MASK (0x8U) +#define MU_TSR_TE3_SHIFT (3U) +/*! TE3 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK) +/*! @} */ + +/*! @name RCR - Receive Control */ +/*! @{ */ + +#define MU_RCR_RIE0_MASK (0x1U) +#define MU_RCR_RIE0_SHIFT (0U) +/*! RIE0 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK) + +#define MU_RCR_RIE1_MASK (0x2U) +#define MU_RCR_RIE1_SHIFT (1U) +/*! RIE1 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK) + +#define MU_RCR_RIE2_MASK (0x4U) +#define MU_RCR_RIE2_SHIFT (2U) +/*! RIE2 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK) + +#define MU_RCR_RIE3_MASK (0x8U) +#define MU_RCR_RIE3_SHIFT (3U) +/*! RIE3 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define MU_RSR_RF0_MASK (0x1U) +#define MU_RSR_RF0_SHIFT (0U) +/*! RF0 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF0(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK) + +#define MU_RSR_RF1_MASK (0x2U) +#define MU_RSR_RF1_SHIFT (1U) +/*! RF1 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF1(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK) + +#define MU_RSR_RF2_MASK (0x4U) +#define MU_RSR_RF2_SHIFT (2U) +/*! RF2 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF2(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK) + +#define MU_RSR_RF3_MASK (0x8U) +#define MU_RSR_RF3_SHIFT (3U) +/*! RF3 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF3(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK) +/*! @} */ + +/*! @name TR - Transmit */ +/*! @{ */ + +#define MU_TR_TR_DATA_MASK (0xFFFFFFFFU) +#define MU_TR_TR_DATA_SHIFT (0U) +/*! TR_DATA - MUB Transmit Data */ +#define MU_TR_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK) +/*! @} */ + +/* The count of MU_TR */ +#define MU_TR_COUNT (4U) + +/*! @name RR - Receive */ +/*! @{ */ + +#define MU_RR_RR_DATA_MASK (0xFFFFFFFFU) +#define MU_RR_RR_DATA_SHIFT (0U) +/*! RR_DATA - MUB Receive Data */ +#define MU_RR_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK) +/*! @} */ + +/* The count of MU_RR */ +#define MU_RR_COUNT (4U) + + +/*! + * @} + */ /* end of group MU_Register_Masks */ + + +/* MU - Peripheral instance base addresses */ +/** Peripheral MU1__MUA base address */ +#define MU1__MUA_BASE (0x44220000u) +/** Peripheral MU1__MUA base pointer */ +#define MU1__MUA ((MU_Type *)MU1__MUA_BASE) +/** Peripheral MU1__MUB base address */ +#define MU1__MUB_BASE (0x44230000u) +/** Peripheral MU1__MUB base pointer */ +#define MU1__MUB ((MU_Type *)MU1__MUB_BASE) +/** Peripheral MU2__MUA base address */ +#define MU2__MUA_BASE (0x42430000u) +/** Peripheral MU2__MUA base pointer */ +#define MU2__MUA ((MU_Type *)MU2__MUA_BASE) +/** Peripheral MU2__MUB base address */ +#define MU2__MUB_BASE (0x42440000u) +/** Peripheral MU2__MUB base pointer */ +#define MU2__MUB ((MU_Type *)MU2__MUB_BASE) +/** Array initializer of MU peripheral base addresses */ +#define MU_BASE_ADDRS { MU1__MUA_BASE, MU1__MUB_BASE, MU2__MUA_BASE, MU2__MUB_BASE } +/** Array initializer of MU peripheral base pointers */ +#define MU_BASE_PTRS { MU1__MUA, MU1__MUB, MU2__MUA, MU2__MUB } + +/*! + * @} + */ /* end of group MU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCRAM_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCRAM_CTRL_Peripheral_Access_Layer OCRAM_CTRL Peripheral Access Layer + * @{ + */ + +/** OCRAM_CTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ + __IO uint32_t RAMIAS; /**< RAM Initialization Address Start, offset: 0x4 */ + __IO uint32_t RAMIAE; /**< RAM Initialization Address End, offset: 0x8 */ + __IO uint32_t RAMSR; /**< RAM Status, offset: 0xC */ + __I uint32_t RAMMEMA; /**< RAM ECC Address, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __I uint32_t RAMSYSA; /**< RAM System Address, offset: 0x18 */ + __IO uint32_t RAMECCNT; /**< RAM Correctable Error Count, offset: 0x1C */ + __IO uint32_t RAMEID0; /**< RAM Error Injection Data 0, offset: 0x20 */ + __IO uint32_t RAMEID1; /**< RAM Error Injection Data 1, offset: 0x24 */ + __IO uint32_t RAMEIDC; /**< RAM Error Injection Data Control, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RAMEIA; /**< RAM Error Injection Base Address, offset: 0x30 */ + __IO uint32_t RAMEIAM; /**< RAM Error Injection Address Mask, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t RAMMAXA; /**< RAM Maximum-Value Address, offset: 0x40 */ + uint8_t RESERVED_3[60]; + __IO uint32_t RAMCR2; /**< RAM Control 2, offset: 0x80 */ +} OCRAM_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- OCRAM_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCRAM_CTRL_Register_Masks OCRAM_CTRL Register Masks + * @{ + */ + +/*! @name RAMCR - RAM Control */ +/*! @{ */ + +#define OCRAM_CTRL_RAMCR_INIT_MASK (0x1U) +#define OCRAM_CTRL_RAMCR_INIT_SHIFT (0U) +/*! INIT - Initialization Request + * 0b0..Not requested + * 0b1..Requested + */ +#define OCRAM_CTRL_RAMCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR_INIT_SHIFT)) & OCRAM_CTRL_RAMCR_INIT_MASK) + +#define OCRAM_CTRL_RAMCR_IWS_MASK (0x6U) +#define OCRAM_CTRL_RAMCR_IWS_SHIFT (1U) +/*! IWS - Initialization Wait States + * 0b00..Zero + * 0b01..One + * 0b10..Two + * 0b11..Three + */ +#define OCRAM_CTRL_RAMCR_IWS(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR_IWS_SHIFT)) & OCRAM_CTRL_RAMCR_IWS_MASK) + +#define OCRAM_CTRL_RAMCR_INIT_SYSA_MASK (0x100U) +#define OCRAM_CTRL_RAMCR_INIT_SYSA_SHIFT (8U) +/*! INIT_SYSA - Initialize With System Address + * 0b0..Local + * 0b1..System + */ +#define OCRAM_CTRL_RAMCR_INIT_SYSA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR_INIT_SYSA_SHIFT)) & OCRAM_CTRL_RAMCR_INIT_SYSA_MASK) +/*! @} */ + +/*! @name RAMIAS - RAM Initialization Address Start */ +/*! @{ */ + +#define OCRAM_CTRL_RAMIAS_IAS_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMIAS_IAS_SHIFT (0U) +/*! IAS - Initialization Address Start */ +#define OCRAM_CTRL_RAMIAS_IAS(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMIAS_IAS_SHIFT)) & OCRAM_CTRL_RAMIAS_IAS_MASK) +/*! @} */ + +/*! @name RAMIAE - RAM Initialization Address End */ +/*! @{ */ + +#define OCRAM_CTRL_RAMIAE_IAE_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMIAE_IAE_SHIFT (0U) +/*! IAE - Initialization Address End */ +#define OCRAM_CTRL_RAMIAE_IAE(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMIAE_IAE_SHIFT)) & OCRAM_CTRL_RAMIAE_IAE_MASK) +/*! @} */ + +/*! @name RAMSR - RAM Status */ +/*! @{ */ + +#define OCRAM_CTRL_RAMSR_IDONE_MASK (0x1U) +#define OCRAM_CTRL_RAMSR_IDONE_SHIFT (0U) +/*! IDONE - Initialization Done + * 0b0..An initialization was not requested, is in progress, or did not complete + * 0b1..An initialization completed successfully + */ +#define OCRAM_CTRL_RAMSR_IDONE(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_IDONE_SHIFT)) & OCRAM_CTRL_RAMSR_IDONE_MASK) + +#define OCRAM_CTRL_RAMSR_BUSERR_MASK (0x2U) +#define OCRAM_CTRL_RAMSR_BUSERR_SHIFT (1U) +/*! BUSERR - Bus Error + * 0b0..No error occurred since the last time this field was cleared + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_BUSERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_BUSERR_SHIFT)) & OCRAM_CTRL_RAMSR_BUSERR_MASK) + +#define OCRAM_CTRL_RAMSR_IPEND_MASK (0x4U) +#define OCRAM_CTRL_RAMSR_IPEND_SHIFT (2U) +/*! IPEND - Initialization Pending + * 0b0..Not in progress + * 0b1..In progress + */ +#define OCRAM_CTRL_RAMSR_IPEND(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_IPEND_SHIFT)) & OCRAM_CTRL_RAMSR_IPEND_MASK) + +#define OCRAM_CTRL_RAMSR_AVALID_MASK (0x8U) +#define OCRAM_CTRL_RAMSR_AVALID_SHIFT (3U) +/*! AVALID - Addresses Valid + * 0b0..Addresses do not correspond to an event + * 0b1..Addresses correspond to an event + */ +#define OCRAM_CTRL_RAMSR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_AVALID_SHIFT)) & OCRAM_CTRL_RAMSR_AVALID_MASK) + +#define OCRAM_CTRL_RAMSR_AERR_MASK (0x20U) +#define OCRAM_CTRL_RAMSR_AERR_SHIFT (5U) +/*! AERR - ECC Address Error + * 0b0..No error occurred + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_AERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_AERR_SHIFT)) & OCRAM_CTRL_RAMSR_AERR_MASK) + +#define OCRAM_CTRL_RAMSR_MLTERR_MASK (0x40U) +#define OCRAM_CTRL_RAMSR_MLTERR_SHIFT (6U) +/*! MLTERR - ECC Multi-Bit Error + * 0b0..No error occurred + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_MLTERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_MLTERR_SHIFT)) & OCRAM_CTRL_RAMSR_MLTERR_MASK) + +#define OCRAM_CTRL_RAMSR_SGLERR_MASK (0x80U) +#define OCRAM_CTRL_RAMSR_SGLERR_SHIFT (7U) +/*! SGLERR - ECC Single-Bit Error + * 0b0..No error occurred + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_SGLERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_SGLERR_SHIFT)) & OCRAM_CTRL_RAMSR_SGLERR_MASK) + +#define OCRAM_CTRL_RAMSR_SYND_MASK (0xFF00U) +#define OCRAM_CTRL_RAMSR_SYND_SHIFT (8U) +/*! SYND - ECC Syndrome Value */ +#define OCRAM_CTRL_RAMSR_SYND(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_SYND_SHIFT)) & OCRAM_CTRL_RAMSR_SYND_MASK) + +#define OCRAM_CTRL_RAMSR_EINFO_MASK (0xFF0000U) +#define OCRAM_CTRL_RAMSR_EINFO_SHIFT (16U) +/*! EINFO - Event Information */ +#define OCRAM_CTRL_RAMSR_EINFO(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_EINFO_SHIFT)) & OCRAM_CTRL_RAMSR_EINFO_MASK) +/*! @} */ + +/*! @name RAMMEMA - RAM ECC Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMMEMA_MEMA_MASK (0x1FFFFU) +#define OCRAM_CTRL_RAMMEMA_MEMA_SHIFT (0U) +/*! MEMA - RAM Bank Address */ +#define OCRAM_CTRL_RAMMEMA_MEMA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMMEMA_MEMA_SHIFT)) & OCRAM_CTRL_RAMMEMA_MEMA_MASK) + +#define OCRAM_CTRL_RAMMEMA_BANK_MASK (0x1F00000U) +#define OCRAM_CTRL_RAMMEMA_BANK_SHIFT (20U) +/*! BANK - RAM Bank ID */ +#define OCRAM_CTRL_RAMMEMA_BANK(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMMEMA_BANK_SHIFT)) & OCRAM_CTRL_RAMMEMA_BANK_MASK) +/*! @} */ + +/*! @name RAMSYSA - RAM System Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMSYSA_SYSA_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMSYSA_SYSA_SHIFT (0U) +/*! SYSA - System Address */ +#define OCRAM_CTRL_RAMSYSA_SYSA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSYSA_SYSA_SHIFT)) & OCRAM_CTRL_RAMSYSA_SYSA_MASK) +/*! @} */ + +/*! @name RAMECCNT - RAM Correctable Error Count */ +/*! @{ */ + +#define OCRAM_CTRL_RAMECCNT_ECCNT_MASK (0xFFU) +#define OCRAM_CTRL_RAMECCNT_ECCNT_SHIFT (0U) +/*! ECCNT - ECC Correctable Error Count */ +#define OCRAM_CTRL_RAMECCNT_ECCNT(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMECCNT_ECCNT_SHIFT)) & OCRAM_CTRL_RAMECCNT_ECCNT_MASK) +/*! @} */ + +/*! @name RAMEID0 - RAM Error Injection Data 0 */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEID0_EID_W0_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEID0_EID_W0_SHIFT (0U) +/*! EID_W0 - Error Injection Data Word 0 */ +#define OCRAM_CTRL_RAMEID0_EID_W0(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEID0_EID_W0_SHIFT)) & OCRAM_CTRL_RAMEID0_EID_W0_MASK) +/*! @} */ + +/*! @name RAMEID1 - RAM Error Injection Data 1 */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEID1_EID_W1_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEID1_EID_W1_SHIFT (0U) +/*! EID_W1 - Error Injection Data Word 1 */ +#define OCRAM_CTRL_RAMEID1_EID_W1(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEID1_EID_W1_SHIFT)) & OCRAM_CTRL_RAMEID1_EID_W1_MASK) +/*! @} */ + +/*! @name RAMEIDC - RAM Error Injection Data Control */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEIDC_EID_CKB_MASK (0xFFU) +#define OCRAM_CTRL_RAMEIDC_EID_CKB_SHIFT (0U) +/*! EID_CKB - Error Injection Data Checkbits */ +#define OCRAM_CTRL_RAMEIDC_EID_CKB(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EID_CKB_SHIFT)) & OCRAM_CTRL_RAMEIDC_EID_CKB_MASK) + +#define OCRAM_CTRL_RAMEIDC_EIP_EN_MASK (0x1000000U) +#define OCRAM_CTRL_RAMEIDC_EIP_EN_SHIFT (24U) +/*! EIP_EN - Error Injection Into Pipeline Enable + * 0b0..No error injected + * 0b1..Error injected + */ +#define OCRAM_CTRL_RAMEIDC_EIP_EN(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EIP_EN_SHIFT)) & OCRAM_CTRL_RAMEIDC_EIP_EN_MASK) + +#define OCRAM_CTRL_RAMEIDC_EIA_EN_MASK (0x40000000U) +#define OCRAM_CTRL_RAMEIDC_EIA_EN_SHIFT (30U) +/*! EIA_EN - Error Injection Address Enable + * 0b0..Ignore RAMEIA and RAMEIAM + * 0b1..Enable RAMEIA and RAMEIAM + */ +#define OCRAM_CTRL_RAMEIDC_EIA_EN(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EIA_EN_SHIFT)) & OCRAM_CTRL_RAMEIDC_EIA_EN_MASK) + +#define OCRAM_CTRL_RAMEIDC_EID_EN_MASK (0x80000000U) +#define OCRAM_CTRL_RAMEIDC_EID_EN_SHIFT (31U) +/*! EID_EN - Error Injection Data Enable + * 0b0..No injection + * 0b1..Local injection + */ +#define OCRAM_CTRL_RAMEIDC_EID_EN(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EID_EN_SHIFT)) & OCRAM_CTRL_RAMEIDC_EID_EN_MASK) +/*! @} */ + +/*! @name RAMEIA - RAM Error Injection Base Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEIA_EIA_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEIA_EIA_SHIFT (0U) +/*! EIA - Error Injection Base Address */ +#define OCRAM_CTRL_RAMEIA_EIA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIA_EIA_SHIFT)) & OCRAM_CTRL_RAMEIA_EIA_MASK) +/*! @} */ + +/*! @name RAMEIAM - RAM Error Injection Address Mask */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEIAM_EIAM_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEIAM_EIAM_SHIFT (0U) +/*! EIAM - Error Injection Address Mask */ +#define OCRAM_CTRL_RAMEIAM_EIAM(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIAM_EIAM_SHIFT)) & OCRAM_CTRL_RAMEIAM_EIAM_MASK) +/*! @} */ + +/*! @name RAMMAXA - RAM Maximum-Value Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMMAXA_MAXA_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMMAXA_MAXA_SHIFT (0U) +/*! MAXA - Maximum Address */ +#define OCRAM_CTRL_RAMMAXA_MAXA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMMAXA_MAXA_SHIFT)) & OCRAM_CTRL_RAMMAXA_MAXA_MASK) +/*! @} */ + +/*! @name RAMCR2 - RAM Control 2 */ +/*! @{ */ + +#define OCRAM_CTRL_RAMCR2_DEM_MASK (0x8U) +#define OCRAM_CTRL_RAMCR2_DEM_SHIFT (3U) +/*! DEM - Disable Exclusive Monitor + * 0b0..Enabled + * 0b1..Disabled + */ +#define OCRAM_CTRL_RAMCR2_DEM(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR2_DEM_SHIFT)) & OCRAM_CTRL_RAMCR2_DEM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCRAM_CTRL_Register_Masks */ + + +/* OCRAM_CTRL - Peripheral instance base addresses */ +/** Peripheral OCRAM_CTRL1 base address */ +#define OCRAM_CTRL1_BASE (0x490A0000u) +/** Peripheral OCRAM_CTRL1 base pointer */ +#define OCRAM_CTRL1 ((OCRAM_CTRL_Type *)OCRAM_CTRL1_BASE) +/** Array initializer of OCRAM_CTRL peripheral base addresses */ +#define OCRAM_CTRL_BASE_ADDRS { OCRAM_CTRL1_BASE } +/** Array initializer of OCRAM_CTRL peripheral base pointers */ +#define OCRAM_CTRL_BASE_PTRS { OCRAM_CTRL1 } + +/*! + * @} + */ /* end of group OCRAM_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer + * @{ + */ + +/** PDM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_1; /**< MICFIL Control 1, offset: 0x0 */ + __IO uint32_t CTRL_2; /**< MICFIL Control 2, offset: 0x4 */ + __IO uint32_t STAT; /**< MICFIL Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control, offset: 0x10 */ + __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __I uint32_t DATACH[8]; /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */ + uint8_t RESERVED_2[32]; + __IO uint32_t DC_CTRL; /**< MICFIL DC Remover Control, offset: 0x64 */ + __IO uint32_t DC_OUT_CTRL; /**< MICFIL Output DC Remover Control, offset: 0x68 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RANGE_CTRL; /**< MICFIL Range Control, offset: 0x74 */ + uint8_t RESERVED_4[4]; + __IO uint32_t RANGE_STAT; /**< MICFIL Range Status, offset: 0x7C */ + __IO uint32_t FSYNC_CTRL; /**< Frame Synchronization Control, offset: 0x80 */ + __I uint32_t VERID; /**< Version ID, offset: 0x84 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x88 */ + uint8_t RESERVED_5[4]; + __IO uint32_t VAD0_CTRL_1; /**< Voice Activity Detector 0 Control, offset: 0x90 */ + __IO uint32_t VAD0_CTRL_2; /**< Voice Activity Detector 0 Control, offset: 0x94 */ + __IO uint32_t VAD0_STAT; /**< Voice Activity Detector 0 Status, offset: 0x98 */ + __IO uint32_t VAD0_SCONFIG; /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */ + __IO uint32_t VAD0_NCONFIG; /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */ + __I uint32_t VAD0_NDATA; /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */ + __IO uint32_t VAD0_ZCD; /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */ +} PDM_Type; + +/* ---------------------------------------------------------------------------- + -- PDM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Register_Masks PDM Register Masks + * @{ + */ + +/*! @name CTRL_1 - MICFIL Control 1 */ +/*! @{ */ + +#define PDM_CTRL_1_CH0EN_MASK (0x1U) +#define PDM_CTRL_1_CH0EN_SHIFT (0U) +/*! CH0EN - Channel 0 Enable */ +#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) + +#define PDM_CTRL_1_CH1EN_MASK (0x2U) +#define PDM_CTRL_1_CH1EN_SHIFT (1U) +/*! CH1EN - Channel 1 Enable */ +#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) + +#define PDM_CTRL_1_CH2EN_MASK (0x4U) +#define PDM_CTRL_1_CH2EN_SHIFT (2U) +/*! CH2EN - Channel 2 Enable */ +#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) + +#define PDM_CTRL_1_CH3EN_MASK (0x8U) +#define PDM_CTRL_1_CH3EN_SHIFT (3U) +/*! CH3EN - Channel 3 Enable */ +#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) + +#define PDM_CTRL_1_CH4EN_MASK (0x10U) +#define PDM_CTRL_1_CH4EN_SHIFT (4U) +/*! CH4EN - Channel 4 Enable */ +#define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK) + +#define PDM_CTRL_1_CH5EN_MASK (0x20U) +#define PDM_CTRL_1_CH5EN_SHIFT (5U) +/*! CH5EN - Channel 5 Enable */ +#define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK) + +#define PDM_CTRL_1_CH6EN_MASK (0x40U) +#define PDM_CTRL_1_CH6EN_SHIFT (6U) +/*! CH6EN - Channel 6 Enable */ +#define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK) + +#define PDM_CTRL_1_CH7EN_MASK (0x80U) +#define PDM_CTRL_1_CH7EN_SHIFT (7U) +/*! CH7EN - Channel 7 Enable */ +#define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK) + +#define PDM_CTRL_1_FSYNCEN_MASK (0x10000U) +#define PDM_CTRL_1_FSYNCEN_SHIFT (16U) +/*! FSYNCEN - Frame Synchronization Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_FSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK) + +#define PDM_CTRL_1_DECFILS_MASK (0x100000U) +#define PDM_CTRL_1_DECFILS_SHIFT (20U) +/*! DECFILS - Decimation Filter Enable in Stop + * 0b0..Stops decimation filter + * 0b1..Keeps decimation filter running + */ +#define PDM_CTRL_1_DECFILS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK) + +#define PDM_CTRL_1_ERREN_MASK (0x800000U) +#define PDM_CTRL_1_ERREN_SHIFT (23U) +/*! ERREN - Error Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) + +#define PDM_CTRL_1_DISEL_MASK (0x3000000U) +#define PDM_CTRL_1_DISEL_SHIFT (24U) +/*! DISEL - DMA Interrupt Selection + * 0b00..Disables DMA and interrupt requests + * 0b01..Enables DMA requests + * 0b10..Enables interrupt requests + * 0b11..Reserved + */ +#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) + +#define PDM_CTRL_1_DBGE_MASK (0x4000000U) +#define PDM_CTRL_1_DBGE_SHIFT (26U) +/*! DBGE - Module Enable in Debug + * 0b0..Disables after completing the current frame + * 0b1..Enables operation + */ +#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) + +#define PDM_CTRL_1_SRES_MASK (0x8000000U) +#define PDM_CTRL_1_SRES_SHIFT (27U) +/*! SRES - Software Reset + * 0b0..No action + * 0b1..Software reset + */ +#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) + +#define PDM_CTRL_1_DBG_MASK (0x10000000U) +#define PDM_CTRL_1_DBG_SHIFT (28U) +/*! DBG - Debug Mode + * 0b0..Normal + * 0b1..Debug + */ +#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) + +#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) +#define PDM_CTRL_1_PDMIEN_SHIFT (29U) +/*! PDMIEN - MICFIL Enable + * 0b0..Stops MICFIL operation + * 0b1..Starts MICFIL operation + */ +#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) + +#define PDM_CTRL_1_DOZEN_MASK (0x40000000U) +#define PDM_CTRL_1_DOZEN_SHIFT (30U) +/*! DOZEN - Stop Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) + +#define PDM_CTRL_1_MDIS_MASK (0x80000000U) +#define PDM_CTRL_1_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Normal mode + * 0b1..DLL mode + */ +#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) +/*! @} */ + +/*! @name CTRL_2 - MICFIL Control 2 */ +/*! @{ */ + +#define PDM_CTRL_2_CLKDIV_MASK (0xFFU) +#define PDM_CTRL_2_CLKDIV_SHIFT (0U) +/*! CLKDIV - Clock Divider + * 0b00000000..Internal clock divider value = 0 + * 0b00000001..Internal clock divider value = 1 + * 0b00000010-0b11111110..... + * 0b11111111..Internal clock divider value = 255 + */ +#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) + +#define PDM_CTRL_2_CICOSR_MASK (0xF0000U) +#define PDM_CTRL_2_CICOSR_SHIFT (16U) +/*! CICOSR - CIC Decimation Rate + * 0b0000..CIC oversampling rate = 0 + * 0b0001..CIC oversampling rate = 1 + * 0b0010-0b1110..... + * 0b1111..CIC oversampling rate = 15 + */ +#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) + +#define PDM_CTRL_2_QSEL_MASK (0xE000000U) +#define PDM_CTRL_2_QSEL_SHIFT (25U) +/*! QSEL - Quality Mode + * 0b000..Medium-Quality mode + * 0b001..High-Quality mode + * 0b100..Very-Low-Quality 2 mode + * 0b101..Very-Low-Quality 1 mode + * 0b110..Very-Low-Quality 0 mode + * 0b111..Low-Quality mode + */ +#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) +/*! @} */ + +/*! @name STAT - MICFIL Status */ +/*! @{ */ + +#define PDM_STAT_CH0F_MASK (0x1U) +#define PDM_STAT_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) + +#define PDM_STAT_CH1F_MASK (0x2U) +#define PDM_STAT_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) + +#define PDM_STAT_CH2F_MASK (0x4U) +#define PDM_STAT_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) + +#define PDM_STAT_CH3F_MASK (0x8U) +#define PDM_STAT_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) + +#define PDM_STAT_CH4F_MASK (0x10U) +#define PDM_STAT_CH4F_SHIFT (4U) +/*! CH4F - Channel 4 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK) + +#define PDM_STAT_CH5F_MASK (0x20U) +#define PDM_STAT_CH5F_SHIFT (5U) +/*! CH5F - Channel 5 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK) + +#define PDM_STAT_CH6F_MASK (0x40U) +#define PDM_STAT_CH6F_SHIFT (6U) +/*! CH6F - Channel 6 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK) + +#define PDM_STAT_CH7F_MASK (0x80U) +#define PDM_STAT_CH7F_SHIFT (7U) +/*! CH7F - Channel 7 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK) + +#define PDM_STAT_LOWFREQF_MASK (0x20000000U) +#define PDM_STAT_LOWFREQF_SHIFT (29U) +/*! LOWFREQF - Low Frequency Flag + * 0b0..CLKDIV value is OK + * 0b1..CLKDIV value is too low + */ +#define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK) + +#define PDM_STAT_FIR_RDY_MASK (0x40000000U) +#define PDM_STAT_FIR_RDY_SHIFT (30U) +/*! FIR_RDY - Filter Data Ready + * 0b0..Not reliable + * 0b1..Reliable + */ +#define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK) + +#define PDM_STAT_BSY_FIL_MASK (0x80000000U) +#define PDM_STAT_BSY_FIL_SHIFT (31U) +/*! BSY_FIL - Busy Flag + * 0b0..MICFIL is stopped + * 0b1..MICFIL is running + */ +#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) +/*! @} */ + +/*! @name FIFO_CTRL - MICFIL FIFO Control */ +/*! @{ */ + +#define PDM_FIFO_CTRL_FIFOWMK_MASK (0x1FU) +#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) +/*! FIFOWMK - FIFO Watermark Control */ +#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) +/*! @} */ + +/*! @name FIFO_STAT - MICFIL FIFO Status */ +/*! @{ */ + +#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) +#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) +/*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) + +#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) +#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) +/*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) + +#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) +#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) +/*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) + +#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) +#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) +/*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) + +#define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U) +#define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U) +/*! FIFOOVF4 - FIFO Overflow Exception Flag for Channel 4 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK) + +#define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) +#define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U) +/*! FIFOOVF5 - FIFO Overflow Exception Flag for Channel 5 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK) + +#define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) +#define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U) +/*! FIFOOVF6 - FIFO Overflow Exception Flag for Channel 6 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK) + +#define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U) +#define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U) +/*! FIFOOVF7 - FIFO Overflow Exception Flag for Channel 7 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK) + +#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) +#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) +/*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) + +#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) +#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) +/*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) + +#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) +#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) +/*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) + +#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) +#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) +/*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) + +#define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U) +#define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U) +/*! FIFOUND4 - FIFO Underflow Exception Flag for Channel 4 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK) + +#define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U) +#define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U) +/*! FIFOUND5 - FIFO Underflow Exception Flag for Channel 5 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK) + +#define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U) +#define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U) +/*! FIFOUND6 - FIFO Underflow Exception Flag for Channel 6 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK) + +#define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U) +#define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U) +/*! FIFOUND7 - FIFO Underflow Exception Flag for Channel 7 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK) +/*! @} */ + +/*! @name DATACH - MICFIL Output Result */ +/*! @{ */ + +#define PDM_DATACH_DATA_MASK (0xFFFFFFFFU) +#define PDM_DATACH_DATA_SHIFT (0U) +/*! DATA - Channel n Data */ +#define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK) +/*! @} */ + +/* The count of PDM_DATACH */ +#define PDM_DATACH_COUNT (8U) + +/*! @name DC_CTRL - MICFIL DC Remover Control */ +/*! @{ */ + +#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) + +#define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U) +#define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U) +/*! DCCONFIG4 - Channel 4 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK) + +#define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U) +#define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U) +/*! DCCONFIG5 - Channel 5 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK) + +#define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U) +#define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U) +/*! DCCONFIG6 - Channel 6 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK) + +#define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U) +#define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U) +/*! DCCONFIG7 - Channel 7 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK) +/*! @} */ + +/*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */ +/*! @{ */ + +#define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG4_MASK (0x300U) +#define PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT (8U) +/*! DCCONFIG4 - Channel 4 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG4_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG5_MASK (0xC00U) +#define PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT (10U) +/*! DCCONFIG5 - Channel 5 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG5_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG6_MASK (0x3000U) +#define PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT (12U) +/*! DCCONFIG6 - Channel 6 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG6_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG7_MASK (0xC000U) +#define PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT (14U) +/*! DCCONFIG7 - Channel 7 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG7_MASK) +/*! @} */ + +/*! @name RANGE_CTRL - MICFIL Range Control */ +/*! @{ */ + +#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) +#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) +/*! RANGEADJ0 - Channel 0 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) +#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) +/*! RANGEADJ1 - Channel 1 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) +#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) +/*! RANGEADJ2 - Channel 2 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) +#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) +/*! RANGEADJ3 - Channel 3 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U) +#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U) +/*! RANGEADJ4 - Channel 4 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U) +#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U) +/*! RANGEADJ5 - Channel 5 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U) +#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U) +/*! RANGEADJ6 - Channel 6 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U) +#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U) +/*! RANGEADJ7 - Channel 7 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK) +/*! @} */ + +/*! @name RANGE_STAT - MICFIL Range Status */ +/*! @{ */ + +#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) +#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) +/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) + +#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) +#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) +/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) + +#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) +#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) +/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) + +#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) +#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) +/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) + +#define PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U) +#define PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U) +/*! RANGEOVF4 - Channel 4 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK) + +#define PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U) +#define PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U) +/*! RANGEOVF5 - Channel 5 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK) + +#define PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U) +#define PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U) +/*! RANGEOVF6 - Channel 6 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK) + +#define PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U) +#define PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U) +/*! RANGEOVF7 - Channel 7 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK) + +#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) +#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) +/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) + +#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) +#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) +/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) + +#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) +#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) +/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) + +#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) +#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) +/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) + +#define PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U) +#define PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U) +/*! RANGEUNF4 - Channel 4 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK) + +#define PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U) +#define PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U) +/*! RANGEUNF5 - Channel 5 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK) + +#define PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U) +#define PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U) +/*! RANGEUNF6 - Channel 6 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK) + +#define PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U) +#define PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U) +/*! RANGEUNF7 - Channel 7 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK) +/*! @} */ + +/*! @name FSYNC_CTRL - Frame Synchronization Control */ +/*! @{ */ + +#define PDM_FSYNC_CTRL_FSYNCLEN_MASK (0xFFFFFFFFU) +#define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT (0U) +/*! FSYNCLEN - Frame Synchronization Window Length */ +#define PDM_FSYNC_CTRL_FSYNCLEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK) +/*! @} */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PDM_VERID_FEATURE_MASK (0xFFFFU) +#define PDM_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define PDM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK) + +#define PDM_VERID_MINOR_MASK (0xFF0000U) +#define PDM_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PDM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK) + +#define PDM_VERID_MAJOR_MASK (0xFF000000U) +#define PDM_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PDM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define PDM_PARAM_NPAIR_MASK (0xFU) +#define PDM_PARAM_NPAIR_SHIFT (0U) +/*! NPAIR - Number of Microphone Pairs + * 0b0000..None + * 0b0001..1 pair + * 0b0010..2 pairs + * 0b0011-0b1110..... + * 0b1111..15 pairs + */ +#define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) + +#define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) +#define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) +/*! FIFO_PTRWID - FIFO Pointer Width + * 0b0000..0 bits + * 0b0001..1 bit + * 0b0010..2 bits + * 0b0011-0b1110..... + * 0b1111..15 bits + */ +#define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) + +#define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) +#define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT (8U) +/*! FIL_OUT_WIDTH_24B - Filter Output Width + * 0b0..16 bits + * 0b1..24 bits + */ +#define PDM_PARAM_FIL_OUT_WIDTH_24B(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK) + +#define PDM_PARAM_LOW_POWER_MASK (0x200U) +#define PDM_PARAM_LOW_POWER_SHIFT (9U) +/*! LOW_POWER - Low-Power Decimation Filter + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_PARAM_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK) + +#define PDM_PARAM_DC_BYPASS_MASK (0x400U) +#define PDM_PARAM_DC_BYPASS_SHIFT (10U) +/*! DC_BYPASS - Input DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK) + +#define PDM_PARAM_DC_OUT_BYPASS_MASK (0x800U) +#define PDM_PARAM_DC_OUT_BYPASS_SHIFT (11U) +/*! DC_OUT_BYPASS - Output DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_OUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK) + +#define PDM_PARAM_HWVAD_MASK (0x10000U) +#define PDM_PARAM_HWVAD_SHIFT (16U) +/*! HWVAD - HWVAD Active + * 0b0..Disabled + * 0b1..Active + */ +#define PDM_PARAM_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_SHIFT)) & PDM_PARAM_HWVAD_MASK) + +#define PDM_PARAM_HWVAD_ENERGY_MODE_MASK (0x20000U) +#define PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT (17U) +/*! HWVAD_ENERGY_MODE - HWVAD Energy Mode Active + * 0b0..Disabled + * 0b1..Active + */ +#define PDM_PARAM_HWVAD_ENERGY_MODE(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT)) & PDM_PARAM_HWVAD_ENERGY_MODE_MASK) + +#define PDM_PARAM_HWVAD_ZCD_MASK (0x80000U) +#define PDM_PARAM_HWVAD_ZCD_SHIFT (19U) +/*! HWVAD_ZCD - HWVAD ZCD Active + * 0b0..Disabled + * 0b1..Active + */ +#define PDM_PARAM_HWVAD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ZCD_SHIFT)) & PDM_PARAM_HWVAD_ZCD_MASK) + +#define PDM_PARAM_NUM_HWVAD_MASK (0xF000000U) +#define PDM_PARAM_NUM_HWVAD_SHIFT (24U) +/*! NUM_HWVAD - Number of HWVADs */ +#define PDM_PARAM_NUM_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NUM_HWVAD_SHIFT)) & PDM_PARAM_NUM_HWVAD_MASK) +/*! @} */ + +/*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control */ +/*! @{ */ + +#define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U) +#define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U) +/*! VADEN - HWVAD Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK) + +#define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U) +#define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U) +/*! VADRST - HWVAD Reset */ +#define PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK) + +#define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U) +#define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U) +/*! VADIE - Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK) + +#define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U) +#define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U) +/*! VADERIE - Error Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK) + +#define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U) +#define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U) +/*! VADST10 - Internal Filters Initialization + * 0b0..Normal operation + * 0b1..Filters initialized + */ +#define PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK) + +#define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U) +#define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U) +/*! VADINITT - Initialization Time + * 0b00000..0 + * 0b00001..1 + * 0b00010-0b11110..... + * 0b11111..31 + */ +#define PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK) + +#define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U) +#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U) +/*! VADCICOSR - CIC Oversampling Rate */ +#define PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK) + +#define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U) +#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U) +/*! VADCHSEL - Channel Selector + * 0b000..PDM Microphone 0 Left + * 0b001..PDM Microphone 0 Right + * 0b010..PDM Microphone 1 Left + * 0b011-0b101..... + * 0b110..PDM Microphone 3 Left + * 0b111..PDM Microphone 3 Right + */ +#define PDM_VAD0_CTRL_1_VADCHSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK) +/*! @} */ + +/*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control */ +/*! @{ */ + +#define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U) +#define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U) +/*! VADHPF - High-Pass Filter + * 0b00..Filter bypassed + * 0b01..Cut-off frequency at 1750 Hz + * 0b10..Cut-off frequency at 215 Hz + * 0b11..Cut-off frequency at 102 Hz + */ +#define PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK) + +#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U) +#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U) +/*! VADINPGAIN - Input Gain + * 0b0000..No shift + * 0b0001..Shift 1 bit to the left + * 0b0010..Shift 2 bits to the left + * 0b0011-0b0110..... + * 0b0111..Shift 7 bits to the left + * 0b1000..Shift 8 bits to the right + * 0b1001..Shift 7 bits to the right + * 0b1010-0b1110..... + * 0b1111..Shift 1 bits to the right + */ +#define PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK) + +#define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U) +#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U) +/*! VADFRAMET - Frame Time + * 0b000000..1 + * 0b000001..2 + * 0b000010-0b111110..... + * 0b111111..63 + */ +#define PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK) + +#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U) +#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U) +/*! VADFOUTDIS - Force Output Disable + * 0b0..Enables + * 0b1..Disables + */ +#define PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK) + +#define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U) +#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U) +/*! VADPREFEN - Pre Filter Enable + * 0b0..Pre-filter bypassed + * 0b1..Pre-filter enabled + */ +#define PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK) + +#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U) +#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U) +/*! VADFRENDIS - Frame Energy Disable + * 0b0..Enables + * 0b1..Disables + */ +#define PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK) +/*! @} */ + +/*! @name VAD0_STAT - Voice Activity Detector 0 Status */ +/*! @{ */ + +#define PDM_VAD0_STAT_VADIF_MASK (0x1U) +#define PDM_VAD0_STAT_VADIF_SHIFT (0U) +/*! VADIF - Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK) + +#define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U) +#define PDM_VAD0_STAT_VADINSATF_SHIFT (16U) +/*! VADINSATF - Input Saturation Flag + * 0b0..No exception + * 0b1..Exception + */ +#define PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK) + +#define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U) +#define PDM_VAD0_STAT_VADINITF_SHIFT (31U) +/*! VADINITF - Initialization Flag + * 0b0..Not being initialized + * 0b1..Being initialized + */ +#define PDM_VAD0_STAT_VADINITF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK) +/*! @} */ + +/*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */ +/*! @{ */ + +#define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU) +#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U) +/*! VADSGAIN - Signal Gain + * 0b0000, 0b0001..Multiplier = 1 + * 0b0010..Multiplier = 2 + * 0b0011-0b1110..... + * 0b1111..Multiplier = 15 + */ +#define PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK) + +#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U) +#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U) +/*! VADSMAXEN - Signal Maximum Enable + * 0b0..Maximum block bypassed + * 0b1..Maximum block enabled + */ +#define PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK) + +#define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) +#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U) +/*! VADSFILEN - Signal Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_SCONFIG_VADSFILEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK) +/*! @} */ + +/*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */ +/*! @{ */ + +#define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU) +#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U) +/*! VADNGAIN - Noise Gain + * 0b0000, 0b0001..Multiplier = 1 + * 0b0010..Multiplier = 2 + * 0b0011-0b1110..... + * 0b1111..Multiplier = 15 + */ +#define PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK) + +#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U) +#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U) +/*! VADNFILADJ - Noise Filter Adjustment + * 0b00000..0 + * 0b00001..1 + * 0b00010-0b11110..... + * 0b11111..31 + */ +#define PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK) + +#define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U) +#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U) +/*! VADNOREN - Noise OR Enable + * 0b0..Not decimated + * 0b1..Decimated + */ +#define PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK) + +#define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U) +#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U) +/*! VADNDECEN - Noise Decimation Enable + * 0b0..Not decimated + * 0b1..Decimated + */ +#define PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK) + +#define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U) +#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U) +/*! VADNMINEN - Noise Minimum Enable + * 0b0..Minimum block bypassed + * 0b1..Minimum block enabled + */ +#define PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK) + +#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U) +#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U) +/*! VADNFILAUTO - Noise Filter Auto + * 0b0..Always enabled + * 0b1..Enabled or disabled based on voice activity information + */ +#define PDM_VAD0_NCONFIG_VADNFILAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK) +/*! @} */ + +/*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */ +/*! @{ */ + +#define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU) +#define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U) +/*! VADNDATA - Noise Data */ +#define PDM_VAD0_NDATA_VADNDATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK) +/*! @} */ + +/*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */ +/*! @{ */ + +#define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U) +#define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U) +/*! VADZCDEN - ZCD Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK) + +#define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U) +#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U) +/*! VADZCDAUTO - ZCD Automatic Threshold + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK) + +#define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) +#define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U) +/*! VADZCDAND - ZCD AND Behavior + * 0b0..OR + * 0b1..AND + */ +#define PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK) + +#define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U) +#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U) +/*! VADZCDADJ - ZCD Adjustment + * 0b0000..0 + * 0b0001..1 + * 0b0010-0b1110..... + * 0b1111..15 + */ +#define PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK) + +#define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U) +#define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U) +/*! VADZCDTH - ZCD Threshold */ +#define PDM_VAD0_ZCD_VADZCDTH(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PDM_Register_Masks */ + + +/* PDM - Peripheral instance base addresses */ +/** Peripheral PDM base address */ +#define PDM_BASE (0x44520000u) +/** Peripheral PDM base pointer */ +#define PDM ((PDM_Type *)PDM_BASE) +/** Array initializer of PDM peripheral base addresses */ +#define PDM_BASE_ADDRS { PDM_BASE } +/** Array initializer of PDM peripheral base pointers */ +#define PDM_BASE_PTRS { PDM } + +/*! + * @} + */ /* end of group PDM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLL_Peripheral_Access_Layer PLL Peripheral Access Layer + * @{ + */ + +/** PLL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< PLL Control, offset: 0x0 */ + __IO uint32_t SET; /**< PLL Control, offset: 0x4 */ + __IO uint32_t CLR; /**< PLL Control, offset: 0x8 */ + __IO uint32_t TOG; /**< PLL Control, offset: 0xC */ + } CTRL; + uint8_t RESERVED_0[32]; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Spread Spectrum, offset: 0x30, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t SET; /**< Spread Spectrum, offset: 0x34, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t CLR; /**< Spread Spectrum, offset: 0x38, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t TOG; /**< Spread Spectrum, offset: 0x3C, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + } SPREAD_SPECTRUM; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Numerator, offset: 0x40, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t SET; /**< Numerator, offset: 0x44, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t CLR; /**< Numerator, offset: 0x48, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t TOG; /**< Numerator, offset: 0x4C, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + } NUMERATOR; + struct { /* offset: 0x50 */ + __IO uint32_t RW; /**< Denominator, offset: 0x50, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t SET; /**< Denominator, offset: 0x54, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t CLR; /**< Denominator, offset: 0x58, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t TOG; /**< Denominator, offset: 0x5C, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + } DENOMINATOR; + struct { /* offset: 0x60 */ + __IO uint32_t RW; /**< PLL Dividers, offset: 0x60 */ + __IO uint32_t SET; /**< PLL Dividers, offset: 0x64 */ + __IO uint32_t CLR; /**< PLL Dividers, offset: 0x68 */ + __IO uint32_t TOG; /**< PLL Dividers, offset: 0x6C */ + } DIV; + struct { /* offset: 0x70, array step: 0x20 */ + struct { /* offset: 0x70 */ + __IO uint32_t RW; /**< DFS Control, offset: 0x70, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t SET; /**< DFS Control, offset: 0x74, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t CLR; /**< DFS Control, offset: 0x78, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t TOG; /**< DFS Control, offset: 0x7C, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + } DFS_CTRL; + struct { /* offset: 0x80 */ + __IO uint32_t RW; /**< DFS Division_N, offset: 0x80, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t SET; /**< DFS Division_N, offset: 0x84, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t CLR; /**< DFS Division_N, offset: 0x88, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t TOG; /**< DFS Division_N, offset: 0x8C, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + } DFS_DIV; + } DFS[3]; + uint8_t RESERVED_1[32]; + __I uint32_t PLL_STATUS; /**< PLL Status, offset: 0xF0 */ + __I uint32_t DFS_STATUS; /**< DFS Status, offset: 0xF4, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ +} PLL_Type; + +/* ---------------------------------------------------------------------------- + -- PLL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLL_Register_Masks PLL Register Masks + * @{ + */ + +/*! @name CTRL - PLL Control */ +/*! @{ */ + +#define PLL_CTRL_POWERUP_MASK (0x1U) +#define PLL_CTRL_POWERUP_SHIFT (0U) +/*! POWERUP - Power Up + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_POWERUP_SHIFT)) & PLL_CTRL_POWERUP_MASK) + +#define PLL_CTRL_CLKMUX_EN_MASK (0x2U) +#define PLL_CTRL_CLKMUX_EN_SHIFT (1U) +/*! CLKMUX_EN - CLKMUX Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_CLKMUX_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_CLKMUX_EN_SHIFT)) & PLL_CTRL_CLKMUX_EN_MASK) + +#define PLL_CTRL_CLKMUX_BYPASS_MASK (0x4U) +#define PLL_CTRL_CLKMUX_BYPASS_SHIFT (2U) +/*! CLKMUX_BYPASS - CLKMUX_Bypass + * 0b0..Normal mode + * 0b1..PLL Bypass mode + */ +#define PLL_CTRL_CLKMUX_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_CLKMUX_BYPASS_SHIFT)) & PLL_CTRL_CLKMUX_BYPASS_MASK) + +#define PLL_CTRL_SPREADCTL_MASK (0x100U) +#define PLL_CTRL_SPREADCTL_SHIFT (8U) +/*! SPREADCTL - Modulation Type Select + * 0b0..Centered around nominal frequency + * 0b1..Spread below nominal frequency + */ +#define PLL_CTRL_SPREADCTL(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_SPREADCTL_SHIFT)) & PLL_CTRL_SPREADCTL_MASK) + +#define PLL_CTRL_HW_CTRL_SEL_MASK (0x10000U) +#define PLL_CTRL_HW_CTRL_SEL_SHIFT (16U) +/*! HW_CTRL_SEL - Hardware Control Select + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_HW_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_HW_CTRL_SEL_SHIFT)) & PLL_CTRL_HW_CTRL_SEL_MASK) + +#define PLL_CTRL_LOCK_BYPASS_MASK (0x80000000U) +#define PLL_CTRL_LOCK_BYPASS_SHIFT (31U) +/*! LOCK_BYPASS - Lock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_LOCK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_LOCK_BYPASS_SHIFT)) & PLL_CTRL_LOCK_BYPASS_MASK) +/*! @} */ + +/*! @name SPREAD_SPECTRUM - Spread Spectrum */ +/*! @{ */ + +#define PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) +#define PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) +/*! STEP - Step */ +#define PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & PLL_SPREAD_SPECTRUM_STEP_MASK) + +#define PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) +#define PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) +/*! ENABLE - Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & PLL_SPREAD_SPECTRUM_ENABLE_MASK) + +#define PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) +#define PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) +/*! STOP - Stop */ +#define PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & PLL_SPREAD_SPECTRUM_STOP_MASK) +/*! @} */ + +/*! @name NUMERATOR - Numerator */ +/*! @{ */ + +#define PLL_NUMERATOR_MFN_MASK (0xFFFFFFFCU) +#define PLL_NUMERATOR_MFN_SHIFT (2U) +/*! MFN - Numerator */ +#define PLL_NUMERATOR_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_NUMERATOR_MFN_SHIFT)) & PLL_NUMERATOR_MFN_MASK) +/*! @} */ + +/*! @name DENOMINATOR - Denominator */ +/*! @{ */ + +#define PLL_DENOMINATOR_MFD_MASK (0x3FFFFFFFU) +#define PLL_DENOMINATOR_MFD_SHIFT (0U) +/*! MFD - Denominator */ +#define PLL_DENOMINATOR_MFD(x) (((uint32_t)(((uint32_t)(x)) << PLL_DENOMINATOR_MFD_SHIFT)) & PLL_DENOMINATOR_MFD_MASK) +/*! @} */ + +/*! @name DIV - PLL Dividers */ +/*! @{ */ + +#define PLL_DIV_ODIV_MASK (0xFFU) +#define PLL_DIV_ODIV_SHIFT (0U) +/*! ODIV - Output Frequency Divider for Clock Output + * 0b00000000..Divide by 2 + * 0b00000001..Divide by 3 + * 0b00000010..Divide by 2 + * 0b00000011..Divide by 3 + * 0b00000100..Divide by 4 + * 0b00000101..Divide by 5 + * 0b00000110..Divide by 6 + * 0b00001010..Divide by 10 + * 0b10000010..Divide by 130 + * 0b11111111..Divide by 255 + */ +#define PLL_DIV_ODIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_ODIV_SHIFT)) & PLL_DIV_ODIV_MASK) + +#define PLL_DIV_RDIV_MASK (0xE000U) +#define PLL_DIV_RDIV_SHIFT (13U) +/*! RDIV - Input Clock Predivider + * 0b000..Divide by 1 + * 0b001..Divide by 1 + * 0b010..Divide by 2 + * 0b011..Divide by 3 + * 0b100..Divide by 4 + * 0b101..Divide by 5 + * 0b110..Divide by 6 + * 0b111..Divide by 7 + */ +#define PLL_DIV_RDIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_RDIV_SHIFT)) & PLL_DIV_RDIV_MASK) + +#define PLL_DIV_MFI_MASK (0x1FF0000U) +#define PLL_DIV_MFI_SHIFT (16U) +/*! MFI - Integer Portion of Loop Divider */ +#define PLL_DIV_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_MFI_SHIFT)) & PLL_DIV_MFI_MASK) +/*! @} */ + +/*! @name DFS - DFS Control */ +/*! @{ */ + +#define PLL_DFS_HW_CTRL_SEL_MASK (0x10000U) +#define PLL_DFS_HW_CTRL_SEL_SHIFT (16U) +/*! HW_CTRL_SEL - Hardware Control Select + * 0b0..Controlled by register + * 0b1..Controlled by hardware inputs + */ +#define PLL_DFS_HW_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_HW_CTRL_SEL_SHIFT)) & PLL_DFS_HW_CTRL_SEL_MASK) + +#define PLL_DFS_BYPASS_EN_MASK (0x800000U) +#define PLL_DFS_BYPASS_EN_SHIFT (23U) +/*! BYPASS_EN - Bypass Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_BYPASS_EN_SHIFT)) & PLL_DFS_BYPASS_EN_MASK) + +#define PLL_DFS_CLKOUT_DIVBY2_EN_MASK (0x20000000U) +#define PLL_DFS_CLKOUT_DIVBY2_EN_SHIFT (29U) +/*! CLKOUT_DIVBY2_EN - DFS Clock Output Divide by 2 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_CLKOUT_DIVBY2_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_CLKOUT_DIVBY2_EN_SHIFT)) & PLL_DFS_CLKOUT_DIVBY2_EN_MASK) + +#define PLL_DFS_CLKOUT_EN_MASK (0x40000000U) +#define PLL_DFS_CLKOUT_EN_SHIFT (30U) +/*! CLKOUT_EN - DFS Clock Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_CLKOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_CLKOUT_EN_SHIFT)) & PLL_DFS_CLKOUT_EN_MASK) + +#define PLL_DFS_ENABLE_MASK (0x80000000U) +#define PLL_DFS_ENABLE_SHIFT (31U) +/*! ENABLE - DFS Block Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_ENABLE_SHIFT)) & PLL_DFS_ENABLE_MASK) +/*! @} */ + +/*! @name DFS - DFS Division_N */ +/*! @{ */ + +#define PLL_DFS_MFN_MASK (0x7U) +#define PLL_DFS_MFN_SHIFT (0U) +/*! MFN - MFN */ +#define PLL_DFS_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_MFN_SHIFT)) & PLL_DFS_MFN_MASK) + +#define PLL_DFS_MFI_MASK (0xFF00U) +#define PLL_DFS_MFI_SHIFT (8U) +/*! MFI - MFI */ +#define PLL_DFS_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_MFI_SHIFT)) & PLL_DFS_MFI_MASK) +/*! @} */ + +/*! @name PLL_STATUS - PLL Status */ +/*! @{ */ + +#define PLL_PLL_STATUS_PLL_LOCK_MASK (0x1U) +#define PLL_PLL_STATUS_PLL_LOCK_SHIFT (0U) +/*! PLL_LOCK - PLL_LOCK */ +#define PLL_PLL_STATUS_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_PLL_LOCK_SHIFT)) & PLL_PLL_STATUS_PLL_LOCK_MASK) + +#define PLL_PLL_STATUS_PLL_LOL_MASK (0x2U) +#define PLL_PLL_STATUS_PLL_LOL_SHIFT (1U) +/*! PLL_LOL - PLL_LOL */ +#define PLL_PLL_STATUS_PLL_LOL(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_PLL_LOL_SHIFT)) & PLL_PLL_STATUS_PLL_LOL_MASK) + +#define PLL_PLL_STATUS_ANA_MFN_MASK (0xFFFFFFFCU) +#define PLL_PLL_STATUS_ANA_MFN_SHIFT (2U) +/*! ANA_MFN - ANA_MFN */ +#define PLL_PLL_STATUS_ANA_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_ANA_MFN_SHIFT)) & PLL_PLL_STATUS_ANA_MFN_MASK) +/*! @} */ + +/*! @name DFS_STATUS - DFS Status */ +/*! @{ */ + +#define PLL_DFS_STATUS_DFS_OK_MASK (0x7U) +#define PLL_DFS_STATUS_DFS_OK_SHIFT (0U) +/*! DFS_OK - DFS OK + * 0b000..Invalid + * 0b001..Valid + */ +#define PLL_DFS_STATUS_DFS_OK(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_STATUS_DFS_OK_SHIFT)) & PLL_DFS_STATUS_DFS_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PLL_Register_Masks */ + + +/* PLL - Peripheral instance base addresses */ +/** Peripheral ARMPLL base address */ +#define ARMPLL_BASE (0x44481000u) +/** Peripheral ARMPLL base pointer */ +#define ARMPLL ((PLL_Type *)ARMPLL_BASE) +/** Peripheral AUDIOPLL base address */ +#define AUDIOPLL_BASE (0x44481200u) +/** Peripheral AUDIOPLL base pointer */ +#define AUDIOPLL ((PLL_Type *)AUDIOPLL_BASE) +/** Peripheral DRAMPLL base address */ +#define DRAMPLL_BASE (0x44481300u) +/** Peripheral DRAMPLL base pointer */ +#define DRAMPLL ((PLL_Type *)DRAMPLL_BASE) +/** Peripheral SYSPLL base address */ +#define SYSPLL_BASE (0x44481100u) +/** Peripheral SYSPLL base pointer */ +#define SYSPLL ((PLL_Type *)SYSPLL_BASE) +/** Peripheral VIDEOPLL base address */ +#define VIDEOPLL_BASE (0x44481400u) +/** Peripheral VIDEOPLL base pointer */ +#define VIDEOPLL ((PLL_Type *)VIDEOPLL_BASE) +/** Array initializer of PLL peripheral base addresses */ +#define PLL_BASE_ADDRS { ARMPLL_BASE, AUDIOPLL_BASE, DRAMPLL_BASE, SYSPLL_BASE, VIDEOPLL_BASE } +/** Array initializer of PLL peripheral base pointers */ +#define PLL_BASE_PTRS { ARMPLL, AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL } + +/*! + * @} + */ /* end of group PLL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RGPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer + * @{ + */ + +/** RGPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LOCK; /**< Lock, offset: 0xC */ + __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ + __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ + __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ + __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ + uint8_t RESERVED_1[32]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __IO uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __IO uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __IO uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_2[4]; + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __IO uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __IO uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_3[24]; + __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} RGPIO_Type; + +/* ---------------------------------------------------------------------------- + -- RGPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RGPIO_Register_Masks RGPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define RGPIO_VERID_FEATURE_MASK (0xFFFFU) +#define RGPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define RGPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_FEATURE_SHIFT)) & RGPIO_VERID_FEATURE_MASK) + +#define RGPIO_VERID_MINOR_MASK (0xFF0000U) +#define RGPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define RGPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MINOR_SHIFT)) & RGPIO_VERID_MINOR_MASK) + +#define RGPIO_VERID_MAJOR_MASK (0xFF000000U) +#define RGPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define RGPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MAJOR_SHIFT)) & RGPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define RGPIO_PARAM_IRQNUM_MASK (0xFU) +#define RGPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define RGPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PARAM_IRQNUM_SHIFT)) & RGPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define RGPIO_LOCK_PCNS_MASK (0x1U) +#define RGPIO_LOCK_PCNS_SHIFT (0U) +/*! PCNS - Lock PCNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNS_SHIFT)) & RGPIO_LOCK_PCNS_MASK) + +#define RGPIO_LOCK_ICNS_MASK (0x2U) +#define RGPIO_LOCK_ICNS_SHIFT (1U) +/*! ICNS - Lock ICNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNS_SHIFT)) & RGPIO_LOCK_ICNS_MASK) + +#define RGPIO_LOCK_PCNP_MASK (0x4U) +#define RGPIO_LOCK_PCNP_SHIFT (2U) +/*! PCNP - Lock PCNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNP_SHIFT)) & RGPIO_LOCK_PCNP_MASK) + +#define RGPIO_LOCK_ICNP_MASK (0x8U) +#define RGPIO_LOCK_ICNP_SHIFT (3U) +/*! ICNP - Lock ICNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNP_SHIFT)) & RGPIO_LOCK_ICNP_MASK) +/*! @} */ + +/*! @name PCNS - Pin Control Nonsecure */ +/*! @{ */ + +#define RGPIO_PCNS_NSE0_MASK (0x1U) +#define RGPIO_PCNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE0_SHIFT)) & RGPIO_PCNS_NSE0_MASK) + +#define RGPIO_PCNS_NSE1_MASK (0x2U) +#define RGPIO_PCNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE1_SHIFT)) & RGPIO_PCNS_NSE1_MASK) + +#define RGPIO_PCNS_NSE2_MASK (0x4U) +#define RGPIO_PCNS_NSE2_SHIFT (2U) +/*! NSE2 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE2_SHIFT)) & RGPIO_PCNS_NSE2_MASK) + +#define RGPIO_PCNS_NSE3_MASK (0x8U) +#define RGPIO_PCNS_NSE3_SHIFT (3U) +/*! NSE3 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE3_SHIFT)) & RGPIO_PCNS_NSE3_MASK) + +#define RGPIO_PCNS_NSE4_MASK (0x10U) +#define RGPIO_PCNS_NSE4_SHIFT (4U) +/*! NSE4 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE4_SHIFT)) & RGPIO_PCNS_NSE4_MASK) + +#define RGPIO_PCNS_NSE5_MASK (0x20U) +#define RGPIO_PCNS_NSE5_SHIFT (5U) +/*! NSE5 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE5_SHIFT)) & RGPIO_PCNS_NSE5_MASK) + +#define RGPIO_PCNS_NSE6_MASK (0x40U) +#define RGPIO_PCNS_NSE6_SHIFT (6U) +/*! NSE6 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE6_SHIFT)) & RGPIO_PCNS_NSE6_MASK) + +#define RGPIO_PCNS_NSE7_MASK (0x80U) +#define RGPIO_PCNS_NSE7_SHIFT (7U) +/*! NSE7 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE7_SHIFT)) & RGPIO_PCNS_NSE7_MASK) + +#define RGPIO_PCNS_NSE8_MASK (0x100U) +#define RGPIO_PCNS_NSE8_SHIFT (8U) +/*! NSE8 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE8_SHIFT)) & RGPIO_PCNS_NSE8_MASK) + +#define RGPIO_PCNS_NSE9_MASK (0x200U) +#define RGPIO_PCNS_NSE9_SHIFT (9U) +/*! NSE9 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE9_SHIFT)) & RGPIO_PCNS_NSE9_MASK) + +#define RGPIO_PCNS_NSE10_MASK (0x400U) +#define RGPIO_PCNS_NSE10_SHIFT (10U) +/*! NSE10 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE10_SHIFT)) & RGPIO_PCNS_NSE10_MASK) + +#define RGPIO_PCNS_NSE11_MASK (0x800U) +#define RGPIO_PCNS_NSE11_SHIFT (11U) +/*! NSE11 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE11_SHIFT)) & RGPIO_PCNS_NSE11_MASK) + +#define RGPIO_PCNS_NSE12_MASK (0x1000U) +#define RGPIO_PCNS_NSE12_SHIFT (12U) +/*! NSE12 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE12_SHIFT)) & RGPIO_PCNS_NSE12_MASK) + +#define RGPIO_PCNS_NSE13_MASK (0x2000U) +#define RGPIO_PCNS_NSE13_SHIFT (13U) +/*! NSE13 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE13_SHIFT)) & RGPIO_PCNS_NSE13_MASK) + +#define RGPIO_PCNS_NSE14_MASK (0x4000U) +#define RGPIO_PCNS_NSE14_SHIFT (14U) +/*! NSE14 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE14_SHIFT)) & RGPIO_PCNS_NSE14_MASK) + +#define RGPIO_PCNS_NSE15_MASK (0x8000U) +#define RGPIO_PCNS_NSE15_SHIFT (15U) +/*! NSE15 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE15_SHIFT)) & RGPIO_PCNS_NSE15_MASK) + +#define RGPIO_PCNS_NSE16_MASK (0x10000U) +#define RGPIO_PCNS_NSE16_SHIFT (16U) +/*! NSE16 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE16_SHIFT)) & RGPIO_PCNS_NSE16_MASK) + +#define RGPIO_PCNS_NSE17_MASK (0x20000U) +#define RGPIO_PCNS_NSE17_SHIFT (17U) +/*! NSE17 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE17_SHIFT)) & RGPIO_PCNS_NSE17_MASK) + +#define RGPIO_PCNS_NSE18_MASK (0x40000U) +#define RGPIO_PCNS_NSE18_SHIFT (18U) +/*! NSE18 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE18_SHIFT)) & RGPIO_PCNS_NSE18_MASK) + +#define RGPIO_PCNS_NSE19_MASK (0x80000U) +#define RGPIO_PCNS_NSE19_SHIFT (19U) +/*! NSE19 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE19_SHIFT)) & RGPIO_PCNS_NSE19_MASK) + +#define RGPIO_PCNS_NSE20_MASK (0x100000U) +#define RGPIO_PCNS_NSE20_SHIFT (20U) +/*! NSE20 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE20_SHIFT)) & RGPIO_PCNS_NSE20_MASK) + +#define RGPIO_PCNS_NSE21_MASK (0x200000U) +#define RGPIO_PCNS_NSE21_SHIFT (21U) +/*! NSE21 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE21_SHIFT)) & RGPIO_PCNS_NSE21_MASK) + +#define RGPIO_PCNS_NSE22_MASK (0x400000U) +#define RGPIO_PCNS_NSE22_SHIFT (22U) +/*! NSE22 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE22_SHIFT)) & RGPIO_PCNS_NSE22_MASK) + +#define RGPIO_PCNS_NSE23_MASK (0x800000U) +#define RGPIO_PCNS_NSE23_SHIFT (23U) +/*! NSE23 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE23_SHIFT)) & RGPIO_PCNS_NSE23_MASK) + +#define RGPIO_PCNS_NSE24_MASK (0x1000000U) +#define RGPIO_PCNS_NSE24_SHIFT (24U) +/*! NSE24 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE24_SHIFT)) & RGPIO_PCNS_NSE24_MASK) + +#define RGPIO_PCNS_NSE25_MASK (0x2000000U) +#define RGPIO_PCNS_NSE25_SHIFT (25U) +/*! NSE25 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE25_SHIFT)) & RGPIO_PCNS_NSE25_MASK) + +#define RGPIO_PCNS_NSE26_MASK (0x4000000U) +#define RGPIO_PCNS_NSE26_SHIFT (26U) +/*! NSE26 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE26_SHIFT)) & RGPIO_PCNS_NSE26_MASK) + +#define RGPIO_PCNS_NSE27_MASK (0x8000000U) +#define RGPIO_PCNS_NSE27_SHIFT (27U) +/*! NSE27 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE27_SHIFT)) & RGPIO_PCNS_NSE27_MASK) + +#define RGPIO_PCNS_NSE28_MASK (0x10000000U) +#define RGPIO_PCNS_NSE28_SHIFT (28U) +/*! NSE28 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE28_SHIFT)) & RGPIO_PCNS_NSE28_MASK) + +#define RGPIO_PCNS_NSE29_MASK (0x20000000U) +#define RGPIO_PCNS_NSE29_SHIFT (29U) +/*! NSE29 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE29_SHIFT)) & RGPIO_PCNS_NSE29_MASK) + +#define RGPIO_PCNS_NSE30_MASK (0x40000000U) +#define RGPIO_PCNS_NSE30_SHIFT (30U) +/*! NSE30 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE30_SHIFT)) & RGPIO_PCNS_NSE30_MASK) + +#define RGPIO_PCNS_NSE31_MASK (0x80000000U) +#define RGPIO_PCNS_NSE31_SHIFT (31U) +/*! NSE31 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE31_SHIFT)) & RGPIO_PCNS_NSE31_MASK) +/*! @} */ + +/*! @name ICNS - Interrupt Control Nonsecure */ +/*! @{ */ + +#define RGPIO_ICNS_NSE0_MASK (0x1U) +#define RGPIO_ICNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE0_SHIFT)) & RGPIO_ICNS_NSE0_MASK) + +#define RGPIO_ICNS_NSE1_MASK (0x2U) +#define RGPIO_ICNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE1_SHIFT)) & RGPIO_ICNS_NSE1_MASK) +/*! @} */ + +/*! @name PCNP - Pin Control Nonprivilege */ +/*! @{ */ + +#define RGPIO_PCNP_NPE0_MASK (0x1U) +#define RGPIO_PCNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE0_SHIFT)) & RGPIO_PCNP_NPE0_MASK) + +#define RGPIO_PCNP_NPE1_MASK (0x2U) +#define RGPIO_PCNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE1_SHIFT)) & RGPIO_PCNP_NPE1_MASK) + +#define RGPIO_PCNP_NPE2_MASK (0x4U) +#define RGPIO_PCNP_NPE2_SHIFT (2U) +/*! NPE2 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE2_SHIFT)) & RGPIO_PCNP_NPE2_MASK) + +#define RGPIO_PCNP_NPE3_MASK (0x8U) +#define RGPIO_PCNP_NPE3_SHIFT (3U) +/*! NPE3 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE3_SHIFT)) & RGPIO_PCNP_NPE3_MASK) + +#define RGPIO_PCNP_NPE4_MASK (0x10U) +#define RGPIO_PCNP_NPE4_SHIFT (4U) +/*! NPE4 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE4_SHIFT)) & RGPIO_PCNP_NPE4_MASK) + +#define RGPIO_PCNP_NPE5_MASK (0x20U) +#define RGPIO_PCNP_NPE5_SHIFT (5U) +/*! NPE5 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE5_SHIFT)) & RGPIO_PCNP_NPE5_MASK) + +#define RGPIO_PCNP_NPE6_MASK (0x40U) +#define RGPIO_PCNP_NPE6_SHIFT (6U) +/*! NPE6 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE6_SHIFT)) & RGPIO_PCNP_NPE6_MASK) + +#define RGPIO_PCNP_NPE7_MASK (0x80U) +#define RGPIO_PCNP_NPE7_SHIFT (7U) +/*! NPE7 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE7_SHIFT)) & RGPIO_PCNP_NPE7_MASK) + +#define RGPIO_PCNP_NPE8_MASK (0x100U) +#define RGPIO_PCNP_NPE8_SHIFT (8U) +/*! NPE8 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE8_SHIFT)) & RGPIO_PCNP_NPE8_MASK) + +#define RGPIO_PCNP_NPE9_MASK (0x200U) +#define RGPIO_PCNP_NPE9_SHIFT (9U) +/*! NPE9 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE9_SHIFT)) & RGPIO_PCNP_NPE9_MASK) + +#define RGPIO_PCNP_NPE10_MASK (0x400U) +#define RGPIO_PCNP_NPE10_SHIFT (10U) +/*! NPE10 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE10_SHIFT)) & RGPIO_PCNP_NPE10_MASK) + +#define RGPIO_PCNP_NPE11_MASK (0x800U) +#define RGPIO_PCNP_NPE11_SHIFT (11U) +/*! NPE11 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE11_SHIFT)) & RGPIO_PCNP_NPE11_MASK) + +#define RGPIO_PCNP_NPE12_MASK (0x1000U) +#define RGPIO_PCNP_NPE12_SHIFT (12U) +/*! NPE12 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE12_SHIFT)) & RGPIO_PCNP_NPE12_MASK) + +#define RGPIO_PCNP_NPE13_MASK (0x2000U) +#define RGPIO_PCNP_NPE13_SHIFT (13U) +/*! NPE13 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE13_SHIFT)) & RGPIO_PCNP_NPE13_MASK) + +#define RGPIO_PCNP_NPE14_MASK (0x4000U) +#define RGPIO_PCNP_NPE14_SHIFT (14U) +/*! NPE14 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE14_SHIFT)) & RGPIO_PCNP_NPE14_MASK) + +#define RGPIO_PCNP_NPE15_MASK (0x8000U) +#define RGPIO_PCNP_NPE15_SHIFT (15U) +/*! NPE15 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE15_SHIFT)) & RGPIO_PCNP_NPE15_MASK) + +#define RGPIO_PCNP_NPE16_MASK (0x10000U) +#define RGPIO_PCNP_NPE16_SHIFT (16U) +/*! NPE16 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE16_SHIFT)) & RGPIO_PCNP_NPE16_MASK) + +#define RGPIO_PCNP_NPE17_MASK (0x20000U) +#define RGPIO_PCNP_NPE17_SHIFT (17U) +/*! NPE17 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE17_SHIFT)) & RGPIO_PCNP_NPE17_MASK) + +#define RGPIO_PCNP_NPE18_MASK (0x40000U) +#define RGPIO_PCNP_NPE18_SHIFT (18U) +/*! NPE18 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE18_SHIFT)) & RGPIO_PCNP_NPE18_MASK) + +#define RGPIO_PCNP_NPE19_MASK (0x80000U) +#define RGPIO_PCNP_NPE19_SHIFT (19U) +/*! NPE19 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE19_SHIFT)) & RGPIO_PCNP_NPE19_MASK) + +#define RGPIO_PCNP_NPE20_MASK (0x100000U) +#define RGPIO_PCNP_NPE20_SHIFT (20U) +/*! NPE20 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE20_SHIFT)) & RGPIO_PCNP_NPE20_MASK) + +#define RGPIO_PCNP_NPE21_MASK (0x200000U) +#define RGPIO_PCNP_NPE21_SHIFT (21U) +/*! NPE21 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE21_SHIFT)) & RGPIO_PCNP_NPE21_MASK) + +#define RGPIO_PCNP_NPE22_MASK (0x400000U) +#define RGPIO_PCNP_NPE22_SHIFT (22U) +/*! NPE22 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE22_SHIFT)) & RGPIO_PCNP_NPE22_MASK) + +#define RGPIO_PCNP_NPE23_MASK (0x800000U) +#define RGPIO_PCNP_NPE23_SHIFT (23U) +/*! NPE23 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE23_SHIFT)) & RGPIO_PCNP_NPE23_MASK) + +#define RGPIO_PCNP_NPE24_MASK (0x1000000U) +#define RGPIO_PCNP_NPE24_SHIFT (24U) +/*! NPE24 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE24_SHIFT)) & RGPIO_PCNP_NPE24_MASK) + +#define RGPIO_PCNP_NPE25_MASK (0x2000000U) +#define RGPIO_PCNP_NPE25_SHIFT (25U) +/*! NPE25 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE25_SHIFT)) & RGPIO_PCNP_NPE25_MASK) + +#define RGPIO_PCNP_NPE26_MASK (0x4000000U) +#define RGPIO_PCNP_NPE26_SHIFT (26U) +/*! NPE26 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE26_SHIFT)) & RGPIO_PCNP_NPE26_MASK) + +#define RGPIO_PCNP_NPE27_MASK (0x8000000U) +#define RGPIO_PCNP_NPE27_SHIFT (27U) +/*! NPE27 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE27_SHIFT)) & RGPIO_PCNP_NPE27_MASK) + +#define RGPIO_PCNP_NPE28_MASK (0x10000000U) +#define RGPIO_PCNP_NPE28_SHIFT (28U) +/*! NPE28 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE28_SHIFT)) & RGPIO_PCNP_NPE28_MASK) + +#define RGPIO_PCNP_NPE29_MASK (0x20000000U) +#define RGPIO_PCNP_NPE29_SHIFT (29U) +/*! NPE29 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE29_SHIFT)) & RGPIO_PCNP_NPE29_MASK) + +#define RGPIO_PCNP_NPE30_MASK (0x40000000U) +#define RGPIO_PCNP_NPE30_SHIFT (30U) +/*! NPE30 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE30_SHIFT)) & RGPIO_PCNP_NPE30_MASK) + +#define RGPIO_PCNP_NPE31_MASK (0x80000000U) +#define RGPIO_PCNP_NPE31_SHIFT (31U) +/*! NPE31 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE31_SHIFT)) & RGPIO_PCNP_NPE31_MASK) +/*! @} */ + +/*! @name ICNP - Interrupt Control Nonprivilege */ +/*! @{ */ + +#define RGPIO_ICNP_NPE0_MASK (0x1U) +#define RGPIO_ICNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE0_SHIFT)) & RGPIO_ICNP_NPE0_MASK) + +#define RGPIO_ICNP_NPE1_MASK (0x2U) +#define RGPIO_ICNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE1_SHIFT)) & RGPIO_ICNP_NPE1_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define RGPIO_PDOR_PDO0_MASK (0x1U) +#define RGPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO0_SHIFT)) & RGPIO_PDOR_PDO0_MASK) + +#define RGPIO_PDOR_PDO1_MASK (0x2U) +#define RGPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO1_SHIFT)) & RGPIO_PDOR_PDO1_MASK) + +#define RGPIO_PDOR_PDO2_MASK (0x4U) +#define RGPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO2_SHIFT)) & RGPIO_PDOR_PDO2_MASK) + +#define RGPIO_PDOR_PDO3_MASK (0x8U) +#define RGPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO3_SHIFT)) & RGPIO_PDOR_PDO3_MASK) + +#define RGPIO_PDOR_PDO4_MASK (0x10U) +#define RGPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO4_SHIFT)) & RGPIO_PDOR_PDO4_MASK) + +#define RGPIO_PDOR_PDO5_MASK (0x20U) +#define RGPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO5_SHIFT)) & RGPIO_PDOR_PDO5_MASK) + +#define RGPIO_PDOR_PDO6_MASK (0x40U) +#define RGPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO6_SHIFT)) & RGPIO_PDOR_PDO6_MASK) + +#define RGPIO_PDOR_PDO7_MASK (0x80U) +#define RGPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO7_SHIFT)) & RGPIO_PDOR_PDO7_MASK) + +#define RGPIO_PDOR_PDO8_MASK (0x100U) +#define RGPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO8_SHIFT)) & RGPIO_PDOR_PDO8_MASK) + +#define RGPIO_PDOR_PDO9_MASK (0x200U) +#define RGPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO9_SHIFT)) & RGPIO_PDOR_PDO9_MASK) + +#define RGPIO_PDOR_PDO10_MASK (0x400U) +#define RGPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO10_SHIFT)) & RGPIO_PDOR_PDO10_MASK) + +#define RGPIO_PDOR_PDO11_MASK (0x800U) +#define RGPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO11_SHIFT)) & RGPIO_PDOR_PDO11_MASK) + +#define RGPIO_PDOR_PDO12_MASK (0x1000U) +#define RGPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO12_SHIFT)) & RGPIO_PDOR_PDO12_MASK) + +#define RGPIO_PDOR_PDO13_MASK (0x2000U) +#define RGPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO13_SHIFT)) & RGPIO_PDOR_PDO13_MASK) + +#define RGPIO_PDOR_PDO14_MASK (0x4000U) +#define RGPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO14_SHIFT)) & RGPIO_PDOR_PDO14_MASK) + +#define RGPIO_PDOR_PDO15_MASK (0x8000U) +#define RGPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO15_SHIFT)) & RGPIO_PDOR_PDO15_MASK) + +#define RGPIO_PDOR_PDO16_MASK (0x10000U) +#define RGPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO16_SHIFT)) & RGPIO_PDOR_PDO16_MASK) + +#define RGPIO_PDOR_PDO17_MASK (0x20000U) +#define RGPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO17_SHIFT)) & RGPIO_PDOR_PDO17_MASK) + +#define RGPIO_PDOR_PDO18_MASK (0x40000U) +#define RGPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO18_SHIFT)) & RGPIO_PDOR_PDO18_MASK) + +#define RGPIO_PDOR_PDO19_MASK (0x80000U) +#define RGPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO19_SHIFT)) & RGPIO_PDOR_PDO19_MASK) + +#define RGPIO_PDOR_PDO20_MASK (0x100000U) +#define RGPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO20_SHIFT)) & RGPIO_PDOR_PDO20_MASK) + +#define RGPIO_PDOR_PDO21_MASK (0x200000U) +#define RGPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO21_SHIFT)) & RGPIO_PDOR_PDO21_MASK) + +#define RGPIO_PDOR_PDO22_MASK (0x400000U) +#define RGPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO22_SHIFT)) & RGPIO_PDOR_PDO22_MASK) + +#define RGPIO_PDOR_PDO23_MASK (0x800000U) +#define RGPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO23_SHIFT)) & RGPIO_PDOR_PDO23_MASK) + +#define RGPIO_PDOR_PDO24_MASK (0x1000000U) +#define RGPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO24_SHIFT)) & RGPIO_PDOR_PDO24_MASK) + +#define RGPIO_PDOR_PDO25_MASK (0x2000000U) +#define RGPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO25_SHIFT)) & RGPIO_PDOR_PDO25_MASK) + +#define RGPIO_PDOR_PDO26_MASK (0x4000000U) +#define RGPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO26_SHIFT)) & RGPIO_PDOR_PDO26_MASK) + +#define RGPIO_PDOR_PDO27_MASK (0x8000000U) +#define RGPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO27_SHIFT)) & RGPIO_PDOR_PDO27_MASK) + +#define RGPIO_PDOR_PDO28_MASK (0x10000000U) +#define RGPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO28_SHIFT)) & RGPIO_PDOR_PDO28_MASK) + +#define RGPIO_PDOR_PDO29_MASK (0x20000000U) +#define RGPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO29_SHIFT)) & RGPIO_PDOR_PDO29_MASK) + +#define RGPIO_PDOR_PDO30_MASK (0x40000000U) +#define RGPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO30_SHIFT)) & RGPIO_PDOR_PDO30_MASK) + +#define RGPIO_PDOR_PDO31_MASK (0x80000000U) +#define RGPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO31_SHIFT)) & RGPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define RGPIO_PSOR_PTSO0_MASK (0x1U) +#define RGPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO0_SHIFT)) & RGPIO_PSOR_PTSO0_MASK) + +#define RGPIO_PSOR_PTSO1_MASK (0x2U) +#define RGPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO1_SHIFT)) & RGPIO_PSOR_PTSO1_MASK) + +#define RGPIO_PSOR_PTSO2_MASK (0x4U) +#define RGPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO2_SHIFT)) & RGPIO_PSOR_PTSO2_MASK) + +#define RGPIO_PSOR_PTSO3_MASK (0x8U) +#define RGPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO3_SHIFT)) & RGPIO_PSOR_PTSO3_MASK) + +#define RGPIO_PSOR_PTSO4_MASK (0x10U) +#define RGPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO4_SHIFT)) & RGPIO_PSOR_PTSO4_MASK) + +#define RGPIO_PSOR_PTSO5_MASK (0x20U) +#define RGPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO5_SHIFT)) & RGPIO_PSOR_PTSO5_MASK) + +#define RGPIO_PSOR_PTSO6_MASK (0x40U) +#define RGPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO6_SHIFT)) & RGPIO_PSOR_PTSO6_MASK) + +#define RGPIO_PSOR_PTSO7_MASK (0x80U) +#define RGPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO7_SHIFT)) & RGPIO_PSOR_PTSO7_MASK) + +#define RGPIO_PSOR_PTSO8_MASK (0x100U) +#define RGPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO8_SHIFT)) & RGPIO_PSOR_PTSO8_MASK) + +#define RGPIO_PSOR_PTSO9_MASK (0x200U) +#define RGPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO9_SHIFT)) & RGPIO_PSOR_PTSO9_MASK) + +#define RGPIO_PSOR_PTSO10_MASK (0x400U) +#define RGPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO10_SHIFT)) & RGPIO_PSOR_PTSO10_MASK) + +#define RGPIO_PSOR_PTSO11_MASK (0x800U) +#define RGPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO11_SHIFT)) & RGPIO_PSOR_PTSO11_MASK) + +#define RGPIO_PSOR_PTSO12_MASK (0x1000U) +#define RGPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO12_SHIFT)) & RGPIO_PSOR_PTSO12_MASK) + +#define RGPIO_PSOR_PTSO13_MASK (0x2000U) +#define RGPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO13_SHIFT)) & RGPIO_PSOR_PTSO13_MASK) + +#define RGPIO_PSOR_PTSO14_MASK (0x4000U) +#define RGPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO14_SHIFT)) & RGPIO_PSOR_PTSO14_MASK) + +#define RGPIO_PSOR_PTSO15_MASK (0x8000U) +#define RGPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO15_SHIFT)) & RGPIO_PSOR_PTSO15_MASK) + +#define RGPIO_PSOR_PTSO16_MASK (0x10000U) +#define RGPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO16_SHIFT)) & RGPIO_PSOR_PTSO16_MASK) + +#define RGPIO_PSOR_PTSO17_MASK (0x20000U) +#define RGPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO17_SHIFT)) & RGPIO_PSOR_PTSO17_MASK) + +#define RGPIO_PSOR_PTSO18_MASK (0x40000U) +#define RGPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO18_SHIFT)) & RGPIO_PSOR_PTSO18_MASK) + +#define RGPIO_PSOR_PTSO19_MASK (0x80000U) +#define RGPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO19_SHIFT)) & RGPIO_PSOR_PTSO19_MASK) + +#define RGPIO_PSOR_PTSO20_MASK (0x100000U) +#define RGPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO20_SHIFT)) & RGPIO_PSOR_PTSO20_MASK) + +#define RGPIO_PSOR_PTSO21_MASK (0x200000U) +#define RGPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO21_SHIFT)) & RGPIO_PSOR_PTSO21_MASK) + +#define RGPIO_PSOR_PTSO22_MASK (0x400000U) +#define RGPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO22_SHIFT)) & RGPIO_PSOR_PTSO22_MASK) + +#define RGPIO_PSOR_PTSO23_MASK (0x800000U) +#define RGPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO23_SHIFT)) & RGPIO_PSOR_PTSO23_MASK) + +#define RGPIO_PSOR_PTSO24_MASK (0x1000000U) +#define RGPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO24_SHIFT)) & RGPIO_PSOR_PTSO24_MASK) + +#define RGPIO_PSOR_PTSO25_MASK (0x2000000U) +#define RGPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO25_SHIFT)) & RGPIO_PSOR_PTSO25_MASK) + +#define RGPIO_PSOR_PTSO26_MASK (0x4000000U) +#define RGPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO26_SHIFT)) & RGPIO_PSOR_PTSO26_MASK) + +#define RGPIO_PSOR_PTSO27_MASK (0x8000000U) +#define RGPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO27_SHIFT)) & RGPIO_PSOR_PTSO27_MASK) + +#define RGPIO_PSOR_PTSO28_MASK (0x10000000U) +#define RGPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO28_SHIFT)) & RGPIO_PSOR_PTSO28_MASK) + +#define RGPIO_PSOR_PTSO29_MASK (0x20000000U) +#define RGPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO29_SHIFT)) & RGPIO_PSOR_PTSO29_MASK) + +#define RGPIO_PSOR_PTSO30_MASK (0x40000000U) +#define RGPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO30_SHIFT)) & RGPIO_PSOR_PTSO30_MASK) + +#define RGPIO_PSOR_PTSO31_MASK (0x80000000U) +#define RGPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO31_SHIFT)) & RGPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define RGPIO_PCOR_PTCO0_MASK (0x1U) +#define RGPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO0_SHIFT)) & RGPIO_PCOR_PTCO0_MASK) + +#define RGPIO_PCOR_PTCO1_MASK (0x2U) +#define RGPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO1_SHIFT)) & RGPIO_PCOR_PTCO1_MASK) + +#define RGPIO_PCOR_PTCO2_MASK (0x4U) +#define RGPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO2_SHIFT)) & RGPIO_PCOR_PTCO2_MASK) + +#define RGPIO_PCOR_PTCO3_MASK (0x8U) +#define RGPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO3_SHIFT)) & RGPIO_PCOR_PTCO3_MASK) + +#define RGPIO_PCOR_PTCO4_MASK (0x10U) +#define RGPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO4_SHIFT)) & RGPIO_PCOR_PTCO4_MASK) + +#define RGPIO_PCOR_PTCO5_MASK (0x20U) +#define RGPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO5_SHIFT)) & RGPIO_PCOR_PTCO5_MASK) + +#define RGPIO_PCOR_PTCO6_MASK (0x40U) +#define RGPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO6_SHIFT)) & RGPIO_PCOR_PTCO6_MASK) + +#define RGPIO_PCOR_PTCO7_MASK (0x80U) +#define RGPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO7_SHIFT)) & RGPIO_PCOR_PTCO7_MASK) + +#define RGPIO_PCOR_PTCO8_MASK (0x100U) +#define RGPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO8_SHIFT)) & RGPIO_PCOR_PTCO8_MASK) + +#define RGPIO_PCOR_PTCO9_MASK (0x200U) +#define RGPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO9_SHIFT)) & RGPIO_PCOR_PTCO9_MASK) + +#define RGPIO_PCOR_PTCO10_MASK (0x400U) +#define RGPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO10_SHIFT)) & RGPIO_PCOR_PTCO10_MASK) + +#define RGPIO_PCOR_PTCO11_MASK (0x800U) +#define RGPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO11_SHIFT)) & RGPIO_PCOR_PTCO11_MASK) + +#define RGPIO_PCOR_PTCO12_MASK (0x1000U) +#define RGPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO12_SHIFT)) & RGPIO_PCOR_PTCO12_MASK) + +#define RGPIO_PCOR_PTCO13_MASK (0x2000U) +#define RGPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO13_SHIFT)) & RGPIO_PCOR_PTCO13_MASK) + +#define RGPIO_PCOR_PTCO14_MASK (0x4000U) +#define RGPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO14_SHIFT)) & RGPIO_PCOR_PTCO14_MASK) + +#define RGPIO_PCOR_PTCO15_MASK (0x8000U) +#define RGPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO15_SHIFT)) & RGPIO_PCOR_PTCO15_MASK) + +#define RGPIO_PCOR_PTCO16_MASK (0x10000U) +#define RGPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO16_SHIFT)) & RGPIO_PCOR_PTCO16_MASK) + +#define RGPIO_PCOR_PTCO17_MASK (0x20000U) +#define RGPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO17_SHIFT)) & RGPIO_PCOR_PTCO17_MASK) + +#define RGPIO_PCOR_PTCO18_MASK (0x40000U) +#define RGPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO18_SHIFT)) & RGPIO_PCOR_PTCO18_MASK) + +#define RGPIO_PCOR_PTCO19_MASK (0x80000U) +#define RGPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO19_SHIFT)) & RGPIO_PCOR_PTCO19_MASK) + +#define RGPIO_PCOR_PTCO20_MASK (0x100000U) +#define RGPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO20_SHIFT)) & RGPIO_PCOR_PTCO20_MASK) + +#define RGPIO_PCOR_PTCO21_MASK (0x200000U) +#define RGPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO21_SHIFT)) & RGPIO_PCOR_PTCO21_MASK) + +#define RGPIO_PCOR_PTCO22_MASK (0x400000U) +#define RGPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO22_SHIFT)) & RGPIO_PCOR_PTCO22_MASK) + +#define RGPIO_PCOR_PTCO23_MASK (0x800000U) +#define RGPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO23_SHIFT)) & RGPIO_PCOR_PTCO23_MASK) + +#define RGPIO_PCOR_PTCO24_MASK (0x1000000U) +#define RGPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO24_SHIFT)) & RGPIO_PCOR_PTCO24_MASK) + +#define RGPIO_PCOR_PTCO25_MASK (0x2000000U) +#define RGPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO25_SHIFT)) & RGPIO_PCOR_PTCO25_MASK) + +#define RGPIO_PCOR_PTCO26_MASK (0x4000000U) +#define RGPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO26_SHIFT)) & RGPIO_PCOR_PTCO26_MASK) + +#define RGPIO_PCOR_PTCO27_MASK (0x8000000U) +#define RGPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO27_SHIFT)) & RGPIO_PCOR_PTCO27_MASK) + +#define RGPIO_PCOR_PTCO28_MASK (0x10000000U) +#define RGPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO28_SHIFT)) & RGPIO_PCOR_PTCO28_MASK) + +#define RGPIO_PCOR_PTCO29_MASK (0x20000000U) +#define RGPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO29_SHIFT)) & RGPIO_PCOR_PTCO29_MASK) + +#define RGPIO_PCOR_PTCO30_MASK (0x40000000U) +#define RGPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO30_SHIFT)) & RGPIO_PCOR_PTCO30_MASK) + +#define RGPIO_PCOR_PTCO31_MASK (0x80000000U) +#define RGPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO31_SHIFT)) & RGPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define RGPIO_PTOR_PTTO0_MASK (0x1U) +#define RGPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO0_SHIFT)) & RGPIO_PTOR_PTTO0_MASK) + +#define RGPIO_PTOR_PTTO1_MASK (0x2U) +#define RGPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO1_SHIFT)) & RGPIO_PTOR_PTTO1_MASK) + +#define RGPIO_PTOR_PTTO2_MASK (0x4U) +#define RGPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO2_SHIFT)) & RGPIO_PTOR_PTTO2_MASK) + +#define RGPIO_PTOR_PTTO3_MASK (0x8U) +#define RGPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO3_SHIFT)) & RGPIO_PTOR_PTTO3_MASK) + +#define RGPIO_PTOR_PTTO4_MASK (0x10U) +#define RGPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO4_SHIFT)) & RGPIO_PTOR_PTTO4_MASK) + +#define RGPIO_PTOR_PTTO5_MASK (0x20U) +#define RGPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO5_SHIFT)) & RGPIO_PTOR_PTTO5_MASK) + +#define RGPIO_PTOR_PTTO6_MASK (0x40U) +#define RGPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO6_SHIFT)) & RGPIO_PTOR_PTTO6_MASK) + +#define RGPIO_PTOR_PTTO7_MASK (0x80U) +#define RGPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO7_SHIFT)) & RGPIO_PTOR_PTTO7_MASK) + +#define RGPIO_PTOR_PTTO8_MASK (0x100U) +#define RGPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO8_SHIFT)) & RGPIO_PTOR_PTTO8_MASK) + +#define RGPIO_PTOR_PTTO9_MASK (0x200U) +#define RGPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO9_SHIFT)) & RGPIO_PTOR_PTTO9_MASK) + +#define RGPIO_PTOR_PTTO10_MASK (0x400U) +#define RGPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO10_SHIFT)) & RGPIO_PTOR_PTTO10_MASK) + +#define RGPIO_PTOR_PTTO11_MASK (0x800U) +#define RGPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO11_SHIFT)) & RGPIO_PTOR_PTTO11_MASK) + +#define RGPIO_PTOR_PTTO12_MASK (0x1000U) +#define RGPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO12_SHIFT)) & RGPIO_PTOR_PTTO12_MASK) + +#define RGPIO_PTOR_PTTO13_MASK (0x2000U) +#define RGPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO13_SHIFT)) & RGPIO_PTOR_PTTO13_MASK) + +#define RGPIO_PTOR_PTTO14_MASK (0x4000U) +#define RGPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO14_SHIFT)) & RGPIO_PTOR_PTTO14_MASK) + +#define RGPIO_PTOR_PTTO15_MASK (0x8000U) +#define RGPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO15_SHIFT)) & RGPIO_PTOR_PTTO15_MASK) + +#define RGPIO_PTOR_PTTO16_MASK (0x10000U) +#define RGPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO16_SHIFT)) & RGPIO_PTOR_PTTO16_MASK) + +#define RGPIO_PTOR_PTTO17_MASK (0x20000U) +#define RGPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO17_SHIFT)) & RGPIO_PTOR_PTTO17_MASK) + +#define RGPIO_PTOR_PTTO18_MASK (0x40000U) +#define RGPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO18_SHIFT)) & RGPIO_PTOR_PTTO18_MASK) + +#define RGPIO_PTOR_PTTO19_MASK (0x80000U) +#define RGPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO19_SHIFT)) & RGPIO_PTOR_PTTO19_MASK) + +#define RGPIO_PTOR_PTTO20_MASK (0x100000U) +#define RGPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO20_SHIFT)) & RGPIO_PTOR_PTTO20_MASK) + +#define RGPIO_PTOR_PTTO21_MASK (0x200000U) +#define RGPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO21_SHIFT)) & RGPIO_PTOR_PTTO21_MASK) + +#define RGPIO_PTOR_PTTO22_MASK (0x400000U) +#define RGPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO22_SHIFT)) & RGPIO_PTOR_PTTO22_MASK) + +#define RGPIO_PTOR_PTTO23_MASK (0x800000U) +#define RGPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO23_SHIFT)) & RGPIO_PTOR_PTTO23_MASK) + +#define RGPIO_PTOR_PTTO24_MASK (0x1000000U) +#define RGPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO24_SHIFT)) & RGPIO_PTOR_PTTO24_MASK) + +#define RGPIO_PTOR_PTTO25_MASK (0x2000000U) +#define RGPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO25_SHIFT)) & RGPIO_PTOR_PTTO25_MASK) + +#define RGPIO_PTOR_PTTO26_MASK (0x4000000U) +#define RGPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO26_SHIFT)) & RGPIO_PTOR_PTTO26_MASK) + +#define RGPIO_PTOR_PTTO27_MASK (0x8000000U) +#define RGPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO27_SHIFT)) & RGPIO_PTOR_PTTO27_MASK) + +#define RGPIO_PTOR_PTTO28_MASK (0x10000000U) +#define RGPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO28_SHIFT)) & RGPIO_PTOR_PTTO28_MASK) + +#define RGPIO_PTOR_PTTO29_MASK (0x20000000U) +#define RGPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO29_SHIFT)) & RGPIO_PTOR_PTTO29_MASK) + +#define RGPIO_PTOR_PTTO30_MASK (0x40000000U) +#define RGPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO30_SHIFT)) & RGPIO_PTOR_PTTO30_MASK) + +#define RGPIO_PTOR_PTTO31_MASK (0x80000000U) +#define RGPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO31_SHIFT)) & RGPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define RGPIO_PDIR_PDI0_MASK (0x1U) +#define RGPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI0_SHIFT)) & RGPIO_PDIR_PDI0_MASK) + +#define RGPIO_PDIR_PDI1_MASK (0x2U) +#define RGPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI1_SHIFT)) & RGPIO_PDIR_PDI1_MASK) + +#define RGPIO_PDIR_PDI2_MASK (0x4U) +#define RGPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI2_SHIFT)) & RGPIO_PDIR_PDI2_MASK) + +#define RGPIO_PDIR_PDI3_MASK (0x8U) +#define RGPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI3_SHIFT)) & RGPIO_PDIR_PDI3_MASK) + +#define RGPIO_PDIR_PDI4_MASK (0x10U) +#define RGPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI4_SHIFT)) & RGPIO_PDIR_PDI4_MASK) + +#define RGPIO_PDIR_PDI5_MASK (0x20U) +#define RGPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI5_SHIFT)) & RGPIO_PDIR_PDI5_MASK) + +#define RGPIO_PDIR_PDI6_MASK (0x40U) +#define RGPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI6_SHIFT)) & RGPIO_PDIR_PDI6_MASK) + +#define RGPIO_PDIR_PDI7_MASK (0x80U) +#define RGPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI7_SHIFT)) & RGPIO_PDIR_PDI7_MASK) + +#define RGPIO_PDIR_PDI8_MASK (0x100U) +#define RGPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI8_SHIFT)) & RGPIO_PDIR_PDI8_MASK) + +#define RGPIO_PDIR_PDI9_MASK (0x200U) +#define RGPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI9_SHIFT)) & RGPIO_PDIR_PDI9_MASK) + +#define RGPIO_PDIR_PDI10_MASK (0x400U) +#define RGPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI10_SHIFT)) & RGPIO_PDIR_PDI10_MASK) + +#define RGPIO_PDIR_PDI11_MASK (0x800U) +#define RGPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI11_SHIFT)) & RGPIO_PDIR_PDI11_MASK) + +#define RGPIO_PDIR_PDI12_MASK (0x1000U) +#define RGPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI12_SHIFT)) & RGPIO_PDIR_PDI12_MASK) + +#define RGPIO_PDIR_PDI13_MASK (0x2000U) +#define RGPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI13_SHIFT)) & RGPIO_PDIR_PDI13_MASK) + +#define RGPIO_PDIR_PDI14_MASK (0x4000U) +#define RGPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI14_SHIFT)) & RGPIO_PDIR_PDI14_MASK) + +#define RGPIO_PDIR_PDI15_MASK (0x8000U) +#define RGPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI15_SHIFT)) & RGPIO_PDIR_PDI15_MASK) + +#define RGPIO_PDIR_PDI16_MASK (0x10000U) +#define RGPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI16_SHIFT)) & RGPIO_PDIR_PDI16_MASK) + +#define RGPIO_PDIR_PDI17_MASK (0x20000U) +#define RGPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI17_SHIFT)) & RGPIO_PDIR_PDI17_MASK) + +#define RGPIO_PDIR_PDI18_MASK (0x40000U) +#define RGPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI18_SHIFT)) & RGPIO_PDIR_PDI18_MASK) + +#define RGPIO_PDIR_PDI19_MASK (0x80000U) +#define RGPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI19_SHIFT)) & RGPIO_PDIR_PDI19_MASK) + +#define RGPIO_PDIR_PDI20_MASK (0x100000U) +#define RGPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI20_SHIFT)) & RGPIO_PDIR_PDI20_MASK) + +#define RGPIO_PDIR_PDI21_MASK (0x200000U) +#define RGPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI21_SHIFT)) & RGPIO_PDIR_PDI21_MASK) + +#define RGPIO_PDIR_PDI22_MASK (0x400000U) +#define RGPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI22_SHIFT)) & RGPIO_PDIR_PDI22_MASK) + +#define RGPIO_PDIR_PDI23_MASK (0x800000U) +#define RGPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI23_SHIFT)) & RGPIO_PDIR_PDI23_MASK) + +#define RGPIO_PDIR_PDI24_MASK (0x1000000U) +#define RGPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI24_SHIFT)) & RGPIO_PDIR_PDI24_MASK) + +#define RGPIO_PDIR_PDI25_MASK (0x2000000U) +#define RGPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI25_SHIFT)) & RGPIO_PDIR_PDI25_MASK) + +#define RGPIO_PDIR_PDI26_MASK (0x4000000U) +#define RGPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI26_SHIFT)) & RGPIO_PDIR_PDI26_MASK) + +#define RGPIO_PDIR_PDI27_MASK (0x8000000U) +#define RGPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI27_SHIFT)) & RGPIO_PDIR_PDI27_MASK) + +#define RGPIO_PDIR_PDI28_MASK (0x10000000U) +#define RGPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI28_SHIFT)) & RGPIO_PDIR_PDI28_MASK) + +#define RGPIO_PDIR_PDI29_MASK (0x20000000U) +#define RGPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI29_SHIFT)) & RGPIO_PDIR_PDI29_MASK) + +#define RGPIO_PDIR_PDI30_MASK (0x40000000U) +#define RGPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI30_SHIFT)) & RGPIO_PDIR_PDI30_MASK) + +#define RGPIO_PDIR_PDI31_MASK (0x80000000U) +#define RGPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI31_SHIFT)) & RGPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define RGPIO_PDDR_PDD0_MASK (0x1U) +#define RGPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD0_SHIFT)) & RGPIO_PDDR_PDD0_MASK) + +#define RGPIO_PDDR_PDD1_MASK (0x2U) +#define RGPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD1_SHIFT)) & RGPIO_PDDR_PDD1_MASK) + +#define RGPIO_PDDR_PDD2_MASK (0x4U) +#define RGPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD2_SHIFT)) & RGPIO_PDDR_PDD2_MASK) + +#define RGPIO_PDDR_PDD3_MASK (0x8U) +#define RGPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD3_SHIFT)) & RGPIO_PDDR_PDD3_MASK) + +#define RGPIO_PDDR_PDD4_MASK (0x10U) +#define RGPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD4_SHIFT)) & RGPIO_PDDR_PDD4_MASK) + +#define RGPIO_PDDR_PDD5_MASK (0x20U) +#define RGPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD5_SHIFT)) & RGPIO_PDDR_PDD5_MASK) + +#define RGPIO_PDDR_PDD6_MASK (0x40U) +#define RGPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD6_SHIFT)) & RGPIO_PDDR_PDD6_MASK) + +#define RGPIO_PDDR_PDD7_MASK (0x80U) +#define RGPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD7_SHIFT)) & RGPIO_PDDR_PDD7_MASK) + +#define RGPIO_PDDR_PDD8_MASK (0x100U) +#define RGPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD8_SHIFT)) & RGPIO_PDDR_PDD8_MASK) + +#define RGPIO_PDDR_PDD9_MASK (0x200U) +#define RGPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD9_SHIFT)) & RGPIO_PDDR_PDD9_MASK) + +#define RGPIO_PDDR_PDD10_MASK (0x400U) +#define RGPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD10_SHIFT)) & RGPIO_PDDR_PDD10_MASK) + +#define RGPIO_PDDR_PDD11_MASK (0x800U) +#define RGPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD11_SHIFT)) & RGPIO_PDDR_PDD11_MASK) + +#define RGPIO_PDDR_PDD12_MASK (0x1000U) +#define RGPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD12_SHIFT)) & RGPIO_PDDR_PDD12_MASK) + +#define RGPIO_PDDR_PDD13_MASK (0x2000U) +#define RGPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD13_SHIFT)) & RGPIO_PDDR_PDD13_MASK) + +#define RGPIO_PDDR_PDD14_MASK (0x4000U) +#define RGPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD14_SHIFT)) & RGPIO_PDDR_PDD14_MASK) + +#define RGPIO_PDDR_PDD15_MASK (0x8000U) +#define RGPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD15_SHIFT)) & RGPIO_PDDR_PDD15_MASK) + +#define RGPIO_PDDR_PDD16_MASK (0x10000U) +#define RGPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD16_SHIFT)) & RGPIO_PDDR_PDD16_MASK) + +#define RGPIO_PDDR_PDD17_MASK (0x20000U) +#define RGPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD17_SHIFT)) & RGPIO_PDDR_PDD17_MASK) + +#define RGPIO_PDDR_PDD18_MASK (0x40000U) +#define RGPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD18_SHIFT)) & RGPIO_PDDR_PDD18_MASK) + +#define RGPIO_PDDR_PDD19_MASK (0x80000U) +#define RGPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD19_SHIFT)) & RGPIO_PDDR_PDD19_MASK) + +#define RGPIO_PDDR_PDD20_MASK (0x100000U) +#define RGPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD20_SHIFT)) & RGPIO_PDDR_PDD20_MASK) + +#define RGPIO_PDDR_PDD21_MASK (0x200000U) +#define RGPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD21_SHIFT)) & RGPIO_PDDR_PDD21_MASK) + +#define RGPIO_PDDR_PDD22_MASK (0x400000U) +#define RGPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD22_SHIFT)) & RGPIO_PDDR_PDD22_MASK) + +#define RGPIO_PDDR_PDD23_MASK (0x800000U) +#define RGPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD23_SHIFT)) & RGPIO_PDDR_PDD23_MASK) + +#define RGPIO_PDDR_PDD24_MASK (0x1000000U) +#define RGPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD24_SHIFT)) & RGPIO_PDDR_PDD24_MASK) + +#define RGPIO_PDDR_PDD25_MASK (0x2000000U) +#define RGPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD25_SHIFT)) & RGPIO_PDDR_PDD25_MASK) + +#define RGPIO_PDDR_PDD26_MASK (0x4000000U) +#define RGPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD26_SHIFT)) & RGPIO_PDDR_PDD26_MASK) + +#define RGPIO_PDDR_PDD27_MASK (0x8000000U) +#define RGPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD27_SHIFT)) & RGPIO_PDDR_PDD27_MASK) + +#define RGPIO_PDDR_PDD28_MASK (0x10000000U) +#define RGPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD28_SHIFT)) & RGPIO_PDDR_PDD28_MASK) + +#define RGPIO_PDDR_PDD29_MASK (0x20000000U) +#define RGPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD29_SHIFT)) & RGPIO_PDDR_PDD29_MASK) + +#define RGPIO_PDDR_PDD30_MASK (0x40000000U) +#define RGPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD30_SHIFT)) & RGPIO_PDDR_PDD30_MASK) + +#define RGPIO_PDDR_PDD31_MASK (0x80000000U) +#define RGPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD31_SHIFT)) & RGPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define RGPIO_PIDR_PID0_MASK (0x1U) +#define RGPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID0_SHIFT)) & RGPIO_PIDR_PID0_MASK) + +#define RGPIO_PIDR_PID1_MASK (0x2U) +#define RGPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID1_SHIFT)) & RGPIO_PIDR_PID1_MASK) + +#define RGPIO_PIDR_PID2_MASK (0x4U) +#define RGPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID2_SHIFT)) & RGPIO_PIDR_PID2_MASK) + +#define RGPIO_PIDR_PID3_MASK (0x8U) +#define RGPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID3_SHIFT)) & RGPIO_PIDR_PID3_MASK) + +#define RGPIO_PIDR_PID4_MASK (0x10U) +#define RGPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID4_SHIFT)) & RGPIO_PIDR_PID4_MASK) + +#define RGPIO_PIDR_PID5_MASK (0x20U) +#define RGPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID5_SHIFT)) & RGPIO_PIDR_PID5_MASK) + +#define RGPIO_PIDR_PID6_MASK (0x40U) +#define RGPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID6_SHIFT)) & RGPIO_PIDR_PID6_MASK) + +#define RGPIO_PIDR_PID7_MASK (0x80U) +#define RGPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID7_SHIFT)) & RGPIO_PIDR_PID7_MASK) + +#define RGPIO_PIDR_PID8_MASK (0x100U) +#define RGPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID8_SHIFT)) & RGPIO_PIDR_PID8_MASK) + +#define RGPIO_PIDR_PID9_MASK (0x200U) +#define RGPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID9_SHIFT)) & RGPIO_PIDR_PID9_MASK) + +#define RGPIO_PIDR_PID10_MASK (0x400U) +#define RGPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID10_SHIFT)) & RGPIO_PIDR_PID10_MASK) + +#define RGPIO_PIDR_PID11_MASK (0x800U) +#define RGPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID11_SHIFT)) & RGPIO_PIDR_PID11_MASK) + +#define RGPIO_PIDR_PID12_MASK (0x1000U) +#define RGPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID12_SHIFT)) & RGPIO_PIDR_PID12_MASK) + +#define RGPIO_PIDR_PID13_MASK (0x2000U) +#define RGPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID13_SHIFT)) & RGPIO_PIDR_PID13_MASK) + +#define RGPIO_PIDR_PID14_MASK (0x4000U) +#define RGPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID14_SHIFT)) & RGPIO_PIDR_PID14_MASK) + +#define RGPIO_PIDR_PID15_MASK (0x8000U) +#define RGPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID15_SHIFT)) & RGPIO_PIDR_PID15_MASK) + +#define RGPIO_PIDR_PID16_MASK (0x10000U) +#define RGPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID16_SHIFT)) & RGPIO_PIDR_PID16_MASK) + +#define RGPIO_PIDR_PID17_MASK (0x20000U) +#define RGPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID17_SHIFT)) & RGPIO_PIDR_PID17_MASK) + +#define RGPIO_PIDR_PID18_MASK (0x40000U) +#define RGPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID18_SHIFT)) & RGPIO_PIDR_PID18_MASK) + +#define RGPIO_PIDR_PID19_MASK (0x80000U) +#define RGPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID19_SHIFT)) & RGPIO_PIDR_PID19_MASK) + +#define RGPIO_PIDR_PID20_MASK (0x100000U) +#define RGPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID20_SHIFT)) & RGPIO_PIDR_PID20_MASK) + +#define RGPIO_PIDR_PID21_MASK (0x200000U) +#define RGPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID21_SHIFT)) & RGPIO_PIDR_PID21_MASK) + +#define RGPIO_PIDR_PID22_MASK (0x400000U) +#define RGPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID22_SHIFT)) & RGPIO_PIDR_PID22_MASK) + +#define RGPIO_PIDR_PID23_MASK (0x800000U) +#define RGPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID23_SHIFT)) & RGPIO_PIDR_PID23_MASK) + +#define RGPIO_PIDR_PID24_MASK (0x1000000U) +#define RGPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID24_SHIFT)) & RGPIO_PIDR_PID24_MASK) + +#define RGPIO_PIDR_PID25_MASK (0x2000000U) +#define RGPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID25_SHIFT)) & RGPIO_PIDR_PID25_MASK) + +#define RGPIO_PIDR_PID26_MASK (0x4000000U) +#define RGPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID26_SHIFT)) & RGPIO_PIDR_PID26_MASK) + +#define RGPIO_PIDR_PID27_MASK (0x8000000U) +#define RGPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID27_SHIFT)) & RGPIO_PIDR_PID27_MASK) + +#define RGPIO_PIDR_PID28_MASK (0x10000000U) +#define RGPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID28_SHIFT)) & RGPIO_PIDR_PID28_MASK) + +#define RGPIO_PIDR_PID29_MASK (0x20000000U) +#define RGPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID29_SHIFT)) & RGPIO_PIDR_PID29_MASK) + +#define RGPIO_PIDR_PID30_MASK (0x40000000U) +#define RGPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID30_SHIFT)) & RGPIO_PIDR_PID30_MASK) + +#define RGPIO_PIDR_PID31_MASK (0x80000000U) +#define RGPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID31_SHIFT)) & RGPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define RGPIO_PDR_PD_MASK (0x1U) +#define RGPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define RGPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << RGPIO_PDR_PD_SHIFT)) & RGPIO_PDR_PD_MASK) +/*! @} */ + +/* The count of RGPIO_PDR */ +#define RGPIO_PDR_COUNT (32U) + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define RGPIO_ICR_IRQC_MASK (0xF0000U) +#define RGPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Reserved + * 0b1110..Reserved + * 0b1111..Reserved + */ +#define RGPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQC_SHIFT)) & RGPIO_ICR_IRQC_MASK) + +#define RGPIO_ICR_IRQS_MASK (0x100000U) +#define RGPIO_ICR_IRQS_SHIFT (20U) +/*! IRQS - Interrupt Select + * 0b0..Interrupt, or DMA request 0 + * 0b1..Interrupt, or DMA request 1 + */ +#define RGPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQS_SHIFT)) & RGPIO_ICR_IRQS_MASK) + +#define RGPIO_ICR_LK_MASK (0x800000U) +#define RGPIO_ICR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Not locked + * 0b1..Locked + */ +#define RGPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_LK_SHIFT)) & RGPIO_ICR_LK_MASK) + +#define RGPIO_ICR_ISF_MASK (0x1000000U) +#define RGPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_ISF_SHIFT)) & RGPIO_ICR_ISF_MASK) +/*! @} */ + +/* The count of RGPIO_ICR */ +#define RGPIO_ICR_COUNT (32U) + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define RGPIO_GICLR_GIWE0_MASK (0x1U) +#define RGPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE0_SHIFT)) & RGPIO_GICLR_GIWE0_MASK) + +#define RGPIO_GICLR_GIWE1_MASK (0x2U) +#define RGPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE1_SHIFT)) & RGPIO_GICLR_GIWE1_MASK) + +#define RGPIO_GICLR_GIWE2_MASK (0x4U) +#define RGPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE2_SHIFT)) & RGPIO_GICLR_GIWE2_MASK) + +#define RGPIO_GICLR_GIWE3_MASK (0x8U) +#define RGPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE3_SHIFT)) & RGPIO_GICLR_GIWE3_MASK) + +#define RGPIO_GICLR_GIWE4_MASK (0x10U) +#define RGPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE4_SHIFT)) & RGPIO_GICLR_GIWE4_MASK) + +#define RGPIO_GICLR_GIWE5_MASK (0x20U) +#define RGPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE5_SHIFT)) & RGPIO_GICLR_GIWE5_MASK) + +#define RGPIO_GICLR_GIWE6_MASK (0x40U) +#define RGPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE6_SHIFT)) & RGPIO_GICLR_GIWE6_MASK) + +#define RGPIO_GICLR_GIWE7_MASK (0x80U) +#define RGPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE7_SHIFT)) & RGPIO_GICLR_GIWE7_MASK) + +#define RGPIO_GICLR_GIWE8_MASK (0x100U) +#define RGPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE8_SHIFT)) & RGPIO_GICLR_GIWE8_MASK) + +#define RGPIO_GICLR_GIWE9_MASK (0x200U) +#define RGPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE9_SHIFT)) & RGPIO_GICLR_GIWE9_MASK) + +#define RGPIO_GICLR_GIWE10_MASK (0x400U) +#define RGPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE10_SHIFT)) & RGPIO_GICLR_GIWE10_MASK) + +#define RGPIO_GICLR_GIWE11_MASK (0x800U) +#define RGPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE11_SHIFT)) & RGPIO_GICLR_GIWE11_MASK) + +#define RGPIO_GICLR_GIWE12_MASK (0x1000U) +#define RGPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE12_SHIFT)) & RGPIO_GICLR_GIWE12_MASK) + +#define RGPIO_GICLR_GIWE13_MASK (0x2000U) +#define RGPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE13_SHIFT)) & RGPIO_GICLR_GIWE13_MASK) + +#define RGPIO_GICLR_GIWE14_MASK (0x4000U) +#define RGPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE14_SHIFT)) & RGPIO_GICLR_GIWE14_MASK) + +#define RGPIO_GICLR_GIWE15_MASK (0x8000U) +#define RGPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE15_SHIFT)) & RGPIO_GICLR_GIWE15_MASK) + +#define RGPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define RGPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define RGPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWD_SHIFT)) & RGPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define RGPIO_GICHR_GIWE16_MASK (0x1U) +#define RGPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE16_SHIFT)) & RGPIO_GICHR_GIWE16_MASK) + +#define RGPIO_GICHR_GIWE17_MASK (0x2U) +#define RGPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE17_SHIFT)) & RGPIO_GICHR_GIWE17_MASK) + +#define RGPIO_GICHR_GIWE18_MASK (0x4U) +#define RGPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE18_SHIFT)) & RGPIO_GICHR_GIWE18_MASK) + +#define RGPIO_GICHR_GIWE19_MASK (0x8U) +#define RGPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE19_SHIFT)) & RGPIO_GICHR_GIWE19_MASK) + +#define RGPIO_GICHR_GIWE20_MASK (0x10U) +#define RGPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE20_SHIFT)) & RGPIO_GICHR_GIWE20_MASK) + +#define RGPIO_GICHR_GIWE21_MASK (0x20U) +#define RGPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE21_SHIFT)) & RGPIO_GICHR_GIWE21_MASK) + +#define RGPIO_GICHR_GIWE22_MASK (0x40U) +#define RGPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE22_SHIFT)) & RGPIO_GICHR_GIWE22_MASK) + +#define RGPIO_GICHR_GIWE23_MASK (0x80U) +#define RGPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE23_SHIFT)) & RGPIO_GICHR_GIWE23_MASK) + +#define RGPIO_GICHR_GIWE24_MASK (0x100U) +#define RGPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE24_SHIFT)) & RGPIO_GICHR_GIWE24_MASK) + +#define RGPIO_GICHR_GIWE25_MASK (0x200U) +#define RGPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE25_SHIFT)) & RGPIO_GICHR_GIWE25_MASK) + +#define RGPIO_GICHR_GIWE26_MASK (0x400U) +#define RGPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE26_SHIFT)) & RGPIO_GICHR_GIWE26_MASK) + +#define RGPIO_GICHR_GIWE27_MASK (0x800U) +#define RGPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE27_SHIFT)) & RGPIO_GICHR_GIWE27_MASK) + +#define RGPIO_GICHR_GIWE28_MASK (0x1000U) +#define RGPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE28_SHIFT)) & RGPIO_GICHR_GIWE28_MASK) + +#define RGPIO_GICHR_GIWE29_MASK (0x2000U) +#define RGPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE29_SHIFT)) & RGPIO_GICHR_GIWE29_MASK) + +#define RGPIO_GICHR_GIWE30_MASK (0x4000U) +#define RGPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE30_SHIFT)) & RGPIO_GICHR_GIWE30_MASK) + +#define RGPIO_GICHR_GIWE31_MASK (0x8000U) +#define RGPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE31_SHIFT)) & RGPIO_GICHR_GIWE31_MASK) + +#define RGPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define RGPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define RGPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWD_SHIFT)) & RGPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define RGPIO_ISFR_ISF0_MASK (0x1U) +#define RGPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF0_SHIFT)) & RGPIO_ISFR_ISF0_MASK) + +#define RGPIO_ISFR_ISF1_MASK (0x2U) +#define RGPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF1_SHIFT)) & RGPIO_ISFR_ISF1_MASK) + +#define RGPIO_ISFR_ISF2_MASK (0x4U) +#define RGPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF2_SHIFT)) & RGPIO_ISFR_ISF2_MASK) + +#define RGPIO_ISFR_ISF3_MASK (0x8U) +#define RGPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF3_SHIFT)) & RGPIO_ISFR_ISF3_MASK) + +#define RGPIO_ISFR_ISF4_MASK (0x10U) +#define RGPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF4_SHIFT)) & RGPIO_ISFR_ISF4_MASK) + +#define RGPIO_ISFR_ISF5_MASK (0x20U) +#define RGPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF5_SHIFT)) & RGPIO_ISFR_ISF5_MASK) + +#define RGPIO_ISFR_ISF6_MASK (0x40U) +#define RGPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF6_SHIFT)) & RGPIO_ISFR_ISF6_MASK) + +#define RGPIO_ISFR_ISF7_MASK (0x80U) +#define RGPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF7_SHIFT)) & RGPIO_ISFR_ISF7_MASK) + +#define RGPIO_ISFR_ISF8_MASK (0x100U) +#define RGPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF8_SHIFT)) & RGPIO_ISFR_ISF8_MASK) + +#define RGPIO_ISFR_ISF9_MASK (0x200U) +#define RGPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF9_SHIFT)) & RGPIO_ISFR_ISF9_MASK) + +#define RGPIO_ISFR_ISF10_MASK (0x400U) +#define RGPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF10_SHIFT)) & RGPIO_ISFR_ISF10_MASK) + +#define RGPIO_ISFR_ISF11_MASK (0x800U) +#define RGPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF11_SHIFT)) & RGPIO_ISFR_ISF11_MASK) + +#define RGPIO_ISFR_ISF12_MASK (0x1000U) +#define RGPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF12_SHIFT)) & RGPIO_ISFR_ISF12_MASK) + +#define RGPIO_ISFR_ISF13_MASK (0x2000U) +#define RGPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF13_SHIFT)) & RGPIO_ISFR_ISF13_MASK) + +#define RGPIO_ISFR_ISF14_MASK (0x4000U) +#define RGPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF14_SHIFT)) & RGPIO_ISFR_ISF14_MASK) + +#define RGPIO_ISFR_ISF15_MASK (0x8000U) +#define RGPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF15_SHIFT)) & RGPIO_ISFR_ISF15_MASK) + +#define RGPIO_ISFR_ISF16_MASK (0x10000U) +#define RGPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF16_SHIFT)) & RGPIO_ISFR_ISF16_MASK) + +#define RGPIO_ISFR_ISF17_MASK (0x20000U) +#define RGPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF17_SHIFT)) & RGPIO_ISFR_ISF17_MASK) + +#define RGPIO_ISFR_ISF18_MASK (0x40000U) +#define RGPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF18_SHIFT)) & RGPIO_ISFR_ISF18_MASK) + +#define RGPIO_ISFR_ISF19_MASK (0x80000U) +#define RGPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF19_SHIFT)) & RGPIO_ISFR_ISF19_MASK) + +#define RGPIO_ISFR_ISF20_MASK (0x100000U) +#define RGPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF20_SHIFT)) & RGPIO_ISFR_ISF20_MASK) + +#define RGPIO_ISFR_ISF21_MASK (0x200000U) +#define RGPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF21_SHIFT)) & RGPIO_ISFR_ISF21_MASK) + +#define RGPIO_ISFR_ISF22_MASK (0x400000U) +#define RGPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF22_SHIFT)) & RGPIO_ISFR_ISF22_MASK) + +#define RGPIO_ISFR_ISF23_MASK (0x800000U) +#define RGPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF23_SHIFT)) & RGPIO_ISFR_ISF23_MASK) + +#define RGPIO_ISFR_ISF24_MASK (0x1000000U) +#define RGPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF24_SHIFT)) & RGPIO_ISFR_ISF24_MASK) + +#define RGPIO_ISFR_ISF25_MASK (0x2000000U) +#define RGPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF25_SHIFT)) & RGPIO_ISFR_ISF25_MASK) + +#define RGPIO_ISFR_ISF26_MASK (0x4000000U) +#define RGPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF26_SHIFT)) & RGPIO_ISFR_ISF26_MASK) + +#define RGPIO_ISFR_ISF27_MASK (0x8000000U) +#define RGPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF27_SHIFT)) & RGPIO_ISFR_ISF27_MASK) + +#define RGPIO_ISFR_ISF28_MASK (0x10000000U) +#define RGPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF28_SHIFT)) & RGPIO_ISFR_ISF28_MASK) + +#define RGPIO_ISFR_ISF29_MASK (0x20000000U) +#define RGPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF29_SHIFT)) & RGPIO_ISFR_ISF29_MASK) + +#define RGPIO_ISFR_ISF30_MASK (0x40000000U) +#define RGPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF30_SHIFT)) & RGPIO_ISFR_ISF30_MASK) + +#define RGPIO_ISFR_ISF31_MASK (0x80000000U) +#define RGPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF31_SHIFT)) & RGPIO_ISFR_ISF31_MASK) +/*! @} */ + +/* The count of RGPIO_ISFR */ +#define RGPIO_ISFR_COUNT (2U) + + +/*! + * @} + */ /* end of group RGPIO_Register_Masks */ + + +/* RGPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x47400000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((RGPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x43810000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((RGPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x43820000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((RGPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x43830000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((RGPIO_Type *)GPIO4_BASE) +/** Array initializer of RGPIO peripheral base addresses */ +#define RGPIO_BASE_ADDRS { GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of RGPIO peripheral base pointers */ +#define RGPIO_BASE_PTRS { GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the RGPIO peripheral type */ +#define RGPIO_IRQS { GPIO1_0_IRQn, GPIO2_0_IRQn, GPIO3_0_IRQn, GPIO4_0_IRQn } + +/*! + * @} + */ /* end of group RGPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SEMA42 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer + * @{ + */ + +/** SEMA42 - Register Layout Typedef */ +typedef struct { + __IO uint8_t GATE3; /**< Gate, offset: 0x0 */ + __IO uint8_t GATE2; /**< Gate, offset: 0x1 */ + __IO uint8_t GATE1; /**< Gate, offset: 0x2 */ + __IO uint8_t GATE0; /**< Gate, offset: 0x3 */ + __IO uint8_t GATE7; /**< Gate, offset: 0x4 */ + __IO uint8_t GATE6; /**< Gate, offset: 0x5 */ + __IO uint8_t GATE5; /**< Gate, offset: 0x6 */ + __IO uint8_t GATE4; /**< Gate, offset: 0x7 */ + __IO uint8_t GATE11; /**< Gate, offset: 0x8 */ + __IO uint8_t GATE10; /**< Gate, offset: 0x9 */ + __IO uint8_t GATE9; /**< Gate, offset: 0xA */ + __IO uint8_t GATE8; /**< Gate, offset: 0xB */ + __IO uint8_t GATE15; /**< Gate, offset: 0xC */ + __IO uint8_t GATE14; /**< Gate, offset: 0xD */ + __IO uint8_t GATE13; /**< Gate, offset: 0xE */ + __IO uint8_t GATE12; /**< Gate, offset: 0xF */ + __IO uint8_t GATE19; /**< Gate, offset: 0x10 */ + __IO uint8_t GATE18; /**< Gate, offset: 0x11 */ + __IO uint8_t GATE17; /**< Gate, offset: 0x12 */ + __IO uint8_t GATE16; /**< Gate, offset: 0x13 */ + __IO uint8_t GATE23; /**< Gate, offset: 0x14 */ + __IO uint8_t GATE22; /**< Gate, offset: 0x15 */ + __IO uint8_t GATE21; /**< Gate, offset: 0x16 */ + __IO uint8_t GATE20; /**< Gate, offset: 0x17 */ + __IO uint8_t GATE27; /**< Gate, offset: 0x18 */ + __IO uint8_t GATE26; /**< Gate, offset: 0x19 */ + __IO uint8_t GATE25; /**< Gate, offset: 0x1A */ + __IO uint8_t GATE24; /**< Gate, offset: 0x1B */ + __IO uint8_t GATE31; /**< Gate, offset: 0x1C */ + __IO uint8_t GATE30; /**< Gate, offset: 0x1D */ + __IO uint8_t GATE29; /**< Gate, offset: 0x1E */ + __IO uint8_t GATE28; /**< Gate, offset: 0x1F */ + __IO uint8_t GATE35; /**< Gate, offset: 0x20 */ + __IO uint8_t GATE34; /**< Gate, offset: 0x21 */ + __IO uint8_t GATE33; /**< Gate, offset: 0x22 */ + __IO uint8_t GATE32; /**< Gate, offset: 0x23 */ + __IO uint8_t GATE39; /**< Gate, offset: 0x24 */ + __IO uint8_t GATE38; /**< Gate, offset: 0x25 */ + __IO uint8_t GATE37; /**< Gate, offset: 0x26 */ + __IO uint8_t GATE36; /**< Gate, offset: 0x27 */ + __IO uint8_t GATE43; /**< Gate, offset: 0x28 */ + __IO uint8_t GATE42; /**< Gate, offset: 0x29 */ + __IO uint8_t GATE41; /**< Gate, offset: 0x2A */ + __IO uint8_t GATE40; /**< Gate, offset: 0x2B */ + __IO uint8_t GATE47; /**< Gate, offset: 0x2C */ + __IO uint8_t GATE46; /**< Gate, offset: 0x2D */ + __IO uint8_t GATE45; /**< Gate, offset: 0x2E */ + __IO uint8_t GATE44; /**< Gate, offset: 0x2F */ + __IO uint8_t GATE51; /**< Gate, offset: 0x30 */ + __IO uint8_t GATE50; /**< Gate, offset: 0x31 */ + __IO uint8_t GATE49; /**< Gate, offset: 0x32 */ + __IO uint8_t GATE48; /**< Gate, offset: 0x33 */ + __IO uint8_t GATE55; /**< Gate, offset: 0x34 */ + __IO uint8_t GATE54; /**< Gate, offset: 0x35 */ + __IO uint8_t GATE53; /**< Gate, offset: 0x36 */ + __IO uint8_t GATE52; /**< Gate, offset: 0x37 */ + __IO uint8_t GATE59; /**< Gate, offset: 0x38 */ + __IO uint8_t GATE58; /**< Gate, offset: 0x39 */ + __IO uint8_t GATE57; /**< Gate, offset: 0x3A */ + __IO uint8_t GATE56; /**< Gate, offset: 0x3B */ + __IO uint8_t GATE63; /**< Gate, offset: 0x3C */ + __IO uint8_t GATE62; /**< Gate, offset: 0x3D */ + __IO uint8_t GATE61; /**< Gate, offset: 0x3E */ + __IO uint8_t GATE60; /**< Gate, offset: 0x3F */ + uint8_t RESERVED_0[2]; + union { /* offset: 0x42 */ + __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ + __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ + }; +} SEMA42_Type; + +/* ---------------------------------------------------------------------------- + -- SEMA42 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks + * @{ + */ + +/*! @name GATE3 - Gate */ +/*! @{ */ + +#define SEMA42_GATE3_GTFSM_MASK (0xFU) +#define SEMA42_GATE3_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) +/*! @} */ + +/*! @name GATE2 - Gate */ +/*! @{ */ + +#define SEMA42_GATE2_GTFSM_MASK (0xFU) +#define SEMA42_GATE2_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) +/*! @} */ + +/*! @name GATE1 - Gate */ +/*! @{ */ + +#define SEMA42_GATE1_GTFSM_MASK (0xFU) +#define SEMA42_GATE1_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) +/*! @} */ + +/*! @name GATE0 - Gate */ +/*! @{ */ + +#define SEMA42_GATE0_GTFSM_MASK (0xFU) +#define SEMA42_GATE0_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) +/*! @} */ + +/*! @name GATE7 - Gate */ +/*! @{ */ + +#define SEMA42_GATE7_GTFSM_MASK (0xFU) +#define SEMA42_GATE7_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) +/*! @} */ + +/*! @name GATE6 - Gate */ +/*! @{ */ + +#define SEMA42_GATE6_GTFSM_MASK (0xFU) +#define SEMA42_GATE6_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) +/*! @} */ + +/*! @name GATE5 - Gate */ +/*! @{ */ + +#define SEMA42_GATE5_GTFSM_MASK (0xFU) +#define SEMA42_GATE5_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) +/*! @} */ + +/*! @name GATE4 - Gate */ +/*! @{ */ + +#define SEMA42_GATE4_GTFSM_MASK (0xFU) +#define SEMA42_GATE4_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) +/*! @} */ + +/*! @name GATE11 - Gate */ +/*! @{ */ + +#define SEMA42_GATE11_GTFSM_MASK (0xFU) +#define SEMA42_GATE11_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) +/*! @} */ + +/*! @name GATE10 - Gate */ +/*! @{ */ + +#define SEMA42_GATE10_GTFSM_MASK (0xFU) +#define SEMA42_GATE10_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) +/*! @} */ + +/*! @name GATE9 - Gate */ +/*! @{ */ + +#define SEMA42_GATE9_GTFSM_MASK (0xFU) +#define SEMA42_GATE9_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) +/*! @} */ + +/*! @name GATE8 - Gate */ +/*! @{ */ + +#define SEMA42_GATE8_GTFSM_MASK (0xFU) +#define SEMA42_GATE8_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) +/*! @} */ + +/*! @name GATE15 - Gate */ +/*! @{ */ + +#define SEMA42_GATE15_GTFSM_MASK (0xFU) +#define SEMA42_GATE15_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) +/*! @} */ + +/*! @name GATE14 - Gate */ +/*! @{ */ + +#define SEMA42_GATE14_GTFSM_MASK (0xFU) +#define SEMA42_GATE14_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) +/*! @} */ + +/*! @name GATE13 - Gate */ +/*! @{ */ + +#define SEMA42_GATE13_GTFSM_MASK (0xFU) +#define SEMA42_GATE13_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) +/*! @} */ + +/*! @name GATE12 - Gate */ +/*! @{ */ + +#define SEMA42_GATE12_GTFSM_MASK (0xFU) +#define SEMA42_GATE12_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) +/*! @} */ + +/*! @name GATE19 - Gate */ +/*! @{ */ + +#define SEMA42_GATE19_GTFSM_MASK (0xFU) +#define SEMA42_GATE19_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE19_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE19_GTFSM_SHIFT)) & SEMA42_GATE19_GTFSM_MASK) +/*! @} */ + +/*! @name GATE18 - Gate */ +/*! @{ */ + +#define SEMA42_GATE18_GTFSM_MASK (0xFU) +#define SEMA42_GATE18_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE18_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE18_GTFSM_SHIFT)) & SEMA42_GATE18_GTFSM_MASK) +/*! @} */ + +/*! @name GATE17 - Gate */ +/*! @{ */ + +#define SEMA42_GATE17_GTFSM_MASK (0xFU) +#define SEMA42_GATE17_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE17_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE17_GTFSM_SHIFT)) & SEMA42_GATE17_GTFSM_MASK) +/*! @} */ + +/*! @name GATE16 - Gate */ +/*! @{ */ + +#define SEMA42_GATE16_GTFSM_MASK (0xFU) +#define SEMA42_GATE16_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE16_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE16_GTFSM_SHIFT)) & SEMA42_GATE16_GTFSM_MASK) +/*! @} */ + +/*! @name GATE23 - Gate */ +/*! @{ */ + +#define SEMA42_GATE23_GTFSM_MASK (0xFU) +#define SEMA42_GATE23_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE23_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE23_GTFSM_SHIFT)) & SEMA42_GATE23_GTFSM_MASK) +/*! @} */ + +/*! @name GATE22 - Gate */ +/*! @{ */ + +#define SEMA42_GATE22_GTFSM_MASK (0xFU) +#define SEMA42_GATE22_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE22_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE22_GTFSM_SHIFT)) & SEMA42_GATE22_GTFSM_MASK) +/*! @} */ + +/*! @name GATE21 - Gate */ +/*! @{ */ + +#define SEMA42_GATE21_GTFSM_MASK (0xFU) +#define SEMA42_GATE21_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE21_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE21_GTFSM_SHIFT)) & SEMA42_GATE21_GTFSM_MASK) +/*! @} */ + +/*! @name GATE20 - Gate */ +/*! @{ */ + +#define SEMA42_GATE20_GTFSM_MASK (0xFU) +#define SEMA42_GATE20_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE20_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE20_GTFSM_SHIFT)) & SEMA42_GATE20_GTFSM_MASK) +/*! @} */ + +/*! @name GATE27 - Gate */ +/*! @{ */ + +#define SEMA42_GATE27_GTFSM_MASK (0xFU) +#define SEMA42_GATE27_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE27_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE27_GTFSM_SHIFT)) & SEMA42_GATE27_GTFSM_MASK) +/*! @} */ + +/*! @name GATE26 - Gate */ +/*! @{ */ + +#define SEMA42_GATE26_GTFSM_MASK (0xFU) +#define SEMA42_GATE26_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE26_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE26_GTFSM_SHIFT)) & SEMA42_GATE26_GTFSM_MASK) +/*! @} */ + +/*! @name GATE25 - Gate */ +/*! @{ */ + +#define SEMA42_GATE25_GTFSM_MASK (0xFU) +#define SEMA42_GATE25_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE25_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE25_GTFSM_SHIFT)) & SEMA42_GATE25_GTFSM_MASK) +/*! @} */ + +/*! @name GATE24 - Gate */ +/*! @{ */ + +#define SEMA42_GATE24_GTFSM_MASK (0xFU) +#define SEMA42_GATE24_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE24_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE24_GTFSM_SHIFT)) & SEMA42_GATE24_GTFSM_MASK) +/*! @} */ + +/*! @name GATE31 - Gate */ +/*! @{ */ + +#define SEMA42_GATE31_GTFSM_MASK (0xFU) +#define SEMA42_GATE31_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE31_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE31_GTFSM_SHIFT)) & SEMA42_GATE31_GTFSM_MASK) +/*! @} */ + +/*! @name GATE30 - Gate */ +/*! @{ */ + +#define SEMA42_GATE30_GTFSM_MASK (0xFU) +#define SEMA42_GATE30_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE30_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE30_GTFSM_SHIFT)) & SEMA42_GATE30_GTFSM_MASK) +/*! @} */ + +/*! @name GATE29 - Gate */ +/*! @{ */ + +#define SEMA42_GATE29_GTFSM_MASK (0xFU) +#define SEMA42_GATE29_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE29_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE29_GTFSM_SHIFT)) & SEMA42_GATE29_GTFSM_MASK) +/*! @} */ + +/*! @name GATE28 - Gate */ +/*! @{ */ + +#define SEMA42_GATE28_GTFSM_MASK (0xFU) +#define SEMA42_GATE28_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE28_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE28_GTFSM_SHIFT)) & SEMA42_GATE28_GTFSM_MASK) +/*! @} */ + +/*! @name GATE35 - Gate */ +/*! @{ */ + +#define SEMA42_GATE35_GTFSM_MASK (0xFU) +#define SEMA42_GATE35_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE35_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE35_GTFSM_SHIFT)) & SEMA42_GATE35_GTFSM_MASK) +/*! @} */ + +/*! @name GATE34 - Gate */ +/*! @{ */ + +#define SEMA42_GATE34_GTFSM_MASK (0xFU) +#define SEMA42_GATE34_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE34_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE34_GTFSM_SHIFT)) & SEMA42_GATE34_GTFSM_MASK) +/*! @} */ + +/*! @name GATE33 - Gate */ +/*! @{ */ + +#define SEMA42_GATE33_GTFSM_MASK (0xFU) +#define SEMA42_GATE33_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE33_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE33_GTFSM_SHIFT)) & SEMA42_GATE33_GTFSM_MASK) +/*! @} */ + +/*! @name GATE32 - Gate */ +/*! @{ */ + +#define SEMA42_GATE32_GTFSM_MASK (0xFU) +#define SEMA42_GATE32_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE32_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE32_GTFSM_SHIFT)) & SEMA42_GATE32_GTFSM_MASK) +/*! @} */ + +/*! @name GATE39 - Gate */ +/*! @{ */ + +#define SEMA42_GATE39_GTFSM_MASK (0xFU) +#define SEMA42_GATE39_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE39_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE39_GTFSM_SHIFT)) & SEMA42_GATE39_GTFSM_MASK) +/*! @} */ + +/*! @name GATE38 - Gate */ +/*! @{ */ + +#define SEMA42_GATE38_GTFSM_MASK (0xFU) +#define SEMA42_GATE38_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE38_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE38_GTFSM_SHIFT)) & SEMA42_GATE38_GTFSM_MASK) +/*! @} */ + +/*! @name GATE37 - Gate */ +/*! @{ */ + +#define SEMA42_GATE37_GTFSM_MASK (0xFU) +#define SEMA42_GATE37_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE37_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE37_GTFSM_SHIFT)) & SEMA42_GATE37_GTFSM_MASK) +/*! @} */ + +/*! @name GATE36 - Gate */ +/*! @{ */ + +#define SEMA42_GATE36_GTFSM_MASK (0xFU) +#define SEMA42_GATE36_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE36_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE36_GTFSM_SHIFT)) & SEMA42_GATE36_GTFSM_MASK) +/*! @} */ + +/*! @name GATE43 - Gate */ +/*! @{ */ + +#define SEMA42_GATE43_GTFSM_MASK (0xFU) +#define SEMA42_GATE43_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE43_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE43_GTFSM_SHIFT)) & SEMA42_GATE43_GTFSM_MASK) +/*! @} */ + +/*! @name GATE42 - Gate */ +/*! @{ */ + +#define SEMA42_GATE42_GTFSM_MASK (0xFU) +#define SEMA42_GATE42_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE42_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE42_GTFSM_SHIFT)) & SEMA42_GATE42_GTFSM_MASK) +/*! @} */ + +/*! @name GATE41 - Gate */ +/*! @{ */ + +#define SEMA42_GATE41_GTFSM_MASK (0xFU) +#define SEMA42_GATE41_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE41_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE41_GTFSM_SHIFT)) & SEMA42_GATE41_GTFSM_MASK) +/*! @} */ + +/*! @name GATE40 - Gate */ +/*! @{ */ + +#define SEMA42_GATE40_GTFSM_MASK (0xFU) +#define SEMA42_GATE40_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE40_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE40_GTFSM_SHIFT)) & SEMA42_GATE40_GTFSM_MASK) +/*! @} */ + +/*! @name GATE47 - Gate */ +/*! @{ */ + +#define SEMA42_GATE47_GTFSM_MASK (0xFU) +#define SEMA42_GATE47_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE47_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE47_GTFSM_SHIFT)) & SEMA42_GATE47_GTFSM_MASK) +/*! @} */ + +/*! @name GATE46 - Gate */ +/*! @{ */ + +#define SEMA42_GATE46_GTFSM_MASK (0xFU) +#define SEMA42_GATE46_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE46_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE46_GTFSM_SHIFT)) & SEMA42_GATE46_GTFSM_MASK) +/*! @} */ + +/*! @name GATE45 - Gate */ +/*! @{ */ + +#define SEMA42_GATE45_GTFSM_MASK (0xFU) +#define SEMA42_GATE45_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE45_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE45_GTFSM_SHIFT)) & SEMA42_GATE45_GTFSM_MASK) +/*! @} */ + +/*! @name GATE44 - Gate */ +/*! @{ */ + +#define SEMA42_GATE44_GTFSM_MASK (0xFU) +#define SEMA42_GATE44_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE44_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE44_GTFSM_SHIFT)) & SEMA42_GATE44_GTFSM_MASK) +/*! @} */ + +/*! @name GATE51 - Gate */ +/*! @{ */ + +#define SEMA42_GATE51_GTFSM_MASK (0xFU) +#define SEMA42_GATE51_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE51_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE51_GTFSM_SHIFT)) & SEMA42_GATE51_GTFSM_MASK) +/*! @} */ + +/*! @name GATE50 - Gate */ +/*! @{ */ + +#define SEMA42_GATE50_GTFSM_MASK (0xFU) +#define SEMA42_GATE50_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE50_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE50_GTFSM_SHIFT)) & SEMA42_GATE50_GTFSM_MASK) +/*! @} */ + +/*! @name GATE49 - Gate */ +/*! @{ */ + +#define SEMA42_GATE49_GTFSM_MASK (0xFU) +#define SEMA42_GATE49_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE49_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE49_GTFSM_SHIFT)) & SEMA42_GATE49_GTFSM_MASK) +/*! @} */ + +/*! @name GATE48 - Gate */ +/*! @{ */ + +#define SEMA42_GATE48_GTFSM_MASK (0xFU) +#define SEMA42_GATE48_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE48_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE48_GTFSM_SHIFT)) & SEMA42_GATE48_GTFSM_MASK) +/*! @} */ + +/*! @name GATE55 - Gate */ +/*! @{ */ + +#define SEMA42_GATE55_GTFSM_MASK (0xFU) +#define SEMA42_GATE55_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE55_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE55_GTFSM_SHIFT)) & SEMA42_GATE55_GTFSM_MASK) +/*! @} */ + +/*! @name GATE54 - Gate */ +/*! @{ */ + +#define SEMA42_GATE54_GTFSM_MASK (0xFU) +#define SEMA42_GATE54_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE54_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE54_GTFSM_SHIFT)) & SEMA42_GATE54_GTFSM_MASK) +/*! @} */ + +/*! @name GATE53 - Gate */ +/*! @{ */ + +#define SEMA42_GATE53_GTFSM_MASK (0xFU) +#define SEMA42_GATE53_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE53_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE53_GTFSM_SHIFT)) & SEMA42_GATE53_GTFSM_MASK) +/*! @} */ + +/*! @name GATE52 - Gate */ +/*! @{ */ + +#define SEMA42_GATE52_GTFSM_MASK (0xFU) +#define SEMA42_GATE52_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE52_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE52_GTFSM_SHIFT)) & SEMA42_GATE52_GTFSM_MASK) +/*! @} */ + +/*! @name GATE59 - Gate */ +/*! @{ */ + +#define SEMA42_GATE59_GTFSM_MASK (0xFU) +#define SEMA42_GATE59_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE59_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE59_GTFSM_SHIFT)) & SEMA42_GATE59_GTFSM_MASK) +/*! @} */ + +/*! @name GATE58 - Gate */ +/*! @{ */ + +#define SEMA42_GATE58_GTFSM_MASK (0xFU) +#define SEMA42_GATE58_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE58_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE58_GTFSM_SHIFT)) & SEMA42_GATE58_GTFSM_MASK) +/*! @} */ + +/*! @name GATE57 - Gate */ +/*! @{ */ + +#define SEMA42_GATE57_GTFSM_MASK (0xFU) +#define SEMA42_GATE57_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE57_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE57_GTFSM_SHIFT)) & SEMA42_GATE57_GTFSM_MASK) +/*! @} */ + +/*! @name GATE56 - Gate */ +/*! @{ */ + +#define SEMA42_GATE56_GTFSM_MASK (0xFU) +#define SEMA42_GATE56_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE56_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE56_GTFSM_SHIFT)) & SEMA42_GATE56_GTFSM_MASK) +/*! @} */ + +/*! @name GATE63 - Gate */ +/*! @{ */ + +#define SEMA42_GATE63_GTFSM_MASK (0xFU) +#define SEMA42_GATE63_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE63_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE63_GTFSM_SHIFT)) & SEMA42_GATE63_GTFSM_MASK) +/*! @} */ + +/*! @name GATE62 - Gate */ +/*! @{ */ + +#define SEMA42_GATE62_GTFSM_MASK (0xFU) +#define SEMA42_GATE62_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE62_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE62_GTFSM_SHIFT)) & SEMA42_GATE62_GTFSM_MASK) +/*! @} */ + +/*! @name GATE61 - Gate */ +/*! @{ */ + +#define SEMA42_GATE61_GTFSM_MASK (0xFU) +#define SEMA42_GATE61_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE61_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE61_GTFSM_SHIFT)) & SEMA42_GATE61_GTFSM_MASK) +/*! @} */ + +/*! @name GATE60 - Gate */ +/*! @{ */ + +#define SEMA42_GATE60_GTFSM_MASK (0xFU) +#define SEMA42_GATE60_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE60_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE60_GTFSM_SHIFT)) & SEMA42_GATE60_GTFSM_MASK) +/*! @} */ + +/*! @name RSTGT_R - Reset Gate Read */ +/*! @{ */ + +#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) +/*! RSTGTN - Reset Gate Number */ +#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) + +#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) +#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) +/*! RSTGMS - Reset Gate Domain */ +#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) + +#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) +#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) +/*! RSTGSM - Reset Gate Finite State Machine + * 0b00..Idle, waiting for the first data pattern write. + * 0b01..Waiting for the second data pattern write + * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, + * this machine returns to the idle (waiting for first data pattern write) state. + * 0b11..This state encoding is never used and therefore reserved. + */ +#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) +/*! @} */ + +/*! @name RSTGT_W - Reset Gate Write */ +/*! @{ */ + +#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) +/*! RSTGTN - Reset Gate Number */ +#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) + +#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) +#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) +/*! RSTGDP - Reset Gate Data Pattern */ +#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SEMA42_Register_Masks */ + + +/* SEMA42 - Peripheral instance base addresses */ +/** Peripheral SEMA42_1 base address */ +#define SEMA42_1_BASE (0x44260000u) +/** Peripheral SEMA42_1 base pointer */ +#define SEMA42_1 ((SEMA42_Type *)SEMA42_1_BASE) +/** Peripheral SEMA42_2 base address */ +#define SEMA42_2_BASE (0x42450000u) +/** Peripheral SEMA42_2 base pointer */ +#define SEMA42_2 ((SEMA42_Type *)SEMA42_2_BASE) +/** Array initializer of SEMA42 peripheral base addresses */ +#define SEMA42_BASE_ADDRS { 0u, SEMA42_1_BASE, SEMA42_2_BASE } +/** Array initializer of SEMA42 peripheral base pointers */ +#define SEMA42_BASE_PTRS { (SEMA42_Type *)0u, SEMA42_1, SEMA42_2 } + +/*! + * @} + */ /* end of group SEMA42_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t VERSION; /**< Version control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< External control register, offset: 0x10 */ + __IO uint32_t SET; /**< External control register, offset: 0x14 */ + __IO uint32_t CLR; /**< External control register, offset: 0x18 */ + __IO uint32_t TOG; /**< External control register, offset: 0x1C */ + } EXT_CTRL; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< External Status register, offset: 0x20 */ + __IO uint32_t SET; /**< External Status register, offset: 0x24 */ + __IO uint32_t CLR; /**< External Status register, offset: 0x28 */ + __IO uint32_t TOG; /**< External Status register, offset: 0x2C */ + } EXT_STATUS; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Interrupt enables for interrupt 0, offset: 0x30 */ + __IO uint32_t SET; /**< Interrupt enables for interrupt 0, offset: 0x34 */ + __IO uint32_t CLR; /**< Interrupt enables for interrupt 0, offset: 0x38 */ + __IO uint32_t TOG; /**< Interrupt enables for interrupt 0, offset: 0x3C */ + } EXT_IER0; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Interrupt enables for interrupt 1, offset: 0x40 */ + __IO uint32_t SET; /**< Interrupt enables for interrupt 1, offset: 0x44 */ + __IO uint32_t CLR; /**< Interrupt enables for interrupt 1, offset: 0x48 */ + __IO uint32_t TOG; /**< Interrupt enables for interrupt 1, offset: 0x4C */ + } EXT_IER1; + struct { /* offset: 0x50 */ + __IO uint32_t RW; /**< External Interrupt Status register, offset: 0x50 */ + __IO uint32_t SET; /**< External Interrupt Status register, offset: 0x54 */ + __IO uint32_t CLR; /**< External Interrupt Status register, offset: 0x58 */ + __IO uint32_t TOG; /**< External Interrupt Status register, offset: 0x5C */ + } EXT_ISR; + uint8_t RESERVED_1[72]; + __I uint32_t DPATH_STATUS; /**< Audio XCVR datapath status, offset: 0xA8 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CLK_CTRL; /**< Clock control register, offset: 0xB0 */ + uint8_t RESERVED_3[204]; + struct { /* offset: 0x180 */ + __IO uint32_t RW; /**< Data path control register, offset: 0x180 */ + __IO uint32_t SET; /**< Data path control register, offset: 0x184 */ + __IO uint32_t CLR; /**< Data path control register, offset: 0x188 */ + __IO uint32_t TOG; /**< Data path control register, offset: 0x18C */ + } RX_DATAPATH_CTRL; + __I uint32_t RX_CS_DATA_BITS[6]; /**< Channel staus bits, array offset: 0x190, array step: 0x4 */ + __I uint32_t RX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0x1A8, array step: 0x4 */ + struct { /* offset: 0x1C0 */ + __IO uint32_t RW; /**< Receive Datapath counter control register, offset: 0x1C0 */ + __IO uint32_t SET; /**< Receive Datapath counter control register, offset: 0x1C4 */ + __IO uint32_t CLR; /**< Receive Datapath counter control register, offset: 0x1C8 */ + __IO uint32_t TOG; /**< Receive Datapath counter control register, offset: 0x1CC */ + } RX_DPATH_CNTR_CTRL; + __I uint32_t RX_DPATH_TSCR; /**< Receive Datapath Timestamp Counter Register, offset: 0x1D0 */ + __I uint32_t RX_DPATH_BCR; /**< Receive Datapath Bit counter register, offset: 0x1D4 */ + __I uint32_t RX_DPATH_BCTR; /**< Receive datapath Bit count timestamp register., offset: 0x1D8 */ + __I uint32_t RX_DPATH_BCRR; /**< Receive datapath Bit read timestamp register., offset: 0x1DC */ + struct { /* offset: 0x1E0 */ + __IO uint32_t RW; /**< Preamble match value register, offset: 0x1E0 */ + __IO uint32_t SET; /**< Preamble match value register, offset: 0x1E4 */ + __IO uint32_t CLR; /**< Preamble match value register, offset: 0x1E8 */ + __IO uint32_t TOG; /**< Preamble match value register, offset: 0x1EC */ + } PRE_MATCH_VAL; + struct { /* offset: 0x1F0 */ + __IO uint32_t RW; /**< Preamble match value register, offset: 0x1F0 */ + __IO uint32_t SET; /**< Preamble match value register, offset: 0x1F4 */ + __IO uint32_t CLR; /**< Preamble match value register, offset: 0x1F8 */ + __IO uint32_t TOG; /**< Preamble match value register, offset: 0x1FC */ + } DTS_PRE_MATCH_VAL; + __IO uint32_t RX_DPATH_PRE_ERR; /**< Error count for IEC60958-1 Block Synchronization., offset: 0x200 */ + __IO uint32_t RX_DPATH_PARITY_ERR; /**< Parity Error count for IEC60958-1 Blocks., offset: 0x204 */ + uint8_t RESERVED_4[8]; + __I uint32_t RX_DPATH_PKT_CNT; /**< Receive Data packet count., offset: 0x210 */ + uint8_t RESERVED_5[4]; + __I uint32_t PRE_MATCH_OFFSET; /**< Preamble match offset value register, offset: 0x218 */ + uint8_t RESERVED_6[4]; + struct { /* offset: 0x220 */ + __IO uint32_t RW; /**< Transmit Data path control register, offset: 0x220 */ + __IO uint32_t SET; /**< Transmit Data path control register, offset: 0x224 */ + __IO uint32_t CLR; /**< Transmit Data path control register, offset: 0x228 */ + __IO uint32_t TOG; /**< Transmit Data path control register, offset: 0x22C */ + } TX_DATAPATH_CTRL; + __IO uint32_t TX_CS_DATA_BITS[6]; /**< Channel staus bits, array offset: 0x230, array step: 0x4 */ + __IO uint32_t TX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0x248, array step: 0x4 */ + struct { /* offset: 0x260 */ + __IO uint32_t RW; /**< Transmit datapath counter control register, offset: 0x260 */ + __IO uint32_t SET; /**< Transmit datapath counter control register, offset: 0x264 */ + __IO uint32_t CLR; /**< Transmit datapath counter control register, offset: 0x268 */ + __IO uint32_t TOG; /**< Transmit datapath counter control register, offset: 0x26C */ + } TX_DPATH_CNTR_CTRL; + __I uint32_t TX_DPATH_TSCR; /**< Transmit Datapath Timestamp Counter Register, offset: 0x270 */ + __I uint32_t TX_DPATH_BCR; /**< Transmit Datapath Bit counter register, offset: 0x274 */ + __I uint32_t TX_DPATH_BCTR; /**< Transmit datapath Bit count timestamp register., offset: 0x278 */ + __I uint32_t TX_DPATH_BCRR; /**< Transmmit datapath Bit read timestamp register., offset: 0x27C */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name VERSION - Version control register */ +/*! @{ */ + +#define SPDIF_VERSION_VERID_MASK (0xFFFFFFFFU) +#define SPDIF_VERSION_VERID_SHIFT (0U) +/*! VERID - Version ID */ +#define SPDIF_VERSION_VERID(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_VERSION_VERID_SHIFT)) & SPDIF_VERSION_VERID_MASK) +/*! @} */ + +/*! @name EXT_CTRL - External control register */ +/*! @{ */ + +#define SPDIF_EXT_CTRL_TX_FIFO_WMARK_MASK (0x7FU) +#define SPDIF_EXT_CTRL_TX_FIFO_WMARK_SHIFT (0U) +/*! TX_FIFO_WMARK - Audio Transmit FIFO Watermark Level */ +#define SPDIF_EXT_CTRL_TX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_TX_FIFO_WMARK_SHIFT)) & SPDIF_EXT_CTRL_TX_FIFO_WMARK_MASK) + +#define SPDIF_EXT_CTRL_RX_FIFO_WMARK_MASK (0x7F00U) +#define SPDIF_EXT_CTRL_RX_FIFO_WMARK_SHIFT (8U) +/*! RX_FIFO_WMARK - Audio Receive FIFO Watermark Level */ +#define SPDIF_EXT_CTRL_RX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_RX_FIFO_WMARK_SHIFT)) & SPDIF_EXT_CTRL_RX_FIFO_WMARK_MASK) + +#define SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_MASK (0x100000U) +#define SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_SHIFT (20U) +/*! EN_SPDIF_WAKEUP - Enable SPDIF wakeup interrupt */ +#define SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_SHIFT)) & SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_MASK) + +#define SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_MASK (0x1000000U) +#define SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT (24U) +/*! SDMA_WR_REQ_DIS - SDMA WR REQ disable */ +#define SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT)) & SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_MASK) + +#define SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_MASK (0x2000000U) +#define SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT (25U) +/*! SDMA_RD_REQ_DIS - SDMA RD REQ disable */ +#define SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT)) & SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_MASK) + +#define SPDIF_EXT_CTRL_TX_DPATH_RESET_MASK (0x8000000U) +#define SPDIF_EXT_CTRL_TX_DPATH_RESET_SHIFT (27U) +/*! TX_DPATH_RESET - Soft reset to SPDIF Transmit datapath */ +#define SPDIF_EXT_CTRL_TX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_TX_DPATH_RESET_SHIFT)) & SPDIF_EXT_CTRL_TX_DPATH_RESET_MASK) + +#define SPDIF_EXT_CTRL_RX_DPATH_RESET_MASK (0x10000000U) +#define SPDIF_EXT_CTRL_RX_DPATH_RESET_SHIFT (28U) +/*! RX_DPATH_RESET - Soft reset to SPDIF Receive datapath */ +#define SPDIF_EXT_CTRL_RX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_RX_DPATH_RESET_SHIFT)) & SPDIF_EXT_CTRL_RX_DPATH_RESET_MASK) +/*! @} */ + +/*! @name EXT_STATUS - External Status register */ +/*! @{ */ + +#define SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK (0xFFU) +#define SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT (0U) +/*! NO_TX_FIFO_ENTRIES - TX FIFO entries */ +#define SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT)) & SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK) + +#define SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK (0xFF00U) +#define SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT (8U) +/*! NO_RX_FIFO_ENTRIES - RX FIFO entries */ +#define SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT)) & SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK) + +#define SPDIF_EXT_STATUS_TX_PIPE_EMPTY_MASK (0x200000U) +#define SPDIF_EXT_STATUS_TX_PIPE_EMPTY_SHIFT (21U) +/*! TX_PIPE_EMPTY - Indicates TX pipe status. */ +#define SPDIF_EXT_STATUS_TX_PIPE_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_TX_PIPE_EMPTY_SHIFT)) & SPDIF_EXT_STATUS_TX_PIPE_EMPTY_MASK) + +#define SPDIF_EXT_STATUS_PREV_UD_0_MASK (0x400000U) +#define SPDIF_EXT_STATUS_PREV_UD_0_SHIFT (22U) +/*! PREV_UD_0 - Last User data received was all 0 */ +#define SPDIF_EXT_STATUS_PREV_UD_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_PREV_UD_0_SHIFT)) & SPDIF_EXT_STATUS_PREV_UD_0_MASK) +/*! @} */ + +/*! @name EXT_IER0 - Interrupt enables for interrupt 0 */ +/*! @{ */ + +#define SPDIF_EXT_IER0_NEW_CS_IE_0_MASK (0x1U) +#define SPDIF_EXT_IER0_NEW_CS_IE_0_SHIFT (0U) +/*! NEW_CS_IE_0 - Enable for New channel status block received interrupt */ +#define SPDIF_EXT_IER0_NEW_CS_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_NEW_CS_IE_0_SHIFT)) & SPDIF_EXT_IER0_NEW_CS_IE_0_MASK) + +#define SPDIF_EXT_IER0_UD_IE_0_MASK (0x2U) +#define SPDIF_EXT_IER0_UD_IE_0_SHIFT (1U) +/*! UD_IE_0 - Enable for user data received interrupt */ +#define SPDIF_EXT_IER0_UD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_UD_IE_0_SHIFT)) & SPDIF_EXT_IER0_UD_IE_0_MASK) + +#define SPDIF_EXT_IER0_MUTE_IE_0_MASK (0x4U) +#define SPDIF_EXT_IER0_MUTE_IE_0_SHIFT (2U) +/*! MUTE_IE_0 - Enable for Mute detected interrupt */ +#define SPDIF_EXT_IER0_MUTE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_MUTE_IE_0_SHIFT)) & SPDIF_EXT_IER0_MUTE_IE_0_MASK) + +#define SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK (0x20U) +#define SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT (5U) +/*! PREAMBLE_MISMATCH_IE_0 - Preamble mismatch interrupt enable. */ +#define SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK (0x40U) +#define SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT (6U) +/*! FIFO_OFLOW_UFLOW_ERR_IE_0 - Receive FIFO overflow error interrupt enable. */ +#define SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT)) & SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK) + +#define SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_MASK (0x200U) +#define SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_SHIFT (9U) +/*! RX_NO_DATA_REC_IE_0 - Indicates no data is received. */ +#define SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_SHIFT)) & SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_MASK) + +#define SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_MASK (0x4000U) +#define SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT (14U) +/*! DMA_RD_REQ_IE_0 - Request to read data from FIFO. */ +#define SPDIF_EXT_IER0_DMA_RD_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT)) & SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_MASK) + +#define SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_MASK (0x8000U) +#define SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT (15U) +/*! DMA_WR_REQ_IE_0 - Request to write data to FIFO. */ +#define SPDIF_EXT_IER0_DMA_WR_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT)) & SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_MASK) + +#define SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_MASK (0x10000U) +#define SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_SHIFT (16U) +/*! RX_DATA_BME_ERR_IE_0 - Bi-phase mark encoding error */ +#define SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_SHIFT)) & SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_MASK) + +#define SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK (0x20000U) +#define SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT (17U) +/*! PREAMBLE_MATCH_IE_0 - Interrupt enable for preamble match received. */ +#define SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK (0x40000U) +#define SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT (18U) +/*! M_W_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame M/W preamble mismatch received. */ +#define SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK (0x80000U) +#define SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT (19U) +/*! B_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame B preamble mismatch received. */ +#define SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK (0x100000U) +#define SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT (20U) +/*! UNEXP_PRE_REC_IE_0 - Interrupt enable for Unexpected preamble received. */ +#define SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT)) & SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK) + +#define SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_MASK (0x400000U) +#define SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_SHIFT (22U) +/*! CS_UD_OFLOW_IE_0 - Channel status or used data could not be stored. */ +#define SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_SHIFT)) & SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_MASK) + +#define SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_MASK (0x800000U) +#define SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_SHIFT (23U) +/*! NEW_BLK_RCVD_IE_0 - New block of data was received. */ +#define SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_SHIFT)) & SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_MASK) + +#define SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_MASK (0x1000000U) +#define SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_SHIFT (24U) +/*! SPDIF_WAKEUP_IE_0 - SPDIF Wakeup interrupt enable. */ +#define SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_SHIFT)) & SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_MASK) +/*! @} */ + +/*! @name EXT_IER1 - Interrupt enables for interrupt 1 */ +/*! @{ */ + +#define SPDIF_EXT_IER1_NEW_CS_IE_1_MASK (0x1U) +#define SPDIF_EXT_IER1_NEW_CS_IE_1_SHIFT (0U) +/*! NEW_CS_IE_1 - Enable for New channel status block received interrupt */ +#define SPDIF_EXT_IER1_NEW_CS_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_NEW_CS_IE_1_SHIFT)) & SPDIF_EXT_IER1_NEW_CS_IE_1_MASK) + +#define SPDIF_EXT_IER1_UD_IE_1_MASK (0x2U) +#define SPDIF_EXT_IER1_UD_IE_1_SHIFT (1U) +/*! UD_IE_1 - Enable for user data received interrupt */ +#define SPDIF_EXT_IER1_UD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_UD_IE_1_SHIFT)) & SPDIF_EXT_IER1_UD_IE_1_MASK) + +#define SPDIF_EXT_IER1_MUTE_IE_1_MASK (0x4U) +#define SPDIF_EXT_IER1_MUTE_IE_1_SHIFT (2U) +/*! MUTE_IE_1 - Enable for Mute detected interrupt */ +#define SPDIF_EXT_IER1_MUTE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_MUTE_IE_1_SHIFT)) & SPDIF_EXT_IER1_MUTE_IE_1_MASK) + +#define SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK (0x20U) +#define SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT (5U) +/*! PREAMBLE_MISMATCH_IE_1 - Preamble mismatch interrupt enable. */ +#define SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK (0x40U) +#define SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT (6U) +/*! FIFO_OFLOW_UFLOW_ERR_IE_1 - Receive FIFO overflow error interrupt enable. */ +#define SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT)) & SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK) + +#define SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_MASK (0x200U) +#define SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_SHIFT (9U) +/*! RX_NO_DATA_REC_IE_1 - Indicates no data is received. */ +#define SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_SHIFT)) & SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_MASK) + +#define SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_MASK (0x4000U) +#define SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT (14U) +/*! DMA_RD_REQ_IE_1 - Request to read data from FIFO. */ +#define SPDIF_EXT_IER1_DMA_RD_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT)) & SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_MASK) + +#define SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_MASK (0x8000U) +#define SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT (15U) +/*! DMA_WR_REQ_IE_1 - Request to write data to FIFO. */ +#define SPDIF_EXT_IER1_DMA_WR_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT)) & SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_MASK) + +#define SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_MASK (0x10000U) +#define SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_SHIFT (16U) +/*! RX_DATA_BME_ERR_IE_1 - Bi-phase mark encoding error */ +#define SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_SHIFT)) & SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_MASK) + +#define SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK (0x20000U) +#define SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT (17U) +/*! PREAMBLE_MATCH_IE_1 - Interrupt enable for preamble match received. */ +#define SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK (0x40000U) +#define SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT (18U) +/*! M_W_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame M/W preamble mismatch received. */ +#define SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK (0x80000U) +#define SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT (19U) +/*! B_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame B preamble mismatch received. */ +#define SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK (0x100000U) +#define SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT (20U) +/*! UNEXP_PRE_REC_IE_1 - Interrupt enable for Unexpected preamble received. */ +#define SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT)) & SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK) + +#define SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_MASK (0x400000U) +#define SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_SHIFT (22U) +/*! CS_UD_OFLOW_IE_1 - Channel status or used data could not be stored. */ +#define SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_SHIFT)) & SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_MASK) + +#define SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_MASK (0x800000U) +#define SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_SHIFT (23U) +/*! NEW_BLK_RCVD_IE_1 - New block of data was received. */ +#define SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_SHIFT)) & SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_MASK) + +#define SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_MASK (0x1000000U) +#define SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_SHIFT (24U) +/*! SPDIF_WAKEUP_IE_1 - SPDIF Wakeup interrupt enable. */ +#define SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_SHIFT)) & SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_MASK) +/*! @} */ + +/*! @name EXT_ISR - External Interrupt Status register */ +/*! @{ */ + +#define SPDIF_EXT_ISR_RX_NEW_CH_STAT_MASK (0x1U) +#define SPDIF_EXT_ISR_RX_NEW_CH_STAT_SHIFT (0U) +/*! RX_NEW_CH_STAT - Received new channel status block */ +#define SPDIF_EXT_ISR_RX_NEW_CH_STAT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_NEW_CH_STAT_SHIFT)) & SPDIF_EXT_ISR_RX_NEW_CH_STAT_MASK) + +#define SPDIF_EXT_ISR_RX_USR_DATA_MASK (0x2U) +#define SPDIF_EXT_ISR_RX_USR_DATA_SHIFT (1U) +/*! RX_USR_DATA - Received User data Information */ +#define SPDIF_EXT_ISR_RX_USR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_USR_DATA_SHIFT)) & SPDIF_EXT_ISR_RX_USR_DATA_MASK) + +#define SPDIF_EXT_ISR_MUTE_DET_MASK (0x4U) +#define SPDIF_EXT_ISR_MUTE_DET_SHIFT (2U) +/*! MUTE_DET - Interrupt to indicate HW mute bit was detected. */ +#define SPDIF_EXT_ISR_MUTE_DET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_MUTE_DET_SHIFT)) & SPDIF_EXT_ISR_MUTE_DET_MASK) + +#define SPDIF_EXT_ISR_PREAMBLE_MISMATCH_MASK (0x20U) +#define SPDIF_EXT_ISR_PREAMBLE_MISMATCH_SHIFT (5U) +/*! PREAMBLE_MISMATCH - Preamble mismatch interrupt */ +#define SPDIF_EXT_ISR_PREAMBLE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_PREAMBLE_MISMATCH_SHIFT)) & SPDIF_EXT_ISR_PREAMBLE_MISMATCH_MASK) + +#define SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK (0x40U) +#define SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT (6U) +/*! FIFO_OFLOW_UFLOW_ERR - Receive FIFO overflow error interrupt */ +#define SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT)) & SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK) + +#define SPDIF_EXT_ISR_RX_NO_DATA_REC_MASK (0x200U) +#define SPDIF_EXT_ISR_RX_NO_DATA_REC_SHIFT (9U) +/*! RX_NO_DATA_REC - No data is received for 1us. */ +#define SPDIF_EXT_ISR_RX_NO_DATA_REC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_NO_DATA_REC_SHIFT)) & SPDIF_EXT_ISR_RX_NO_DATA_REC_MASK) + +#define SPDIF_EXT_ISR_DMA_RD_REQ_MASK (0x4000U) +#define SPDIF_EXT_ISR_DMA_RD_REQ_SHIFT (14U) +/*! DMA_RD_REQ - Set when DMA read request is asserted. */ +#define SPDIF_EXT_ISR_DMA_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_DMA_RD_REQ_SHIFT)) & SPDIF_EXT_ISR_DMA_RD_REQ_MASK) + +#define SPDIF_EXT_ISR_DMA_WR_REQ_MASK (0x8000U) +#define SPDIF_EXT_ISR_DMA_WR_REQ_SHIFT (15U) +/*! DMA_WR_REQ - Set when DMA write request is asserted. */ +#define SPDIF_EXT_ISR_DMA_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_DMA_WR_REQ_SHIFT)) & SPDIF_EXT_ISR_DMA_WR_REQ_MASK) + +#define SPDIF_EXT_ISR_RX_BME_BIT_ERR_MASK (0x10000U) +#define SPDIF_EXT_ISR_RX_BME_BIT_ERR_SHIFT (16U) +/*! RX_BME_BIT_ERR - Set when RX BME data has an error. */ +#define SPDIF_EXT_ISR_RX_BME_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_BME_BIT_ERR_SHIFT)) & SPDIF_EXT_ISR_RX_BME_BIT_ERR_MASK) + +#define SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_MASK (0x20000U) +#define SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT (17U) +/*! PREAMBLE_MATCH_INT - Interrupt to indicate PA PB / DTC CD preamble match was detected. */ +#define SPDIF_EXT_ISR_PREAMBLE_MATCH_INT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT)) & SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_MASK) + +#define SPDIF_EXT_ISR_M_W_PRE_MISMATCH_MASK (0x40000U) +#define SPDIF_EXT_ISR_M_W_PRE_MISMATCH_SHIFT (18U) +/*! M_W_PRE_MISMATCH - Set when SPDIF preamble of M/W has an error. */ +#define SPDIF_EXT_ISR_M_W_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_M_W_PRE_MISMATCH_SHIFT)) & SPDIF_EXT_ISR_M_W_PRE_MISMATCH_MASK) + +#define SPDIF_EXT_ISR_B_PRE_MISMATCH_MASK (0x80000U) +#define SPDIF_EXT_ISR_B_PRE_MISMATCH_SHIFT (19U) +/*! B_PRE_MISMATCH - Set when SPDIF B preamble has an error. */ +#define SPDIF_EXT_ISR_B_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_B_PRE_MISMATCH_SHIFT)) & SPDIF_EXT_ISR_B_PRE_MISMATCH_MASK) + +#define SPDIF_EXT_ISR_UNEXP_PRE_REC_MASK (0x100000U) +#define SPDIF_EXT_ISR_UNEXP_PRE_REC_SHIFT (20U) +/*! UNEXP_PRE_REC - Set when SPDIF preamble was received after unexpected number of input bits. */ +#define SPDIF_EXT_ISR_UNEXP_PRE_REC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_UNEXP_PRE_REC_SHIFT)) & SPDIF_EXT_ISR_UNEXP_PRE_REC_MASK) + +#define SPDIF_EXT_ISR_CS_OR_UD_OFLOW_MASK (0x400000U) +#define SPDIF_EXT_ISR_CS_OR_UD_OFLOW_SHIFT (22U) +/*! CS_OR_UD_OFLOW - Channel status or used data could not be stored. */ +#define SPDIF_EXT_ISR_CS_OR_UD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_CS_OR_UD_OFLOW_SHIFT)) & SPDIF_EXT_ISR_CS_OR_UD_OFLOW_MASK) + +#define SPDIF_EXT_ISR_NEW_BLK_RCVD_MASK (0x800000U) +#define SPDIF_EXT_ISR_NEW_BLK_RCVD_SHIFT (23U) +/*! NEW_BLK_RCVD - New block of data was received. */ +#define SPDIF_EXT_ISR_NEW_BLK_RCVD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_NEW_BLK_RCVD_SHIFT)) & SPDIF_EXT_ISR_NEW_BLK_RCVD_MASK) + +#define SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_MASK (0x1000000U) +#define SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_SHIFT (24U) +/*! SPDIF_WAKEUP_REC - SPDIF Wakeup received. */ +#define SPDIF_EXT_ISR_SPDIF_WAKEUP_REC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_SHIFT)) & SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_MASK) +/*! @} */ + +/*! @name DPATH_STATUS - Audio XCVR datapath status */ +/*! @{ */ + +#define SPDIF_DPATH_STATUS_RX_FRM_CNT_MASK (0xFFU) +#define SPDIF_DPATH_STATUS_RX_FRM_CNT_SHIFT (0U) +/*! RX_FRM_CNT - Count of received frames in a block */ +#define SPDIF_DPATH_STATUS_RX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DPATH_STATUS_RX_FRM_CNT_SHIFT)) & SPDIF_DPATH_STATUS_RX_FRM_CNT_MASK) + +#define SPDIF_DPATH_STATUS_TX_FRM_CNT_MASK (0xFF00U) +#define SPDIF_DPATH_STATUS_TX_FRM_CNT_SHIFT (8U) +/*! TX_FRM_CNT - Count of transmitted frames in a block */ +#define SPDIF_DPATH_STATUS_TX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DPATH_STATUS_TX_FRM_CNT_SHIFT)) & SPDIF_DPATH_STATUS_TX_FRM_CNT_MASK) +/*! @} */ + +/*! @name CLK_CTRL - Clock control register */ +/*! @{ */ + +#define SPDIF_CLK_CTRL_CLKDIV_MASK (0x3FFU) +#define SPDIF_CLK_CTRL_CLKDIV_SHIFT (0U) +/*! CLKDIV - Clock divider value */ +#define SPDIF_CLK_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_CLK_CTRL_CLKDIV_SHIFT)) & SPDIF_CLK_CTRL_CLKDIV_MASK) +/*! @} */ + +/*! @name RX_DATAPATH_CTRL - Data path control register */ +/*! @{ */ + +#define SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK (0x1U) +#define SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT (0U) +#define SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK (0x20U) +#define SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT (5U) +/*! RST_PKT_CNT_FIFO - Resets the packet count fifo. */ +#define SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_STORE_FMT_MASK (0x40U) +#define SPDIF_RX_DATAPATH_CTRL_STORE_FMT_SHIFT (6U) +/*! STORE_FMT - Receive Data store format. */ +#define SPDIF_RX_DATAPATH_CTRL_STORE_FMT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_STORE_FMT_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_STORE_FMT_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK (0x80U) +#define SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT (7U) +/*! EN_PARITY_CALC - Enable Parity calculation. */ +#define SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_UDR_MASK (0x100U) +#define SPDIF_RX_DATAPATH_CTRL_UDR_SHIFT (8U) +/*! UDR - User data reset */ +#define SPDIF_RX_DATAPATH_CTRL_UDR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_UDR_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_UDR_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_CSR_MASK (0x200U) +#define SPDIF_RX_DATAPATH_CTRL_CSR_SHIFT (9U) +/*! CSR - Channel Status reset */ +#define SPDIF_RX_DATAPATH_CTRL_CSR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_CSR_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_CSR_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_UDA_MASK (0x400U) +#define SPDIF_RX_DATAPATH_CTRL_UDA_SHIFT (10U) +/*! UDA - User Data Acknowledge */ +#define SPDIF_RX_DATAPATH_CTRL_UDA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_UDA_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_UDA_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_CSA_MASK (0x800U) +#define SPDIF_RX_DATAPATH_CTRL_CSA_SHIFT (11U) +/*! CSA - Channel Status Acknowledge */ +#define SPDIF_RX_DATAPATH_CTRL_CSA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_CSA_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_CSA_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK (0x1000U) +#define SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT (12U) +/*! CLR_RX_FIFO - Clear Receive FIFO */ +#define SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK (0xC000U) +#define SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT (14U) +/*! RX_DATA_FMT - Indicates format of data stored in memory. */ +#define SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_MASK (0x70000U) +#define SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_SHIFT (16U) +/*! SPDIF_TGL_CNT - SPDIF wakeup source toggle count. */ +#define SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_PABS_MASK (0x80000U) +#define SPDIF_RX_DATAPATH_CTRL_PABS_SHIFT (19U) +/*! PABS - Enable preamble search */ +#define SPDIF_RX_DATAPATH_CTRL_PABS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_PABS_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_PABS_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_DTS_CDS_MASK (0x100000U) +#define SPDIF_RX_DATAPATH_CTRL_DTS_CDS_SHIFT (20U) +/*! DTS_CDS - Enable DTS CD 14 preamble search */ +#define SPDIF_RX_DATAPATH_CTRL_DTS_CDS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_DTS_CDS_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_DTS_CDS_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_MASK (0x400000U) +#define SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT (22U) +/*! MUTE_CTRL - M0+ mute request */ +#define SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_MASK (0x800000U) +#define SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT (23U) +/*! MUTE_MODE - Mute mode control */ +#define SPDIF_RX_DATAPATH_CTRL_MUTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_FSM_MASK (0xC0000000U) +#define SPDIF_RX_DATAPATH_CTRL_FSM_SHIFT (30U) +/*! FSM - IEC60958-1 Frame Synchronization Mode */ +#define SPDIF_RX_DATAPATH_CTRL_FSM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_FSM_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_FSM_MASK) +/*! @} */ + +/*! @name RX_CS_DATA_BITS - Channel staus bits */ +/*! @{ */ + +#define SPDIF_RX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_RX_CS_DATA_BITS_CS_DATA_SHIFT (0U) +/*! CS_DATA - Channel Status bits */ +#define SPDIF_RX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_CS_DATA_BITS_CS_DATA_SHIFT)) & SPDIF_RX_CS_DATA_BITS_CS_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_RX_CS_DATA_BITS */ +#define SPDIF_RX_CS_DATA_BITS_COUNT (6U) + +/*! @name RX_USER_DATA_BITS - User data bits */ +/*! @{ */ + +#define SPDIF_RX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_RX_USER_DATA_BITS_U_DATA_SHIFT (0U) +/*! U_DATA - User data bits */ +#define SPDIF_RX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_USER_DATA_BITS_U_DATA_SHIFT)) & SPDIF_RX_USER_DATA_BITS_U_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_RX_USER_DATA_BITS */ +#define SPDIF_RX_USER_DATA_BITS_COUNT (6U) + +/*! @name RX_DPATH_CNTR_CTRL - Receive Datapath counter control register */ +/*! @{ */ + +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U) +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U) +/*! TS_EN - Timestamp counter enable */ +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_MASK) + +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U) +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U) +/*! TS_INC - Timestamp Increment */ +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_MASK) + +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U) +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U) +/*! RST_BIT_CNTR - Reset bit counter. */ +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK) + +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U) +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U) +/*! RST_TS_CNTR - Reset timestamp counter. */ +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK) +/*! @} */ + +/*! @name RX_DPATH_TSCR - Receive Datapath Timestamp Counter Register */ +/*! @{ */ + +#define SPDIF_RX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_TSCR_CVAL_SHIFT (0U) +/*! CVAL - Timestamp counter value */ +#define SPDIF_RX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_TSCR_CVAL_SHIFT)) & SPDIF_RX_DPATH_TSCR_CVAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_BCR - Receive Datapath Bit counter register */ +/*! @{ */ + +#define SPDIF_RX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_BCR_CVAL_SHIFT (0U) +/*! CVAL - Bit count value */ +#define SPDIF_RX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_BCR_CVAL_SHIFT)) & SPDIF_RX_DPATH_BCR_CVAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_BCTR - Receive datapath Bit count timestamp register. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_BCTR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_RX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_BCTR_BCT_VAL_SHIFT)) & SPDIF_RX_DPATH_BCTR_BCT_VAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_BCRR - Receive datapath Bit read timestamp register. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_BCRR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_RX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_BCRR_BCT_VAL_SHIFT)) & SPDIF_RX_DPATH_BCRR_BCT_VAL_MASK) +/*! @} */ + +/*! @name PRE_MATCH_VAL - Preamble match value register */ +/*! @{ */ + +#define SPDIF_PRE_MATCH_VAL_PB_VAL_MASK (0xFFFFU) +#define SPDIF_PRE_MATCH_VAL_PB_VAL_SHIFT (0U) +/*! PB_VAL - Preamble PB value */ +#define SPDIF_PRE_MATCH_VAL_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_PRE_MATCH_VAL_PB_VAL_SHIFT)) & SPDIF_PRE_MATCH_VAL_PB_VAL_MASK) + +#define SPDIF_PRE_MATCH_VAL_PA_VAL_MASK (0xFFFF0000U) +#define SPDIF_PRE_MATCH_VAL_PA_VAL_SHIFT (16U) +/*! PA_VAL - Preamble PA value */ +#define SPDIF_PRE_MATCH_VAL_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_PRE_MATCH_VAL_PA_VAL_SHIFT)) & SPDIF_PRE_MATCH_VAL_PA_VAL_MASK) +/*! @} */ + +/*! @name DTS_PRE_MATCH_VAL - Preamble match value register */ +/*! @{ */ + +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK (0xFFFFU) +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT (0U) +/*! DTS_PB_VAL - Preamble value */ +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT)) & SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK) + +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK (0xFFFF0000U) +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT (16U) +/*! DTS_PA_VAL - Preamble value */ +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT)) & SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_PRE_ERR - Error count for IEC60958-1 Block Synchronization. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_MASK (0xFFFFU) +#define SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT (0U) +/*! PRE_ERRS - Preamble Error counter */ +#define SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT)) & SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_MASK) + +#define SPDIF_RX_DPATH_PRE_ERR_CLEAR_MASK (0x80000000U) +#define SPDIF_RX_DPATH_PRE_ERR_CLEAR_SHIFT (31U) +/*! CLEAR - Clear bit for error counter. */ +#define SPDIF_RX_DPATH_PRE_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PRE_ERR_CLEAR_SHIFT)) & SPDIF_RX_DPATH_PRE_ERR_CLEAR_MASK) +/*! @} */ + +/*! @name RX_DPATH_PARITY_ERR - Parity Error count for IEC60958-1 Blocks. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK (0xFFFFU) +#define SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT (0U) +/*! PRE_ERRS - Parity Error counter */ +#define SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT)) & SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK) + +#define SPDIF_RX_DPATH_PARITY_ERR_CLEAR_MASK (0x80000000U) +#define SPDIF_RX_DPATH_PARITY_ERR_CLEAR_SHIFT (31U) +/*! CLEAR - Clear bit for error counter. */ +#define SPDIF_RX_DPATH_PARITY_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PARITY_ERR_CLEAR_SHIFT)) & SPDIF_RX_DPATH_PARITY_ERR_CLEAR_MASK) +/*! @} */ + +/*! @name RX_DPATH_PKT_CNT - Receive Data packet count. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_PKT_CNT_VAL_MASK (0x7FFFFFFFU) +#define SPDIF_RX_DPATH_PKT_CNT_VAL_SHIFT (0U) +/*! VAL - Data packet counter */ +#define SPDIF_RX_DPATH_PKT_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PKT_CNT_VAL_SHIFT)) & SPDIF_RX_DPATH_PKT_CNT_VAL_MASK) +/*! @} */ + +/*! @name PRE_MATCH_OFFSET - Preamble match offset value register */ +/*! @{ */ + +#define SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_MASK (0xFFFFFFFFU) +#define SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT (0U) +/*! PA_OFFSET - Sample count value for PA offset match */ +#define SPDIF_PRE_MATCH_OFFSET_PA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT)) & SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_MASK) +/*! @} */ + +/*! @name TX_DATAPATH_CTRL - Transmit Data path control register */ +/*! @{ */ + +#define SPDIF_TX_DATAPATH_CTRL_CS_ACK_MASK (0x1U) +#define SPDIF_TX_DATAPATH_CTRL_CS_ACK_SHIFT (0U) +/*! CS_ACK - Channel Status ACK */ +#define SPDIF_TX_DATAPATH_CTRL_CS_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_CS_ACK_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_CS_ACK_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_UD_ACK_MASK (0x2U) +#define SPDIF_TX_DATAPATH_CTRL_UD_ACK_SHIFT (1U) +/*! UD_ACK - User Data ACK */ +#define SPDIF_TX_DATAPATH_CTRL_UD_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_UD_ACK_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_UD_ACK_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_CS_MOD_MASK (0x4U) +#define SPDIF_TX_DATAPATH_CTRL_CS_MOD_SHIFT (2U) +/*! CS_MOD - Enable Channel Status insertion */ +#define SPDIF_TX_DATAPATH_CTRL_CS_MOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_CS_MOD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_CS_MOD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_UD_MOD_MASK (0x8U) +#define SPDIF_TX_DATAPATH_CTRL_UD_MOD_SHIFT (3U) +/*! UD_MOD - Enable User Data insertion */ +#define SPDIF_TX_DATAPATH_CTRL_UD_MOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_UD_MOD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_UD_MOD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_VLD_MOD_MASK (0x10U) +#define SPDIF_TX_DATAPATH_CTRL_VLD_MOD_SHIFT (4U) +/*! VLD_MOD - Enable Valid bit insertion */ +#define SPDIF_TX_DATAPATH_CTRL_VLD_MOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_VLD_MOD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_VLD_MOD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_FRM_VLD_MASK (0x20U) +#define SPDIF_TX_DATAPATH_CTRL_FRM_VLD_SHIFT (5U) +/*! FRM_VLD - Valid bit value */ +#define SPDIF_TX_DATAPATH_CTRL_FRM_VLD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_FRM_VLD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_FRM_VLD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_EN_PARITY_MASK (0x40U) +#define SPDIF_TX_DATAPATH_CTRL_EN_PARITY_SHIFT (6U) +/*! EN_PARITY - Enable parity insertion */ +#define SPDIF_TX_DATAPATH_CTRL_EN_PARITY(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_EN_PARITY_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_EN_PARITY_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK (0x80U) +#define SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT (7U) +/*! EN_PREAMBLE - Enable preamble insertion */ +#define SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_FRM_FMT_MASK (0x800U) +#define SPDIF_TX_DATAPATH_CTRL_FRM_FMT_SHIFT (11U) +/*! FRM_FMT - Frame format of input data */ +#define SPDIF_TX_DATAPATH_CTRL_FRM_FMT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_FRM_FMT_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_FRM_FMT_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_MASK (0x3000U) +#define SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT (12U) +/*! TX_FORMAT - Transmit data format */ +#define SPDIF_TX_DATAPATH_CTRL_TX_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK (0x4000U) +#define SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT (14U) +/*! STRT_DATA_TX - Start transmit of data. */ +#define SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK) +/*! @} */ + +/*! @name TX_CS_DATA_BITS - Channel staus bits */ +/*! @{ */ + +#define SPDIF_TX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_TX_CS_DATA_BITS_CS_DATA_SHIFT (0U) +/*! CS_DATA - Channel Status bits / block */ +#define SPDIF_TX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_CS_DATA_BITS_CS_DATA_SHIFT)) & SPDIF_TX_CS_DATA_BITS_CS_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_TX_CS_DATA_BITS */ +#define SPDIF_TX_CS_DATA_BITS_COUNT (6U) + +/*! @name TX_USER_DATA_BITS - User data bits */ +/*! @{ */ + +#define SPDIF_TX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_TX_USER_DATA_BITS_U_DATA_SHIFT (0U) +/*! U_DATA - User data bits/block */ +#define SPDIF_TX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_USER_DATA_BITS_U_DATA_SHIFT)) & SPDIF_TX_USER_DATA_BITS_U_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_TX_USER_DATA_BITS */ +#define SPDIF_TX_USER_DATA_BITS_COUNT (6U) + +/*! @name TX_DPATH_CNTR_CTRL - Transmit datapath counter control register */ +/*! @{ */ + +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U) +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U) +/*! TS_EN - Timestamp counter enable */ +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_MASK) + +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U) +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U) +/*! TS_INC - Timestamp Increment */ +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_MASK) + +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U) +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U) +/*! RST_BIT_CNTR - Reset bit counter. */ +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK) + +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U) +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U) +/*! RST_TS_CNTR - Reset timestamp counter. */ +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK) +/*! @} */ + +/*! @name TX_DPATH_TSCR - Transmit Datapath Timestamp Counter Register */ +/*! @{ */ + +#define SPDIF_TX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_TSCR_CVAL_SHIFT (0U) +/*! CVAL - Timestamp counter value */ +#define SPDIF_TX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_TSCR_CVAL_SHIFT)) & SPDIF_TX_DPATH_TSCR_CVAL_MASK) +/*! @} */ + +/*! @name TX_DPATH_BCR - Transmit Datapath Bit counter register */ +/*! @{ */ + +#define SPDIF_TX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_BCR_CVAL_SHIFT (0U) +/*! CVAL - Bit count value */ +#define SPDIF_TX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_BCR_CVAL_SHIFT)) & SPDIF_TX_DPATH_BCR_CVAL_MASK) +/*! @} */ + +/*! @name TX_DPATH_BCTR - Transmit datapath Bit count timestamp register. */ +/*! @{ */ + +#define SPDIF_TX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_BCTR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_TX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_BCTR_BCT_VAL_SHIFT)) & SPDIF_TX_DPATH_BCTR_BCT_VAL_MASK) +/*! @} */ + +/*! @name TX_DPATH_BCRR - Transmmit datapath Bit read timestamp register. */ +/*! @{ */ + +#define SPDIF_TX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_BCRR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_TX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_BCRR_BCT_VAL_SHIFT)) & SPDIF_TX_DPATH_BCRR_BCT_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x42680000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC_GENERAL_REG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_GENERAL_REG_Peripheral_Access_Layer SRC_GENERAL_REG Peripheral Access Layer + * @{ + */ + +/** SRC_GENERAL_REG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t AUTHEN_CTRL; /**< Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SRTMR; /**< SRC RESET TRIGGER MODE REGISTER, offset: 0x14 */ + __IO uint32_t SRMASK; /**< SRC RESET TRIGGER MODE REGISTER, offset: 0x18 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SRMR1; /**< SRC RESET MODE REGISTER 1, offset: 0x20 */ + __IO uint32_t SRMR2; /**< SRC RESET MODE REGISTER 2, offset: 0x24 */ + __IO uint32_t SRMR3; /**< SRC RESET MODE REGISTER 3, offset: 0x28 */ + __IO uint32_t SRMR4; /**< SRC RESET MODE REGISTER 4, offset: 0x2C */ + uint8_t RESERVED_3[16]; + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x40 */ + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x44 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x50 */ + __IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x54 */ + __IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x58 */ + __IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x5C */ + __IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x60 */ + __IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x64 */ + __IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x68 */ + __IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x6C */ + __IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x70 */ + __IO uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x74 */ + __IO uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x78 */ + __IO uint32_t GPR11; /**< SRC General Purpose Register 11, offset: 0x7C */ + __IO uint32_t GPR12; /**< SRC General Purpose Register 12, offset: 0x80 */ + __IO uint32_t GPR13; /**< SRC General Purpose Register 13, offset: 0x84 */ + __IO uint32_t GPR14; /**< SRC General Purpose Register 14, offset: 0x88 */ + __IO uint32_t GPR15; /**< SRC General Purpose Register 15, offset: 0x8C */ + __IO uint32_t GPR16; /**< SRC General Purpose Register 16, offset: 0x90 */ + __IO uint32_t GPR17; /**< SRC General Purpose Register 17, offset: 0x94 */ + __IO uint32_t GPR18; /**< SRC General Purpose Register 18, offset: 0x98 */ + __IO uint32_t GPR19; /**< SRC General Purpose Register 19, offset: 0x9C */ + uint8_t RESERVED_5[96]; + __IO uint32_t GPR20; /**< SRC General Purpose Register 20, offset: 0x100 */ + uint8_t RESERVED_6[4]; + __IO uint32_t COLD_RESET_SSAR_ACK_CTRL; /**< Cold reset SSAR acknowledge control, offset: 0x108 */ + __IO uint32_t SP_ISO_CTRL; /**< SRC special ISO Control, offset: 0x10C */ + __IO uint32_t ROM_LP_CTRL; /**< ROM Low Power Control, offset: 0x110 */ + __I uint32_t A55_DENY_STAT; /**< A55 Q_Channel Deny Status, offset: 0x114 */ +} SRC_GENERAL_REG_Type; + +/* ---------------------------------------------------------------------------- + -- SRC_GENERAL_REG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_GENERAL_REG_Register_Masks SRC_GENERAL_REG Register Masks + * @{ + */ + +/*! @name AUTHEN_CTRL - Authentication Control */ +/*! @{ */ + +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..General registers are not locked. + * 0b1..LOCK_CFG and registers in the list are locked. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_MASK (0x100U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_SHIFT (8U) +/*! TZ_USER - Allow user mode access + * 0b0..General registers can only be written in privilege mode. + * 0b1..General registers can be written either in privilege mode or user mode. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_MASK (0x200U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_SHIFT (9U) +/*! TZ_NS - Allow non-secure mode access + * 0b0..General registers can only be written in secure mode. + * 0b1..General registers can be written either in secure mode or non-secure mode. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_MASK (0x800U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TZ_NS and TZ_USER bits + * 0b0..TZ_NS and TZ_USER value can be changed. + * 0b1..LOCK_TZ, TZ_NS and TZ_USER value cannot be changed. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST value can be changed. + * 0b1..LOCK_LIST and WHITE_LIST value cannot be changed. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list + * 0b0000000000000001..Core with domain ID=0 can write General registers. + * 0b0000000000000010..Core with domain ID=1 can write General registers. + * 0b0000000000000100..Core with domain ID=2 can write General registers. + * 0b0000000000001000..Core with domain ID=3 can write General registers. + * 0b0000000000010000..Core with domain ID=4 can write General registers. + * 0b0000000000100000..Core with domain ID=5 can write General registers. + * 0b0000000001000000..Core with domain ID=6 can write General registers. + * 0b0000000010000000..Core with domain ID=7 can write General registers. + * 0b0000000100000000..Core with domain ID=8 can write General registers. + * 0b0000001000000000..Core with domain ID=9 can write General registers. + * 0b0000010000000000..Core with domain ID=10 can write General registers. + * 0b0000100000000000..Core with domain ID=11 can write General registers. + * 0b0001000000000000..Core with domain ID=12 can write General registers. + * 0b0010000000000000..Core with domain ID=13 can write General registers. + * 0b0100000000000000..Core with domain ID=14 can write General registers. + * 0b1000000000000000..Core with domain ID=15 can write General registers. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name SRTMR - SRC RESET TRIGGER MODE REGISTER */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_MASK (0x1U) +#define SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_SHIFT (0U) +/*! WDOG1_TRIG_MODE - WDOG1 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_MASK (0x2U) +#define SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_SHIFT (1U) +/*! WDOG2_TRIG_MODE - WDOG2 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_MASK (0x4U) +#define SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_SHIFT (2U) +/*! WDOG3_TRIG_MODE - WDOG3 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_MASK (0x8U) +#define SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_SHIFT (3U) +/*! WDOG4_TRIG_MODE - WDOG4 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_MASK (0x10U) +#define SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_SHIFT (4U) +/*! WDOG5_TRIG_MODE - WDOG5 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_MASK (0x20U) +#define SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_SHIFT (5U) +/*! TEMPSENSE_TRIG_MODE - Tempsense reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_MASK (0x40U) +#define SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_SHIFT (6U) +/*! CSU_TRIG_MODE - CSU reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_MASK (0x80U) +#define SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_SHIFT (7U) +/*! JTAGSW_TRIG_MODE - JTAGSW reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_JTAG_RST_B_MASK (0x200U) +#define SRC_GENERAL_REG_SRTMR_JTAG_RST_B_SHIFT (9U) +/*! JTAG_RST_B - JTAG_RST_B trigger mode configuration, locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_JTAG_RST_B_SHIFT)) & SRC_GENERAL_REG_SRTMR_JTAG_RST_B_MASK) +/*! @} */ + +/*! @name SRMASK - SRC RESET TRIGGER MODE REGISTER */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMASK_WDOG1_MASK_MASK (0x1U) +#define SRC_GENERAL_REG_SRMASK_WDOG1_MASK_SHIFT (0U) +/*! WDOG1_MASK - WDOG1 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG1_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG1_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG2_MASK_MASK (0x2U) +#define SRC_GENERAL_REG_SRMASK_WDOG2_MASK_SHIFT (1U) +/*! WDOG2_MASK - WDOG2 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG2_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG2_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG3_MASK_MASK (0x4U) +#define SRC_GENERAL_REG_SRMASK_WDOG3_MASK_SHIFT (2U) +/*! WDOG3_MASK - WDOG3 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG3_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG3_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG4_MASK_MASK (0x8U) +#define SRC_GENERAL_REG_SRMASK_WDOG4_MASK_SHIFT (3U) +/*! WDOG4_MASK - WDOG4 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG4_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG4_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG4_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG5_MASK_MASK (0x10U) +#define SRC_GENERAL_REG_SRMASK_WDOG5_MASK_SHIFT (4U) +/*! WDOG5_MASK - WDOG5 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG5_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG5_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG5_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_MASK (0x20U) +#define SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_SHIFT (5U) +/*! TEMPSENSE_MASK - Tempsense reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_CSU_MASK_MASK (0x40U) +#define SRC_GENERAL_REG_SRMASK_CSU_MASK_SHIFT (6U) +/*! CSU_MASK - CSU reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_CSU_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_CSU_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_CSU_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_MASK (0x80U) +#define SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_SHIFT (7U) +/*! JTAGSW_MASK - JTAG SW reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_JTAGSW_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_MASK (0x200U) +#define SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_SHIFT (9U) +/*! JTAG_RST_B_MASK - JTAG_RST_B mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_MASK) +/*! @} */ + +/*! @name SRMR1 - SRC RESET MODE REGISTER 1 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_SHIFT (0U) +/*! WDOG1_RESET_MODE - WDOG1 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_SHIFT (16U) +/*! WDOG2_RESET_MODE - WDOG2 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_MASK) +/*! @} */ + +/*! @name SRMR2 - SRC RESET MODE REGISTER 2 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_SHIFT (0U) +/*! WDOG3_RESET_MODE - WDOG3 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_SHIFT (16U) +/*! WDOG4_RESET_MODE - WDOG4 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_MASK) +/*! @} */ + +/*! @name SRMR3 - SRC RESET MODE REGISTER 3 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_SHIFT (0U) +/*! WDOG5_RESET_MODE - WDOG5 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_SHIFT (16U) +/*! TEMPSENSE_RESET_MODE - Tempsense reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_MASK) +/*! @} */ + +/*! @name SRMR4 - SRC RESET MODE REGISTER 4 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_SHIFT (0U) +/*! CSU_RESET_MODE - CSU reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_SHIFT (16U) +/*! JTAGSW_RESET_MODE - JTAG SW reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SBMR1_BOOT_CFG0_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_SBMR1_BOOT_CFG0_SHIFT (0U) +/*! BOOT_CFG0 - This bit field stores the BOOT_CFG8 fuse values. Please refer to the Fusemap for the fuse details. */ +#define SRC_GENERAL_REG_SBMR1_BOOT_CFG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR1_BOOT_CFG0_SHIFT)) & SRC_GENERAL_REG_SBMR1_BOOT_CFG0_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SBMR2_BOOT_CFG1_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SBMR2_BOOT_CFG1_SHIFT (0U) +/*! BOOT_CFG1 - This bit field stores the BOOT_CFG0[15:0] fuse values. Please refer to the Fusemap for the fuse details. */ +#define SRC_GENERAL_REG_SBMR2_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_BOOT_CFG1_SHIFT)) & SRC_GENERAL_REG_SBMR2_BOOT_CFG1_MASK) + +#define SRC_GENERAL_REG_SBMR2_SDP_DIS_MASK (0x10000U) +#define SRC_GENERAL_REG_SBMR2_SDP_DIS_SHIFT (16U) +/*! SDP_DIS - Please see the fusemap for fuse details. */ +#define SRC_GENERAL_REG_SBMR2_SDP_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_SDP_DIS_SHIFT)) & SRC_GENERAL_REG_SBMR2_SDP_DIS_MASK) + +#define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_MASK (0x3F000000U) +#define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_SHIFT (24U) +/*! IPP_BOOT_MODE - Boot mode from pins */ +#define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_MASK) + +#define SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_MASK (0x80000000U) +#define SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_SHIFT (31U) +/*! DIT_BT_DIS - Please see the fusemap for fuse details. */ +#define SRC_GENERAL_REG_SBMR2_DIT_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_SHIFT)) & SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRSR_SRC_POR_B_MASK (0x1U) +#define SRC_GENERAL_REG_SRSR_SRC_POR_B_SHIFT (0U) +/*! SRC_POR_B - Indicates whether the reset was the result of the system_por_b or jtag_rst_b. + * 0b0..Reset is not caused by system_por_b or jtag_rst_b event. + * 0b1..Reset is caused by system_por_b or jtag_rst_b event. + */ +#define SRC_GENERAL_REG_SRSR_SRC_POR_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_SRC_POR_B_SHIFT)) & SRC_GENERAL_REG_SRSR_SRC_POR_B_MASK) + +#define SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_MASK (0x4U) +#define SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_SHIFT (2U) +/*! IPP_USER_RESET_B - Indicates whether the reset was the result of ipp_user_reset_b. + * 0b0..Reset is not caused by IPP_USER_RESET_B. + * 0b1..Reset is caused by IPP_USER_RESET_B. + */ +#define SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG1_RST_B_MASK (0x8U) +#define SRC_GENERAL_REG_SRSR_WDOG1_RST_B_SHIFT (3U) +/*! WDOG1_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog1 time-out event. + * 0b0..Reset is not caused by the watchdog1 time-out event. + * 0b1..Reset is caused by the watchdog1 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG1_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG1_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG1_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG2_RST_B_MASK (0x10U) +#define SRC_GENERAL_REG_SRSR_WDOG2_RST_B_SHIFT (4U) +/*! WDOG2_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog2 time-out event. + * 0b0..Reset is not caused by the watchdog2 time-out event. + * 0b1..Reset is caused by the watchdog2 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG2_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG2_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG2_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG3_RST_B_MASK (0x20U) +#define SRC_GENERAL_REG_SRSR_WDOG3_RST_B_SHIFT (5U) +/*! WDOG3_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog3 time-out + * 0b0..Reset is not caused by the watchdog3 time-out event. + * 0b1..Reset is caused by the watchdog3 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG3_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG3_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG4_RST_B_MASK (0x40U) +#define SRC_GENERAL_REG_SRSR_WDOG4_RST_B_SHIFT (6U) +/*! WDOG4_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog4 time-out + * 0b0..Reset is not caused by the watchdog4 time-out event. + * 0b1..Reset is caused by the watchdog4 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG4_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG4_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG4_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG5_RST_B_MASK (0x80U) +#define SRC_GENERAL_REG_SRSR_WDOG5_RST_B_SHIFT (7U) +/*! WDOG5_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog5 time-out + * 0b0..Reset is not caused by the watchdog5 time-out event. + * 0b1..Reset is caused by the watchdog5 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG5_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG5_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG5_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! TEMPSENSE_RST_B - Temper Sensor software reset. Indicates whether the reset was the result of Temperature Sensor. + * 0b0..Reset is not caused by Temperature Sensor. + * 0b1..Reset is caused by Temperature Sensor. + */ +#define SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_CSU_RESET_B_MASK (0x200U) +#define SRC_GENERAL_REG_SRSR_CSU_RESET_B_SHIFT (9U) +/*! CSU_RESET_B - Indicates whether the reset was the result of the csu_reset_b input. + * 0b0..Reset is not caused by the csu_reset_b event. + * 0b1..Reset is caused by the csu_reset_b event. + */ +#define SRC_GENERAL_REG_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_CSU_RESET_B_SHIFT)) & SRC_GENERAL_REG_SRSR_CSU_RESET_B_MASK) + +#define SRC_GENERAL_REG_SRSR_JTAG_SW_RST_MASK (0x400U) +#define SRC_GENERAL_REG_SRSR_JTAG_SW_RST_SHIFT (10U) +/*! JTAG_SW_RST - JTAG software reset. Indicates whether the reset was the result of JTAG_SW_RST. + * 0b0..Reset is not caused by JTAG_SW_RST. + * 0b1..Reset is caused by JTAG_SW_RST. + */ +#define SRC_GENERAL_REG_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_JTAG_SW_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_JTAG_SW_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_JTAG_RST_B_MASK (0x1000U) +#define SRC_GENERAL_REG_SRSR_JTAG_RST_B_SHIFT (12U) +/*! JTAG_RST_B - Indicates a reset has been caused by JTAG_RST_B + * 0b0..Reset is not caused by JTAG_RST_B. + * 0b1..Reset is caused by JTAG_RST_B. + */ +#define SRC_GENERAL_REG_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_JTAG_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_JTAG_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_AONMIX_RST_MASK (0x10000U) +#define SRC_GENERAL_REG_SRSR_AONMIX_RST_SHIFT (16U) +/*! AONMIX_RST - Indicates whether a AONMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..AONMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_AONMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_AONMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_AONMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_MASK (0x20000U) +#define SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_SHIFT (17U) +/*! WAKEUPMIX_RST - Indicates whether a WAKEUPMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..WAKEUPMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_DDRMIX_RST_MASK (0x40000U) +#define SRC_GENERAL_REG_SRSR_DDRMIX_RST_SHIFT (18U) +/*! DDRMIX_RST - Indicates whether a DDRMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..DDRMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_DDRMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_DDRMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_DDRMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_DDRPHY_RST_MASK (0x80000U) +#define SRC_GENERAL_REG_SRSR_DDRPHY_RST_SHIFT (19U) +/*! DDRPHY_RST - Indicates whether a DDRPHY slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..DDRPHY slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_DDRPHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_DDRPHY_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_DDRPHY_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_NICMIX_RST_MASK (0x200000U) +#define SRC_GENERAL_REG_SRSR_NICMIX_RST_SHIFT (21U) +/*! NICMIX_RST - Indicates whether a NICMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..NICMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_NICMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_NICMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_NICMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_HSIOMIX_RST_MASK (0x400000U) +#define SRC_GENERAL_REG_SRSR_HSIOMIX_RST_SHIFT (22U) +/*! HSIOMIX_RST - Indicates whether a HSIOMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..HSIOMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_HSIOMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_HSIOMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_HSIOMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_MASK (0x800000U) +#define SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_SHIFT (23U) +/*! MEDIAMIX_RST - Indicates whether a MEDIAMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..MEDIAMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_MEDIAMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_A55C0MIX_RST_MASK (0x2000000U) +#define SRC_GENERAL_REG_SRSR_A55C0MIX_RST_SHIFT (25U) +/*! A55C0MIX_RST - Indicates whether a A55C0MIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..A55C0MIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_A55C0MIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_A55C0MIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_A55C0MIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_A55PMIX_RST_MASK (0x8000000U) +#define SRC_GENERAL_REG_SRSR_A55PMIX_RST_SHIFT (27U) +/*! A55PMIX_RST - Indicates whether a A55PMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..A55PMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_A55PMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_A55PMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_A55PMIX_RST_MASK) +/*! @} */ + +/*! @name GPR1 - SRC General Purpose Register 1 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR1_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR1_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR1_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR1_GPR_SHIFT)) & SRC_GENERAL_REG_GPR1_GPR_MASK) +/*! @} */ + +/*! @name GPR2 - SRC General Purpose Register 2 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR2_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR2_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR2_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR2_GPR_SHIFT)) & SRC_GENERAL_REG_GPR2_GPR_MASK) +/*! @} */ + +/*! @name GPR3 - SRC General Purpose Register 3 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR3_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR3_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR3_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR3_GPR_SHIFT)) & SRC_GENERAL_REG_GPR3_GPR_MASK) +/*! @} */ + +/*! @name GPR4 - SRC General Purpose Register 4 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR4_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR4_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR4_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR4_GPR_SHIFT)) & SRC_GENERAL_REG_GPR4_GPR_MASK) +/*! @} */ + +/*! @name GPR5 - SRC General Purpose Register 5 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR5_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR5_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR5_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR5_GPR_SHIFT)) & SRC_GENERAL_REG_GPR5_GPR_MASK) +/*! @} */ + +/*! @name GPR6 - SRC General Purpose Register 6 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR6_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR6_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR6_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR6_GPR_SHIFT)) & SRC_GENERAL_REG_GPR6_GPR_MASK) +/*! @} */ + +/*! @name GPR7 - SRC General Purpose Register 7 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR7_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR7_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR7_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR7_GPR_SHIFT)) & SRC_GENERAL_REG_GPR7_GPR_MASK) +/*! @} */ + +/*! @name GPR8 - SRC General Purpose Register 8 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR8_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR8_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR8_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR8_GPR_SHIFT)) & SRC_GENERAL_REG_GPR8_GPR_MASK) +/*! @} */ + +/*! @name GPR9 - SRC General Purpose Register 9 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR9_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR9_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR9_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR9_GPR_SHIFT)) & SRC_GENERAL_REG_GPR9_GPR_MASK) +/*! @} */ + +/*! @name GPR10 - SRC General Purpose Register 10 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR10_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR10_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR10_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR10_GPR_SHIFT)) & SRC_GENERAL_REG_GPR10_GPR_MASK) +/*! @} */ + +/*! @name GPR11 - SRC General Purpose Register 11 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR11_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR11_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR11_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR11_GPR_SHIFT)) & SRC_GENERAL_REG_GPR11_GPR_MASK) +/*! @} */ + +/*! @name GPR12 - SRC General Purpose Register 12 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR12_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR12_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR12_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR12_GPR_SHIFT)) & SRC_GENERAL_REG_GPR12_GPR_MASK) +/*! @} */ + +/*! @name GPR13 - SRC General Purpose Register 13 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR13_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR13_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR13_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR13_GPR_SHIFT)) & SRC_GENERAL_REG_GPR13_GPR_MASK) +/*! @} */ + +/*! @name GPR14 - SRC General Purpose Register 14 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR14_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR14_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR14_GPR_SHIFT)) & SRC_GENERAL_REG_GPR14_GPR_MASK) +/*! @} */ + +/*! @name GPR15 - SRC General Purpose Register 15 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR15_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR15_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR15_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR15_GPR_SHIFT)) & SRC_GENERAL_REG_GPR15_GPR_MASK) +/*! @} */ + +/*! @name GPR16 - SRC General Purpose Register 16 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR16_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR16_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR16_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR16_GPR_SHIFT)) & SRC_GENERAL_REG_GPR16_GPR_MASK) +/*! @} */ + +/*! @name GPR17 - SRC General Purpose Register 17 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR17_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR17_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR17_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR17_GPR_SHIFT)) & SRC_GENERAL_REG_GPR17_GPR_MASK) +/*! @} */ + +/*! @name GPR18 - SRC General Purpose Register 18 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR18_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR18_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR18_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR18_GPR_SHIFT)) & SRC_GENERAL_REG_GPR18_GPR_MASK) +/*! @} */ + +/*! @name GPR19 - SRC General Purpose Register 19 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR19_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR19_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR19_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR19_GPR_SHIFT)) & SRC_GENERAL_REG_GPR19_GPR_MASK) +/*! @} */ + +/*! @name GPR20 - SRC General Purpose Register 20 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_MASK (0x1U) +#define SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_SHIFT (0U) +/*! ANAMIX_ATX_SENSE_BUS_ENABLE_LV - ANAMIX ATX sense bus enable */ +#define SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_SHIFT)) & SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_MASK) + +#define SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_MASK (0x1EU) +#define SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_SHIFT (1U) +/*! ANAMIX_PLL_CLK_MUX - ANAMIX PLL clock mux */ +#define SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_SHIFT)) & SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_MASK) + +#define SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_MASK (0x60U) +#define SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_SHIFT (5U) +/*! ANAMIX_REF_SEL - ANAMIX reference clock select + * 0b00..OSC24M + * 0b01..CLKIN1 + * 0b10..CLKIN2 + * 0b11..Reserved + */ +#define SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_SHIFT)) & SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_MASK) + +#define SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_MASK (0x180U) +#define SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_SHIFT (7U) +/*! CCM_24MCLK_SEL - ANAMIX reference clock select + * 0b00..OSC24M + * 0b01..CLKIN1 + * 0b10..CLKIN2 + * 0b11..CLKIN1 or CLKIN2 + */ +#define SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_SHIFT)) & SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_MASK) + +#define SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_MASK (0x200U) +#define SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_SHIFT (9U) +/*! CLKIN1_ENABLE - CLKIN1 input buffer enable + * 0b0..Input buffer disable + * 0b1..Input buffer enabled. Needed to enable CLKIN1 as an input. + */ +#define SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_SHIFT)) & SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_MASK) + +#define SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_MASK (0x400U) +#define SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_SHIFT (10U) +/*! CLKIN2_ENABLE - CLKIN2 input buffer enable + * 0b0..Input buffer disable + * 0b1..Input buffer enabled. Needed to enable CLKIN2 as an input. + */ +#define SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_SHIFT)) & SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_MASK) +/*! @} */ + +/*! @name COLD_RESET_SSAR_ACK_CTRL - Cold reset SSAR acknowledge control */ +/*! @{ */ + +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK (0x3FFFU) +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT (0U) +/*! SSAR_CNT_CFG - ssar count configure. Usage depends on CNT_MODE, locked by LOCK_CFG field */ +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT)) & SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK) + +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field + * 0b00..Not use counter, raise done to cold_reset_controller once get EdgeLock Enclave ack + * 0b01..Delay after receiving EdgeLock Enclave ack, delay cycle number is CNT_CFG + * 0b10..Ignore EdgeLock Enclave ack, raise done to cold_reset_controller when counting to CNT_CFG value + * 0b11..Time out mode, raise done to cold_reset_controller when either EdgeLock Enclave ack received or counting to CNT_CFG value + */ +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name SP_ISO_CTRL - SRC special ISO Control */ +/*! @{ */ + +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_MASK (0x1U) +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_SHIFT (0U) +/*! USB_PHY1_ISO - Software control USB PHY1 isolation enable + * 0b0..Isolation disable + * 0b1..Isolation enable + */ +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_SHIFT)) & SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_MASK) + +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_MASK (0x2U) +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_SHIFT (1U) +/*! USB_PHY2_ISO - Software control USB PHY2 isolation enable + * 0b0..Isolation disable + * 0b1..Isolation enable + */ +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_SHIFT)) & SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_MASK) +/*! @} */ + +/*! @name ROM_LP_CTRL - ROM Low Power Control */ +/*! @{ */ + +#define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_MASK (0x1U) +#define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_SHIFT (0U) +/*! AONMIX_ROM_LP_EN - ROM in AONMIX low power control enable */ +#define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_SHIFT)) & SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_MASK) +/*! @} */ + +/*! @name A55_DENY_STAT - A55 Q_Channel Deny Status */ +/*! @{ */ + +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_MASK (0x1U) +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_SHIFT (0U) +/*! A55_CORE0_PWRDN_DENY_STAT - A55 CORE 0 Q_Channel pwrdn deny status */ +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_MASK) + +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_MASK (0x4U) +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_SHIFT (2U) +/*! A55_CLUSTER_PWRDN_DENY_STAT - A55 Cluster Q_Channel pwrdn deny status */ +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_MASK) + +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_MASK (0x8U) +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_SHIFT (3U) +/*! A55_CLUSTER_CLKOFF_DENY_STAT - A55 Cluster Q_Channel clockoff deny status */ +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRC_GENERAL_REG_Register_Masks */ + + +/* SRC_GENERAL_REG - Peripheral instance base addresses */ +/** Peripheral SRC__SRC_GENERAL_REG base address */ +#define SRC__SRC_GENERAL_REG_BASE (0x44460000u) +/** Peripheral SRC__SRC_GENERAL_REG base pointer */ +#define SRC__SRC_GENERAL_REG ((SRC_GENERAL_REG_Type *)SRC__SRC_GENERAL_REG_BASE) +/** Array initializer of SRC_GENERAL_REG peripheral base addresses */ +#define SRC_GENERAL_REG_BASE_ADDRS { SRC__SRC_GENERAL_REG_BASE } +/** Array initializer of SRC_GENERAL_REG peripheral base pointers */ +#define SRC_GENERAL_REG_BASE_PTRS { SRC__SRC_GENERAL_REG } + +/*! + * @} + */ /* end of group SRC_GENERAL_REG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC_MEM_SLICE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MEM_SLICE_Peripheral_Access_Layer SRC_MEM_SLICE Peripheral Access Layer + * @{ + */ + +/** SRC_MEM_SLICE - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t MEM_CTRL; /**< MEM Low Power Control, offset: 0x4 */ + __IO uint32_t MEMLP_CTRL_0; /**< MEM Low Power Control_0, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MEMLP_CTRL_1; /**< MEM Low Power Control_1, offset: 0x10 */ + __IO uint32_t MEMLP_CTRL_2; /**< MEM Low Power Control_2, offset: 0x14 */ + __I uint32_t MEM_STAT; /**< MEM Status, offset: 0x18 */ +} SRC_MEM_SLICE_Type; + +/* ---------------------------------------------------------------------------- + -- SRC_MEM_SLICE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MEM_SLICE_Register_Masks SRC_MEM_SLICE Register Masks + * @{ + */ + +/*! @name MEM_CTRL - MEM Low Power Control */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_MASK (0x1U) +#define SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_SHIFT (0U) +/*! SW_MEM_CTRL - Software control MEM low power + * 0b0..software control MEM to exit low power + * 0b1..software control MEM to enter low power + */ +#define SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_MASK (0x2U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_SHIFT (1U) +/*! MEM_LP_MODE - MEM low power mode. Locked by LOCK_CFG field. + * 0b0..Power down mode + * 0b1..Retention mode + */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_MASK (0x4U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_SHIFT (2U) +/*! MEM_LP_EN - Enable MEM low power control. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_MASK (0xFF00U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_SHIFT (8U) +/*! MEM_LF_CNT_CFG - MEM power up counter */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_MASK (0xFF0000U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_SHIFT (16U) +/*! MEM_HF_CNT_CFG - MEM power up counter */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_MASK (0x1000000U) +#define SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_SHIFT (24U) +/*! LOCK_CFG - Configuration lock + * 0b0..Not locked. + * 0b1..Locked. + */ +#define SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_MASK) +/*! @} */ + +/*! @name MEMLP_CTRL_0 - MEM Low Power Control_0 */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_MASK (0xFFFFFFFFU) +#define SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_SHIFT (0U) +/*! MEMLP_ENT_CNT - Delay counter to start entering to memory low power mode. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_SHIFT)) & SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_MASK) +/*! @} */ + +/*! @name MEMLP_CTRL_1 - MEM Low Power Control_1 */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_MASK (0xFFFFFFFFU) +#define SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_SHIFT (0U) +/*! MEMLP_RET_PGEN_CNT - Delay counter to interval for retn to pgen. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_SHIFT)) & SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_MASK) +/*! @} */ + +/*! @name MEMLP_CTRL_2 - MEM Low Power Control_2 */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_MASK (0xFFFFFFFFU) +#define SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_SHIFT (0U) +/*! MEMLP_EXT_CNT - Delay counter to start exiting from memory low power mode. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_SHIFT)) & SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_MASK) +/*! @} */ + +/*! @name MEM_STAT - MEM Status */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_MASK (0xFU) +#define SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_SHIFT (0U) +/*! MEM_FSM_STAT - MEM FSM status */ +#define SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_MASK (0x10U) +#define SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_SHIFT (4U) +/*! RET2N_STAT - RET2N status */ +#define SRC_MEM_SLICE_MEM_STAT_RET2N_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_MASK (0x20U) +#define SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_SHIFT (5U) +/*! RET1N_STAT - RET1N status */ +#define SRC_MEM_SLICE_MEM_STAT_RET1N_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_MASK (0x40U) +#define SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_SHIFT (6U) +/*! PGEN_STAT - PGEN status */ +#define SRC_MEM_SLICE_MEM_STAT_PGEN_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_MEM_STAT_MASK (0x100U) +#define SRC_MEM_SLICE_MEM_STAT_MEM_STAT_SHIFT (8U) +/*! MEM_STAT - MEM status + * 0b0..MEM exit low power + * 0b1..MEM enter low power - rentention1 mode or power down mode + */ +#define SRC_MEM_SLICE_MEM_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_MEM_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_MEM_STAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRC_MEM_SLICE_Register_Masks */ + + +/* SRC_MEM_SLICE - Peripheral instance base addresses */ +/** Peripheral SRC__SRC_A55C0_MEM base address */ +#define SRC__SRC_A55C0_MEM_BASE (0x44465C00u) +/** Peripheral SRC__SRC_A55C0_MEM base pointer */ +#define SRC__SRC_A55C0_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_A55C0_MEM_BASE) +/** Peripheral SRC__SRC_A55_SCU_MEM base address */ +#define SRC__SRC_A55_SCU_MEM_BASE (0x44466400u) +/** Peripheral SRC__SRC_A55_SCU_MEM base pointer */ +#define SRC__SRC_A55_SCU_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_A55_SCU_MEM_BASE) +/** Peripheral SRC__SRC_AON_MEM base address */ +#define SRC__SRC_AON_MEM_BASE (0x44463800u) +/** Peripheral SRC__SRC_AON_MEM base pointer */ +#define SRC__SRC_AON_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_AON_MEM_BASE) +/** Peripheral SRC__SRC_DDR_MEM base address */ +#define SRC__SRC_DDR_MEM_BASE (0x44464000u) +/** Peripheral SRC__SRC_DDR_MEM base pointer */ +#define SRC__SRC_DDR_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_DDR_MEM_BASE) +/** Peripheral SRC__SRC_DPHY_MEM base address */ +#define SRC__SRC_DPHY_MEM_BASE (0x44464400u) +/** Peripheral SRC__SRC_DPHY_MEM base pointer */ +#define SRC__SRC_DPHY_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_DPHY_MEM_BASE) +/** Peripheral SRC__SRC_HSIO_MEM base address */ +#define SRC__SRC_HSIO_MEM_BASE (0x44465400u) +/** Peripheral SRC__SRC_HSIO_MEM base pointer */ +#define SRC__SRC_HSIO_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_HSIO_MEM_BASE) +/** Peripheral SRC__SRC_MEDIA_MEM base address */ +#define SRC__SRC_MEDIA_MEM_BASE (0x44465800u) +/** Peripheral SRC__SRC_MEDIA_MEM base pointer */ +#define SRC__SRC_MEDIA_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_MEDIA_MEM_BASE) +/** Peripheral SRC__SRC_NIC_MEM base address */ +#define SRC__SRC_NIC_MEM_BASE (0x44464C00u) +/** Peripheral SRC__SRC_NIC_MEM base pointer */ +#define SRC__SRC_NIC_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_NIC_MEM_BASE) +/** Peripheral SRC__SRC_NIC_OCRAM base address */ +#define SRC__SRC_NIC_OCRAM_BASE (0x44465000u) +/** Peripheral SRC__SRC_NIC_OCRAM base pointer */ +#define SRC__SRC_NIC_OCRAM ((SRC_MEM_SLICE_Type *)SRC__SRC_NIC_OCRAM_BASE) +/** Peripheral SRC__SRC_WKUP_MEM base address */ +#define SRC__SRC_WKUP_MEM_BASE (0x44463C00u) +/** Peripheral SRC__SRC_WKUP_MEM base pointer */ +#define SRC__SRC_WKUP_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_WKUP_MEM_BASE) +/** Array initializer of SRC_MEM_SLICE peripheral base addresses */ +#define SRC_MEM_SLICE_BASE_ADDRS { SRC__SRC_A55C0_MEM_BASE, SRC__SRC_A55_SCU_MEM_BASE, SRC__SRC_AON_MEM_BASE, SRC__SRC_DDR_MEM_BASE, SRC__SRC_DPHY_MEM_BASE, SRC__SRC_HSIO_MEM_BASE, SRC__SRC_MEDIA_MEM_BASE, SRC__SRC_NIC_MEM_BASE, SRC__SRC_NIC_OCRAM_BASE, SRC__SRC_WKUP_MEM_BASE } +/** Array initializer of SRC_MEM_SLICE peripheral base pointers */ +#define SRC_MEM_SLICE_BASE_PTRS { SRC__SRC_A55C0_MEM, SRC__SRC_A55_SCU_MEM, SRC__SRC_AON_MEM, SRC__SRC_DDR_MEM, SRC__SRC_DPHY_MEM, SRC__SRC_HSIO_MEM, SRC__SRC_MEDIA_MEM, SRC__SRC_NIC_MEM, SRC__SRC_NIC_OCRAM, SRC__SRC_WKUP_MEM } + +/*! + * @} + */ /* end of group SRC_MEM_SLICE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC_MIX_SLICE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MIX_SLICE_Peripheral_Access_Layer SRC_MIX_SLICE Peripheral Access Layer + * @{ + */ + +/** SRC_MIX_SLICE - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t AUTHEN_CTRL; /**< Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t LPM_SETTING_0; /**< Low power mode setting, offset: 0x10 */ + __IO uint32_t LPM_SETTING_1; /**< Low power mode setting, offset: 0x14 */ + __IO uint32_t LPM_SETTING_2; /**< Low power mode setting, offset: 0x18 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SLICE_SW_CTRL; /**< Slice software control, offset: 0x20 */ + __IO uint32_t SINGLE_RESET_SW_CTRL; /**< Single reset by software control, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t A55_HDSK_ACK_CTRL; /**< A55 handshake acknowledge control, offset: 0x40 */ + __I uint32_t A55_HDSK_ACK_STAT; /**< A55 handshake acknowledge status, offset: 0x44 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SSAR_ACK_CTRL; /**< SSAR acknowledge control, offset: 0x50 */ + __I uint32_t SSAR_ACK_STAT; /**< SSAR acknowledge status, offset: 0x54 */ + uint8_t RESERVED_5[4]; + __IO uint32_t ISO_OFF_DLY_POR; /**< iso off delay control when por, offset: 0x5C */ + __IO uint32_t ISO_ON_DLY; /**< iso on delay control, offset: 0x60 */ + __IO uint32_t ISO_OFF_DLY; /**< iso off delay control, offset: 0x64 */ + __IO uint32_t PSW_OFF_LF_DLY; /**< psw off lf delay control, offset: 0x68 */ + uint8_t RESERVED_6[4]; + __IO uint32_t PSW_OFF_HF_DLY; /**< psw off hf delay control, offset: 0x70 */ + __IO uint32_t PSW_ON_LF_DLY; /**< psw on lf delay control, offset: 0x74 */ + __IO uint32_t PSW_ON_HF_DLY; /**< psw on hf delay control, offset: 0x78 */ + uint8_t RESERVED_7[4]; + __IO uint32_t PSW_ACK_CTRL_0; /**< Power switch acknowledge control, offset: 0x80 */ + __IO uint32_t PSW_ACK_CTRL_1; /**< Power switch acknowledge control, offset: 0x84 */ + __I uint32_t PSW_ACK_STAT; /**< PSW acknowledge status, offset: 0x88 */ + uint8_t RESERVED_8[4]; + __IO uint32_t MTR_ACK_CTRL; /**< MTR acknowledge control, offset: 0x90 */ + __I uint32_t MTR_ACK_STAT; /**< MTR acknowledge status, offset: 0x94 */ + uint8_t RESERVED_9[8]; + __I uint32_t UPI_STAT_0; /**< UPI status 0, offset: 0xA0 */ + __I uint32_t UPI_STAT_1; /**< UPI status 1, offset: 0xA4 */ + __I uint32_t UPI_STAT_2; /**< UPI status 2, offset: 0xA8 */ + __I uint32_t UPI_STAT_3; /**< UPI status 3, offset: 0xAC */ + __I uint32_t FSM_STAT; /**< FSM status, offset: 0xB0 */ + __I uint32_t FUNC_STAT; /**< function status, offset: 0xB4 */ +} SRC_MIX_SLICE_Type; + +/* ---------------------------------------------------------------------------- + -- SRC_MIX_SLICE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MIX_SLICE_Register_Masks SRC_MIX_SLICE Register Masks + * @{ + */ + +/*! @name AUTHEN_CTRL - Authentication Control */ +/*! @{ */ + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_MASK (0x4U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_SHIFT (2U) +/*! LPM_MODE - Low power control mode + * 0b0..Low power mode controlled by software + * 0b1..Low power mode controlled by GPC hardware + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..Low power configuration fields are not locked. + * 0b1..Low power configuration fields are locked. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_MASK (0x100U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_SHIFT (8U) +/*! TZ_USER - Allow user mode access + * 0b0..This MIX SLICE registers can only be written in privilege mode. + * 0b1..This MIX SLICE registers can be written either in privilege mode or user mode. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_MASK (0x200U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_SHIFT (9U) +/*! TZ_NS - Allow non-secure mode access + * 0b0..This MIX SLICE registers can only be written in secure mode. + * 0b1..This MIX SLICE registers can be written either in secure mode or non-secure mode. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_MASK (0x800U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock NONSECURE and USER + * 0b0..TZ_NS and TZ_USER value can be changed. + * 0b1..TZ_NS and TZ_USER value cannot be changed. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST value can be changed. + * 0b1..WHITE_LIST value cannot be changed. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list + * 0b0000000000000001..Core with domain ID=0 can write SRC MIX SLICE registers. + * 0b0000000000000010..Core with domain ID=1 can write SRC MIX SLICE registers. + * 0b0000000000000100..Core with domain ID=2 can write SRC MIX SLICE registers. + * 0b0000000000001000..Core with domain ID=3 can write SRC MIX SLICE registers. + * 0b0000000000010000..Core with domain ID=4 can write SRC MIX SLICE registers. + * 0b0000000000100000..Core with domain ID=5 can write SRC MIX SLICE registers. + * 0b0000000001000000..Core with domain ID=6 can write SRC MIX SLICE registers. + * 0b0000000010000000..Core with domain ID=7 can write SRC MIX SLICE registers. + * 0b0000000100000000..Core with domain ID=8 can write SRC MIX SLICE registers. + * 0b0000001000000000..Core with domain ID=9 can write SRC MIX SLICE registers. + * 0b0000010000000000..Core with domain ID=10 can write SRC MIX SLICE registers. + * 0b0000100000000000..Core with domain ID=11 can write SRC MIX SLICE registers. + * 0b0001000000000000..Core with domain ID=12 can write SRC MIX SLICE registers. + * 0b0010000000000000..Core with domain ID=13 can write SRC MIX SLICE registers. + * 0b0100000000000000..Core with domain ID=14 can write SRC MIX SLICE registers. + * 0b1000000000000000..Core with domain ID=15 can write SRC MIX SLICE registers. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name LPM_SETTING_0 - Low power mode setting */ +/*! @{ */ + +#define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_MASK (0x7U) +#define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_SHIFT (0U) +/*! LPM_SETTING_CD - LPM setting of current domain + * 0b000..Power always off + * 0b001..Power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..Power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..Power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..Power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_MASK) +/*! @} */ + +/*! @name LPM_SETTING_1 - Low power mode setting */ +/*! @{ */ + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_MASK (0x7U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_SHIFT (0U) +/*! LPM_SETTING_D0 - LPM setting of domain 0 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_MASK (0x70U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_SHIFT (4U) +/*! LPM_SETTING_D1 - LPM setting of domain 1 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_MASK (0x700U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_SHIFT (8U) +/*! LPM_SETTING_D2 - LPM setting of domain 2 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_MASK (0x7000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_SHIFT (12U) +/*! LPM_SETTING_D3 - LPM setting of domain 3 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_MASK (0x70000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_SHIFT (16U) +/*! LPM_SETTING_D4 - LPM setting of domain 4 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_MASK (0x700000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_SHIFT (20U) +/*! LPM_SETTING_D5 - LPM setting of domain 5 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_MASK (0x7000000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_SHIFT (24U) +/*! LPM_SETTING_D6 - LPM setting of domain 6 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_MASK (0x70000000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_SHIFT (28U) +/*! LPM_SETTING_D7 - LPM setting of domain 7 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_MASK) +/*! @} */ + +/*! @name LPM_SETTING_2 - Low power mode setting */ +/*! @{ */ + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_MASK (0x7U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_SHIFT (0U) +/*! LPM_SETTING_D8 - LPM setting of domain 8 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_MASK (0x70U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_SHIFT (4U) +/*! LPM_SETTING_D9 - LPM setting of domain 9 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_MASK (0x700U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_SHIFT (8U) +/*! LPM_SETTING_D10 - LPM setting of domain 10 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_MASK (0x7000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_SHIFT (12U) +/*! LPM_SETTING_D11 - LPM setting of domain 11 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_MASK (0x70000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_SHIFT (16U) +/*! LPM_SETTING_D12 - LPM setting of domain 12 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_MASK (0x700000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_SHIFT (20U) +/*! LPM_SETTING_D13 - LPM setting of domain 13 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_MASK (0x7000000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_SHIFT (24U) +/*! LPM_SETTING_D14 - LPM setting of domain 14 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_MASK (0x70000000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_SHIFT (28U) +/*! LPM_SETTING_D15 - LPM setting of domain 15 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_MASK) +/*! @} */ + +/*! @name SLICE_SW_CTRL - Slice software control */ +/*! @{ */ + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_MASK (0x1U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_SHIFT (0U) +/*! RST_CTRL_SOFT - Software reset control. Locked by LPM_MODE field. + * 0b0..No effect or software reset deassert + * 0b1..Software reset assert + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_MASK (0x4U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_SHIFT (2U) +/*! ISO_CTRL_SOFT - Software isolation control. Locked by LPM_MODE field. + * 0b0..No effect or software iso off + * 0b1..Software iso on + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_MASK (0x10U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_SHIFT (4U) +/*! PSW_CTRL_SOFT - Software power switch control. Locked by LPM_MODE field. + * 0b0..No effect or software power switch on + * 0b1..Software power switch off + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_MASK (0x40U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_SHIFT (6U) +/*! MTR_LOAD_SOFT - Software control MTR repair load. Locked by LPM_MODE field. + * 0b0..No effect + * 0b1..Software load MTR repair + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_MASK (0x100U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_SHIFT (8U) +/*! SSAR_CTRL_SOFT - Software SSAR control. Locked by LPM_MODE field. + * 0b0..No effect or software SSAR restore + * 0b1..Software SSAR save + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_MASK (0x400U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_SHIFT (10U) +/*! A55_HDSK_CTRL_SOFT - Software A55 handshake control. Locked by LPM_MODE field. + * 0b0..No effect or software notify A55 power up info + * 0b1..Software notify A55 power down info + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_MASK (0x80000000U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_SHIFT (31U) +/*! PDN_SOFT - Software power trans control, including reset, iso, and power switch. Locked by LPM_MODE field. + * 0b0..No effect or software power up + * 0b1..Software power down + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_MASK) +/*! @} */ + +/*! @name SINGLE_RESET_SW_CTRL - Single reset by software control */ +/*! @{ */ + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_MASK (0x1U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_SHIFT (0U) +/*! RST_CTRL_SOFT_0 - Locked by LPM_MODE field. */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_MASK (0x4U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_SHIFT (2U) +/*! RST_CTRL_SOFT_1 - Locked by LPM_MODE field. */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_MASK (0x10U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_SHIFT (4U) +/*! RST_CTRL_SOFT_2 - Locked by LPM_MODE field. + * 0b0..Software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_MASK (0x40U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_SHIFT (6U) +/*! RST_CTRL_SOFT_3 - Locked by LPM_MODE field. + * 0b0..Software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_MASK (0x100U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_SHIFT (8U) +/*! RST_CTRL_SOFT_4 - Locked by LPM_MODE field. + * 0b0..Software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_MASK (0x400U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_SHIFT (10U) +/*! RST_CTRL_SOFT_5 - Locked by LPM_MODE field. + * 0b0..software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_MASK) +/*! @} */ + +/*! @name A55_HDSK_ACK_CTRL - A55 handshake acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_MASK (0xFFU) +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_SHIFT (0U) +/*! A55_HDSK_CNT_CFG - A55 handshake count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise a55_hdsk done to GPC once get A55 ack + * 0b01..Delay after receiving a55 ack, delay cycle number is CNT_CFG + * 0b10..Ignore A55 ack, raise a55_hdsk done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise a55_hdsk done to GPC when either A55 ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name A55_HDSK_ACK_STAT - A55 handshake acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_MASK (0xFFU) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_SHIFT (0U) +/*! PDN_ACK_CNT - A55 handshake power down acknowledge count. */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_MASK (0xFF0000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_SHIFT (16U) +/*! PUP_ACK_CNT - A55 handshake power up acknowledge count */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_MASK (0x40000000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_SHIFT (30U) +/*! BUSY_A55_PDN_HDSK - Busy requesting A55 power down handshake */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_MASK (0x80000000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_SHIFT (31U) +/*! BUSY_A55_PUP_HDSK - Busy requesting A55 power up handshake */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_MASK) +/*! @} */ + +/*! @name SSAR_ACK_CTRL - SSAR acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK (0x3FFFU) +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT (0U) +/*! SSAR_CNT_CFG - ssar count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise ssar_save/restore done to GPC once get Edgelock Enclave ack + * 0b01..Delay after receiving Edgelock Enclave ack, delay cycle number is CNT_CFG + * 0b10..Ignore Edgelock Enclave ack, raise ssar_save/restore done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise ssar_save/restore done to GPC when either Edgelock Enclave ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name SSAR_ACK_STAT - SSAR acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK (0x3FFFU) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT (0U) +/*! SAVE_ACK_CNT - SAVE acknowledge count, record the delay from stat change to acknowledge received */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK (0xFFFC000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT (14U) +/*! RESTORE_ACK_CNT - RESTORE acknowledge count, record the delay from stat change to acknowledge received */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_MASK (0x20000000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_SHIFT (29U) +/*! SAVED - Indicate this mix power down info have accepted Edgelock Enclave ack */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_MASK (0x40000000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_SHIFT (30U) +/*! BUSY_SAVED - Busy requesting SSAR save */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_MASK (0x80000000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_SHIFT (31U) +/*! BUSY_RESTORE - Busy requesting SSAR restore */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_MASK) +/*! @} */ + +/*! @name ISO_OFF_DLY_POR - iso off delay control when por */ +/*! @{ */ + +#define SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_SHIFT (0U) +/*! DLY_PRE_ISO_OFF_POR - Delay from receiving iso off request to isolation disable. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_SHIFT)) & SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_MASK) +/*! @} */ + +/*! @name ISO_ON_DLY - iso on delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_SHIFT (0U) +/*! DLY_PRE_ISO_ON - Delay from receiving iso_on request to isolation enable. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_SHIFT)) & SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_MASK) +/*! @} */ + +/*! @name ISO_OFF_DLY - iso off delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_SHIFT (0U) +/*! DLY_PRE_ISO_OFF - Delay from receiving iso off request to isolation disable. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_SHIFT)) & SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_MASK) +/*! @} */ + +/*! @name PSW_OFF_LF_DLY - psw off lf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_SHIFT (0U) +/*! DLY_PRE_PSW_OFF_LF - Delay from receiving power off lf request to power switch shut off. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_SHIFT)) & SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_MASK) +/*! @} */ + +/*! @name PSW_OFF_HF_DLY - psw off hf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_SHIFT (0U) +/*! DLY_PRE_PSW_OFF_HF - Delay from receiving power off hf request to power switch shut off. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_SHIFT)) & SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_MASK) +/*! @} */ + +/*! @name PSW_ON_LF_DLY - psw on lf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_SHIFT (0U) +/*! DLY_PRE_PSW_ON_LF - Delay from receiving power on lf request to power switch turns on. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_SHIFT)) & SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_MASK) +/*! @} */ + +/*! @name PSW_ON_HF_DLY - psw on hf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_SHIFT (0U) +/*! DLY_PRE_PSW_ON_HF - Delay from receiving power on lf request to power switch turns on. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_SHIFT)) & SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_MASK) +/*! @} */ + +/*! @name PSW_ACK_CTRL_0 - Power switch acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_MASK (0x3FFU) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_SHIFT (0U) +/*! PUP_LF_CNT_CFG - PUP LF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_MASK (0x3FF0000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_SHIFT (16U) +/*! PUP_HF_CNT_CFG - PUP HF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_MASK (0x30000000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise power_on/off done to GPC once get psw ack + * 0b01..Delay after receiving psw ack, delay cycle number is CNT_CFG + * 0b10..Ignore psw ack, raise power_on/off done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise power_on/off done to GPC when either psw ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_MASK (0x40000000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_SHIFT (30U) +/*! LF_ACK_INVERT - LF Acknowledge value is inverted from power switch control. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_MASK (0x80000000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_SHIFT (31U) +/*! HF_ACK_INVERT - HF Acknowledge value is inverted from power switch control. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_MASK) +/*! @} */ + +/*! @name PSW_ACK_CTRL_1 - Power switch acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_MASK (0x3FFU) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_SHIFT (0U) +/*! PDN_LF_CNT_CFG - PDN LF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_MASK (0x3FF0000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_SHIFT (16U) +/*! PDN_HF_CNT_CFG - PDN HF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_MASK) +/*! @} */ + +/*! @name PSW_ACK_STAT - PSW acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_MASK (0x3FFU) +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_SHIFT (0U) +/*! LF_ACK_CNT - LF PSW acknowledge count */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_MASK (0x3FF0000U) +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_SHIFT (16U) +/*! HF_ACK_CNT - HF PSW acknowledge count */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_MASK (0x40000000U) +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_SHIFT (30U) +/*! LF_ACK_STAT - LF PSW acknowledge status */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_MASK (0x80000000U) +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_SHIFT (31U) +/*! HF_ACK_STAT - HF PSW acknowledge status */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_MASK) +/*! @} */ + +/*! @name MTR_ACK_CTRL - MTR acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_MASK (0xFFU) +#define SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_SHIFT (0U) +/*! MTR_CNT_CFG - MTR count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise mtr done to GPC once get MTR ack + * 0b01..Delay after receiving MTR ack, delay cycle number is CNT_CFG + * 0b10..Ignore MTR ack, raise mtr done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise mtr done to GPC when either MTR ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name MTR_ACK_STAT - MTR acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_MASK (0xFFU) +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_SHIFT (0U) +/*! MTR_ACK_CNT - MTR acknowledge count, record the delay from stat change to acknowledge received */ +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_MASK (0x40000000U) +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_SHIFT (30U) +/*! MTR_DONE - Indicate MTR load repair finished */ +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_MASK) + +#define SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_MASK (0x80000000U) +#define SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_SHIFT (31U) +/*! BUSY_MTR - Busy requesting MTR */ +#define SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_MASK) +/*! @} */ + +/*! @name UPI_STAT_0 - UPI status 0 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT (0U) +/*! UPI_ISO_REQUEST - CPU mode trans iso request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_MASK) + +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_SHIFT (16U) +/*! UPI_POWER_REQUEST - CPU mode trans power request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_MASK) +/*! @} */ + +/*! @name UPI_STAT_1 - UPI status 1 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT (0U) +/*! UPI_RESET_REQUEST - CPU mode trans reset request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_MASK) + +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_SHIFT (16U) +/*! UPI_SSAR_REQUEST - CPU mode trans ssar request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_MASK) +/*! @} */ + +/*! @name UPI_STAT_2 - UPI status 2 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_SHIFT (0U) +/*! UPI_MTR_REQUEST - CPU mode trans mtr request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_MASK) + +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_SHIFT (16U) +/*! UPI_A55_HDSK_REQUEST - CPU mode trans A55 handshake request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_MASK) +/*! @} */ + +/*! @name UPI_STAT_3 - UPI status 3 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_SHIFT (0U) +/*! UPI_MEM_REQUEST - CPU mode trans mem request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_MASK) +/*! @} */ + +/*! @name FSM_STAT - FSM status */ +/*! @{ */ + +#define SRC_MIX_SLICE_FSM_STAT_PSW_STAT_MASK (0xFU) +#define SRC_MIX_SLICE_FSM_STAT_PSW_STAT_SHIFT (0U) +/*! PSW_STAT - Power switch FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_PSW_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_PSW_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_PSW_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_RST_STAT_MASK (0xF0U) +#define SRC_MIX_SLICE_FSM_STAT_RST_STAT_SHIFT (4U) +/*! RST_STAT - Reset FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_RST_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_RST_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_ISO_STAT_MASK (0xF00U) +#define SRC_MIX_SLICE_FSM_STAT_ISO_STAT_SHIFT (8U) +/*! ISO_STAT - Isolation FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_ISO_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_ISO_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_MTR_STAT_MASK (0x7000U) +#define SRC_MIX_SLICE_FSM_STAT_MTR_STAT_SHIFT (12U) +/*! MTR_STAT - MTR FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_MTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_MTR_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_MTR_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_MASK (0x70000U) +#define SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_SHIFT (16U) +/*! SSAR_STAT - SSAR FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_SSAR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_MASK (0xF00000U) +#define SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_SHIFT (20U) +/*! A55_HDSK_STAT - A55 handshake FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_MEM_STAT_MASK (0x7000000U) +#define SRC_MIX_SLICE_FSM_STAT_MEM_STAT_SHIFT (24U) +/*! MEM_STAT - Memory FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_MEM_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_MEM_STAT_MASK) +/*! @} */ + +/*! @name FUNC_STAT - function status */ +/*! @{ */ + +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_MASK (0x1U) +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_SHIFT (0U) +/*! PSW_STAT - Power switch status + * 0b0..Power switch on + * 0b1..Power switch off + */ +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT_MASK (0x4U) +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT_SHIFT (2U) +/*! RST_STAT - Reset status + * 0b0..Reset assert + * 0b1..Reset release + */ +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_RST_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_RST_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_MASK (0x10U) +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_SHIFT (4U) +/*! ISO_STAT - Isolation status + * 0b0..Isolation off + * 0b1..Isolation on + */ +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_MASK (0x40U) +#define SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_SHIFT (6U) +/*! MTR_STAT - MTR status + * 0b0..No effect + * 0b1..Memory repair/trim done + */ +#define SRC_MIX_SLICE_FUNC_STAT_MTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_MASK (0x100U) +#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_SHIFT (8U) +/*! SSAR_STAT - ssar status + * 0b0..No effect or power up handshake with Edgelock Enclave done + * 0b1..Power down handshake with Edgelock Enclave done + */ +#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_MASK (0x400U) +#define SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_SHIFT (10U) +/*! A55_HDSK_STAT - A55 handshake status + * 0b0..No effect or power up handshake with A55 done(just for A55 SLICE) + * 0b1..Power down handshake with A55 done(just for A55 SLICE) + */ +#define SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_MASK (0x1000U) +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_SHIFT (12U) +/*! MEM_STAT - Memory w/ status + * 0b0..No effect or memory w/ exit LP done + * 0b1..Memory w/ enter LP done + */ +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRC_MIX_SLICE_Register_Masks */ + + +/* SRC_MIX_SLICE - Peripheral instance base addresses */ +/** Peripheral SRC__SRC_A55C0_SLICE base address */ +#define SRC__SRC_A55C0_SLICE_BASE (0x44462C00u) +/** Peripheral SRC__SRC_A55C0_SLICE base pointer */ +#define SRC__SRC_A55C0_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_A55C0_SLICE_BASE) +/** Peripheral SRC__SRC_A55P_SLICE base address */ +#define SRC__SRC_A55P_SLICE_BASE (0x44463400u) +/** Peripheral SRC__SRC_A55P_SLICE base pointer */ +#define SRC__SRC_A55P_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_A55P_SLICE_BASE) +/** Peripheral SRC__SRC_AON_SLICE base address */ +#define SRC__SRC_AON_SLICE_BASE (0x44460800u) +/** Peripheral SRC__SRC_AON_SLICE base pointer */ +#define SRC__SRC_AON_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_AON_SLICE_BASE) +/** Peripheral SRC__SRC_DDR_SLICE base address */ +#define SRC__SRC_DDR_SLICE_BASE (0x44461000u) +/** Peripheral SRC__SRC_DDR_SLICE base pointer */ +#define SRC__SRC_DDR_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_DDR_SLICE_BASE) +/** Peripheral SRC__SRC_DPHY_SLICE base address */ +#define SRC__SRC_DPHY_SLICE_BASE (0x44461400u) +/** Peripheral SRC__SRC_DPHY_SLICE base pointer */ +#define SRC__SRC_DPHY_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_DPHY_SLICE_BASE) +/** Peripheral SRC__SRC_EDGELOCK_SLICE base address */ +#define SRC__SRC_EDGELOCK_SLICE_BASE (0x44460400u) +/** Peripheral SRC__SRC_EDGELOCK_SLICE base pointer */ +#define SRC__SRC_EDGELOCK_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_EDGELOCK_SLICE_BASE) +/** Peripheral SRC__SRC_HSIO_SLICE base address */ +#define SRC__SRC_HSIO_SLICE_BASE (0x44462000u) +/** Peripheral SRC__SRC_HSIO_SLICE base pointer */ +#define SRC__SRC_HSIO_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_HSIO_SLICE_BASE) +/** Peripheral SRC__SRC_MEDIA_SLICE base address */ +#define SRC__SRC_MEDIA_SLICE_BASE (0x44462400u) +/** Peripheral SRC__SRC_MEDIA_SLICE base pointer */ +#define SRC__SRC_MEDIA_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_MEDIA_SLICE_BASE) +/** Peripheral SRC__SRC_NIC_SLICE base address */ +#define SRC__SRC_NIC_SLICE_BASE (0x44461C00u) +/** Peripheral SRC__SRC_NIC_SLICE base pointer */ +#define SRC__SRC_NIC_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_NIC_SLICE_BASE) +/** Peripheral SRC__SRC_WKUP_SLICE base address */ +#define SRC__SRC_WKUP_SLICE_BASE (0x44460C00u) +/** Peripheral SRC__SRC_WKUP_SLICE base pointer */ +#define SRC__SRC_WKUP_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_WKUP_SLICE_BASE) +/** Array initializer of SRC_MIX_SLICE peripheral base addresses */ +#define SRC_MIX_SLICE_BASE_ADDRS { SRC__SRC_A55C0_SLICE_BASE, SRC__SRC_A55P_SLICE_BASE, SRC__SRC_AON_SLICE_BASE, SRC__SRC_DDR_SLICE_BASE, SRC__SRC_DPHY_SLICE_BASE, SRC__SRC_EDGELOCK_SLICE_BASE, SRC__SRC_HSIO_SLICE_BASE, SRC__SRC_MEDIA_SLICE_BASE, SRC__SRC_NIC_SLICE_BASE, SRC__SRC_WKUP_SLICE_BASE } +/** Array initializer of SRC_MIX_SLICE peripheral base pointers */ +#define SRC_MIX_SLICE_BASE_PTRS { SRC__SRC_A55C0_SLICE, SRC__SRC_A55P_SLICE, SRC__SRC_AON_SLICE, SRC__SRC_DDR_SLICE, SRC__SRC_DPHY_SLICE, SRC__SRC_EDGELOCK_SLICE, SRC__SRC_HSIO_SLICE, SRC__SRC_MEDIA_SLICE, SRC__SRC_NIC_SLICE, SRC__SRC_WKUP_SLICE } + +/*! + * @} + */ /* end of group SRC_MIX_SLICE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_COMPARE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_COMPARE_Peripheral_Access_Layer SYS_CTR_COMPARE Peripheral Access Layer + * @{ + */ + +/** SYS_CTR_COMPARE - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CMPCVL0; /**< Compare Count Value Low, offset: 0x20 */ + __IO uint32_t CMPCVH0; /**< Compare Count Value High, offset: 0x24 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CMPCR0; /**< Compare Control, offset: 0x2C */ + uint8_t RESERVED_2[240]; + __IO uint32_t CMPCVL1; /**< Compare Count Value Low, offset: 0x120 */ + __IO uint32_t CMPCVH1; /**< Compare Count Value High, offset: 0x124 */ + uint8_t RESERVED_3[4]; + __IO uint32_t CMPCR1; /**< Compare Control, offset: 0x12C */ + uint8_t RESERVED_4[3744]; + __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ +} SYS_CTR_COMPARE_Type; + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_COMPARE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_COMPARE_Register_Masks SYS_CTR_COMPARE Register Masks + * @{ + */ + +/*! @name CMPCVL0 - Compare Count Value Low */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT (0U) +/*! CMPCV0 - Compare Count Value Bits [31:0] */ +#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK) +/*! @} */ + +/*! @name CMPCVH0 - Compare Count Value High */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK (0xFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT (0U) +/*! CMPCV1 - Compare Count Value Bits [55:32] */ +#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK) +/*! @} */ + +/*! @name CMPCR0 - Compare Control */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCR0_EN_MASK (0x1U) +#define SYS_CTR_COMPARE_CMPCR0_EN_SHIFT (0U) +/*! EN - Compare Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SYS_CTR_COMPARE_CMPCR0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_EN_MASK) + +#define SYS_CTR_COMPARE_CMPCR0_IMASK_MASK (0x2U) +#define SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT (1U) +/*! IMASK - Interrupt Request Mask + * 0b0..Not masked + * 0b1..Masked + */ +#define SYS_CTR_COMPARE_CMPCR0_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_IMASK_MASK) + +#define SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK (0x4U) +#define SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT (2U) +/*! ISTAT - Compare Interrupt Status + * 0b0..Either less than the compare value or compare is disabled + * 0b1..Greater than or equal to the compare value and compare is enabled + */ +#define SYS_CTR_COMPARE_CMPCR0_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK) +/*! @} */ + +/*! @name CMPCVL1 - Compare Count Value Low */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT (0U) +/*! CMPCV0 - Compare Count Value Bits [31:0] */ +#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK) +/*! @} */ + +/*! @name CMPCVH1 - Compare Count Value High */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK (0xFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT (0U) +/*! CMPCV1 - Compare Count Value Bits [55:32] */ +#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK) +/*! @} */ + +/*! @name CMPCR1 - Compare Control */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCR1_EN_MASK (0x1U) +#define SYS_CTR_COMPARE_CMPCR1_EN_SHIFT (0U) +/*! EN - Compare Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SYS_CTR_COMPARE_CMPCR1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_EN_MASK) + +#define SYS_CTR_COMPARE_CMPCR1_IMASK_MASK (0x2U) +#define SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT (1U) +/*! IMASK - Interrupt Request Mask + * 0b0..Not masked + * 0b1..Masked + */ +#define SYS_CTR_COMPARE_CMPCR1_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_IMASK_MASK) + +#define SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK (0x4U) +#define SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT (2U) +/*! ISTAT - Compare Interrupt Status + * 0b0..Either less than the compare value or compare is disabled + * 0b1..Greater than or equal to the compare value and compare is enabled + */ +#define SYS_CTR_COMPARE_CMPCR1_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK) +/*! @} */ + +/*! @name CNTID0 - Counter ID */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CNTID0_CNTID_MASK (0xFFFFFFFFU) +#define SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT (0U) +/*! CNTID - Counter Identification */ +#define SYS_CTR_COMPARE_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT)) & SYS_CTR_COMPARE_CNTID0_CNTID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYS_CTR_COMPARE_Register_Masks */ + + +/* SYS_CTR_COMPARE - Peripheral instance base addresses */ +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_COMPARE base address */ +#define SYS_CTR_CTLBASE1__SYS_CTR_COMPARE_BASE (0x442A0000u) +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_COMPARE base pointer */ +#define SYS_CTR_CTLBASE1__SYS_CTR_COMPARE ((SYS_CTR_COMPARE_Type *)SYS_CTR_CTLBASE1__SYS_CTR_COMPARE_BASE) +/** Array initializer of SYS_CTR_COMPARE peripheral base addresses */ +#define SYS_CTR_COMPARE_BASE_ADDRS { SYS_CTR_CTLBASE1__SYS_CTR_COMPARE_BASE } +/** Array initializer of SYS_CTR_COMPARE peripheral base pointers */ +#define SYS_CTR_COMPARE_BASE_PTRS { SYS_CTR_CTLBASE1__SYS_CTR_COMPARE } + +/*! + * @} + */ /* end of group SYS_CTR_COMPARE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_CONTROL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_CONTROL_Peripheral_Access_Layer SYS_CTR_CONTROL Peripheral Access Layer + * @{ + */ + +/** SYS_CTR_CONTROL - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTCR; /**< Counter Control, offset: 0x0 */ + __I uint32_t CNTSR; /**< Counter Status, offset: 0x4 */ + __IO uint32_t CNTCV0; /**< Counter Count Value Low, offset: 0x8 */ + __IO uint32_t CNTCV1; /**< Counter Count Value High, offset: 0xC */ + uint8_t RESERVED_0[16]; + __I uint32_t CNTFID0; /**< Frequency-Modes Table 0, offset: 0x20 */ + __I uint32_t CNTFID1; /**< Frequency-Modes Table 1, offset: 0x24 */ + __I uint32_t CNTFID2; /**< Frequency-Modes Table 2, offset: 0x28 */ + uint8_t RESERVED_1[148]; + __IO uint32_t CNTCR2; /**< Counter Control 2, offset: 0xC0 */ + uint8_t RESERVED_2[3852]; + __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ +} SYS_CTR_CONTROL_Type; + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_CONTROL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_CONTROL_Register_Masks SYS_CTR_CONTROL Register Masks + * @{ + */ + +/*! @name CNTCR - Counter Control */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCR_EN_MASK (0x1U) +#define SYS_CTR_CONTROL_CNTCR_EN_SHIFT (0U) +/*! EN - Enable Counting + * 0b0..Disable + * 0b1..Enable + */ +#define SYS_CTR_CONTROL_CNTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR_EN_MASK) + +#define SYS_CTR_CONTROL_CNTCR_HDBG_MASK (0x2U) +#define SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT (1U) +/*! HDBG - Enable Debug Halt + * 0b0..Ignored + * 0b1..Causes SYS_CTR to halt + */ +#define SYS_CTR_CONTROL_CNTCR_HDBG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT)) & SYS_CTR_CONTROL_CNTCR_HDBG_MASK) + +#define SYS_CTR_CONTROL_CNTCR_FCR0_MASK (0x100U) +#define SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT (8U) +/*! FCR0 - Frequency Change Request, ID 0 + * 0b0..No change + * 0b1..Base frequency + */ +#define SYS_CTR_CONTROL_CNTCR_FCR0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR0_MASK) + +#define SYS_CTR_CONTROL_CNTCR_FCR1_MASK (0x200U) +#define SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT (9U) +/*! FCR1 - Frequency Change Request, ID 1 + * 0b0..No change + * 0b1..Alternate frequency + */ +#define SYS_CTR_CONTROL_CNTCR_FCR1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR1_MASK) +/*! @} */ + +/*! @name CNTSR - Counter Status */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTSR_DBGH_MASK (0x1U) +#define SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT (0U) +/*! DBGH - Debug Halt + * 0b0..Did not halt + * 0b1..Halted + */ +#define SYS_CTR_CONTROL_CNTSR_DBGH(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT)) & SYS_CTR_CONTROL_CNTSR_DBGH_MASK) + +#define SYS_CTR_CONTROL_CNTSR_FCA0_MASK (0x100U) +#define SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT (8U) +/*! FCA0 - Frequency Change Acknowledge, ID 0 + * 0b0..Not selected + * 0b1..Selected + */ +#define SYS_CTR_CONTROL_CNTSR_FCA0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA0_MASK) + +#define SYS_CTR_CONTROL_CNTSR_FCA1_MASK (0x200U) +#define SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT (9U) +/*! FCA1 - Frequency Change Acknowledge, ID 1 + * 0b0..Not selected + * 0b1..Selected + */ +#define SYS_CTR_CONTROL_CNTSR_FCA1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA1_MASK) +/*! @} */ + +/*! @name CNTCV0 - Counter Count Value Low */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT (0U) +/*! CNTCV0 - Counter Count Value Bits [31:0] */ +#define SYS_CTR_CONTROL_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK) +/*! @} */ + +/*! @name CNTCV1 - Counter Count Value High */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK (0xFFFFFFU) +#define SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT (0U) +/*! CNTCV1 - Counter Count Value Bits [55:32] */ +#define SYS_CTR_CONTROL_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK) +/*! @} */ + +/*! @name CNTFID0 - Frequency-Modes Table 0 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT (0U) +/*! CNTFID0 - Counter Frequency ID 0 */ +#define SYS_CTR_CONTROL_CNTFID0_CNTFID0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT)) & SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK) +/*! @} */ + +/*! @name CNTFID1 - Frequency-Modes Table 1 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT (0U) +/*! CNTFID1 - Counter Frequency ID 1 */ +#define SYS_CTR_CONTROL_CNTFID1_CNTFID1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT)) & SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK) +/*! @} */ + +/*! @name CNTFID2 - Frequency-Modes Table 2 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT (0U) +/*! CNTFID2 - Counter Frequency ID 2 */ +#define SYS_CTR_CONTROL_CNTFID2_CNTFID2(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT)) & SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK) +/*! @} */ + +/*! @name CNTCR2 - Counter Control 2 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK (0x1U) +#define SYS_CTR_CONTROL_CNTCR2_HWFC_EN_SHIFT (0U) +/*! HWFC_EN - Hardware Frequency Change Enable + * 0b0..No effect + * 0b1..Same as performed via software + */ +#define SYS_CTR_CONTROL_CNTCR2_HWFC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR2_HWFC_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK) +/*! @} */ + +/*! @name CNTID0 - Counter ID */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTID0_CNTID_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT (0U) +/*! CNTID - Counter Identification */ +#define SYS_CTR_CONTROL_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT)) & SYS_CTR_CONTROL_CNTID0_CNTID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYS_CTR_CONTROL_Register_Masks */ + + +/* SYS_CTR_CONTROL - Peripheral instance base addresses */ +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_CONTROL base address */ +#define SYS_CTR_CTLBASE1__SYS_CTR_CONTROL_BASE (0x44290000u) +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_CONTROL base pointer */ +#define SYS_CTR_CTLBASE1__SYS_CTR_CONTROL ((SYS_CTR_CONTROL_Type *)SYS_CTR_CTLBASE1__SYS_CTR_CONTROL_BASE) +/** Array initializer of SYS_CTR_CONTROL peripheral base addresses */ +#define SYS_CTR_CONTROL_BASE_ADDRS { SYS_CTR_CTLBASE1__SYS_CTR_CONTROL_BASE } +/** Array initializer of SYS_CTR_CONTROL peripheral base pointers */ +#define SYS_CTR_CONTROL_BASE_PTRS { SYS_CTR_CTLBASE1__SYS_CTR_CONTROL } + +/*! + * @} + */ /* end of group SYS_CTR_CONTROL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_READ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_READ_Peripheral_Access_Layer SYS_CTR_READ Peripheral Access Layer + * @{ + */ + +/** SYS_CTR_READ - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint32_t CNTCV0; /**< Counter Count Value Low, offset: 0x8 */ + __I uint32_t CNTCV1; /**< Counter Count Value High, offset: 0xC */ + uint8_t RESERVED_1[4032]; + __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ +} SYS_CTR_READ_Type; + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_READ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_READ_Register_Masks SYS_CTR_READ Register Masks + * @{ + */ + +/*! @name CNTCV0 - Counter Count Value Low */ +/*! @{ */ + +#define SYS_CTR_READ_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT (0U) +/*! CNTCV0 - Counter Count Value Bits [31:0] */ +#define SYS_CTR_READ_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_READ_CNTCV0_CNTCV0_MASK) +/*! @} */ + +/*! @name CNTCV1 - Counter Count Value High */ +/*! @{ */ + +#define SYS_CTR_READ_CNTCV1_CNTCV1_MASK (0xFFFFFFU) +#define SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT (0U) +/*! CNTCV1 - Counter Count Value Bits [55:32] */ +#define SYS_CTR_READ_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_READ_CNTCV1_CNTCV1_MASK) +/*! @} */ + +/*! @name CNTID0 - Counter ID */ +/*! @{ */ + +#define SYS_CTR_READ_CNTID0_CNTID_MASK (0xFFFFFFFFU) +#define SYS_CTR_READ_CNTID0_CNTID_SHIFT (0U) +/*! CNTID - Counter Identification */ +#define SYS_CTR_READ_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTID0_CNTID_SHIFT)) & SYS_CTR_READ_CNTID0_CNTID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYS_CTR_READ_Register_Masks */ + + +/* SYS_CTR_READ - Peripheral instance base addresses */ +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_READ base address */ +#define SYS_CTR_CTLBASE1__SYS_CTR_READ_BASE (0x442B0000u) +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_READ base pointer */ +#define SYS_CTR_CTLBASE1__SYS_CTR_READ ((SYS_CTR_READ_Type *)SYS_CTR_CTLBASE1__SYS_CTR_READ_BASE) +/** Array initializer of SYS_CTR_READ peripheral base addresses */ +#define SYS_CTR_READ_BASE_ADDRS { SYS_CTR_CTLBASE1__SYS_CTR_READ_BASE } +/** Array initializer of SYS_CTR_READ peripheral base pointers */ +#define SYS_CTR_READ_BASE_PTRS { SYS_CTR_CTLBASE1__SYS_CTR_READ } + +/*! + * @} + */ /* end of group SYS_CTR_READ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TCD_Peripheral_Access_Layer TCD Peripheral Access Layer + * @{ + */ + +/** TCD - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x0, array step: 0x10000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x4, array step: 0x10000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8, array step: 0x10000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0xC, array step: 0x10000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10, array step: 0x10000 */ + uint8_t RESERVED_0[12]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x20, array step: 0x10000 */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x24, array step: 0x10000 */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x26, array step: 0x10000 */ + union { /* offset: 0x28, array step: 0x10000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x28, array step: 0x10000 */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x28, array step: 0x10000 */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x2C, array step: 0x10000 */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x30, array step: 0x10000 */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x34, array step: 0x10000 */ + union { /* offset: 0x36, array step: 0x10000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x36, array step: 0x10000 */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x36, array step: 0x10000 */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x38, array step: 0x10000 */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x3C, array step: 0x10000 */ + union { /* offset: 0x3E, array step: 0x10000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x3E, array step: 0x10000 */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x3E, array step: 0x10000 */ + }; + uint8_t RESERVED_1[65472]; + } CH[31]; +} TCD_Type; + +/* ---------------------------------------------------------------------------- + -- TCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TCD_Register_Masks TCD Register Masks + * @{ + */ + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define TCD_CH_CSR_ERQ_MASK (0x1U) +#define TCD_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define TCD_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_ERQ_SHIFT)) & TCD_CH_CSR_ERQ_MASK) + +#define TCD_CH_CSR_EARQ_MASK (0x2U) +#define TCD_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define TCD_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_EARQ_SHIFT)) & TCD_CH_CSR_EARQ_MASK) + +#define TCD_CH_CSR_EEI_MASK (0x4U) +#define TCD_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define TCD_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_EEI_SHIFT)) & TCD_CH_CSR_EEI_MASK) + +#define TCD_CH_CSR_EBW_MASK (0x8U) +#define TCD_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define TCD_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_EBW_SHIFT)) & TCD_CH_CSR_EBW_MASK) + +#define TCD_CH_CSR_DONE_MASK (0x40000000U) +#define TCD_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define TCD_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_DONE_SHIFT)) & TCD_CH_CSR_DONE_MASK) + +#define TCD_CH_CSR_ACTIVE_MASK (0x80000000U) +#define TCD_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define TCD_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_ACTIVE_SHIFT)) & TCD_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of TCD_CH_CSR */ +#define TCD_CH_CSR_COUNT (31U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define TCD_CH_ES_DBE_MASK (0x1U) +#define TCD_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define TCD_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_DBE_SHIFT)) & TCD_CH_ES_DBE_MASK) + +#define TCD_CH_ES_SBE_MASK (0x2U) +#define TCD_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define TCD_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SBE_SHIFT)) & TCD_CH_ES_SBE_MASK) + +#define TCD_CH_ES_SGE_MASK (0x4U) +#define TCD_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define TCD_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SGE_SHIFT)) & TCD_CH_ES_SGE_MASK) + +#define TCD_CH_ES_NCE_MASK (0x8U) +#define TCD_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define TCD_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_NCE_SHIFT)) & TCD_CH_ES_NCE_MASK) + +#define TCD_CH_ES_DOE_MASK (0x10U) +#define TCD_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define TCD_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_DOE_SHIFT)) & TCD_CH_ES_DOE_MASK) + +#define TCD_CH_ES_DAE_MASK (0x20U) +#define TCD_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define TCD_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_DAE_SHIFT)) & TCD_CH_ES_DAE_MASK) + +#define TCD_CH_ES_SOE_MASK (0x40U) +#define TCD_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define TCD_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SOE_SHIFT)) & TCD_CH_ES_SOE_MASK) + +#define TCD_CH_ES_SAE_MASK (0x80U) +#define TCD_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define TCD_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SAE_SHIFT)) & TCD_CH_ES_SAE_MASK) + +#define TCD_CH_ES_ERR_MASK (0x80000000U) +#define TCD_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define TCD_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_ERR_SHIFT)) & TCD_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of TCD_CH_ES */ +#define TCD_CH_ES_COUNT (31U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define TCD_CH_INT_INT_MASK (0x1U) +#define TCD_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define TCD_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_INT_INT_SHIFT)) & TCD_CH_INT_INT_MASK) +/*! @} */ + +/* The count of TCD_CH_INT */ +#define TCD_CH_INT_COUNT (31U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define TCD_CH_SBR_MID_MASK (0xFU) +#define TCD_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define TCD_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_MID_SHIFT)) & TCD_CH_SBR_MID_MASK) + +#define TCD_CH_SBR_SEC_MASK (0x4000U) +#define TCD_CH_SBR_SEC_SHIFT (14U) +/*! SEC - Security Level + * 0b0..Nonsecure protection level for DMA transfers + * 0b1..Secure protection level for DMA transfers + */ +#define TCD_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_SEC_SHIFT)) & TCD_CH_SBR_SEC_MASK) + +#define TCD_CH_SBR_PAL_MASK (0x8000U) +#define TCD_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define TCD_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_PAL_SHIFT)) & TCD_CH_SBR_PAL_MASK) + +#define TCD_CH_SBR_EMI_MASK (0x10000U) +#define TCD_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID Replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define TCD_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_EMI_SHIFT)) & TCD_CH_SBR_EMI_MASK) + +#define TCD_CH_SBR_ATTR_MASK (0x7E0000U) +#define TCD_CH_SBR_ATTR_SHIFT (17U) +/*! ATTR - Attribute Output */ +#define TCD_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_ATTR_SHIFT)) & TCD_CH_SBR_ATTR_MASK) +/*! @} */ + +/* The count of TCD_CH_SBR */ +#define TCD_CH_SBR_COUNT (31U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define TCD_CH_PRI_APL_MASK (0x7U) +#define TCD_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define TCD_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_PRI_APL_SHIFT)) & TCD_CH_PRI_APL_MASK) + +#define TCD_CH_PRI_DPA_MASK (0x40000000U) +#define TCD_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define TCD_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_PRI_DPA_SHIFT)) & TCD_CH_PRI_DPA_MASK) + +#define TCD_CH_PRI_ECP_MASK (0x80000000U) +#define TCD_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define TCD_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_PRI_ECP_SHIFT)) & TCD_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of TCD_CH_PRI */ +#define TCD_CH_PRI_COUNT (31U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define TCD_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define TCD_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define TCD_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_SADDR_SADDR_SHIFT)) & TCD_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of TCD_TCD_SADDR */ +#define TCD_TCD_SADDR_COUNT (31U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define TCD_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define TCD_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define TCD_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_SOFF_SOFF_SHIFT)) & TCD_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of TCD_TCD_SOFF */ +#define TCD_TCD_SOFF_COUNT (31U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define TCD_TCD_ATTR_DSIZE_MASK (0x7U) +#define TCD_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define TCD_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_DSIZE_SHIFT)) & TCD_TCD_ATTR_DSIZE_MASK) + +#define TCD_TCD_ATTR_DMOD_MASK (0xF8U) +#define TCD_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define TCD_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_DMOD_SHIFT)) & TCD_TCD_ATTR_DMOD_MASK) + +#define TCD_TCD_ATTR_SSIZE_MASK (0x700U) +#define TCD_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110..64-byte + * 0b111.. + */ +#define TCD_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_SSIZE_SHIFT)) & TCD_TCD_ATTR_SSIZE_MASK) + +#define TCD_TCD_ATTR_SMOD_MASK (0xF800U) +#define TCD_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] + */ +#define TCD_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_SMOD_SHIFT)) & TCD_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of TCD_TCD_ATTR */ +#define TCD_TCD_ATTR_COUNT (31U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define TCD_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define TCD_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define TCD_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & TCD_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define TCD_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define TCD_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define TCD_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define TCD_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define TCD_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define TCD_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of TCD_TCD_NBYTES_MLOFFNO */ +#define TCD_TCD_NBYTES_MLOFFNO_COUNT (31U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define TCD_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define TCD_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define TCD_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define TCD_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define TCD_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define TCD_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define TCD_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define TCD_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define TCD_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define TCD_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define TCD_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define TCD_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of TCD_TCD_NBYTES_MLOFFYES */ +#define TCD_TCD_NBYTES_MLOFFYES_COUNT (31U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define TCD_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define TCD_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define TCD_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & TCD_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of TCD_TCD_SLAST_SDA */ +#define TCD_TCD_SLAST_SDA_COUNT (31U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define TCD_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define TCD_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define TCD_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_DADDR_DADDR_SHIFT)) & TCD_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of TCD_TCD_DADDR */ +#define TCD_TCD_DADDR_COUNT (31U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define TCD_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define TCD_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define TCD_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_DOFF_DOFF_SHIFT)) & TCD_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of TCD_TCD_DOFF */ +#define TCD_TCD_DOFF_COUNT (31U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define TCD_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define TCD_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define TCD_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKNO_CITER_SHIFT)) & TCD_TCD_CITER_ELINKNO_CITER_MASK) + +#define TCD_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define TCD_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKNO_ELINK_SHIFT)) & TCD_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_CITER_ELINKNO */ +#define TCD_TCD_CITER_ELINKNO_COUNT (31U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define TCD_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define TCD_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define TCD_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKYES_CITER_SHIFT)) & TCD_TCD_CITER_ELINKYES_CITER_MASK) + +#define TCD_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define TCD_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define TCD_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & TCD_TCD_CITER_ELINKYES_LINKCH_MASK) + +#define TCD_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define TCD_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKYES_ELINK_SHIFT)) & TCD_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_CITER_ELINKYES */ +#define TCD_TCD_CITER_ELINKYES_COUNT (31U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define TCD_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define TCD_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define TCD_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & TCD_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of TCD_TCD_DLAST_SGA */ +#define TCD_TCD_DLAST_SGA_COUNT (31U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define TCD_TCD_CSR_START_MASK (0x1U) +#define TCD_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define TCD_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_START_SHIFT)) & TCD_TCD_CSR_START_MASK) + +#define TCD_TCD_CSR_INTMAJOR_MASK (0x2U) +#define TCD_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define TCD_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_INTMAJOR_SHIFT)) & TCD_TCD_CSR_INTMAJOR_MASK) + +#define TCD_TCD_CSR_INTHALF_MASK (0x4U) +#define TCD_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define TCD_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_INTHALF_SHIFT)) & TCD_TCD_CSR_INTHALF_MASK) + +#define TCD_TCD_CSR_DREQ_MASK (0x8U) +#define TCD_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define TCD_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_DREQ_SHIFT)) & TCD_TCD_CSR_DREQ_MASK) + +#define TCD_TCD_CSR_ESG_MASK (0x10U) +#define TCD_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define TCD_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_ESG_SHIFT)) & TCD_TCD_CSR_ESG_MASK) + +#define TCD_TCD_CSR_MAJORELINK_MASK (0x20U) +#define TCD_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_MAJORELINK_SHIFT)) & TCD_TCD_CSR_MAJORELINK_MASK) + +#define TCD_TCD_CSR_EEOP_MASK (0x40U) +#define TCD_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define TCD_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_EEOP_SHIFT)) & TCD_TCD_CSR_EEOP_MASK) + +#define TCD_TCD_CSR_ESDA_MASK (0x80U) +#define TCD_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define TCD_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_ESDA_SHIFT)) & TCD_TCD_CSR_ESDA_MASK) + +#define TCD_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) +#define TCD_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define TCD_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_MAJORLINKCH_SHIFT)) & TCD_TCD_CSR_MAJORLINKCH_MASK) + +#define TCD_TCD_CSR_BWC_MASK (0xC000U) +#define TCD_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define TCD_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_BWC_SHIFT)) & TCD_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of TCD_TCD_CSR */ +#define TCD_TCD_CSR_COUNT (31U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define TCD_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define TCD_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define TCD_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKNO_BITER_SHIFT)) & TCD_TCD_BITER_ELINKNO_BITER_MASK) + +#define TCD_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define TCD_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKNO_ELINK_SHIFT)) & TCD_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_BITER_ELINKNO */ +#define TCD_TCD_BITER_ELINKNO_COUNT (31U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define TCD_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define TCD_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define TCD_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKYES_BITER_SHIFT)) & TCD_TCD_BITER_ELINKYES_BITER_MASK) + +#define TCD_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define TCD_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define TCD_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & TCD_TCD_BITER_ELINKYES_LINKCH_MASK) + +#define TCD_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define TCD_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKYES_ELINK_SHIFT)) & TCD_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_BITER_ELINKYES */ +#define TCD_TCD_BITER_ELINKYES_COUNT (31U) + + +/*! + * @} + */ /* end of group TCD_Register_Masks */ + + +/* TCD - Peripheral instance base addresses */ +/** Peripheral EDMA3_1__TCD base address */ +#define EDMA3_1__TCD_BASE (0x44010000u) +/** Peripheral EDMA3_1__TCD base pointer */ +#define EDMA3_1__TCD ((TCD_Type *)EDMA3_1__TCD_BASE) +/** Array initializer of TCD peripheral base addresses */ +#define TCD_BASE_ADDRS { EDMA3_1__TCD_BASE } +/** Array initializer of TCD peripheral base pointers */ +#define TCD_BASE_PTRS { EDMA3_1__TCD } + +/*! + * @} + */ /* end of group TCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPSENSE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPSENSE_Peripheral_Access_Layer TEMPSENSE Peripheral Access Layer + * @{ + */ + +/** TEMPSENSE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Control 0, offset: 0x0 */ + __IO uint32_t SET; /**< Control 0, offset: 0x4 */ + __IO uint32_t CLR; /**< Control 0, offset: 0x8 */ + __IO uint32_t TOG; /**< Control 0, offset: 0xC */ + } CTRL0; + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< Status 0, offset: 0x10 */ + __IO uint32_t SET; /**< Status 0, offset: 0x14 */ + __IO uint32_t CLR; /**< Status 0, offset: 0x18 */ + __IO uint32_t TOG; /**< Status 0, offset: 0x1C */ + } STAT0; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< Data 0, offset: 0x20 */ + __IO uint32_t SET; /**< Data 0, offset: 0x24 */ + __IO uint32_t CLR; /**< Data 0, offset: 0x28 */ + __IO uint32_t TOG; /**< Data 0, offset: 0x2C */ + } DATA0; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Threshold Control 01, offset: 0x30 */ + __IO uint32_t SET; /**< Threshold Control 01, offset: 0x34 */ + __IO uint32_t CLR; /**< Threshold Control 01, offset: 0x38 */ + __IO uint32_t TOG; /**< Threshold Control 01, offset: 0x3C */ + } THR_CTRL01; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Threshold Control 23, offset: 0x40 */ + __IO uint32_t SET; /**< Threshold Control 23, offset: 0x44 */ + __IO uint32_t CLR; /**< Threshold Control 23, offset: 0x48 */ + __IO uint32_t TOG; /**< Threshold Control 23, offset: 0x4C */ + } THR_CTRL23; + uint8_t RESERVED_0[432]; + struct { /* offset: 0x200 */ + __IO uint32_t RW; /**< Control 1, offset: 0x200 */ + __IO uint32_t SET; /**< Control 1, offset: 0x204 */ + __IO uint32_t CLR; /**< Control 1, offset: 0x208 */ + __IO uint32_t TOG; /**< Control 1, offset: 0x20C */ + } CTRL1; + struct { /* offset: 0x210 */ + __IO uint32_t RW; /**< Status 1, offset: 0x210 */ + __IO uint32_t SET; /**< Status 1, offset: 0x214 */ + __IO uint32_t CLR; /**< Status 1, offset: 0x218 */ + __IO uint32_t TOG; /**< Status 1, offset: 0x21C */ + } STAT1; + struct { /* offset: 0x220 */ + __IO uint32_t RW; /**< Data 1, offset: 0x220 */ + __IO uint32_t SET; /**< Data 1, offset: 0x224 */ + __IO uint32_t CLR; /**< Data 1, offset: 0x228 */ + __IO uint32_t TOG; /**< Data 1, offset: 0x22C */ + } DATA1; + uint8_t RESERVED_1[32]; + struct { /* offset: 0x250 */ + __IO uint32_t RW; /**< Threshold Control 45, offset: 0x250 */ + __IO uint32_t SET; /**< Threshold Control 45, offset: 0x254 */ + __IO uint32_t CLR; /**< Threshold Control 45, offset: 0x258 */ + __IO uint32_t TOG; /**< Threshold Control 45, offset: 0x25C */ + } THR_CTRL45; + uint8_t RESERVED_2[16]; + struct { /* offset: 0x270 */ + __IO uint32_t RW; /**< Measurement Period Control, offset: 0x270 */ + __IO uint32_t SET; /**< Measurement Period Control, offset: 0x274 */ + __IO uint32_t CLR; /**< Measurement Period Control, offset: 0x278 */ + __IO uint32_t TOG; /**< Measurement Period Control, offset: 0x27C */ + } PERIOD_CTRL; + __IO uint32_t REF_DIV; /**< Reference Clock Divider Control, offset: 0x280 */ + uint8_t RESERVED_3[44]; + struct { /* offset: 0x2B0 */ + __IO uint32_t RW; /**< Power-Up Delay Control, offset: 0x2B0 */ + __IO uint32_t SET; /**< Power-Up Delay Control, offset: 0x2B4 */ + __IO uint32_t CLR; /**< Power-Up Delay Control, offset: 0x2B8 */ + __IO uint32_t TOG; /**< Power-Up Delay Control, offset: 0x2BC */ + } PUD_ST_CTRL; + uint8_t RESERVED_4[32]; + struct { /* offset: 0x2E0 */ + __IO uint32_t RW; /**< Trim Control 1, offset: 0x2E0 */ + __IO uint32_t SET; /**< Trim Control 1, offset: 0x2E4 */ + __IO uint32_t CLR; /**< Trim Control 1, offset: 0x2E8 */ + __IO uint32_t TOG; /**< Trim Control 1, offset: 0x2EC */ + } TRIM1; + struct { /* offset: 0x2F0 */ + __IO uint32_t RW; /**< Trim Control 2, offset: 0x2F0 */ + __IO uint32_t SET; /**< Trim Control 2, offset: 0x2F4 */ + __IO uint32_t CLR; /**< Trim Control 2, offset: 0x2F8 */ + __IO uint32_t TOG; /**< Trim Control 2, offset: 0x2FC */ + } TRIM2; +} TEMPSENSE_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPSENSE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPSENSE_Register_Masks TEMPSENSE Register Masks + * @{ + */ + +/*! @name CTRL0 - Control 0 */ +/*! @{ */ + +#define TEMPSENSE_CTRL0_THR0_MODE_MASK (0x3U) +#define TEMPSENSE_CTRL0_THR0_MODE_SHIFT (0U) +/*! THR0_MODE - Threshold0 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL0_THR0_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR0_MODE_SHIFT)) & TEMPSENSE_CTRL0_THR0_MODE_MASK) + +#define TEMPSENSE_CTRL0_THR1_MODE_MASK (0xCU) +#define TEMPSENSE_CTRL0_THR1_MODE_SHIFT (2U) +/*! THR1_MODE - Threshold1 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL0_THR1_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR1_MODE_SHIFT)) & TEMPSENSE_CTRL0_THR1_MODE_MASK) + +#define TEMPSENSE_CTRL0_THR2_MODE_MASK (0x30U) +#define TEMPSENSE_CTRL0_THR2_MODE_SHIFT (4U) +/*! THR2_MODE - Threshold2 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL0_THR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR2_MODE_SHIFT)) & TEMPSENSE_CTRL0_THR2_MODE_MASK) + +#define TEMPSENSE_CTRL0_THR0_IE_MASK (0x100U) +#define TEMPSENSE_CTRL0_THR0_IE_SHIFT (8U) +/*! THR0_IE - Threshold0 Comparator Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_THR0_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR0_IE_SHIFT)) & TEMPSENSE_CTRL0_THR0_IE_MASK) + +#define TEMPSENSE_CTRL0_THR1_IE_MASK (0x200U) +#define TEMPSENSE_CTRL0_THR1_IE_SHIFT (9U) +/*! THR1_IE - Threshold1 Comparator Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_THR1_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR1_IE_SHIFT)) & TEMPSENSE_CTRL0_THR1_IE_MASK) + +#define TEMPSENSE_CTRL0_THR2_IE_MASK (0x400U) +#define TEMPSENSE_CTRL0_THR2_IE_SHIFT (10U) +/*! THR2_IE - Threshold2 Comparator Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_THR2_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR2_IE_SHIFT)) & TEMPSENSE_CTRL0_THR2_IE_MASK) + +#define TEMPSENSE_CTRL0_N_FILT_0_MASK (0xF000U) +#define TEMPSENSE_CTRL0_N_FILT_0_SHIFT (12U) +/*! N_FILT_0 - Filter Length for Threshold Flag */ +#define TEMPSENSE_CTRL0_N_FILT_0(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_N_FILT_0_SHIFT)) & TEMPSENSE_CTRL0_N_FILT_0_MASK) + +#define TEMPSENSE_CTRL0_DRDY0_IE_MASK (0x10000U) +#define TEMPSENSE_CTRL0_DRDY0_IE_SHIFT (16U) +/*! DRDY0_IE - Data-Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_DRDY0_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_DRDY0_IE_SHIFT)) & TEMPSENSE_CTRL0_DRDY0_IE_MASK) + +#define TEMPSENSE_CTRL0_FILT0_CNT_CLR_MASK (0x100000U) +#define TEMPSENSE_CTRL0_FILT0_CNT_CLR_SHIFT (20U) +/*! FILT0_CNT_CLR - Filter 0 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL0_FILT0_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_FILT0_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL0_FILT0_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL0_FILT1_CNT_CLR_MASK (0x200000U) +#define TEMPSENSE_CTRL0_FILT1_CNT_CLR_SHIFT (21U) +/*! FILT1_CNT_CLR - Filter 1 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL0_FILT1_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_FILT1_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL0_FILT1_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL0_FILT2_CNT_CLR_MASK (0x400000U) +#define TEMPSENSE_CTRL0_FILT2_CNT_CLR_SHIFT (22U) +/*! FILT2_CNT_CLR - Filter 2 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL0_FILT2_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_FILT2_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL0_FILT2_CNT_CLR_MASK) +/*! @} */ + +/*! @name STAT0 - Status 0 */ +/*! @{ */ + +#define TEMPSENSE_STAT0_THR0_IF_MASK (0x100U) +#define TEMPSENSE_STAT0_THR0_IF_SHIFT (8U) +/*! THR0_IF - Threshold0 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT0_THR0_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR0_IF_SHIFT)) & TEMPSENSE_STAT0_THR0_IF_MASK) + +#define TEMPSENSE_STAT0_THR1_IF_MASK (0x200U) +#define TEMPSENSE_STAT0_THR1_IF_SHIFT (9U) +/*! THR1_IF - Threshold1 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT0_THR1_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR1_IF_SHIFT)) & TEMPSENSE_STAT0_THR1_IF_MASK) + +#define TEMPSENSE_STAT0_THR2_IF_MASK (0x400U) +#define TEMPSENSE_STAT0_THR2_IF_SHIFT (10U) +/*! THR2_IF - Threshold2 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT0_THR2_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR2_IF_SHIFT)) & TEMPSENSE_STAT0_THR2_IF_MASK) + +#define TEMPSENSE_STAT0_THR0_STAT_MASK (0x1000U) +#define TEMPSENSE_STAT0_THR0_STAT_SHIFT (12U) +/*! THR0_STAT - Threshold0 State */ +#define TEMPSENSE_STAT0_THR0_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR0_STAT_SHIFT)) & TEMPSENSE_STAT0_THR0_STAT_MASK) + +#define TEMPSENSE_STAT0_THR1_STAT_MASK (0x2000U) +#define TEMPSENSE_STAT0_THR1_STAT_SHIFT (13U) +/*! THR1_STAT - Threshold1 State */ +#define TEMPSENSE_STAT0_THR1_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR1_STAT_SHIFT)) & TEMPSENSE_STAT0_THR1_STAT_MASK) + +#define TEMPSENSE_STAT0_THR2_STAT_MASK (0x4000U) +#define TEMPSENSE_STAT0_THR2_STAT_SHIFT (14U) +/*! THR2_STAT - Threshold2 State */ +#define TEMPSENSE_STAT0_THR2_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR2_STAT_SHIFT)) & TEMPSENSE_STAT0_THR2_STAT_MASK) + +#define TEMPSENSE_STAT0_DRDY0_IF_MASK (0x10000U) +#define TEMPSENSE_STAT0_DRDY0_IF_SHIFT (16U) +/*! DRDY0_IF - Data Ready Flag + * 0b0..No new data available + * 0b1..New data available + */ +#define TEMPSENSE_STAT0_DRDY0_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_DRDY0_IF_SHIFT)) & TEMPSENSE_STAT0_DRDY0_IF_MASK) + +#define TEMPSENSE_STAT0_IDLE_MASK (0x80000000U) +#define TEMPSENSE_STAT0_IDLE_SHIFT (31U) +/*! IDLE - Idle State + * 0b0..Conversion + * 0b1..Idle + */ +#define TEMPSENSE_STAT0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_IDLE_SHIFT)) & TEMPSENSE_STAT0_IDLE_MASK) +/*! @} */ + +/*! @name DATA0 - Data 0 */ +/*! @{ */ + +#define TEMPSENSE_DATA0_DATA_VAL_MASK (0xFFFFU) +#define TEMPSENSE_DATA0_DATA_VAL_SHIFT (0U) +/*! DATA_VAL - Temperature Data Value */ +#define TEMPSENSE_DATA0_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_DATA0_DATA_VAL_SHIFT)) & TEMPSENSE_DATA0_DATA_VAL_MASK) +/*! @} */ + +/*! @name THR_CTRL01 - Threshold Control 01 */ +/*! @{ */ + +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_MASK (0xFFFFU) +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_SHIFT (0U) +/*! TEMPERATURE_THRESHOLD0 - Temperature Threshold0 */ +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_SHIFT)) & TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_MASK) + +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_MASK (0xFFFF0000U) +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_SHIFT (16U) +/*! TEMPERATURE_THRESHOLD1 - Temperature Threshold1 */ +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_SHIFT)) & TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_MASK) +/*! @} */ + +/*! @name THR_CTRL23 - Threshold Control 23 */ +/*! @{ */ + +#define TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_MASK (0xFFFFU) +#define TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_SHIFT (0U) +/*! TEMPERATURE_THRESHOLD2 - Temperature Threshold2 */ +#define TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_SHIFT)) & TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define TEMPSENSE_CTRL1_THR4_MODE_MASK (0x3U) +#define TEMPSENSE_CTRL1_THR4_MODE_SHIFT (0U) +/*! THR4_MODE - Threshold4 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL1_THR4_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR4_MODE_SHIFT)) & TEMPSENSE_CTRL1_THR4_MODE_MASK) + +#define TEMPSENSE_CTRL1_THR5_MODE_MASK (0xCU) +#define TEMPSENSE_CTRL1_THR5_MODE_SHIFT (2U) +/*! THR5_MODE - Threshold5 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL1_THR5_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR5_MODE_SHIFT)) & TEMPSENSE_CTRL1_THR5_MODE_MASK) + +#define TEMPSENSE_CTRL1_THR4_IE_MASK (0x100U) +#define TEMPSENSE_CTRL1_THR4_IE_SHIFT (8U) +/*! THR4_IE - Threshold Comparator4 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_THR4_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR4_IE_SHIFT)) & TEMPSENSE_CTRL1_THR4_IE_MASK) + +#define TEMPSENSE_CTRL1_THR5_IE_MASK (0x200U) +#define TEMPSENSE_CTRL1_THR5_IE_SHIFT (9U) +/*! THR5_IE - Threshold Comparator5 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_THR5_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR5_IE_SHIFT)) & TEMPSENSE_CTRL1_THR5_IE_MASK) + +#define TEMPSENSE_CTRL1_N_FILT_1_MASK (0xF000U) +#define TEMPSENSE_CTRL1_N_FILT_1_SHIFT (12U) +/*! N_FILT_1 - Filter Length for Threshold Flag */ +#define TEMPSENSE_CTRL1_N_FILT_1(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_N_FILT_1_SHIFT)) & TEMPSENSE_CTRL1_N_FILT_1_MASK) + +#define TEMPSENSE_CTRL1_DRDY1_IE_MASK (0x10000U) +#define TEMPSENSE_CTRL1_DRDY1_IE_SHIFT (16U) +/*! DRDY1_IE - Data-Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_DRDY1_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_DRDY1_IE_SHIFT)) & TEMPSENSE_CTRL1_DRDY1_IE_MASK) + +#define TEMPSENSE_CTRL1_RESOLUTION_MASK (0xC0000U) +#define TEMPSENSE_CTRL1_RESOLUTION_SHIFT (18U) +/*! RESOLUTION - Resolution Mode + * 0b00..0.59325 ms + * 0b01..1.10525 ms + * 0b10..2.12925 ms + * 0b11..4.17725 ms + */ +#define TEMPSENSE_CTRL1_RESOLUTION(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_RESOLUTION_SHIFT)) & TEMPSENSE_CTRL1_RESOLUTION_MASK) + +#define TEMPSENSE_CTRL1_FILT4_CNT_CLR_MASK (0x100000U) +#define TEMPSENSE_CTRL1_FILT4_CNT_CLR_SHIFT (20U) +/*! FILT4_CNT_CLR - Filter 4 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL1_FILT4_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_FILT4_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL1_FILT4_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL1_FILT5_CNT_CLR_MASK (0x200000U) +#define TEMPSENSE_CTRL1_FILT5_CNT_CLR_SHIFT (21U) +/*! FILT5_CNT_CLR - Filter 5 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL1_FILT5_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_FILT5_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL1_FILT5_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL1_MEAS_MODE_MASK (0x3000000U) +#define TEMPSENSE_CTRL1_MEAS_MODE_SHIFT (24U) +/*! MEAS_MODE - Measurement Mode + * 0b00..Single One-Shot Measurement + * 0b01..Continuous Measurement + * 0b10..Periodic One-Shot Measurement + * 0b11..Reserved + */ +#define TEMPSENSE_CTRL1_MEAS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_MEAS_MODE_SHIFT)) & TEMPSENSE_CTRL1_MEAS_MODE_MASK) + +#define TEMPSENSE_CTRL1_STOP_MASK (0x20000000U) +#define TEMPSENSE_CTRL1_STOP_SHIFT (29U) +/*! STOP - Stop Measurement + * 0b0..Clear after conversion is over + * 0b1..Stop the conversion + */ +#define TEMPSENSE_CTRL1_STOP(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_STOP_SHIFT)) & TEMPSENSE_CTRL1_STOP_MASK) + +#define TEMPSENSE_CTRL1_START_MASK (0x40000000U) +#define TEMPSENSE_CTRL1_START_SHIFT (30U) +/*! START - Start Measurement + * 0b0..No effect + * 0b1..Start the measurement + */ +#define TEMPSENSE_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_START_SHIFT)) & TEMPSENSE_CTRL1_START_MASK) + +#define TEMPSENSE_CTRL1_ENABLE_MASK (0x80000000U) +#define TEMPSENSE_CTRL1_ENABLE_SHIFT (31U) +/*! ENABLE - TEMPSENSE Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_ENABLE_SHIFT)) & TEMPSENSE_CTRL1_ENABLE_MASK) +/*! @} */ + +/*! @name STAT1 - Status 1 */ +/*! @{ */ + +#define TEMPSENSE_STAT1_THR4_IF_MASK (0x100U) +#define TEMPSENSE_STAT1_THR4_IF_SHIFT (8U) +/*! THR4_IF - Threshold4 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT1_THR4_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR4_IF_SHIFT)) & TEMPSENSE_STAT1_THR4_IF_MASK) + +#define TEMPSENSE_STAT1_THR5_IF_MASK (0x200U) +#define TEMPSENSE_STAT1_THR5_IF_SHIFT (9U) +/*! THR5_IF - Threshold5 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT1_THR5_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR5_IF_SHIFT)) & TEMPSENSE_STAT1_THR5_IF_MASK) + +#define TEMPSENSE_STAT1_THR4_STAT_MASK (0x1000U) +#define TEMPSENSE_STAT1_THR4_STAT_SHIFT (12U) +/*! THR4_STAT - Threshold4 State */ +#define TEMPSENSE_STAT1_THR4_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR4_STAT_SHIFT)) & TEMPSENSE_STAT1_THR4_STAT_MASK) + +#define TEMPSENSE_STAT1_THR5_STAT_MASK (0x2000U) +#define TEMPSENSE_STAT1_THR5_STAT_SHIFT (13U) +/*! THR5_STAT - Threshold5 State */ +#define TEMPSENSE_STAT1_THR5_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR5_STAT_SHIFT)) & TEMPSENSE_STAT1_THR5_STAT_MASK) + +#define TEMPSENSE_STAT1_DRDY1_IF_MASK (0x10000U) +#define TEMPSENSE_STAT1_DRDY1_IF_SHIFT (16U) +/*! DRDY1_IF - Data Ready Flag + * 0b0..No new data + * 0b1..New data + */ +#define TEMPSENSE_STAT1_DRDY1_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_DRDY1_IF_SHIFT)) & TEMPSENSE_STAT1_DRDY1_IF_MASK) + +#define TEMPSENSE_STAT1_IDLE_MASK (0x80000000U) +#define TEMPSENSE_STAT1_IDLE_SHIFT (31U) +/*! IDLE - Idle State + * 0b0..Conversion + * 0b1..Idle + */ +#define TEMPSENSE_STAT1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_IDLE_SHIFT)) & TEMPSENSE_STAT1_IDLE_MASK) +/*! @} */ + +/*! @name DATA1 - Data 1 */ +/*! @{ */ + +#define TEMPSENSE_DATA1_DATA_VAL_MASK (0xFFFFU) +#define TEMPSENSE_DATA1_DATA_VAL_SHIFT (0U) +/*! DATA_VAL - Temperature Data Value */ +#define TEMPSENSE_DATA1_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_DATA1_DATA_VAL_SHIFT)) & TEMPSENSE_DATA1_DATA_VAL_MASK) +/*! @} */ + +/*! @name THR_CTRL45 - Threshold Control 45 */ +/*! @{ */ + +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_MASK (0xFFFFU) +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_SHIFT (0U) +/*! TEMPERATURE_THRESHOLD4 - Temperature Threshold4 */ +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_SHIFT)) & TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_MASK) + +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_MASK (0xFFFF0000U) +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_SHIFT (16U) +/*! TEMPERATURE_THRESHOLD5 - Temperature Threshold5 */ +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_SHIFT)) & TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_MASK) +/*! @} */ + +/*! @name PERIOD_CTRL - Measurement Period Control */ +/*! @{ */ + +#define TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_MASK (0xFFFFFFU) +#define TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_SHIFT (0U) +/*! MEAS_FREQ - TEMPSENSE Periodic Measurement Frequency */ +#define TEMPSENSE_PERIOD_CTRL_MEAS_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_SHIFT)) & TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_MASK) +/*! @} */ + +/*! @name REF_DIV - Reference Clock Divider Control */ +/*! @{ */ + +#define TEMPSENSE_REF_DIV_DIV_MASK (0xFF0000U) +#define TEMPSENSE_REF_DIV_DIV_SHIFT (16U) +/*! DIV - Divider Value + * 0b00000000..Output clock frequency = input clock frequency + * 0b00000001..Output clock frequency = input clock frequency / 2 + * 0b00000010..Output clock frequency = input clock frequency / 3 + * 0b00000011..... + * 0b11111111..Output clock frequency = input clock frequency / 256 + */ +#define TEMPSENSE_REF_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_REF_DIV_DIV_SHIFT)) & TEMPSENSE_REF_DIV_DIV_MASK) + +#define TEMPSENSE_REF_DIV_DE_MASK (0x80000000U) +#define TEMPSENSE_REF_DIV_DE_SHIFT (31U) +/*! DE - Divider Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_REF_DIV_DE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_REF_DIV_DE_SHIFT)) & TEMPSENSE_REF_DIV_DE_MASK) +/*! @} */ + +/*! @name PUD_ST_CTRL - Power-Up Delay Control */ +/*! @{ */ + +#define TEMPSENSE_PUD_ST_CTRL_PUD_MASK (0xFF0000U) +#define TEMPSENSE_PUD_ST_CTRL_PUD_SHIFT (16U) +/*! PUD - Power-Up Delay */ +#define TEMPSENSE_PUD_ST_CTRL_PUD(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_PUD_ST_CTRL_PUD_SHIFT)) & TEMPSENSE_PUD_ST_CTRL_PUD_MASK) +/*! @} */ + +/*! @name TRIM1 - Trim Control 1 */ +/*! @{ */ + +#define TEMPSENSE_TRIM1_VAL_A_MASK (0xFFFFU) +#define TEMPSENSE_TRIM1_VAL_A_SHIFT (0U) +/*! VAL_A - VAL_A */ +#define TEMPSENSE_TRIM1_VAL_A(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM1_VAL_A_SHIFT)) & TEMPSENSE_TRIM1_VAL_A_MASK) + +#define TEMPSENSE_TRIM1_VAL_B_MASK (0xFFFF0000U) +#define TEMPSENSE_TRIM1_VAL_B_SHIFT (16U) +/*! VAL_B - VAL_B */ +#define TEMPSENSE_TRIM1_VAL_B(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM1_VAL_B_SHIFT)) & TEMPSENSE_TRIM1_VAL_B_MASK) +/*! @} */ + +/*! @name TRIM2 - Trim Control 2 */ +/*! @{ */ + +#define TEMPSENSE_TRIM2_VAL_ALPHA_MASK (0xFFFFU) +#define TEMPSENSE_TRIM2_VAL_ALPHA_SHIFT (0U) +/*! VAL_ALPHA - VAL_ALPHA */ +#define TEMPSENSE_TRIM2_VAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM2_VAL_ALPHA_SHIFT)) & TEMPSENSE_TRIM2_VAL_ALPHA_MASK) + +#define TEMPSENSE_TRIM2_VAL_OFFSET_MASK (0xFFFF0000U) +#define TEMPSENSE_TRIM2_VAL_OFFSET_SHIFT (16U) +/*! VAL_OFFSET - VAL_OFFSET */ +#define TEMPSENSE_TRIM2_VAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM2_VAL_OFFSET_SHIFT)) & TEMPSENSE_TRIM2_VAL_OFFSET_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TEMPSENSE_Register_Masks */ + + +/* TEMPSENSE - Peripheral instance base addresses */ +/** Peripheral U_TEMP_ANAMIX base address */ +#define U_TEMP_ANAMIX_BASE (0x44482000u) +/** Peripheral U_TEMP_ANAMIX base pointer */ +#define U_TEMP_ANAMIX ((TEMPSENSE_Type *)U_TEMP_ANAMIX_BASE) +/** Array initializer of TEMPSENSE peripheral base addresses */ +#define TEMPSENSE_BASE_ADDRS { U_TEMP_ANAMIX_BASE } +/** Array initializer of TEMPSENSE peripheral base pointers */ +#define TEMPSENSE_BASE_PTRS { U_TEMP_ANAMIX } + +/*! + * @} + */ /* end of group TEMPSENSE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TPM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer + * @{ + */ + +/** TPM - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< TPM Global, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SC; /**< Status and Control, offset: 0x10 */ + __IO uint32_t CNT; /**< Counter, offset: 0x14 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x18 */ + __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */ + struct { /* offset: 0x20, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel n Status and Control, array offset: 0x20, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel n Value, array offset: 0x24, array step: 0x8 */ + } CONTROLS[4]; + uint8_t RESERVED_1[36]; + __IO uint32_t COMBINE; /**< Combine Channel, offset: 0x64 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ + uint8_t RESERVED_4[4]; + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ +} TPM_Type; + +/* ---------------------------------------------------------------------------- + -- TPM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TPM_Register_Masks TPM Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define TPM_VERID_FEATURE_MASK (0xFFFFU) +#define TPM_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with the filter and combine registers implemented + * 0b0000000000000101..Standard feature set with the quadrature register implemented + * 0b0000000000000111..Standard feature set with the filter, combine, and quadrature registers implemented + */ +#define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK) + +#define TPM_VERID_MINOR_MASK (0xFF0000U) +#define TPM_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK) + +#define TPM_VERID_MAJOR_MASK (0xFF000000U) +#define TPM_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define TPM_PARAM_CHAN_MASK (0xFFU) +#define TPM_PARAM_CHAN_SHIFT (0U) +/*! CHAN - Channel Count */ +#define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK) + +#define TPM_PARAM_TRIG_MASK (0xFF00U) +#define TPM_PARAM_TRIG_SHIFT (8U) +/*! TRIG - Trigger Count */ +#define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK) + +#define TPM_PARAM_WIDTH_MASK (0xFF0000U) +#define TPM_PARAM_WIDTH_SHIFT (16U) +/*! WIDTH - Counter Width */ +#define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK) +/*! @} */ + +/*! @name GLOBAL - TPM Global */ +/*! @{ */ + +#define TPM_GLOBAL_NOUPDATE_MASK (0x1U) +#define TPM_GLOBAL_NOUPDATE_SHIFT (0U) +/*! NOUPDATE - No Update + * 0b0..Internal double-buffered registers update as normal + * 0b1..Internal double-buffered registers do not update + */ +#define TPM_GLOBAL_NOUPDATE(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK) + +#define TPM_GLOBAL_RST_MASK (0x2U) +#define TPM_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ +#define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name SC - Status and Control */ +/*! @{ */ + +#define TPM_SC_PS_MASK (0x7U) +#define TPM_SC_PS_SHIFT (0U) +/*! PS - Prescale Factor Selection + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) + +#define TPM_SC_CMOD_MASK (0x18U) +#define TPM_SC_CMOD_SHIFT (3U) +/*! CMOD - Clock Mode Selection + * 0b00..TPM counter is disabled + * 0b01..TPM counter increments on every TPM counter clock + * 0b10..TPM counter increments on the rising edge of EXTCLK synchronized to the TPM counter clock + * 0b11..TPM counter increments on the rising edge of the selected external input trigger + */ +#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) + +#define TPM_SC_CPWMS_MASK (0x20U) +#define TPM_SC_CPWMS_SHIFT (5U) +/*! CPWMS - Center-Aligned PWM Select + * 0b0..Up counting mode + * 0b1..Up-down counting mode + */ +#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) + +#define TPM_SC_TOIE_MASK (0x40U) +#define TPM_SC_TOIE_SHIFT (6U) +/*! TOIE - Timer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) + +#define TPM_SC_TOF_MASK (0x80U) +#define TPM_SC_TOF_SHIFT (7U) +/*! TOF - Timer Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) + +#define TPM_SC_DMA_MASK (0x100U) +#define TPM_SC_DMA_SHIFT (8U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) +/*! @} */ + +/*! @name CNT - Counter */ +/*! @{ */ + +#define TPM_CNT_COUNT_MASK (0xFFFFFFFFU) +#define TPM_CNT_COUNT_SHIFT (0U) +/*! COUNT - Counter Value */ +#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) +/*! @} */ + +/*! @name MOD - Modulo */ +/*! @{ */ + +#define TPM_MOD_MOD_MASK (0xFFFFFFFFU) +#define TPM_MOD_MOD_SHIFT (0U) +/*! MOD - Modulo Value */ +#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) +/*! @} */ + +/*! @name STATUS - Capture and Compare Status */ +/*! @{ */ + +#define TPM_STATUS_CH0F_MASK (0x1U) +#define TPM_STATUS_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) + +#define TPM_STATUS_CH1F_MASK (0x2U) +#define TPM_STATUS_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) + +#define TPM_STATUS_CH2F_MASK (0x4U) +#define TPM_STATUS_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) + +#define TPM_STATUS_CH3F_MASK (0x8U) +#define TPM_STATUS_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) + +#define TPM_STATUS_TOF_MASK (0x100U) +#define TPM_STATUS_TOF_SHIFT (8U) +/*! TOF - Timer Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) +/*! @} */ + +/*! @name CnSC - Channel n Status and Control */ +/*! @{ */ + +#define TPM_CnSC_DMA_MASK (0x1U) +#define TPM_CnSC_DMA_SHIFT (0U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) + +#define TPM_CnSC_ELSA_MASK (0x4U) +#define TPM_CnSC_ELSA_SHIFT (2U) +/*! ELSA - Edge or Level Select A */ +#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) + +#define TPM_CnSC_ELSB_MASK (0x8U) +#define TPM_CnSC_ELSB_SHIFT (3U) +/*! ELSB - Edge or Level Select B */ +#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) + +#define TPM_CnSC_MSA_MASK (0x10U) +#define TPM_CnSC_MSA_SHIFT (4U) +/*! MSA - Channel Mode Select A */ +#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) + +#define TPM_CnSC_MSB_MASK (0x20U) +#define TPM_CnSC_MSB_SHIFT (5U) +/*! MSB - Channel Mode Select B */ +#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) + +#define TPM_CnSC_CHIE_MASK (0x40U) +#define TPM_CnSC_CHIE_SHIFT (6U) +/*! CHIE - Channel Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) + +#define TPM_CnSC_CHF_MASK (0x80U) +#define TPM_CnSC_CHF_SHIFT (7U) +/*! CHF - Channel Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) +/*! @} */ + +/* The count of TPM_CnSC */ +#define TPM_CnSC_COUNT (4U) + +/*! @name CnV - Channel n Value */ +/*! @{ */ + +#define TPM_CnV_VAL_MASK (0xFFFFFFFFU) +#define TPM_CnV_VAL_SHIFT (0U) +/*! VAL - Channel Value */ +#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) +/*! @} */ + +/* The count of TPM_CnV */ +#define TPM_CnV_COUNT (4U) + +/*! @name COMBINE - Combine Channel */ +/*! @{ */ + +#define TPM_COMBINE_COMBINE0_MASK (0x1U) +#define TPM_COMBINE_COMBINE0_SHIFT (0U) +/*! COMBINE0 - Combine Channels 0 and 1 + * 0b0..Independent + * 0b1..Combined + */ +#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) + +#define TPM_COMBINE_COMSWAP0_MASK (0x2U) +#define TPM_COMBINE_COMSWAP0_SHIFT (1U) +/*! COMSWAP0 - Combine Channel 0 and 1 Swap + * 0b0..Even channel + * 0b1..Odd channel + */ +#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) + +#define TPM_COMBINE_COMBINE1_MASK (0x100U) +#define TPM_COMBINE_COMBINE1_SHIFT (8U) +/*! COMBINE1 - Combine Channels 2 and 3 + * 0b0..Independent + * 0b1..Combined + */ +#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) + +#define TPM_COMBINE_COMSWAP1_MASK (0x200U) +#define TPM_COMBINE_COMSWAP1_SHIFT (9U) +/*! COMSWAP1 - Combine Channels 2 and 3 Swap + * 0b0..Even channel + * 0b1..Odd channel + */ +#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) +/*! @} */ + +/*! @name TRIG - Channel Trigger */ +/*! @{ */ + +#define TPM_TRIG_TRIG0_MASK (0x1U) +#define TPM_TRIG_TRIG0_SHIFT (0U) +/*! TRIG0 - Channel 0 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 0 to be used by channel 0 + */ +#define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK) + +#define TPM_TRIG_TRIG1_MASK (0x2U) +#define TPM_TRIG_TRIG1_SHIFT (1U) +/*! TRIG1 - Channel 1 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 1 to be used by channel 1 + */ +#define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK) + +#define TPM_TRIG_TRIG2_MASK (0x4U) +#define TPM_TRIG_TRIG2_SHIFT (2U) +/*! TRIG2 - Channel 2 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 0 to be used by channel 2 + */ +#define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK) + +#define TPM_TRIG_TRIG3_MASK (0x8U) +#define TPM_TRIG_TRIG3_SHIFT (3U) +/*! TRIG3 - Channel 3 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 1 to be used by channel 3 + */ +#define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK) +/*! @} */ + +/*! @name POL - Channel Polarity */ +/*! @{ */ + +#define TPM_POL_POL0_MASK (0x1U) +#define TPM_POL_POL0_SHIFT (0U) +/*! POL0 - Channel 0 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) + +#define TPM_POL_POL1_MASK (0x2U) +#define TPM_POL_POL1_SHIFT (1U) +/*! POL1 - Channel 1 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) + +#define TPM_POL_POL2_MASK (0x4U) +#define TPM_POL_POL2_SHIFT (2U) +/*! POL2 - Channel 2 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) + +#define TPM_POL_POL3_MASK (0x8U) +#define TPM_POL_POL3_SHIFT (3U) +/*! POL3 - Channel 3 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) +/*! @} */ + +/*! @name FILTER - Filter Control */ +/*! @{ */ + +#define TPM_FILTER_CH0FVAL_MASK (0xFU) +#define TPM_FILTER_CH0FVAL_SHIFT (0U) +/*! CH0FVAL - Channel 0 Filter Value */ +#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) + +#define TPM_FILTER_CH1FVAL_MASK (0xF0U) +#define TPM_FILTER_CH1FVAL_SHIFT (4U) +/*! CH1FVAL - Channel 1 Filter Value */ +#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) + +#define TPM_FILTER_CH2FVAL_MASK (0xF00U) +#define TPM_FILTER_CH2FVAL_SHIFT (8U) +/*! CH2FVAL - Channel 2 Filter Value */ +#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) + +#define TPM_FILTER_CH3FVAL_MASK (0xF000U) +#define TPM_FILTER_CH3FVAL_SHIFT (12U) +/*! CH3FVAL - Channel 3 Filter Value */ +#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) +/*! @} */ + +/*! @name QDCTRL - Quadrature Decoder Control and Status */ +/*! @{ */ + +#define TPM_QDCTRL_QUADEN_MASK (0x1U) +#define TPM_QDCTRL_QUADEN_SHIFT (0U) +/*! QUADEN - Quadrature Decoder Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) + +#define TPM_QDCTRL_TOFDIR_MASK (0x2U) +#define TPM_QDCTRL_TOFDIR_SHIFT (1U) +/*! TOFDIR - Timer Overflow Direction + * 0b0..Bottom of counting + * 0b1..Top of counting + */ +#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) + +#define TPM_QDCTRL_QUADIR_MASK (0x4U) +#define TPM_QDCTRL_QUADIR_SHIFT (2U) +/*! QUADIR - Counter Direction in Quadrature Decode Mode + * 0b0..Decreasing (counter decrement) + * 0b1..Increasing (counter increment) + */ +#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) + +#define TPM_QDCTRL_QUADMODE_MASK (0x8U) +#define TPM_QDCTRL_QUADMODE_SHIFT (3U) +/*! QUADMODE - Quadrature Decoder Mode + * 0b0..Phase encoding mode + * 0b1..Count and direction encoding mode + */ +#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) +/*! @} */ + +/*! @name CONF - Configuration */ +/*! @{ */ + +#define TPM_CONF_DOZEEN_MASK (0x20U) +#define TPM_CONF_DOZEEN_SHIFT (5U) +/*! DOZEEN - Doze Enable + * 0b0..TPM counter continues + * 0b1..TPM counter pauses + */ +#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) + +#define TPM_CONF_DBGMODE_MASK (0xC0U) +#define TPM_CONF_DBGMODE_SHIFT (6U) +/*! DBGMODE - Debug Mode + * 0b00..TPM counter pauses + * 0b11..TPM counter continues + */ +#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) + +#define TPM_CONF_GTBSYNC_MASK (0x100U) +#define TPM_CONF_GTBSYNC_SHIFT (8U) +/*! GTBSYNC - GTB Synchronization + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) + +#define TPM_CONF_GTBEEN_MASK (0x200U) +#define TPM_CONF_GTBEEN_SHIFT (9U) +/*! GTBEEN - GTB Enable + * 0b0..Internally generated TPM counter + * 0b1..Externally generated GTB counter + */ +#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) + +#define TPM_CONF_CSOT_MASK (0x10000U) +#define TPM_CONF_CSOT_SHIFT (16U) +/*! CSOT - Counter Start on Trigger + * 0b0..Counter starts immediately + * 0b1..Counter starts after detection of a rising edge on the selected input trigger + */ +#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) + +#define TPM_CONF_CSOO_MASK (0x20000U) +#define TPM_CONF_CSOO_SHIFT (17U) +/*! CSOO - Counter Stop on Overflow + * 0b0..TPM counter continues + * 0b1..TPM counter stops + */ +#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) + +#define TPM_CONF_CROT_MASK (0x40000U) +#define TPM_CONF_CROT_SHIFT (18U) +/*! CROT - Counter Reload on Trigger + * 0b0..No reload + * 0b1..Reload + */ +#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) + +#define TPM_CONF_CPOT_MASK (0x80000U) +#define TPM_CONF_CPOT_SHIFT (19U) +/*! CPOT - Counter Pause on Trigger + * 0b0..TPM counter continues + * 0b1..TPM counter pauses + */ +#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) + +#define TPM_CONF_TRGPOL_MASK (0x400000U) +#define TPM_CONF_TRGPOL_SHIFT (22U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) + +#define TPM_CONF_TRGSRC_MASK (0x800000U) +#define TPM_CONF_TRGSRC_SHIFT (23U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal (channel pin input capture) + */ +#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) + +#define TPM_CONF_TRGSEL_MASK (0x3000000U) +#define TPM_CONF_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select + * 0b01..Channel 0 pin input capture + * 0b10..Channel 1 pin input capture + * 0b11..Channel 0 or channel 1 pin input capture + */ +#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TPM_Register_Masks */ + + +/* TPM - Peripheral instance base addresses */ +/** Peripheral TPM1 base address */ +#define TPM1_BASE (0x44310000u) +/** Peripheral TPM1 base pointer */ +#define TPM1 ((TPM_Type *)TPM1_BASE) +/** Peripheral TPM2 base address */ +#define TPM2_BASE (0x44320000u) +/** Peripheral TPM2 base pointer */ +#define TPM2 ((TPM_Type *)TPM2_BASE) +/** Peripheral TPM3 base address */ +#define TPM3_BASE (0x424E0000u) +/** Peripheral TPM3 base pointer */ +#define TPM3 ((TPM_Type *)TPM3_BASE) +/** Peripheral TPM4 base address */ +#define TPM4_BASE (0x424F0000u) +/** Peripheral TPM4 base pointer */ +#define TPM4 ((TPM_Type *)TPM4_BASE) +/** Peripheral TPM5 base address */ +#define TPM5_BASE (0x42500000u) +/** Peripheral TPM5 base pointer */ +#define TPM5 ((TPM_Type *)TPM5_BASE) +/** Peripheral TPM6 base address */ +#define TPM6_BASE (0x42510000u) +/** Peripheral TPM6 base pointer */ +#define TPM6 ((TPM_Type *)TPM6_BASE) +/** Array initializer of TPM peripheral base addresses */ +#define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } +/** Array initializer of TPM peripheral base pointers */ +#define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } +/** Interrupt vectors for the TPM peripheral type */ +#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } + +/*! + * @} + */ /* end of group TPM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC0 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC0_Peripheral_Access_Layer TRDC_MBC0 Peripheral Access Layer + * @{ + */ + +/** TRDC_MBC0 - Register Layout Typedef */ +typedef struct { + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + uint8_t RESERVED_1[8]; + __I uint8_t DACFG[7]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1, irregular array, not all indices are valid */ + uint8_t RESERVED_2[185]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ + uint8_t RESERVED_3[28]; + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ + uint8_t RESERVED_4[12]; + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_5[1472]; + struct { /* offset: 0x800, array step: 0x20 */ + struct { /* offset: 0x800, array step: index*0x20, index2*0x4 */ + __IO uint32_t MDA_W_DFMT1; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4, irregular array, not all indices are valid */ + } MDA_Wx_DFMT1[1]; + uint8_t RESERVED_0[28]; + } MDA_Wx_y_DFMT[7]; +} TRDC_MBC0_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC0 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC0_Register_Masks TRDC_MBC0 Register Masks + * @{ + */ + +/*! @name TRDC_CR - TRDC Register */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_CR_GVLDM_MASK (0x1U) +#define TRDC_MBC0_TRDC_CR_GVLDM_SHIFT (0U) +/*! GVLDM - Global Valid for Domain Assignment Controllers + * 0b0..TRDC DACs are disabled. + * 0b1..TRDC DACs are enabled. + */ +#define TRDC_MBC0_TRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_GVLDM_SHIFT)) & TRDC_MBC0_TRDC_CR_GVLDM_MASK) + +#define TRDC_MBC0_TRDC_CR_HRL_MASK (0x1EU) +#define TRDC_MBC0_TRDC_CR_HRL_SHIFT (1U) +/*! HRL - Hardware Revision Level */ +#define TRDC_MBC0_TRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_HRL_SHIFT)) & TRDC_MBC0_TRDC_CR_HRL_MASK) + +#define TRDC_MBC0_TRDC_CR_GVLDB_MASK (0x4000U) +#define TRDC_MBC0_TRDC_CR_GVLDB_SHIFT (14U) +/*! GVLDB - Global Valid for Memory Block Checkers + * 0b0..TRDC MBCs are disabled. + * 0b1..TRDC MBCs are enabled. + */ +#define TRDC_MBC0_TRDC_CR_GVLDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_GVLDB_SHIFT)) & TRDC_MBC0_TRDC_CR_GVLDB_MASK) + +#define TRDC_MBC0_TRDC_CR_GVLDR_MASK (0x8000U) +#define TRDC_MBC0_TRDC_CR_GVLDR_SHIFT (15U) +/*! GVLDR - Global Valid for Memory Region Checkers + * 0b0..TRDC MRCs are disabled. + * 0b1..TRDC MRCs are enabled. + */ +#define TRDC_MBC0_TRDC_CR_GVLDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_GVLDR_SHIFT)) & TRDC_MBC0_TRDC_CR_GVLDR_MASK) + +#define TRDC_MBC0_TRDC_CR_LK1_MASK (0x40000000U) +#define TRDC_MBC0_TRDC_CR_LK1_SHIFT (30U) +/*! LK1 - Lock Status + * 0b0..The CR can be written by any secure privileged write. + * 0b1..The CR is locked (read-only) until the next reset. + */ +#define TRDC_MBC0_TRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_LK1_SHIFT)) & TRDC_MBC0_TRDC_CR_LK1_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG0 - TRDC Hardware Configuration Register 0 */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_HWCFG0_NDID_MASK (0x1FU) +#define TRDC_MBC0_TRDC_HWCFG0_NDID_SHIFT (0U) +/*! NDID - Number of domains */ +#define TRDC_MBC0_TRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NDID_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) +#define TRDC_MBC0_TRDC_HWCFG0_NMSTR_SHIFT (8U) +/*! NMSTR - Number of bus masters */ +#define TRDC_MBC0_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NMSTR_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_NMBC_MASK (0xF0000U) +#define TRDC_MBC0_TRDC_HWCFG0_NMBC_SHIFT (16U) +/*! NMBC - Number of MBCs */ +#define TRDC_MBC0_TRDC_HWCFG0_NMBC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NMBC_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_NMRC_MASK (0x1F000000U) +#define TRDC_MBC0_TRDC_HWCFG0_NMRC_SHIFT (24U) +/*! NMRC - Number of MRCs */ +#define TRDC_MBC0_TRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NMRC_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_MID_MASK (0xE0000000U) +#define TRDC_MBC0_TRDC_HWCFG0_MID_SHIFT (29U) +/*! MID - Module ID */ +#define TRDC_MBC0_TRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_MID_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_MID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_HWCFG1_DID_MASK (0xFU) +#define TRDC_MBC0_TRDC_HWCFG1_DID_SHIFT (0U) +/*! DID - Domain identifier number */ +#define TRDC_MBC0_TRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG1_DID_SHIFT)) & TRDC_MBC0_TRDC_HWCFG1_DID_MASK) +/*! @} */ + +/*! @name DACFG - Domain Assignment Configuration Register */ +/*! @{ */ + +#define TRDC_MBC0_DACFG_NMDAR_MASK (0xFU) +#define TRDC_MBC0_DACFG_NMDAR_SHIFT (0U) +/*! NMDAR - Number of master domain assignment registers for bus master m */ +#define TRDC_MBC0_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC0_DACFG_NMDAR_SHIFT)) & TRDC_MBC0_DACFG_NMDAR_MASK) + +#define TRDC_MBC0_DACFG_NCM_MASK (0x80U) +#define TRDC_MBC0_DACFG_NCM_SHIFT (7U) +/*! NCM - Non-CPU Master + * 0b0..Bus master is a processor. + * 0b1..Bus master is a non-processor. + */ +#define TRDC_MBC0_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC0_DACFG_NCM_SHIFT)) & TRDC_MBC0_DACFG_NCM_MASK) +/*! @} */ + +/* The count of TRDC_MBC0_DACFG */ +#define TRDC_MBC0_DACFG_COUNT (7U) + +/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_IDAU_CR_VLD_MASK (0x1U) +#define TRDC_MBC0_TRDC_IDAU_CR_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC0_TRDC_IDAU_CR_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_VLD_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_MASK (0x8U) +#define TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_SHIFT (3U) +/*! CFGSECEXT - Configure Security Extension + * 0b0..Armv8M Security Extension is disabled + * 0b1..Armv8-M Security Extension is enabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_MASK (0x10U) +#define TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_SHIFT (4U) +/*! MPUSDIS - Secure Memory Protection Unit Disabled + * 0b0..Secure MPU is enabled + * 0b1..Secure MPU is disabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_MASK (0x20U) +#define TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_SHIFT (5U) +/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled + * 0b0..Nonsecure MPU is enabled + * 0b1..Nonsecure MPU is disabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_MASK (0x40U) +#define TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_SHIFT (6U) +/*! SAUDIS - Security Attribution Unit Disable + * 0b0..SAU is enabled + * 0b1..SAU is disabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_SAUDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_MASK (0x100U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT (8U) +/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers + * 0b0..Unlock these registers + * 0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_MASK (0x200U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_SHIFT (9U) +/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register + * 0b0..Unlock this register + * 0b1..Disable writes to the VTOR_NS register + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_MASK (0x400U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_SHIFT (10U) +/*! LKSMPU - Lock Secure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or + * from a debug agent connected to the processor in Secure state + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_MASK (0x800U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_SHIFT (11U) +/*! LKNSMPU - Lock Nonsecure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKSAU_MASK (0x1000U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKSAU_SHIFT (12U) +/*! LKSAU - Lock SAU + * 0b0..Unlock these registers + * 0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKSAU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKSAU_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_MASK (0x80000000U) +#define TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_SHIFT (31U) +/*! PCURRNS - Processor current security + * 0b0..Processor is in Secure state + * 0b1..Processor is in Nonsecure state + */ +#define TRDC_MBC0_TRDC_IDAU_CR_PCURRNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_MASK) +/*! @} */ + +/*! @name TRDC_FLW_CTL - TRDC FLW Control */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_CTL_LK_MASK (0x40000000U) +#define TRDC_MBC0_TRDC_FLW_CTL_LK_SHIFT (30U) +/*! LK - Lock bit + * 0b0..FLW registers may be modified. + * 0b1..FLW registers are locked until the next reset. + */ +#define TRDC_MBC0_TRDC_FLW_CTL_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_MBC0_TRDC_FLW_CTL_LK_MASK) + +#define TRDC_MBC0_TRDC_FLW_CTL_V_MASK (0x80000000U) +#define TRDC_MBC0_TRDC_FLW_CTL_V_SHIFT (31U) +/*! V - Valid bit + * 0b0..FLW function is disabled. + * 0b1..FLW function is enabled. + */ +#define TRDC_MBC0_TRDC_FLW_CTL_V(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_CTL_V_SHIFT)) & TRDC_MBC0_TRDC_FLW_CTL_V_MASK) +/*! @} */ + +/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_PBASE_PBASE_MASK (0xFFFFFFFFU) +#define TRDC_MBC0_TRDC_FLW_PBASE_PBASE_SHIFT (0U) +/*! PBASE - Physical base address */ +#define TRDC_MBC0_TRDC_FLW_PBASE_PBASE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_MBC0_TRDC_FLW_PBASE_PBASE_MASK) +/*! @} */ + +/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_MASK (0x3F8000U) +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_SHIFT (15U) +/*! ABASE_L - Array base address low */ +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_MASK) + +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_MASK (0xFFC00000U) +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_SHIFT (22U) +/*! ABASE_H - Array base address high */ +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_MASK) +/*! @} */ + +/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_BCNT_BCNT_MASK (0x7FFFU) +#define TRDC_MBC0_TRDC_FLW_BCNT_BCNT_SHIFT (0U) +/*! BCNT - Block Count */ +#define TRDC_MBC0_TRDC_FLW_BCNT_BCNT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_MBC0_TRDC_FLW_BCNT_BCNT_MASK) +/*! @} */ + +/*! @name TRDC_FDID - TRDC Fault Domain ID */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FDID_FDID_MASK (0xFU) +#define TRDC_MBC0_TRDC_FDID_FDID_SHIFT (0U) +/*! FDID - Domain ID of Faulted Access */ +#define TRDC_MBC0_TRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FDID_FDID_SHIFT)) & TRDC_MBC0_TRDC_FDID_FDID_MASK) +/*! @} */ + +/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_DERRLOC_MBCINST_MASK (0xFFU) +#define TRDC_MBC0_TRDC_DERRLOC_MBCINST_SHIFT (0U) +/*! MBCINST - MBC instance */ +#define TRDC_MBC0_TRDC_DERRLOC_MBCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_DERRLOC_MBCINST_SHIFT)) & TRDC_MBC0_TRDC_DERRLOC_MBCINST_MASK) + +#define TRDC_MBC0_TRDC_DERRLOC_MRCINST_MASK (0xFFFF0000U) +#define TRDC_MBC0_TRDC_DERRLOC_MRCINST_SHIFT (16U) +/*! MRCINST - MRC instance */ +#define TRDC_MBC0_TRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_MBC0_TRDC_DERRLOC_MRCINST_MASK) +/*! @} */ + +/* The count of TRDC_MBC0_TRDC_DERRLOC */ +#define TRDC_MBC0_TRDC_DERRLOC_COUNT (16U) + +/*! @name MDA_W_DFMT1 - DAC Master Domain Assignment Register */ +/*! @{ */ + +#define TRDC_MBC0_MDA_W_DFMT1_DID_MASK (0xFU) +#define TRDC_MBC0_MDA_W_DFMT1_DID_SHIFT (0U) +/*! DID - Domain identifier */ +#define TRDC_MBC0_MDA_W_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_DID_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_DID_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_PA_MASK (0x30U) +#define TRDC_MBC0_MDA_W_DFMT1_PA_SHIFT (4U) +/*! PA - Privileged attribute + * 0b00..Force the bus attribute for this master to user. + * 0b01..Force the bus attribute for this master to privileged. + * 0b10..Use the bus master's privileged/user attribute directly. + * 0b11..Use the bus master's privileged/user attribute directly. + */ +#define TRDC_MBC0_MDA_W_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_PA_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_PA_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_SA_MASK (0xC0U) +#define TRDC_MBC0_MDA_W_DFMT1_SA_SHIFT (6U) +/*! SA - Secure attribute + * 0b00..Force the bus attribute for this master to secure. + * 0b01..Force the bus attribute for this master to nonsecure. + * 0b10..Use the bus master's secure/nonsecure attribute directly. + * 0b11..Use the bus master's secure/nonsecure attribute directly. + */ +#define TRDC_MBC0_MDA_W_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_SA_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_SA_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_DIDB_MASK (0x100U) +#define TRDC_MBC0_MDA_W_DFMT1_DIDB_SHIFT (8U) +/*! DIDB - DID Bypass + * 0b0..Use MDAn[3:0] as the domain identifier. + * 0b1..Use the DID input as the domain identifier. + */ +#define TRDC_MBC0_MDA_W_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_DIDB_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_DIDB_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_DFMT_MASK (0x20000000U) +#define TRDC_MBC0_MDA_W_DFMT1_DFMT_SHIFT (29U) +/*! DFMT - Domain format + * 0b0..Processor-core domain assignment + * 0b1..Non-processor domain assignment + */ +#define TRDC_MBC0_MDA_W_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_DFMT_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_DFMT_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_LK1_MASK (0x40000000U) +#define TRDC_MBC0_MDA_W_DFMT1_LK1_SHIFT (30U) +/*! LK1 - 1-bit Lock + * 0b0..Register can be written by any secure privileged write. + * 0b1..Register is locked (read-only) until the next reset. + */ +#define TRDC_MBC0_MDA_W_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_LK1_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_LK1_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_VLD_MASK (0x80000000U) +#define TRDC_MBC0_MDA_W_DFMT1_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..The Wr domain assignment is invalid. + * 0b1..The Wr domain assignment is valid. + */ +#define TRDC_MBC0_MDA_W_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_VLD_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_VLD_MASK) +/*! @} */ + +/* The count of TRDC_MBC0_MDA_W_DFMT1 */ +#define TRDC_MBC0_MDA_W_DFMT1_COUNT (7U) + +/* The count of TRDC_MBC0_MDA_W_DFMT1 */ +#define TRDC_MBC0_MDA_W_DFMT1_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_MBC0_Register_Masks */ + + +/* TRDC_MBC0 - Peripheral instance base addresses */ +/** Peripheral TRDC3 base address */ +#define TRDC3_BASE (0x42810000u) +/** Peripheral TRDC3 base pointer */ +#define TRDC3 ((TRDC_MBC0_Type *)TRDC3_BASE) +/** Peripheral TRDC5 base address */ +#define TRDC5_BASE (0x4AC30000u) +/** Peripheral TRDC5 base pointer */ +#define TRDC5 ((TRDC_MBC0_Type *)TRDC5_BASE) +/** Peripheral TRDC6 base address */ +#define TRDC6_BASE (0x4C030000u) +/** Peripheral TRDC6 base pointer */ +#define TRDC6 ((TRDC_MBC0_Type *)TRDC6_BASE) +/** Array initializer of TRDC_MBC0 peripheral base addresses */ +#define TRDC_MBC0_BASE_ADDRS { 0u, 0u, 0u, TRDC3_BASE, 0u, TRDC5_BASE, TRDC6_BASE } +/** Array initializer of TRDC_MBC0 peripheral base pointers */ +#define TRDC_MBC0_BASE_PTRS { (TRDC_MBC0_Type *)0u, (TRDC_MBC0_Type *)0u, (TRDC_MBC0_Type *)0u, TRDC3, (TRDC_MBC0_Type *)0u, TRDC5, TRDC6 } + +/*! + * @} + */ /* end of group TRDC_MBC0_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC2 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC2_Peripheral_Access_Layer TRDC_MBC2 Peripheral Access Layer + * @{ + */ + +/** TRDC_MBC2 - Register Layout Typedef */ +typedef struct { + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + uint8_t RESERVED_1[8]; + __I uint8_t DACFG[5]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1, valid indices: [2-4] */ + uint8_t RESERVED_2[187]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ + uint8_t RESERVED_3[28]; + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ + uint8_t RESERVED_4[12]; + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_5[448]; + struct { /* offset: 0x400, array step: 0x10 */ + __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10, irregular array, not all indices are valid */ + __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10, irregular array, not all indices are valid */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10, irregular array, not all indices are valid */ + } MBC_DERR[2]; + uint8_t RESERVED_6[96]; + struct { /* offset: 0x480, array step: 0x10 */ + __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + } MRC_DERR[2]; + uint8_t RESERVED_7[864]; + struct { /* offset: 0x800, array step: 0x20 */ + struct { /* offset: 0x800, array step: index*0x20, index2*0x4 */ + __IO uint32_t MDA_W_DFMT1; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4, valid indices: [2-4][0] */ + } MDA_Wx_DFMT1[1]; + uint8_t RESERVED_0[28]; + } MDA_Wx_y_DFMT[5]; + uint8_t RESERVED_8[63328]; + struct { /* offset: 0x10000, array step: 0x2000 */ + __I uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_0[192]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[48]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_2[28]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_4[28]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_5[4]; + __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_6[20]; + __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_7[76]; + __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_8[192]; + __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_9[48]; + __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_10[28]; + __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_11[4]; + __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_12[28]; + __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_13[4]; + __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_14[20]; + __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_15[76]; + __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_16[192]; + __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_17[48]; + __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_18[28]; + __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_19[4]; + __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_20[28]; + __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_21[4]; + __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_22[20]; + __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_23[76]; + __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_24[192]; + __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_25[48]; + __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_26[28]; + __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_27[4]; + __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_28[28]; + __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_29[4]; + __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_30[20]; + __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_31[76]; + __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_32[192]; + __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_33[48]; + __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_34[28]; + __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_35[4]; + __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_36[28]; + __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_37[4]; + __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_38[20]; + __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_39[76]; + __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_40[192]; + __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_41[48]; + __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_42[28]; + __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_43[4]; + __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_44[28]; + __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_45[4]; + __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_46[20]; + __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_47[76]; + __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_48[192]; + __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_49[48]; + __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_50[28]; + __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_51[4]; + __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_52[28]; + __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_53[4]; + __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_54[20]; + __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_55[76]; + __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_56[192]; + __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_57[48]; + __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_58[28]; + __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_59[4]; + __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_60[28]; + __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_61[4]; + __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_62[20]; + __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_63[76]; + __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_64[192]; + __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_65[48]; + __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_66[28]; + __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_67[4]; + __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_68[28]; + __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_69[4]; + __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_70[20]; + __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_71[76]; + __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_72[192]; + __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_73[48]; + __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_74[28]; + __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_75[4]; + __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_76[28]; + __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_77[4]; + __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_78[20]; + __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_79[76]; + __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_80[192]; + __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_81[48]; + __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_82[28]; + __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_83[4]; + __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_84[28]; + __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_85[4]; + __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_86[20]; + __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_87[76]; + __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_88[192]; + __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_89[48]; + __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_90[28]; + __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_91[4]; + __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_92[28]; + __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_93[4]; + __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_94[20]; + __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_95[76]; + __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_96[192]; + __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_97[48]; + __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_98[28]; + __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_99[4]; + __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_100[28]; + __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_101[4]; + __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_102[20]; + __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_103[76]; + __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_104[192]; + __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_105[48]; + __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_106[28]; + __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_107[4]; + __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_108[28]; + __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_109[4]; + __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_110[20]; + __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_111[76]; + __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_112[192]; + __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_113[48]; + __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_114[28]; + __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_115[4]; + __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_116[28]; + __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_117[4]; + __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_118[20]; + __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_119[76]; + __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_120[192]; + __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_121[48]; + __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_122[28]; + __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_123[4]; + __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_124[28]; + __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_125[4]; + __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_126[20]; + __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_127[12]; + } MBC_INDEX[2]; + struct { /* offset: 0x14000, array step: 0x1000 */ + __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_0[12]; + __IO uint32_t MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_GLBAC[8]; /**< MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_DOM0_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14040, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_1[64]; + __IO uint32_t MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_2[124]; + __IO uint32_t MRC_DOM1_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14140, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_3[64]; + __IO uint32_t MRC_DOM1_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_4[124]; + __IO uint32_t MRC_DOM2_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14240, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_5[64]; + __IO uint32_t MRC_DOM2_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_6[124]; + __IO uint32_t MRC_DOM3_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14340, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_7[64]; + __IO uint32_t MRC_DOM3_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_8[124]; + __IO uint32_t MRC_DOM4_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14440, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_9[64]; + __IO uint32_t MRC_DOM4_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_10[124]; + __IO uint32_t MRC_DOM5_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14540, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_11[64]; + __IO uint32_t MRC_DOM5_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_12[124]; + __IO uint32_t MRC_DOM6_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14640, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_13[64]; + __IO uint32_t MRC_DOM6_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_14[124]; + __IO uint32_t MRC_DOM7_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14740, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_15[64]; + __IO uint32_t MRC_DOM7_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_16[124]; + __IO uint32_t MRC_DOM8_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14840, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_17[64]; + __IO uint32_t MRC_DOM8_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_18[124]; + __IO uint32_t MRC_DOM9_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14940, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_19[64]; + __IO uint32_t MRC_DOM9_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_20[124]; + __IO uint32_t MRC_DOM10_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_21[64]; + __IO uint32_t MRC_DOM10_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_22[124]; + __IO uint32_t MRC_DOM11_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_23[64]; + __IO uint32_t MRC_DOM11_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_24[124]; + __IO uint32_t MRC_DOM12_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_25[64]; + __IO uint32_t MRC_DOM12_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_26[124]; + __IO uint32_t MRC_DOM13_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_27[64]; + __IO uint32_t MRC_DOM13_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_28[124]; + __IO uint32_t MRC_DOM14_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_29[64]; + __IO uint32_t MRC_DOM14_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_30[124]; + __IO uint32_t MRC_DOM15_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_31[64]; + __IO uint32_t MRC_DOM15_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_32[60]; + } MRC_INDEX[2]; +} TRDC_MBC2_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC2 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC2_Register_Masks TRDC_MBC2 Register Masks + * @{ + */ + +/*! @name TRDC_CR - TRDC Register */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_CR_GVLDM_MASK (0x1U) +#define TRDC_MBC2_TRDC_CR_GVLDM_SHIFT (0U) +/*! GVLDM - Global Valid for Domain Assignment Controllers + * 0b0..TRDC DACs are disabled. + * 0b1..TRDC DACs are enabled. + */ +#define TRDC_MBC2_TRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_GVLDM_SHIFT)) & TRDC_MBC2_TRDC_CR_GVLDM_MASK) + +#define TRDC_MBC2_TRDC_CR_HRL_MASK (0x1EU) +#define TRDC_MBC2_TRDC_CR_HRL_SHIFT (1U) +/*! HRL - Hardware Revision Level */ +#define TRDC_MBC2_TRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_HRL_SHIFT)) & TRDC_MBC2_TRDC_CR_HRL_MASK) + +#define TRDC_MBC2_TRDC_CR_GVLDB_MASK (0x4000U) +#define TRDC_MBC2_TRDC_CR_GVLDB_SHIFT (14U) +/*! GVLDB - Global Valid for Memory Block Checkers + * 0b0..TRDC MBCs are disabled. + * 0b1..TRDC MBCs are enabled. + */ +#define TRDC_MBC2_TRDC_CR_GVLDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_GVLDB_SHIFT)) & TRDC_MBC2_TRDC_CR_GVLDB_MASK) + +#define TRDC_MBC2_TRDC_CR_GVLDR_MASK (0x8000U) +#define TRDC_MBC2_TRDC_CR_GVLDR_SHIFT (15U) +/*! GVLDR - Global Valid for Memory Region Checkers + * 0b0..TRDC MRCs are disabled. + * 0b1..TRDC MRCs are enabled. + */ +#define TRDC_MBC2_TRDC_CR_GVLDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_GVLDR_SHIFT)) & TRDC_MBC2_TRDC_CR_GVLDR_MASK) + +#define TRDC_MBC2_TRDC_CR_LK1_MASK (0x40000000U) +#define TRDC_MBC2_TRDC_CR_LK1_SHIFT (30U) +/*! LK1 - Lock Status + * 0b0..The CR can be written by any secure privileged write. + * 0b1..The CR is locked (read-only) until the next reset. + */ +#define TRDC_MBC2_TRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_LK1_SHIFT)) & TRDC_MBC2_TRDC_CR_LK1_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG0 - TRDC Hardware Configuration Register 0 */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_HWCFG0_NDID_MASK (0x1FU) +#define TRDC_MBC2_TRDC_HWCFG0_NDID_SHIFT (0U) +/*! NDID - Number of domains */ +#define TRDC_MBC2_TRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NDID_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) +#define TRDC_MBC2_TRDC_HWCFG0_NMSTR_SHIFT (8U) +/*! NMSTR - Number of bus masters */ +#define TRDC_MBC2_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NMSTR_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_NMBC_MASK (0xF0000U) +#define TRDC_MBC2_TRDC_HWCFG0_NMBC_SHIFT (16U) +/*! NMBC - Number of MBCs */ +#define TRDC_MBC2_TRDC_HWCFG0_NMBC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NMBC_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_NMRC_MASK (0x1F000000U) +#define TRDC_MBC2_TRDC_HWCFG0_NMRC_SHIFT (24U) +/*! NMRC - Number of MRCs */ +#define TRDC_MBC2_TRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NMRC_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_MID_MASK (0xE0000000U) +#define TRDC_MBC2_TRDC_HWCFG0_MID_SHIFT (29U) +/*! MID - Module ID */ +#define TRDC_MBC2_TRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_MID_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_MID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_HWCFG1_DID_MASK (0xFU) +#define TRDC_MBC2_TRDC_HWCFG1_DID_SHIFT (0U) +/*! DID - Domain identifier number */ +#define TRDC_MBC2_TRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG1_DID_SHIFT)) & TRDC_MBC2_TRDC_HWCFG1_DID_MASK) +/*! @} */ + +/*! @name DACFG - Domain Assignment Configuration Register */ +/*! @{ */ + +#define TRDC_MBC2_DACFG_NMDAR_MASK (0xFU) +#define TRDC_MBC2_DACFG_NMDAR_SHIFT (0U) +/*! NMDAR - Number of master domain assignment registers for bus master m */ +#define TRDC_MBC2_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC2_DACFG_NMDAR_SHIFT)) & TRDC_MBC2_DACFG_NMDAR_MASK) + +#define TRDC_MBC2_DACFG_NCM_MASK (0x80U) +#define TRDC_MBC2_DACFG_NCM_SHIFT (7U) +/*! NCM - Non-CPU Master + * 0b0..Bus master is a processor. + * 0b1..Bus master is a non-processor. + */ +#define TRDC_MBC2_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC2_DACFG_NCM_SHIFT)) & TRDC_MBC2_DACFG_NCM_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_DACFG */ +#define TRDC_MBC2_DACFG_COUNT (5U) + +/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_IDAU_CR_VLD_MASK (0x1U) +#define TRDC_MBC2_TRDC_IDAU_CR_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_TRDC_IDAU_CR_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_VLD_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_MASK (0x8U) +#define TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_SHIFT (3U) +/*! CFGSECEXT - Configure Security Extension + * 0b0..Armv8M Security Extension is disabled + * 0b1..Armv8-M Security Extension is enabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_MASK (0x10U) +#define TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_SHIFT (4U) +/*! MPUSDIS - Secure Memory Protection Unit Disabled + * 0b0..Secure MPU is enabled + * 0b1..Secure MPU is disabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_MASK (0x20U) +#define TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_SHIFT (5U) +/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled + * 0b0..Nonsecure MPU is enabled + * 0b1..Nonsecure MPU is disabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_MASK (0x40U) +#define TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_SHIFT (6U) +/*! SAUDIS - Security Attribution Unit Disable + * 0b0..SAU is enabled + * 0b1..SAU is disabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_SAUDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_MASK (0x100U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT (8U) +/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers + * 0b0..Unlock these registers + * 0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_MASK (0x200U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_SHIFT (9U) +/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register + * 0b0..Unlock this register + * 0b1..Disable writes to the VTOR_NS register + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_MASK (0x400U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_SHIFT (10U) +/*! LKSMPU - Lock Secure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or + * from a debug agent connected to the processor in Secure state + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_MASK (0x800U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_SHIFT (11U) +/*! LKNSMPU - Lock Nonsecure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKSAU_MASK (0x1000U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKSAU_SHIFT (12U) +/*! LKSAU - Lock SAU + * 0b0..Unlock these registers + * 0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKSAU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKSAU_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_MASK (0x80000000U) +#define TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_SHIFT (31U) +/*! PCURRNS - Processor current security + * 0b0..Processor is in Secure state + * 0b1..Processor is in Nonsecure state + */ +#define TRDC_MBC2_TRDC_IDAU_CR_PCURRNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_MASK) +/*! @} */ + +/*! @name TRDC_FLW_CTL - TRDC FLW Control */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_CTL_LK_MASK (0x40000000U) +#define TRDC_MBC2_TRDC_FLW_CTL_LK_SHIFT (30U) +/*! LK - Lock bit + * 0b0..FLW registers may be modified. + * 0b1..FLW registers are locked until the next reset. + */ +#define TRDC_MBC2_TRDC_FLW_CTL_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_MBC2_TRDC_FLW_CTL_LK_MASK) + +#define TRDC_MBC2_TRDC_FLW_CTL_V_MASK (0x80000000U) +#define TRDC_MBC2_TRDC_FLW_CTL_V_SHIFT (31U) +/*! V - Valid bit + * 0b0..FLW function is disabled. + * 0b1..FLW function is enabled. + */ +#define TRDC_MBC2_TRDC_FLW_CTL_V(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_CTL_V_SHIFT)) & TRDC_MBC2_TRDC_FLW_CTL_V_MASK) +/*! @} */ + +/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_PBASE_PBASE_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_TRDC_FLW_PBASE_PBASE_SHIFT (0U) +/*! PBASE - Physical base address */ +#define TRDC_MBC2_TRDC_FLW_PBASE_PBASE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_MBC2_TRDC_FLW_PBASE_PBASE_MASK) +/*! @} */ + +/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_MASK (0x3F8000U) +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_SHIFT (15U) +/*! ABASE_L - Array base address low */ +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_MASK) + +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_MASK (0xFFC00000U) +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_SHIFT (22U) +/*! ABASE_H - Array base address high */ +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_MASK) +/*! @} */ + +/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_BCNT_BCNT_MASK (0x7FFFU) +#define TRDC_MBC2_TRDC_FLW_BCNT_BCNT_SHIFT (0U) +/*! BCNT - Block Count */ +#define TRDC_MBC2_TRDC_FLW_BCNT_BCNT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_MBC2_TRDC_FLW_BCNT_BCNT_MASK) +/*! @} */ + +/*! @name TRDC_FDID - TRDC Fault Domain ID */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FDID_FDID_MASK (0xFU) +#define TRDC_MBC2_TRDC_FDID_FDID_SHIFT (0U) +/*! FDID - Domain ID of Faulted Access */ +#define TRDC_MBC2_TRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FDID_FDID_SHIFT)) & TRDC_MBC2_TRDC_FDID_FDID_MASK) +/*! @} */ + +/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_DERRLOC_MBCINST_MASK (0xFFU) +#define TRDC_MBC2_TRDC_DERRLOC_MBCINST_SHIFT (0U) +/*! MBCINST - MBC instance */ +#define TRDC_MBC2_TRDC_DERRLOC_MBCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_DERRLOC_MBCINST_SHIFT)) & TRDC_MBC2_TRDC_DERRLOC_MBCINST_MASK) + +#define TRDC_MBC2_TRDC_DERRLOC_MRCINST_MASK (0xFFFF0000U) +#define TRDC_MBC2_TRDC_DERRLOC_MRCINST_SHIFT (16U) +/*! MRCINST - MRC instance */ +#define TRDC_MBC2_TRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_MBC2_TRDC_DERRLOC_MRCINST_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_TRDC_DERRLOC */ +#define TRDC_MBC2_TRDC_DERRLOC_COUNT (16U) + +/*! @name W0 - MBC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC2_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC2_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W0_EADDR_SHIFT)) & TRDC_MBC2_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W0 */ +#define TRDC_MBC2_W0_COUNT (2U) + +/*! @name W1 - MBC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC2_W1_EDID_MASK (0xFU) +#define TRDC_MBC2_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC2_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EDID_SHIFT)) & TRDC_MBC2_W1_EDID_MASK) + +#define TRDC_MBC2_W1_EATR_MASK (0x700U) +#define TRDC_MBC2_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC2_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EATR_SHIFT)) & TRDC_MBC2_W1_EATR_MASK) + +#define TRDC_MBC2_W1_ERW_MASK (0x800U) +#define TRDC_MBC2_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC2_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_ERW_SHIFT)) & TRDC_MBC2_W1_ERW_MASK) + +#define TRDC_MBC2_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC2_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port + * 0b000..mbcxslv0 + * 0b001..mbcxslv1 + * 0b010..mbcxslv2 + * 0b011..mbcxslv3 + */ +#define TRDC_MBC2_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EPORT_SHIFT)) & TRDC_MBC2_W1_EPORT_MASK) + +#define TRDC_MBC2_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC2_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC2_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EST_SHIFT)) & TRDC_MBC2_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W1 */ +#define TRDC_MBC2_W1_COUNT (2U) + +/*! @name W3 - MBC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC2_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC2_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC2_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W3_RECR_SHIFT)) & TRDC_MBC2_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W3 */ +#define TRDC_MBC2_W3_COUNT (2U) + +/*! @name W0 - MRC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC2_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC2_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W0_EADDR_SHIFT)) & TRDC_MBC2_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W0 */ +#define TRDC_MBC2_MRC_DERR_W0_COUNT (2U) + +/*! @name W1 - MRC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC2_W1_EDID_MASK (0xFU) +#define TRDC_MBC2_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC2_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EDID_SHIFT)) & TRDC_MBC2_W1_EDID_MASK) + +#define TRDC_MBC2_W1_EATR_MASK (0x700U) +#define TRDC_MBC2_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC2_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EATR_SHIFT)) & TRDC_MBC2_W1_EATR_MASK) + +#define TRDC_MBC2_W1_ERW_MASK (0x800U) +#define TRDC_MBC2_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC2_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_ERW_SHIFT)) & TRDC_MBC2_W1_ERW_MASK) + +#define TRDC_MBC2_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC2_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port */ +#define TRDC_MBC2_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EPORT_SHIFT)) & TRDC_MBC2_W1_EPORT_MASK) + +#define TRDC_MBC2_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC2_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC2_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EST_SHIFT)) & TRDC_MBC2_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W1 */ +#define TRDC_MBC2_MRC_DERR_W1_COUNT (2U) + +/*! @name W3 - MRC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC2_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC2_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC2_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W3_RECR_SHIFT)) & TRDC_MBC2_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W3 */ +#define TRDC_MBC2_MRC_DERR_W3_COUNT (2U) + +/*! @name MDA_W_DFMT1 - DAC Master Domain Assignment Register */ +/*! @{ */ + +#define TRDC_MBC2_MDA_W_DFMT1_DID_MASK (0xFU) +#define TRDC_MBC2_MDA_W_DFMT1_DID_SHIFT (0U) +/*! DID - Domain identifier */ +#define TRDC_MBC2_MDA_W_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_DID_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_DID_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_PA_MASK (0x30U) +#define TRDC_MBC2_MDA_W_DFMT1_PA_SHIFT (4U) +/*! PA - Privileged attribute + * 0b00..Force the bus attribute for this master to user. + * 0b01..Force the bus attribute for this master to privileged. + * 0b10..Use the bus master's privileged/user attribute directly. + * 0b11..Use the bus master's privileged/user attribute directly. + */ +#define TRDC_MBC2_MDA_W_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_PA_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_PA_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_SA_MASK (0xC0U) +#define TRDC_MBC2_MDA_W_DFMT1_SA_SHIFT (6U) +/*! SA - Secure attribute + * 0b00..Force the bus attribute for this master to secure. + * 0b01..Force the bus attribute for this master to nonsecure. + * 0b10..Use the bus master's secure/nonsecure attribute directly. + * 0b11..Use the bus master's secure/nonsecure attribute directly. + */ +#define TRDC_MBC2_MDA_W_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_SA_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_SA_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_DIDB_MASK (0x100U) +#define TRDC_MBC2_MDA_W_DFMT1_DIDB_SHIFT (8U) +/*! DIDB - DID Bypass + * 0b0..Use MDAn[3:0] as the domain identifier. + * 0b1..Use the DID input as the domain identifier. + */ +#define TRDC_MBC2_MDA_W_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_DIDB_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_DIDB_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_DFMT_MASK (0x20000000U) +#define TRDC_MBC2_MDA_W_DFMT1_DFMT_SHIFT (29U) +/*! DFMT - Domain format + * 0b0..Processor-core domain assignment + * 0b1..Non-processor domain assignment + */ +#define TRDC_MBC2_MDA_W_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_DFMT_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_DFMT_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_LK1_MASK (0x40000000U) +#define TRDC_MBC2_MDA_W_DFMT1_LK1_SHIFT (30U) +/*! LK1 - 1-bit Lock + * 0b0..Register can be written by any secure privileged write. + * 0b1..Register is locked (read-only) until the next reset. + */ +#define TRDC_MBC2_MDA_W_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_LK1_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_LK1_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_VLD_MASK (0x80000000U) +#define TRDC_MBC2_MDA_W_DFMT1_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..The Wr domain assignment is invalid. + * 0b1..The Wr domain assignment is valid. + */ +#define TRDC_MBC2_MDA_W_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_VLD_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_VLD_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MDA_W_DFMT1 */ +#define TRDC_MBC2_MDA_W_DFMT1_COUNT (5U) + +/* The count of TRDC_MBC2_MDA_W_DFMT1 */ +#define TRDC_MBC2_MDA_W_DFMT1_COUNT2 (1U) + +/*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_MEM_GLBCFG */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_MEM_GLBCFG */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_MASK (0x1U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_SHIFT (0U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_COUNT (2U) + +/*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC2_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_SET */ +#define TRDC_MBC2_MBC_NSE_BLK_SET_COUNT (2U) + +/*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_CLR */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_COUNT (2U) + +/*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_COUNT (2U) + +/*! @name MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_MEMN_GLBAC */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_MEMN_GLBAC */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM3_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM3_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM3_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM4_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM4_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM4_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM5_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM5_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM5_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM6_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM6_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM6_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM7_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM7_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM7_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM8_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM8_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM8_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM9_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM9_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM9_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM10_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM10_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM10_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM11_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM11_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM11_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM12_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM12_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM12_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM13_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM13_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM13_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM14_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM14_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM14_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM15_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM15_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM15_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MRC_GLBCFG - MRC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC2_MRC_GLBCFG_NRGNS_MASK (0x1FU) +#define TRDC_MBC2_MRC_GLBCFG_NRGNS_SHIFT (0U) +/*! NRGNS - Number of regions [1-16] */ +#define TRDC_MBC2_MRC_GLBCFG_NRGNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBCFG_NRGNS_SHIFT)) & TRDC_MBC2_MRC_GLBCFG_NRGNS_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_GLBCFG */ +#define TRDC_MBC2_MRC_GLBCFG_COUNT (2U) + +/*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_INDIRECT */ +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_COUNT (2U) + +/*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_MASK (0xFFFFU) +#define TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC2_MRC_NSE_RGN_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_SET */ +#define TRDC_MBC2_MRC_NSE_RGN_SET_COUNT (2U) + +/*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_MASK (0xFFFFU) +#define TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_CLR */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_COUNT (2U) + +/*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_CLR_ALL */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_COUNT (2U) + +/*! @name MRC_GLBAC - MRC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC2_MRC_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC2_MRC_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NUX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NUX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC2_MRC_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NUW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NUW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC2_MRC_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NUR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NUR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC2_MRC_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NPX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NPX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC2_MRC_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NPW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NPW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC2_MRC_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NPR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NPR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC2_MRC_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SUX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SUX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC2_MRC_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SUW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SUW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC2_MRC_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SUR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SUR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC2_MRC_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SPX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SPX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC2_MRC_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SPW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SPW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC2_MRC_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SPR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SPR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC2_MRC_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked (read-only) and cannot be altered. + */ +#define TRDC_MBC2_MRC_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_LK_SHIFT)) & TRDC_MBC2_MRC_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_GLBAC */ +#define TRDC_MBC2_MRC_GLBAC_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_GLBAC */ +#define TRDC_MBC2_MRC_GLBAC_COUNT2 (8U) + +/*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_W */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_W */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_W */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_W */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_W */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_W */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_W */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_W */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_W */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM3_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_W */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_W */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_W */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM3_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM4_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_W */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_W */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_W */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM4_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM5_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_W */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_W */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_W */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM5_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM6_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_W */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_W */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_W */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM6_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM7_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_W */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_W */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_W */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM7_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM8_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_W */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_W */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_W */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM8_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM9_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_W */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_W */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_W */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM9_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM10_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_W */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_W */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_W */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM10_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM11_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_W */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_W */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_W */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM11_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM12_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_W */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_W */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_W */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM12_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM13_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_W */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_W */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_W */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM13_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM14_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_W */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_W */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_W */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM14_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM15_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_W */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_W */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_W */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM15_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_COUNT (2U) + + +/*! + * @} + */ /* end of group TRDC_MBC2_Register_Masks */ + + +/* TRDC_MBC2 - Peripheral instance base addresses */ +/** Peripheral TRDC1 base address */ +#define TRDC1_BASE (0x44270000u) +/** Peripheral TRDC1 base pointer */ +#define TRDC1 ((TRDC_MBC2_Type *)TRDC1_BASE) +/** Peripheral TRDC2 base address */ +#define TRDC2_BASE (0x42460000u) +/** Peripheral TRDC2 base pointer */ +#define TRDC2 ((TRDC_MBC2_Type *)TRDC2_BASE) +/** Array initializer of TRDC_MBC2 peripheral base addresses */ +#define TRDC_MBC2_BASE_ADDRS { 0u, TRDC1_BASE, TRDC2_BASE } +/** Array initializer of TRDC_MBC2 peripheral base pointers */ +#define TRDC_MBC2_BASE_PTRS { (TRDC_MBC2_Type *)0u, TRDC1, TRDC2 } + +/*! + * @} + */ /* end of group TRDC_MBC2_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC4 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC4_Peripheral_Access_Layer TRDC_MBC4 Peripheral Access Layer + * @{ + */ + +/** TRDC_MBC4 - Register Layout Typedef */ +typedef struct { + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + __I uint32_t TRDC_HWCFG2; /**< TRDC Hardware Configuration Register 2, offset: 0xF8 */ + __I uint32_t TRDC_HWCFG3; /**< TRDC Hardware Configuration Register 3, offset: 0xFC */ + __I uint8_t DACFG[2]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */ + uint8_t RESERVED_1[190]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ + uint8_t RESERVED_3[12]; + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_4[448]; + struct { /* offset: 0x400, array step: 0x10 */ + __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */ + __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ + } MBC_DERR[4]; + uint8_t RESERVED_5[64]; + struct { /* offset: 0x480, array step: 0x10 */ + __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */ + __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ + } MRC_DERR[1]; + uint8_t RESERVED_6[880]; + struct { /* offset: 0x800, array step: 0x20 */ + union { /* offset: 0x800, array step: 0x20 */ + struct { /* offset: 0x800, array step: index*0x20, index2*0x4 */ + __IO uint32_t MDA_W_DFMT0; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4 */ + } MDA_Wx_DFMT0[4]; + } MDA_W_DFMT; + uint8_t RESERVED_0[16]; + } MDA_Wx_y_DFMT[2]; + uint8_t RESERVED_7[63424]; + struct { /* offset: 0x10000, array step: 0x2000 */ + __I uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_0[228]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_1[56]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_2[20]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_4[12]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_5[8]; + __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_6[72]; + __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_7[228]; + __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_8[56]; + __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_9[20]; + __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_10[4]; + __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_11[12]; + __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_12[8]; + __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_13[72]; + __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_14[228]; + __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_15[56]; + __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_16[20]; + __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_18[12]; + __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_19[8]; + __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_20[72]; + __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_21[228]; + __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_22[56]; + __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_23[20]; + __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_24[4]; + __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_25[12]; + __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_26[8]; + __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_27[72]; + __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_28[228]; + __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_29[56]; + __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_30[20]; + __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_31[4]; + __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_32[12]; + __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_33[8]; + __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_34[72]; + __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_35[228]; + __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_36[56]; + __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_37[20]; + __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_38[4]; + __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_39[12]; + __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_40[8]; + __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_41[72]; + __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_42[228]; + __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_43[56]; + __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_44[20]; + __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_45[4]; + __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_46[12]; + __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_47[8]; + __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_48[72]; + __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_49[228]; + __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_50[56]; + __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_51[20]; + __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_52[4]; + __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_53[12]; + __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_54[8]; + __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_55[72]; + __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_56[228]; + __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_57[56]; + __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_58[20]; + __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_59[4]; + __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_60[12]; + __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_61[8]; + __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_62[72]; + __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_63[228]; + __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_64[56]; + __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_65[20]; + __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_66[4]; + __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_67[12]; + __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_68[8]; + __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_69[72]; + __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_70[228]; + __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_71[56]; + __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_72[20]; + __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_73[4]; + __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_74[12]; + __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_75[8]; + __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_76[72]; + __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_77[228]; + __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_78[56]; + __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_79[20]; + __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_80[4]; + __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_81[12]; + __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_82[8]; + __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_83[72]; + __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_84[228]; + __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_85[56]; + __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_86[20]; + __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_87[4]; + __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_88[12]; + __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_89[8]; + __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_90[72]; + __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_91[228]; + __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_92[56]; + __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_93[20]; + __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_94[4]; + __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_95[12]; + __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_96[8]; + __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_97[72]; + __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_98[228]; + __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_99[56]; + __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_100[20]; + __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_101[4]; + __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_102[12]; + __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_103[8]; + __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_104[72]; + __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_105[228]; + __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_106[56]; + __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_107[20]; + __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_108[4]; + __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_109[12]; + __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_110[8]; + __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_111[8]; + } MBC_INDEX[4]; + struct { /* offset: 0x18000, array step: 0xFC4 */ + __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x18000, array step: 0xFC4 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x18010, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x18014, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x18018, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1801C, array step: 0xFC4 */ + __IO uint32_t MRC_GLBAC[8]; /**< MRC Global Access Control, array offset: 0x18020, array step: index*0xFC4, index2*0x4 */ + __IO uint32_t MRC_DOM0_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18040, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x180C0, array step: 0xFC4 */ + uint8_t RESERVED_1[124]; + __IO uint32_t MRC_DOM1_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18140, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM1_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x181C0, array step: 0xFC4 */ + uint8_t RESERVED_2[124]; + __IO uint32_t MRC_DOM2_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18240, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM2_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x182C0, array step: 0xFC4 */ + uint8_t RESERVED_3[124]; + __IO uint32_t MRC_DOM3_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18340, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM3_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x183C0, array step: 0xFC4 */ + uint8_t RESERVED_4[124]; + __IO uint32_t MRC_DOM4_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18440, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM4_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x184C0, array step: 0xFC4 */ + uint8_t RESERVED_5[124]; + __IO uint32_t MRC_DOM5_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18540, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM5_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x185C0, array step: 0xFC4 */ + uint8_t RESERVED_6[124]; + __IO uint32_t MRC_DOM6_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18640, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM6_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x186C0, array step: 0xFC4 */ + uint8_t RESERVED_7[124]; + __IO uint32_t MRC_DOM7_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18740, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM7_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x187C0, array step: 0xFC4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t MRC_DOM8_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18840, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM8_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x188C0, array step: 0xFC4 */ + uint8_t RESERVED_9[124]; + __IO uint32_t MRC_DOM9_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18940, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM9_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x189C0, array step: 0xFC4 */ + uint8_t RESERVED_10[124]; + __IO uint32_t MRC_DOM10_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18A40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM10_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18AC0, array step: 0xFC4 */ + uint8_t RESERVED_11[124]; + __IO uint32_t MRC_DOM11_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18B40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM11_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18BC0, array step: 0xFC4 */ + uint8_t RESERVED_12[124]; + __IO uint32_t MRC_DOM12_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18C40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM12_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18CC0, array step: 0xFC4 */ + uint8_t RESERVED_13[124]; + __IO uint32_t MRC_DOM13_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18D40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM13_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18DC0, array step: 0xFC4 */ + uint8_t RESERVED_14[124]; + __IO uint32_t MRC_DOM14_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18E40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM14_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18EC0, array step: 0xFC4 */ + uint8_t RESERVED_15[124]; + __IO uint32_t MRC_DOM15_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18F40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM15_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18FC0, array step: 0xFC4 */ + } MRC_INDEX[1]; +} TRDC_MBC4_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC4_Register_Masks TRDC_MBC4 Register Masks + * @{ + */ + +/*! @name TRDC_CR - TRDC Register */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_CR_GVLDM_MASK (0x1U) +#define TRDC_MBC4_TRDC_CR_GVLDM_SHIFT (0U) +/*! GVLDM - Global Valid for Domain Assignment Controllers + * 0b0..TRDC DACs are disabled. + * 0b1..TRDC DACs are enabled. + */ +#define TRDC_MBC4_TRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_GVLDM_SHIFT)) & TRDC_MBC4_TRDC_CR_GVLDM_MASK) + +#define TRDC_MBC4_TRDC_CR_HRL_MASK (0x1EU) +#define TRDC_MBC4_TRDC_CR_HRL_SHIFT (1U) +/*! HRL - Hardware Revision Level */ +#define TRDC_MBC4_TRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_HRL_SHIFT)) & TRDC_MBC4_TRDC_CR_HRL_MASK) + +#define TRDC_MBC4_TRDC_CR_GVLDB_MASK (0x4000U) +#define TRDC_MBC4_TRDC_CR_GVLDB_SHIFT (14U) +/*! GVLDB - Global Valid for Memory Block Checkers + * 0b0..TRDC MBCs are disabled. + * 0b1..TRDC MBCs are enabled. + */ +#define TRDC_MBC4_TRDC_CR_GVLDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_GVLDB_SHIFT)) & TRDC_MBC4_TRDC_CR_GVLDB_MASK) + +#define TRDC_MBC4_TRDC_CR_GVLDR_MASK (0x8000U) +#define TRDC_MBC4_TRDC_CR_GVLDR_SHIFT (15U) +/*! GVLDR - Global Valid for Memory Region Checkers + * 0b0..TRDC MRCs are disabled. + * 0b1..TRDC MRCs are enabled. + */ +#define TRDC_MBC4_TRDC_CR_GVLDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_GVLDR_SHIFT)) & TRDC_MBC4_TRDC_CR_GVLDR_MASK) + +#define TRDC_MBC4_TRDC_CR_LK1_MASK (0x40000000U) +#define TRDC_MBC4_TRDC_CR_LK1_SHIFT (30U) +/*! LK1 - Lock Status + * 0b0..The CR can be written by any secure privileged write. + * 0b1..The CR is locked (read-only) until the next reset. + */ +#define TRDC_MBC4_TRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_LK1_SHIFT)) & TRDC_MBC4_TRDC_CR_LK1_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG0 - TRDC Hardware Configuration Register 0 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG0_NDID_MASK (0x1FU) +#define TRDC_MBC4_TRDC_HWCFG0_NDID_SHIFT (0U) +/*! NDID - Number of domains */ +#define TRDC_MBC4_TRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NDID_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) +#define TRDC_MBC4_TRDC_HWCFG0_NMSTR_SHIFT (8U) +/*! NMSTR - Number of bus masters */ +#define TRDC_MBC4_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NMSTR_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_NMBC_MASK (0xF0000U) +#define TRDC_MBC4_TRDC_HWCFG0_NMBC_SHIFT (16U) +/*! NMBC - Number of MBCs */ +#define TRDC_MBC4_TRDC_HWCFG0_NMBC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NMBC_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_NMRC_MASK (0x1F000000U) +#define TRDC_MBC4_TRDC_HWCFG0_NMRC_SHIFT (24U) +/*! NMRC - Number of MRCs */ +#define TRDC_MBC4_TRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NMRC_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_MID_MASK (0xE0000000U) +#define TRDC_MBC4_TRDC_HWCFG0_MID_SHIFT (29U) +/*! MID - Module ID */ +#define TRDC_MBC4_TRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_MID_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_MID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG1_DID_MASK (0xFU) +#define TRDC_MBC4_TRDC_HWCFG1_DID_SHIFT (0U) +/*! DID - Domain identifier number */ +#define TRDC_MBC4_TRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG1_DID_SHIFT)) & TRDC_MBC4_TRDC_HWCFG1_DID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG2 - TRDC Hardware Configuration Register 2 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG2_PIDPn_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_TRDC_HWCFG2_PIDPn_SHIFT (0U) +/*! PIDPn - Process identifier present */ +#define TRDC_MBC4_TRDC_HWCFG2_PIDPn(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG2_PIDPn_SHIFT)) & TRDC_MBC4_TRDC_HWCFG2_PIDPn_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG3 - TRDC Hardware Configuration Register 3 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG3_PIDPn_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_TRDC_HWCFG3_PIDPn_SHIFT (0U) +/*! PIDPn - Process identifier present */ +#define TRDC_MBC4_TRDC_HWCFG3_PIDPn(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG3_PIDPn_SHIFT)) & TRDC_MBC4_TRDC_HWCFG3_PIDPn_MASK) +/*! @} */ + +/*! @name DACFG - Domain Assignment Configuration Register */ +/*! @{ */ + +#define TRDC_MBC4_DACFG_NMDAR_MASK (0xFU) +#define TRDC_MBC4_DACFG_NMDAR_SHIFT (0U) +/*! NMDAR - Number of master domain assignment registers for bus master m */ +#define TRDC_MBC4_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC4_DACFG_NMDAR_SHIFT)) & TRDC_MBC4_DACFG_NMDAR_MASK) + +#define TRDC_MBC4_DACFG_NCM_MASK (0x80U) +#define TRDC_MBC4_DACFG_NCM_SHIFT (7U) +/*! NCM - Non-CPU Master + * 0b0..Bus master is a processor. + * 0b1..Bus master is a non-processor. + */ +#define TRDC_MBC4_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC4_DACFG_NCM_SHIFT)) & TRDC_MBC4_DACFG_NCM_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_DACFG */ +#define TRDC_MBC4_DACFG_COUNT (2U) + +/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_IDAU_CR_VLD_MASK (0x1U) +#define TRDC_MBC4_TRDC_IDAU_CR_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_TRDC_IDAU_CR_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_VLD_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_MASK (0x8U) +#define TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_SHIFT (3U) +/*! CFGSECEXT - Configure Security Extension + * 0b0..Armv8M Security Extension is disabled + * 0b1..Armv8-M Security Extension is enabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_MASK (0x10U) +#define TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_SHIFT (4U) +/*! MPUSDIS - Secure Memory Protection Unit Disabled + * 0b0..Secure MPU is enabled + * 0b1..Secure MPU is disabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_MASK (0x20U) +#define TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_SHIFT (5U) +/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled + * 0b0..Nonsecure MPU is enabled + * 0b1..Nonsecure MPU is disabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_MASK (0x40U) +#define TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_SHIFT (6U) +/*! SAUDIS - Security Attribution Unit Disable + * 0b0..SAU is enabled + * 0b1..SAU is disabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_SAUDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_MASK (0x100U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT (8U) +/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers + * 0b0..Unlock these registers + * 0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_MASK (0x200U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_SHIFT (9U) +/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register + * 0b0..Unlock this register + * 0b1..Disable writes to the VTOR_NS register + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_MASK (0x400U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_SHIFT (10U) +/*! LKSMPU - Lock Secure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or + * from a debug agent connected to the processor in Secure state + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_MASK (0x800U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_SHIFT (11U) +/*! LKNSMPU - Lock Nonsecure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKSAU_MASK (0x1000U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKSAU_SHIFT (12U) +/*! LKSAU - Lock SAU + * 0b0..Unlock these registers + * 0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKSAU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKSAU_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_MASK (0x80000000U) +#define TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_SHIFT (31U) +/*! PCURRNS - Processor current security + * 0b0..Processor is in Secure state + * 0b1..Processor is in Nonsecure state + */ +#define TRDC_MBC4_TRDC_IDAU_CR_PCURRNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_MASK) +/*! @} */ + +/*! @name TRDC_FLW_CTL - TRDC FLW Control */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_CTL_LK_MASK (0x40000000U) +#define TRDC_MBC4_TRDC_FLW_CTL_LK_SHIFT (30U) +/*! LK - Lock bit + * 0b0..FLW registers may be modified. + * 0b1..FLW registers are locked until the next reset. + */ +#define TRDC_MBC4_TRDC_FLW_CTL_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_MBC4_TRDC_FLW_CTL_LK_MASK) + +#define TRDC_MBC4_TRDC_FLW_CTL_V_MASK (0x80000000U) +#define TRDC_MBC4_TRDC_FLW_CTL_V_SHIFT (31U) +/*! V - Valid bit + * 0b0..FLW function is disabled. + * 0b1..FLW function is enabled. + */ +#define TRDC_MBC4_TRDC_FLW_CTL_V(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_CTL_V_SHIFT)) & TRDC_MBC4_TRDC_FLW_CTL_V_MASK) +/*! @} */ + +/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_PBASE_PBASE_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_TRDC_FLW_PBASE_PBASE_SHIFT (0U) +/*! PBASE - Physical base address */ +#define TRDC_MBC4_TRDC_FLW_PBASE_PBASE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_MBC4_TRDC_FLW_PBASE_PBASE_MASK) +/*! @} */ + +/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_MASK (0x3F8000U) +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_SHIFT (15U) +/*! ABASE_L - Array base address low */ +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_MASK) + +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_MASK (0xFFC00000U) +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_SHIFT (22U) +/*! ABASE_H - Array base address high */ +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_MASK) +/*! @} */ + +/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_BCNT_BCNT_MASK (0x7FFFU) +#define TRDC_MBC4_TRDC_FLW_BCNT_BCNT_SHIFT (0U) +/*! BCNT - Block Count */ +#define TRDC_MBC4_TRDC_FLW_BCNT_BCNT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_MBC4_TRDC_FLW_BCNT_BCNT_MASK) +/*! @} */ + +/*! @name TRDC_FDID - TRDC Fault Domain ID */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FDID_FDID_MASK (0xFU) +#define TRDC_MBC4_TRDC_FDID_FDID_SHIFT (0U) +/*! FDID - Domain ID of Faulted Access */ +#define TRDC_MBC4_TRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FDID_FDID_SHIFT)) & TRDC_MBC4_TRDC_FDID_FDID_MASK) +/*! @} */ + +/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_DERRLOC_MBCINST_MASK (0xFFU) +#define TRDC_MBC4_TRDC_DERRLOC_MBCINST_SHIFT (0U) +/*! MBCINST - MBC instance */ +#define TRDC_MBC4_TRDC_DERRLOC_MBCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_DERRLOC_MBCINST_SHIFT)) & TRDC_MBC4_TRDC_DERRLOC_MBCINST_MASK) + +#define TRDC_MBC4_TRDC_DERRLOC_MRCINST_MASK (0xFFFF0000U) +#define TRDC_MBC4_TRDC_DERRLOC_MRCINST_SHIFT (16U) +/*! MRCINST - MRC instance */ +#define TRDC_MBC4_TRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_MBC4_TRDC_DERRLOC_MRCINST_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_TRDC_DERRLOC */ +#define TRDC_MBC4_TRDC_DERRLOC_COUNT (16U) + +/*! @name W0 - MBC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC4_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC4_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W0_EADDR_SHIFT)) & TRDC_MBC4_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W0 */ +#define TRDC_MBC4_W0_COUNT (4U) + +/*! @name W1 - MBC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC4_W1_EDID_MASK (0xFU) +#define TRDC_MBC4_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC4_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EDID_SHIFT)) & TRDC_MBC4_W1_EDID_MASK) + +#define TRDC_MBC4_W1_EATR_MASK (0x700U) +#define TRDC_MBC4_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC4_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EATR_SHIFT)) & TRDC_MBC4_W1_EATR_MASK) + +#define TRDC_MBC4_W1_ERW_MASK (0x800U) +#define TRDC_MBC4_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC4_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_ERW_SHIFT)) & TRDC_MBC4_W1_ERW_MASK) + +#define TRDC_MBC4_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC4_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port + * 0b000..mbcxslv0 + * 0b001..mbcxslv1 + * 0b010..mbcxslv2 + * 0b011..mbcxslv3 + */ +#define TRDC_MBC4_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EPORT_SHIFT)) & TRDC_MBC4_W1_EPORT_MASK) + +#define TRDC_MBC4_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC4_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC4_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EST_SHIFT)) & TRDC_MBC4_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W1 */ +#define TRDC_MBC4_W1_COUNT (4U) + +/*! @name W3 - MBC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC4_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC4_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC4_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W3_RECR_SHIFT)) & TRDC_MBC4_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W3 */ +#define TRDC_MBC4_W3_COUNT (4U) + +/*! @name W0 - MRC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC4_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC4_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W0_EADDR_SHIFT)) & TRDC_MBC4_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W0 */ +#define TRDC_MBC4_MRC_DERR_W0_COUNT (1U) + +/*! @name W1 - MRC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC4_W1_EDID_MASK (0xFU) +#define TRDC_MBC4_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC4_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EDID_SHIFT)) & TRDC_MBC4_W1_EDID_MASK) + +#define TRDC_MBC4_W1_EATR_MASK (0x700U) +#define TRDC_MBC4_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC4_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EATR_SHIFT)) & TRDC_MBC4_W1_EATR_MASK) + +#define TRDC_MBC4_W1_ERW_MASK (0x800U) +#define TRDC_MBC4_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC4_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_ERW_SHIFT)) & TRDC_MBC4_W1_ERW_MASK) + +#define TRDC_MBC4_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC4_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port */ +#define TRDC_MBC4_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EPORT_SHIFT)) & TRDC_MBC4_W1_EPORT_MASK) + +#define TRDC_MBC4_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC4_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC4_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EST_SHIFT)) & TRDC_MBC4_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W1 */ +#define TRDC_MBC4_MRC_DERR_W1_COUNT (1U) + +/*! @name W3 - MRC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC4_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC4_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC4_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W3_RECR_SHIFT)) & TRDC_MBC4_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W3 */ +#define TRDC_MBC4_MRC_DERR_W3_COUNT (1U) + +/*! @name MDA_W_DFMT0 - DAC Master Domain Assignment Register */ +/*! @{ */ + +#define TRDC_MBC4_MDA_W_DFMT0_DID_MASK (0xFU) +#define TRDC_MBC4_MDA_W_DFMT0_DID_SHIFT (0U) +/*! DID - Domain identifier */ +#define TRDC_MBC4_MDA_W_DFMT0_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_DID_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_DID_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_DIDS_MASK (0x30U) +#define TRDC_MBC4_MDA_W_DFMT0_DIDS_SHIFT (4U) +/*! DIDS - DID Select + * 0b00..Use MDAm[3:0] as the domain identifier. + * 0b01..Use the input DID as the domain identifier. + * 0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. + * 0b11..Reserved for future use. + */ +#define TRDC_MBC4_MDA_W_DFMT0_DIDS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_DIDS_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_DIDS_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_PE_MASK (0xC0U) +#define TRDC_MBC4_MDA_W_DFMT0_PE_SHIFT (6U) +/*! PE - Process identifier enable + * 0b00..No process identifier is included in the domain hit evaluation. + * 0b01..No process identifier is included in the domain hit evaluation. + * 0b10..PE = 2 + * 0b11..PE = 3 + */ +#define TRDC_MBC4_MDA_W_DFMT0_PE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_PE_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_PE_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_PIDM_MASK (0x3F00U) +#define TRDC_MBC4_MDA_W_DFMT0_PIDM_SHIFT (8U) +/*! PIDM - Process Identifier Mask */ +#define TRDC_MBC4_MDA_W_DFMT0_PIDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_PIDM_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_PIDM_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_SA_MASK (0xC000U) +#define TRDC_MBC4_MDA_W_DFMT0_SA_SHIFT (14U) +/*! SA - Secure attribute + * 0b00..Force the bus attribute for this master to secure. + * 0b01..Force the bus attribute for this master to nonsecure. + * 0b10..Use the bus master's secure/nonsecure attribute directly. + * 0b11..Use the bus master's secure/nonsecure attribute directly. + */ +#define TRDC_MBC4_MDA_W_DFMT0_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_SA_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_SA_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_PID_MASK (0x3F0000U) +#define TRDC_MBC4_MDA_W_DFMT0_PID_SHIFT (16U) +/*! PID - Process Identifier */ +#define TRDC_MBC4_MDA_W_DFMT0_PID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_PID_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_PID_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_DFMT_MASK (0x20000000U) +#define TRDC_MBC4_MDA_W_DFMT0_DFMT_SHIFT (29U) +/*! DFMT - Domain format + * 0b0..Processor-core domain assignment + * 0b1..Non-processor domain assignment + */ +#define TRDC_MBC4_MDA_W_DFMT0_DFMT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_DFMT_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_DFMT_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_LK1_MASK (0x40000000U) +#define TRDC_MBC4_MDA_W_DFMT0_LK1_SHIFT (30U) +/*! LK1 - 1-bit Lock + * 0b0..Register can be written by any secure privileged write. + * 0b1..Register is locked (read-only) until the next reset. + */ +#define TRDC_MBC4_MDA_W_DFMT0_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_LK1_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_LK1_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_VLD_MASK (0x80000000U) +#define TRDC_MBC4_MDA_W_DFMT0_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..The Wr domain assignment is invalid. + * 0b1..The Wr domain assignment is valid. + */ +#define TRDC_MBC4_MDA_W_DFMT0_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_VLD_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_VLD_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MDA_W_DFMT0 */ +#define TRDC_MBC4_MDA_W_DFMT0_COUNT (2U) + +/* The count of TRDC_MBC4_MDA_W_DFMT0 */ +#define TRDC_MBC4_MDA_W_DFMT0_COUNT2 (4U) + +/*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_MEM_GLBCFG */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_MEM_GLBCFG */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_MASK (0x1U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_SHIFT (0U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_COUNT (4U) + +/*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC4_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_SET */ +#define TRDC_MBC4_MBC_NSE_BLK_SET_COUNT (4U) + +/*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_CLR */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_COUNT (4U) + +/*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_COUNT (4U) + +/*! @name MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_MEMN_GLBAC */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_MEMN_GLBAC */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM3_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM3_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM3_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM3_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM3_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM3_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM3_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM4_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM4_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM4_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM4_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM4_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM4_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM4_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM5_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM5_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM5_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM5_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM5_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM5_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM5_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM6_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM6_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM6_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM6_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM6_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM6_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM6_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM7_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM7_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM7_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM7_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM7_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM7_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM7_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM8_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM8_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM8_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM8_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM8_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM8_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM8_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM9_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM9_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM9_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM9_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM9_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM9_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM9_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM10_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM10_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM10_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM10_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM10_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM10_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM10_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM11_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM11_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM11_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM11_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM11_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM11_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM11_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM12_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM12_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM12_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM12_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM12_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM12_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM12_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM13_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM13_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM13_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM13_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM13_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM13_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM13_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM14_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM14_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM14_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM14_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM14_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM14_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM14_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM15_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM15_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM15_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM15_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM15_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM15_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM15_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MRC_GLBCFG - MRC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC4_MRC_GLBCFG_NRGNS_MASK (0x1FU) +#define TRDC_MBC4_MRC_GLBCFG_NRGNS_SHIFT (0U) +/*! NRGNS - Number of regions [1-16] */ +#define TRDC_MBC4_MRC_GLBCFG_NRGNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBCFG_NRGNS_SHIFT)) & TRDC_MBC4_MRC_GLBCFG_NRGNS_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_GLBCFG */ +#define TRDC_MBC4_MRC_GLBCFG_COUNT (1U) + +/*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_INDIRECT */ +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_COUNT (1U) + +/*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_MASK (0xFFFFU) +#define TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC4_MRC_NSE_RGN_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_SET */ +#define TRDC_MBC4_MRC_NSE_RGN_SET_COUNT (1U) + +/*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_MASK (0xFFFFU) +#define TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_CLR */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_COUNT (1U) + +/*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_CLR_ALL */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_COUNT (1U) + +/*! @name MRC_GLBAC - MRC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC4_MRC_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC4_MRC_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NUX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NUX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC4_MRC_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NUW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NUW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC4_MRC_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NUR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NUR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC4_MRC_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NPX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NPX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC4_MRC_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NPW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NPW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC4_MRC_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NPR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NPR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC4_MRC_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SUX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SUX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC4_MRC_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SUW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SUW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC4_MRC_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SUR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SUR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC4_MRC_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SPX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SPX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC4_MRC_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SPW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SPW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC4_MRC_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SPR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SPR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC4_MRC_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked (read-only) and cannot be altered. + */ +#define TRDC_MBC4_MRC_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_LK_SHIFT)) & TRDC_MBC4_MRC_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_GLBAC */ +#define TRDC_MBC4_MRC_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_GLBAC */ +#define TRDC_MBC4_MRC_GLBAC_COUNT2 (8U) + +/*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_W */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_W */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_W */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_W */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_W */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_W */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_W */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_W */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_W */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM3_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_W */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_W */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_W */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM3_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM4_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_W */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_W */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_W */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM4_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM5_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_W */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_W */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_W */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM5_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM6_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_W */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_W */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_W */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM6_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM7_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_W */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_W */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_W */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM7_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM8_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_W */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_W */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_W */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM8_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM9_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_W */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_W */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_W */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM9_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM10_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_W */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_W */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_W */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM10_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM11_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_W */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_W */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_W */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM11_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM12_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_W */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_W */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_W */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM12_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM13_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_W */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_W */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_W */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM13_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM14_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_W */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_W */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_W */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM14_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM15_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_W */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_W */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_W */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM15_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_COUNT (1U) + + +/*! + * @} + */ /* end of group TRDC_MBC4_Register_Masks */ + + +/* TRDC_MBC4 - Peripheral instance base addresses */ +/** Peripheral TRDC4 base address */ +#define TRDC4_BASE (0x49010000u) +/** Peripheral TRDC4 base pointer */ +#define TRDC4 ((TRDC_MBC4_Type *)TRDC4_BASE) +/** Array initializer of TRDC_MBC4 peripheral base addresses */ +#define TRDC_MBC4_BASE_ADDRS { 0u, 0u, 0u, 0u, TRDC4_BASE } +/** Array initializer of TRDC_MBC4 peripheral base pointers */ +#define TRDC_MBC4_BASE_PTRS { (TRDC_MBC4_Type *)0u, (TRDC_MBC4_Type *)0u, (TRDC_MBC4_Type *)0u, (TRDC_MBC4_Type *)0u, TRDC4 } + +/*! + * @} + */ /* end of group TRDC_MBC4_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRGMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer + * @{ + */ + +/** TRGMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< TRGMUX REG0, offset: 0x0 */ +} TRGMUX_Type; + +/* ---------------------------------------------------------------------------- + -- TRGMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks + * @{ + */ + +/*! @name REG0 - TRGMUX REG0 */ +/*! @{ */ + +#define TRGMUX_REG0_SEL0_MASK (0xFU) +#define TRGMUX_REG0_SEL0_SHIFT (0U) +/*! SEL0 - TRGMUX Source Select 0 */ +#define TRGMUX_REG0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_REG0_SEL0_SHIFT)) & TRGMUX_REG0_SEL0_MASK) + +#define TRGMUX_REG0_SEL1_MASK (0xF00U) +#define TRGMUX_REG0_SEL1_SHIFT (8U) +/*! SEL1 - TRGMUX Source Select 1 */ +#define TRGMUX_REG0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_REG0_SEL1_SHIFT)) & TRGMUX_REG0_SEL1_MASK) + +#define TRGMUX_REG0_LK_MASK (0x80000000U) +#define TRGMUX_REG0_LK_SHIFT (31U) +/*! LK - TRGMUX Register Lock + * 0b0..Register is writable + * 0b1..Register is not writable until the next system reset + */ +#define TRGMUX_REG0_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_REG0_LK_SHIFT)) & TRGMUX_REG0_LK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRGMUX_Register_Masks */ + + +/* TRGMUX - Peripheral instance base addresses */ +/** Peripheral TRGMUX base address */ +#define TRGMUX_BASE (0x44531000u) +/** Peripheral TRGMUX base pointer */ +#define TRGMUX ((TRGMUX_Type *)TRGMUX_BASE) +/** Array initializer of TRGMUX peripheral base addresses */ +#define TRGMUX_BASE_ADDRS { TRGMUX_BASE } +/** Array initializer of TRGMUX peripheral base pointers */ +#define TRGMUX_BASE_PTRS { TRGMUX } + +/*! + * @} + */ /* end of group TRGMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer + * @{ + */ + +/** TSTMR - Register Layout Typedef */ +typedef struct { + __I uint32_t L; /**< Timestamp Timer Low, offset: 0x0 */ + __I uint32_t H; /**< Timestamp Timer High, offset: 0x4 */ +} TSTMR_Type; + +/* ---------------------------------------------------------------------------- + -- TSTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSTMR_Register_Masks TSTMR Register Masks + * @{ + */ + +/*! @name L - Timestamp Timer Low */ +/*! @{ */ + +#define TSTMR_L_VALUE_MASK (0xFFFFFFFFU) +#define TSTMR_L_VALUE_SHIFT (0U) +/*! VALUE - Timestamp Timer Low */ +#define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK) +/*! @} */ + +/*! @name H - Timestamp Timer High */ +/*! @{ */ + +#define TSTMR_H_VALUE_MASK (0xFFFFFFU) +#define TSTMR_H_VALUE_SHIFT (0U) +/*! VALUE - Timestamp Timer High */ +#define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TSTMR_Register_Masks */ + + +/* TSTMR - Peripheral instance base addresses */ +/** Peripheral TSTMR1__TSTMRA base address */ +#define TSTMR1__TSTMRA_BASE (0x442C0000u) +/** Peripheral TSTMR1__TSTMRA base pointer */ +#define TSTMR1__TSTMRA ((TSTMR_Type *)TSTMR1__TSTMRA_BASE) +/** Peripheral TSTMR2__TSTMRA base address */ +#define TSTMR2__TSTMRA_BASE (0x42480000u) +/** Peripheral TSTMR2__TSTMRA base pointer */ +#define TSTMR2__TSTMRA ((TSTMR_Type *)TSTMR2__TSTMRA_BASE) +/** Array initializer of TSTMR peripheral base addresses */ +#define TSTMR_BASE_ADDRS { TSTMR1__TSTMRA_BASE, TSTMR2__TSTMRA_BASE } +/** Array initializer of TSTMR peripheral base pointers */ +#define TSTMR_BASE_PTRS { TSTMR1__TSTMRA, TSTMR2__TSTMRA } +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + + +/*! + * @} + */ /* end of group TSTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + struct { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + } DEVICE; + struct { /* offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + } HOST; + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL1; /**< Endpoint Control 1, offset: 0x1C4 */ + __IO uint32_t ENDPTCTRL2; /**< Endpoint Control 2, offset: 0x1C8 */ + __IO uint32_t ENDPTCTRL3; /**< Endpoint Control 3, offset: 0x1CC */ + __IO uint32_t ENDPTCTRL4; /**< Endpoint Control 4, offset: 0x1D0 */ + __IO uint32_t ENDPTCTRL5; /**< Endpoint Control 5, offset: 0x1D4 */ + __IO uint32_t ENDPTCTRL6; /**< Endpoint Control 6, offset: 0x1D8 */ + __IO uint32_t ENDPTCTRL7; /**< Endpoint Control 7, offset: 0x1DC */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +/*! ID - ID */ +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) + +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +/*! NID - NID */ +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) + +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +/*! REVISION - REVISION */ +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ + +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW - PHYW + * 0b00..8 bit wide data bus (Software non-programmable) + * 0b01..16 bit wide data bus (Software non-programmable) + * 0b10..Reset to 8 bit wide data bus (Software programmable) + * 0b11..Reset to 16 bit wide data bus (Software programmable) + */ +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) + +#define USB_HWGENERAL_PHYM_MASK (0x3C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM - PHYM + * 0b0000..UTMI/UMTI+ + * 0b0001..ULPI DDR + * 0b0010..ULPI + * 0b0011..Serial only + * 0b0100..Software programmable - reset to UTMI/UTMI+ + * 0b0101..Software programmable - reset to ULPI DDR + * 0b0110..Software programmable - reset to ULPI + * 0b0111..Software programmable - reset to serial + * 0b1000..IC - USB + * 0b1001..Software programmable - reset to IC - USB + * 0b1010..HSIC + * 0b1011..Software programmable - reset to HSIC + * 0b1100..Reserved + * 0b1111..Reserved + */ +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) + +#define USB_HWGENERAL_SM_MASK (0xC00U) +#define USB_HWGENERAL_SM_SHIFT (10U) +/*! SM - SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ + +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +/*! HC - HC + * 0b0..Not supported + * 0b1..Supported + */ +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) + +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +/*! NPORT - NPORT */ +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ + +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC - DC + * 0b0..Not supported + * 0b1..Supported + */ +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) + +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +/*! DEVEP - DEVEP */ +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ + +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +/*! TXBURST - TXBURST */ +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) + +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +/*! TXCHANADD - TXCHANADD */ +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ + +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +/*! RXBURST - RXBURST */ +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) + +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +/*! RXADD - RXADD */ +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ + +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +/*! GPTLD - GPTLD */ +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ + +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - GPTCNT */ +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) + +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) + +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) + +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ + +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +/*! GPTLD - GPTLD */ +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ + +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - GPTCNT */ +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) + +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) + +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) + +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ + +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST - AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ + +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - CAPLENGTH */ +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ + +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +/*! HCIVERSION - HCIVERSION */ +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - N_PORTS */ +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) + +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - PPC */ +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) + +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +/*! N_PCC - N_PCC */ +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) + +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC - N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) + +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +/*! PI - PI */ +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) + +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +/*! N_PTT - N_PTT */ +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) + +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +/*! N_TT - N_TT */ +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ + +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +/*! ADC - ADC */ +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) + +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +/*! PFL - PFL */ +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) + +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +/*! ASP - ASP */ +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) + +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +/*! IST - IST */ +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) + +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +/*! EECP - EECP */ +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ + +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +/*! DCIVERSION - DCIVERSION */ +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ + +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +/*! DEN - DEN */ +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) + +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +/*! DC - DC */ +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) + +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +/*! HC - HC */ +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command */ +/*! @{ */ + +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +/*! RS - RS */ +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) + +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +/*! RST - RST */ +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) + +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +/*! FS_1 - FS_1 */ +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) + +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE - PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) + +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE - ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) + +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +/*! IAA - IAA */ +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) + +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +/*! ASP - ASP */ +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) + +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +/*! ASPE - ASPE */ +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) + +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +/*! SUTW - SUTW */ +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) + +#define USB_USBCMD_ATDTW_MASK (0x4000U) +#define USB_USBCMD_ATDTW_SHIFT (14U) +/*! ATDTW - ATDTW */ +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) + +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 - FS_2 */ +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) + +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC - ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status */ +/*! @{ */ + +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +/*! UI - UI */ +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) + +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +/*! UEI - UEI */ +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) + +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +/*! PCI - PCI */ +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) + +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +/*! FRI - FRI */ +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) + +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +/*! SEI - SEI */ +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) + +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +/*! AAI - AAI */ +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) + +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +/*! URI - URI */ +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) + +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +/*! SRI - SRI */ +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) + +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +/*! SLI - SLI */ +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) + +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +/*! ULPII - ULPII */ +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) + +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +/*! HCH - HCH */ +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) + +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +/*! RCL - RCL */ +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) + +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +/*! PS - PS */ +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) + +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +/*! AS - AS */ +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) + +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +/*! NAKI - NAKI */ +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) + +#define USB_USBSTS_UAI_MASK (0x40000U) +#define USB_USBSTS_UAI_SHIFT (18U) +/*! UAI - USB Host Asynchronous Interrupt + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Interrupt occurred + * 0b1..Clear the flag + */ +#define USB_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UAI_SHIFT)) & USB_USBSTS_UAI_MASK) + +#define USB_USBSTS_UPI_MASK (0x80000U) +#define USB_USBSTS_UPI_SHIFT (19U) +/*! UPI - USB Host Periodic Interrupt + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Interrupt occurred + * 0b1..Clear the flag + */ +#define USB_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UPI_SHIFT)) & USB_USBSTS_UPI_MASK) + +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +/*! TI0 - TI0 */ +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) + +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +/*! TI1 - TI1 */ +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable */ +/*! @{ */ + +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +/*! UE - UE */ +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) + +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +/*! UEE - UEE */ +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) + +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +/*! PCE - PCE */ +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) + +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +/*! FRE - FRE */ +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) + +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +/*! SEE - SEE */ +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) + +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +/*! AAE - AAE */ +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) + +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +/*! URE - URE */ +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) + +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +/*! SRE - SRE */ +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) + +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +/*! SLE - SLE */ +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) + +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +/*! NAKE - NAKE */ +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) + +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +/*! UAIE - UAIE */ +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) + +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +/*! UPIE - UPIE */ +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) + +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +/*! TIE0 - TIE0 */ +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) + +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +/*! TIE1 - TIE1 */ +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ + +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX - FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ + +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +/*! USBADRA - USBADRA */ +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) + +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +/*! USBADR - USBADR */ +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ + +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +/*! EPBASE - EPBASE */ +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ + +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +/*! BASEADR - BASEADR */ +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ + +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +/*! ASYBASE - ASYBASE */ +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ + +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +/*! RXPBURST - RXPBURST */ +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) + +#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +/*! TXPBURST - TXPBURST */ +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ + +#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +/*! TXSCHOH - TXSCHOH */ +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) + +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +/*! TXSCHHEALTH - TXSCHHEALTH */ +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) + +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +/*! TXFIFOTHRES - TXFIFOTHRES */ +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ + +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +/*! EPRN - EPRN */ +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) + +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +/*! EPTN - EPTN */ +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ + +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +/*! EPRNE - EPRNE */ +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) + +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +/*! EPTNE - EPTNE */ +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag */ +/*! @{ */ + +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF - CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ + +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +/*! CCS - CCS */ +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) + +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +/*! CSC - CSC */ +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) + +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +/*! PE - PE */ +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) + +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +/*! PEC - PEC */ +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) + +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA - OCA + * 0b0..This port does not have an over-current condition. + * 0b1..This port currently has an over-current condition + */ +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) + +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +/*! OCC - OCC */ +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) + +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +/*! FPR - FPR */ +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) + +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - SUSP */ +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) + +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +/*! PR - PR */ +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) + +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +/*! HSP - HSP */ +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) + +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +/*! LS - LS + * 0b00..SE0 + * 0b01..K-state + * 0b10..J-state + * 0b11..Undefined + */ +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) + +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +/*! PP - PP */ +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) + +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +/*! PO - PO */ +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) + +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC - PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) + +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC - PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + * 0b1000-0b1111..Reserved + */ +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) + +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +/*! WKCN - WKCN */ +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) + +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +/*! WKDC - WKDC */ +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) + +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +/*! WKOC - WKOC */ +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) + +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD - PHCD + * 0b0..Enable PHY clock + * 0b1..Disable PHY clock + */ +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) + +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC - PFSC + * 0b0..Normal operation + * 0b1..Forced to full speed + */ +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) + +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +/*! PTS_2 - PTS_2 */ +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) + +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD - PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) + +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW - PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) + +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +/*! STS - STS */ +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) + +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +/*! PTS_1 - PTS_1 */ +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ + +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +/*! VD - VD */ +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) + +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +/*! VC - VC */ +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) + +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +/*! OT - OT */ +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) + +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +/*! DP - DP */ +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) + +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +/*! IDPU - IDPU */ +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) + +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +/*! ID - ID */ +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) + +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +/*! AVV - AVV */ +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) + +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +/*! ASV - ASV */ +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) + +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +/*! BSV - BSV */ +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) + +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +/*! BSE - BSE */ +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) + +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +/*! TOG_1MS - TOG_1MS */ +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) + +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +/*! DPS - DPS */ +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) + +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +/*! IDIS - IDIS */ +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) + +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +/*! AVVIS - AVVIS */ +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) + +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +/*! ASVIS - ASVIS */ +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) + +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +/*! BSVIS - BSVIS */ +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) + +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +/*! BSEIS - BSEIS */ +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) + +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +/*! STATUS_1MS - STATUS_1MS */ +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) + +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +/*! DPIS - DPIS */ +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) + +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +/*! IDIE - IDIE */ +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) + +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +/*! AVVIE - AVVIE */ +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) + +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +/*! ASVIE - ASVIE */ +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) + +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +/*! BSVIE - BSVIE */ +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) + +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +/*! BSEIE - BSEIE */ +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) + +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +/*! EN_1MS - EN_1MS */ +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) + +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +/*! DPIE - DPIE */ +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ + +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +/*! CM - CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) + +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +/*! ES - ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) + +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM - SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off + */ +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) + +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +/*! SDIS - SDIS */ +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ + +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +/*! ENDPTSETUPSTAT - ENDPTSETUPSTAT */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ + +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +/*! PERB - PERB */ +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) + +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +/*! PETB - PETB */ +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ + +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +/*! FERB - FERB */ +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) + +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +/*! FETB - FETB */ +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ + +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +/*! ERBR - ERBR */ +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) + +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +/*! ETBR - ETBR */ +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ + +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +/*! ERCE - ERCE */ +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) + +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +/*! ETCE - ETCE */ +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ + +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) + +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) + +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) + +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) + +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) + +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL1 - Endpoint Control 1 */ +/*! @{ */ + +#define USB_ENDPTCTRL1_RXS_MASK (0x1U) +#define USB_ENDPTCTRL1_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL1_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXS_SHIFT)) & USB_ENDPTCTRL1_RXS_MASK) + +#define USB_ENDPTCTRL1_RXD_MASK (0x2U) +#define USB_ENDPTCTRL1_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL1_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXD_SHIFT)) & USB_ENDPTCTRL1_RXD_MASK) + +#define USB_ENDPTCTRL1_RXT_MASK (0xCU) +#define USB_ENDPTCTRL1_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL1_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXT_SHIFT)) & USB_ENDPTCTRL1_RXT_MASK) + +#define USB_ENDPTCTRL1_RXI_MASK (0x20U) +#define USB_ENDPTCTRL1_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL1_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXI_SHIFT)) & USB_ENDPTCTRL1_RXI_MASK) + +#define USB_ENDPTCTRL1_RXR_MASK (0x40U) +#define USB_ENDPTCTRL1_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL1_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXR_SHIFT)) & USB_ENDPTCTRL1_RXR_MASK) + +#define USB_ENDPTCTRL1_RXE_MASK (0x80U) +#define USB_ENDPTCTRL1_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL1_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXE_SHIFT)) & USB_ENDPTCTRL1_RXE_MASK) + +#define USB_ENDPTCTRL1_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL1_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL1_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXS_SHIFT)) & USB_ENDPTCTRL1_TXS_MASK) + +#define USB_ENDPTCTRL1_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL1_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL1_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXD_SHIFT)) & USB_ENDPTCTRL1_TXD_MASK) + +#define USB_ENDPTCTRL1_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL1_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL1_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXT_SHIFT)) & USB_ENDPTCTRL1_TXT_MASK) + +#define USB_ENDPTCTRL1_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL1_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL1_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXI_SHIFT)) & USB_ENDPTCTRL1_TXI_MASK) + +#define USB_ENDPTCTRL1_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL1_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL1_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXR_SHIFT)) & USB_ENDPTCTRL1_TXR_MASK) + +#define USB_ENDPTCTRL1_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL1_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL1_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXE_SHIFT)) & USB_ENDPTCTRL1_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL2 - Endpoint Control 2 */ +/*! @{ */ + +#define USB_ENDPTCTRL2_RXS_MASK (0x1U) +#define USB_ENDPTCTRL2_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL2_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXS_SHIFT)) & USB_ENDPTCTRL2_RXS_MASK) + +#define USB_ENDPTCTRL2_RXD_MASK (0x2U) +#define USB_ENDPTCTRL2_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL2_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXD_SHIFT)) & USB_ENDPTCTRL2_RXD_MASK) + +#define USB_ENDPTCTRL2_RXT_MASK (0xCU) +#define USB_ENDPTCTRL2_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL2_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXT_SHIFT)) & USB_ENDPTCTRL2_RXT_MASK) + +#define USB_ENDPTCTRL2_RXI_MASK (0x20U) +#define USB_ENDPTCTRL2_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL2_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXI_SHIFT)) & USB_ENDPTCTRL2_RXI_MASK) + +#define USB_ENDPTCTRL2_RXR_MASK (0x40U) +#define USB_ENDPTCTRL2_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL2_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXR_SHIFT)) & USB_ENDPTCTRL2_RXR_MASK) + +#define USB_ENDPTCTRL2_RXE_MASK (0x80U) +#define USB_ENDPTCTRL2_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL2_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXE_SHIFT)) & USB_ENDPTCTRL2_RXE_MASK) + +#define USB_ENDPTCTRL2_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL2_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL2_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXS_SHIFT)) & USB_ENDPTCTRL2_TXS_MASK) + +#define USB_ENDPTCTRL2_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL2_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL2_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXD_SHIFT)) & USB_ENDPTCTRL2_TXD_MASK) + +#define USB_ENDPTCTRL2_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL2_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL2_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXT_SHIFT)) & USB_ENDPTCTRL2_TXT_MASK) + +#define USB_ENDPTCTRL2_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL2_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL2_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXI_SHIFT)) & USB_ENDPTCTRL2_TXI_MASK) + +#define USB_ENDPTCTRL2_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL2_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL2_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXR_SHIFT)) & USB_ENDPTCTRL2_TXR_MASK) + +#define USB_ENDPTCTRL2_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL2_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL2_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXE_SHIFT)) & USB_ENDPTCTRL2_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL3 - Endpoint Control 3 */ +/*! @{ */ + +#define USB_ENDPTCTRL3_RXS_MASK (0x1U) +#define USB_ENDPTCTRL3_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL3_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXS_SHIFT)) & USB_ENDPTCTRL3_RXS_MASK) + +#define USB_ENDPTCTRL3_RXD_MASK (0x2U) +#define USB_ENDPTCTRL3_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL3_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXD_SHIFT)) & USB_ENDPTCTRL3_RXD_MASK) + +#define USB_ENDPTCTRL3_RXT_MASK (0xCU) +#define USB_ENDPTCTRL3_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL3_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXT_SHIFT)) & USB_ENDPTCTRL3_RXT_MASK) + +#define USB_ENDPTCTRL3_RXI_MASK (0x20U) +#define USB_ENDPTCTRL3_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL3_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXI_SHIFT)) & USB_ENDPTCTRL3_RXI_MASK) + +#define USB_ENDPTCTRL3_RXR_MASK (0x40U) +#define USB_ENDPTCTRL3_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL3_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXR_SHIFT)) & USB_ENDPTCTRL3_RXR_MASK) + +#define USB_ENDPTCTRL3_RXE_MASK (0x80U) +#define USB_ENDPTCTRL3_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL3_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXE_SHIFT)) & USB_ENDPTCTRL3_RXE_MASK) + +#define USB_ENDPTCTRL3_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL3_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL3_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXS_SHIFT)) & USB_ENDPTCTRL3_TXS_MASK) + +#define USB_ENDPTCTRL3_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL3_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL3_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXD_SHIFT)) & USB_ENDPTCTRL3_TXD_MASK) + +#define USB_ENDPTCTRL3_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL3_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL3_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXT_SHIFT)) & USB_ENDPTCTRL3_TXT_MASK) + +#define USB_ENDPTCTRL3_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL3_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL3_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXI_SHIFT)) & USB_ENDPTCTRL3_TXI_MASK) + +#define USB_ENDPTCTRL3_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL3_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL3_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXR_SHIFT)) & USB_ENDPTCTRL3_TXR_MASK) + +#define USB_ENDPTCTRL3_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL3_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL3_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXE_SHIFT)) & USB_ENDPTCTRL3_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL4 - Endpoint Control 4 */ +/*! @{ */ + +#define USB_ENDPTCTRL4_RXS_MASK (0x1U) +#define USB_ENDPTCTRL4_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL4_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXS_SHIFT)) & USB_ENDPTCTRL4_RXS_MASK) + +#define USB_ENDPTCTRL4_RXD_MASK (0x2U) +#define USB_ENDPTCTRL4_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL4_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXD_SHIFT)) & USB_ENDPTCTRL4_RXD_MASK) + +#define USB_ENDPTCTRL4_RXT_MASK (0xCU) +#define USB_ENDPTCTRL4_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL4_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXT_SHIFT)) & USB_ENDPTCTRL4_RXT_MASK) + +#define USB_ENDPTCTRL4_RXI_MASK (0x20U) +#define USB_ENDPTCTRL4_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL4_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXI_SHIFT)) & USB_ENDPTCTRL4_RXI_MASK) + +#define USB_ENDPTCTRL4_RXR_MASK (0x40U) +#define USB_ENDPTCTRL4_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL4_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXR_SHIFT)) & USB_ENDPTCTRL4_RXR_MASK) + +#define USB_ENDPTCTRL4_RXE_MASK (0x80U) +#define USB_ENDPTCTRL4_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL4_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXE_SHIFT)) & USB_ENDPTCTRL4_RXE_MASK) + +#define USB_ENDPTCTRL4_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL4_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL4_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXS_SHIFT)) & USB_ENDPTCTRL4_TXS_MASK) + +#define USB_ENDPTCTRL4_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL4_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL4_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXD_SHIFT)) & USB_ENDPTCTRL4_TXD_MASK) + +#define USB_ENDPTCTRL4_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL4_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL4_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXT_SHIFT)) & USB_ENDPTCTRL4_TXT_MASK) + +#define USB_ENDPTCTRL4_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL4_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL4_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXI_SHIFT)) & USB_ENDPTCTRL4_TXI_MASK) + +#define USB_ENDPTCTRL4_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL4_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL4_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXR_SHIFT)) & USB_ENDPTCTRL4_TXR_MASK) + +#define USB_ENDPTCTRL4_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL4_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL4_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXE_SHIFT)) & USB_ENDPTCTRL4_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL5 - Endpoint Control 5 */ +/*! @{ */ + +#define USB_ENDPTCTRL5_RXS_MASK (0x1U) +#define USB_ENDPTCTRL5_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL5_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXS_SHIFT)) & USB_ENDPTCTRL5_RXS_MASK) + +#define USB_ENDPTCTRL5_RXD_MASK (0x2U) +#define USB_ENDPTCTRL5_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL5_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXD_SHIFT)) & USB_ENDPTCTRL5_RXD_MASK) + +#define USB_ENDPTCTRL5_RXT_MASK (0xCU) +#define USB_ENDPTCTRL5_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL5_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXT_SHIFT)) & USB_ENDPTCTRL5_RXT_MASK) + +#define USB_ENDPTCTRL5_RXI_MASK (0x20U) +#define USB_ENDPTCTRL5_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL5_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXI_SHIFT)) & USB_ENDPTCTRL5_RXI_MASK) + +#define USB_ENDPTCTRL5_RXR_MASK (0x40U) +#define USB_ENDPTCTRL5_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL5_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXR_SHIFT)) & USB_ENDPTCTRL5_RXR_MASK) + +#define USB_ENDPTCTRL5_RXE_MASK (0x80U) +#define USB_ENDPTCTRL5_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL5_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXE_SHIFT)) & USB_ENDPTCTRL5_RXE_MASK) + +#define USB_ENDPTCTRL5_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL5_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL5_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXS_SHIFT)) & USB_ENDPTCTRL5_TXS_MASK) + +#define USB_ENDPTCTRL5_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL5_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL5_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXD_SHIFT)) & USB_ENDPTCTRL5_TXD_MASK) + +#define USB_ENDPTCTRL5_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL5_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL5_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXT_SHIFT)) & USB_ENDPTCTRL5_TXT_MASK) + +#define USB_ENDPTCTRL5_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL5_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL5_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXI_SHIFT)) & USB_ENDPTCTRL5_TXI_MASK) + +#define USB_ENDPTCTRL5_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL5_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL5_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXR_SHIFT)) & USB_ENDPTCTRL5_TXR_MASK) + +#define USB_ENDPTCTRL5_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL5_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL5_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXE_SHIFT)) & USB_ENDPTCTRL5_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL6 - Endpoint Control 6 */ +/*! @{ */ + +#define USB_ENDPTCTRL6_RXS_MASK (0x1U) +#define USB_ENDPTCTRL6_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL6_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXS_SHIFT)) & USB_ENDPTCTRL6_RXS_MASK) + +#define USB_ENDPTCTRL6_RXD_MASK (0x2U) +#define USB_ENDPTCTRL6_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL6_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXD_SHIFT)) & USB_ENDPTCTRL6_RXD_MASK) + +#define USB_ENDPTCTRL6_RXT_MASK (0xCU) +#define USB_ENDPTCTRL6_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL6_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXT_SHIFT)) & USB_ENDPTCTRL6_RXT_MASK) + +#define USB_ENDPTCTRL6_RXI_MASK (0x20U) +#define USB_ENDPTCTRL6_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL6_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXI_SHIFT)) & USB_ENDPTCTRL6_RXI_MASK) + +#define USB_ENDPTCTRL6_RXR_MASK (0x40U) +#define USB_ENDPTCTRL6_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL6_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXR_SHIFT)) & USB_ENDPTCTRL6_RXR_MASK) + +#define USB_ENDPTCTRL6_RXE_MASK (0x80U) +#define USB_ENDPTCTRL6_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL6_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXE_SHIFT)) & USB_ENDPTCTRL6_RXE_MASK) + +#define USB_ENDPTCTRL6_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL6_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL6_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXS_SHIFT)) & USB_ENDPTCTRL6_TXS_MASK) + +#define USB_ENDPTCTRL6_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL6_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL6_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXD_SHIFT)) & USB_ENDPTCTRL6_TXD_MASK) + +#define USB_ENDPTCTRL6_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL6_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL6_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXT_SHIFT)) & USB_ENDPTCTRL6_TXT_MASK) + +#define USB_ENDPTCTRL6_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL6_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL6_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXI_SHIFT)) & USB_ENDPTCTRL6_TXI_MASK) + +#define USB_ENDPTCTRL6_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL6_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL6_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXR_SHIFT)) & USB_ENDPTCTRL6_TXR_MASK) + +#define USB_ENDPTCTRL6_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL6_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL6_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXE_SHIFT)) & USB_ENDPTCTRL6_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL7 - Endpoint Control 7 */ +/*! @{ */ + +#define USB_ENDPTCTRL7_RXS_MASK (0x1U) +#define USB_ENDPTCTRL7_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL7_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXS_SHIFT)) & USB_ENDPTCTRL7_RXS_MASK) + +#define USB_ENDPTCTRL7_RXD_MASK (0x2U) +#define USB_ENDPTCTRL7_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL7_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXD_SHIFT)) & USB_ENDPTCTRL7_RXD_MASK) + +#define USB_ENDPTCTRL7_RXT_MASK (0xCU) +#define USB_ENDPTCTRL7_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL7_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXT_SHIFT)) & USB_ENDPTCTRL7_RXT_MASK) + +#define USB_ENDPTCTRL7_RXI_MASK (0x20U) +#define USB_ENDPTCTRL7_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL7_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXI_SHIFT)) & USB_ENDPTCTRL7_RXI_MASK) + +#define USB_ENDPTCTRL7_RXR_MASK (0x40U) +#define USB_ENDPTCTRL7_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL7_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXR_SHIFT)) & USB_ENDPTCTRL7_RXR_MASK) + +#define USB_ENDPTCTRL7_RXE_MASK (0x80U) +#define USB_ENDPTCTRL7_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL7_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXE_SHIFT)) & USB_ENDPTCTRL7_RXE_MASK) + +#define USB_ENDPTCTRL7_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL7_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL7_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXS_SHIFT)) & USB_ENDPTCTRL7_TXS_MASK) + +#define USB_ENDPTCTRL7_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL7_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL7_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXD_SHIFT)) & USB_ENDPTCTRL7_TXD_MASK) + +#define USB_ENDPTCTRL7_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL7_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL7_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXT_SHIFT)) & USB_ENDPTCTRL7_TXT_MASK) + +#define USB_ENDPTCTRL7_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL7_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL7_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXI_SHIFT)) & USB_ENDPTCTRL7_TXI_MASK) + +#define USB_ENDPTCTRL7_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL7_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL7_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXR_SHIFT)) & USB_ENDPTCTRL7_TXR_MASK) + +#define USB_ENDPTCTRL7_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL7_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL7_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXE_SHIFT)) & USB_ENDPTCTRL7_TXE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB__USB_OTG1 base address */ +#define USB__USB_OTG1_BASE (0x4C100000u) +/** Peripheral USB__USB_OTG1 base pointer */ +#define USB__USB_OTG1 ((USB_Type *)USB__USB_OTG1_BASE) +/** Peripheral USB__USB_OTG2 base address */ +#define USB__USB_OTG2_BASE (0x4C200000u) +/** Peripheral USB__USB_OTG2 base pointer */ +#define USB__USB_OTG2 ((USB_Type *)USB__USB_OTG2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB__USB_OTG1_BASE, USB__USB_OTG2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB__USB_OTG1, USB__USB_OTG2 } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ + uint8_t RESERVED_0[36]; + __IO uint32_t HSIC_DLL_CFG4; /**< HSIC DLL Configure Register 4, offset: 0x2C */ + __IO uint32_t UTMIPHY_CFG1; /**< PHY Configure 1, offset: 0x30 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name CTRL1 - USB OTG Control 1 */ +/*! @{ */ + +#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS - OVER_CUR_DIS + * 0b0..Enables overcurrent detection + * 0b1..Disables overcurrent detection + */ +#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) + +#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) +#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL - OVER_CUR_POL + * 0b0..High active (high on this signal represents an overcurrent condition) + * 0b1..Low active (low on this signal represents an overcurrent condition) + */ +#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) + +#define USBNC_CTRL1_PWR_POL_MASK (0x200U) +#define USBNC_CTRL1_PWR_POL_SHIFT (9U) +/*! PWR_POL - PWR_POL + * 0b0..PMIC Power Pin is Low active. + * 0b1..PMIC Power Pin is High active. + */ +#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) + +#define USBNC_CTRL1_WIE_MASK (0x400U) +#define USBNC_CTRL1_WIE_SHIFT (10U) +/*! WIE - WIE + * 0b0..Interrupt Disabled + * 0b1..Interrupt Enabled + */ +#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) + +#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN - WKUP_SW_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) + +#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) +#define USBNC_CTRL1_WKUP_SW_SHIFT (15U) +/*! WKUP_SW - WKUP_SW + * 0b0..Inactive + * 0b1..Force wake-up + */ +#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) + +#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN - WKUP_ID_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) + +#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN - WKUP_VBUS_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) + +#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN - Wake-up on DP/DM change enable + * 0b0..DP/DM changes wake-up to be disabled only when VBUS is 0. + * 0b1..(Default) DP/DM changes wake-up to be enabled, it is for device only. + */ +#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) + +#define USBNC_CTRL1_WIR_MASK (0x80000000U) +#define USBNC_CTRL1_WIR_SHIFT (31U) +/*! WIR - WIR + * 0b0..No wake-up interrupt request received + * 0b1..Wake-up Interrupt Request received + */ +#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) +/*! @} */ + +/*! @name CTRL2 - USB OTG Control 2 */ +/*! @{ */ + +#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) +#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL + * 0b00..vbus_valid + * 0b01..sess_valid + * 0b10..sess_valid + * 0b11..sess_valid + */ +#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) + +#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) +#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) +/*! AUTURESUME_EN - Auto Resume Enable + * 0b0..Default + */ +#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) + +#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) +#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) +/*! LOWSPEED_EN - Low speed enable + * 0b0..Default + */ +#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) + +#define USBNC_CTRL2_OPMODE_OVERRIDE_MASK (0xC0U) +#define USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT (6U) +/*! OPMODE_OVERRIDE - utmi_OpMode[1:0] override value + * 0b00..utmi_OpMode[1:0] override to 2'b00. + * 0b01..utmi_OpMode[1:0] override to 2'b01. + * 0b10..utmi_OpMode[1:0] override to 2'b10. + * 0b11..utmi_OpMode[1:0] override to 2'b11. + */ +#define USBNC_CTRL2_OPMODE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDE_MASK) + +#define USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK (0x100U) +#define USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT (8U) +/*! OPMODE_OVERRIDEEN - utmi_OpMode[1:0] override enable + * 0b0..utmi_OpMode[1:0] override disable. + * 0b1..utmi_OpMode[1:0] override enable. + */ +#define USBNC_CTRL2_OPMODE_OVERRIDEEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK) + +#define USBNC_CTRL2_SHORT_PKT_EN_MASK (0x800000U) +#define USBNC_CTRL2_SHORT_PKT_EN_SHIFT (23U) +/*! SHORT_PKT_EN - Short Packet Interrupt + * 0b0..Default + */ +#define USBNC_CTRL2_SHORT_PKT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_SHORT_PKT_EN_SHIFT)) & USBNC_CTRL2_SHORT_PKT_EN_MASK) + +#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD - UTMI_CLK_VLD + * 0b0..Default + */ +#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) +/*! @} */ + +/*! @name HSIC_DLL_CFG4 - HSIC DLL Configure Register 4 */ +/*! @{ */ + +#define USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_MASK (0x80000000U) +#define USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_SHIFT (31U) +/*! FS_ISO_B2B_FIXEN - FS Isochronous Back to Back Transfer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_SHIFT)) & USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_MASK) +/*! @} */ + +/*! @name UTMIPHY_CFG1 - PHY Configure 1 */ +/*! @{ */ + +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_MASK (0x70U) +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_SHIFT (4U) +/*! COMPDISTUNE0 - Disconnect Threshold Adjustment + * 0b000..-9.71% + * 0b001..-6.85% + * 0b010..-3.36% + * 0b011..0, Design default + * 0b100..+4.04% + * 0b101..+8.22% + * 0b110..+13.18% + * 0b111..+18.39% + */ +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_COMPDISTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_COMPDISTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0_MASK (0x380U) +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0_SHIFT (7U) +/*! SQRXTUNE0 - Squelch Threshold Adjustment + * 0b000..+15.19% + * 0b001..+10.04% + * 0b010..+5.14% + * 0b011..0, design default + * 0b100..-5.04% + * 0b101..-10.19% + * 0b110..-15.09% + * 0b111..-20.24% + */ +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_SQRXTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_SQRXTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_OTGTUNE0_MASK (0x1C00U) +#define USBNC_UTMIPHY_CFG1_OTGTUNE0_SHIFT (10U) +/*! OTGTUNE0 - VBUS Valid Threshold Adjustment + * 0b000..-9% + * 0b001..-6% + * 0b010..-3% + * 0b011..0, Design default + * 0b100..+3% + * 0b101..+6% + * 0b110..+9% + * 0b111..+12% + */ +#define USBNC_UTMIPHY_CFG1_OTGTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_OTGTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_OTGTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_MASK (0x6000U) +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_SHIFT (13U) +/*! TXHSXVTUNE0 - Transmitter High-Speed Crossover Adjustment + * 0b00..Reserved + * 0b01..-17.31 mV + * 0b10..-16.69 mV + * 0b11..0, design default + */ +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_PHY_POR_SW_MASK (0x8000U) +#define USBNC_UTMIPHY_CFG1_PHY_POR_SW_SHIFT (15U) +/*! PHY_POR_SW - PHY software POR + * 0b0..Do not perform the Power-On Reset by software. + * 0b1..Perform the Power-On Reset by software. + */ +#define USBNC_UTMIPHY_CFG1_PHY_POR_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_PHY_POR_SW_SHIFT)) & USBNC_UTMIPHY_CFG1_PHY_POR_SW_MASK) + +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_MASK (0xF0000U) +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_SHIFT (16U) +/*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment + * 0b0000..+6.27% + * 0b0001..+3.02% + * 0b0011..0, design default + * 0b0111..-3.23% + * 0b1111..-6.25% + */ +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_MASK (0xF00000U) +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_SHIFT (20U) +/*! TXVREFTUNE0 - HS DC Voltage Level Adjustment + * 0b0000..-5.88% + * 0b0001..-3.92% + * 0b0010..-1.96% + * 0b0011..0, design default + * 0b0100..+1.96% + * 0b0101..+3.92% + * 0b0110..+5.88% + * 0b0111..+7.84% + * 0b1000..+9.80% + * 0b1001..+11.75% + * 0b1010..+13.71% + * 0b1011..+15.67% + * 0b1100..+17.63% + * 0b1101..+19.59% + * 0b1110..+21.55% + * 0b1111..+23.51% + */ +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXVREFTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXVREFTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0_MASK (0x3000000U) +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0_SHIFT (24U) +/*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment + * 0b00..+3.46% + * 0b01..0, Design default + * 0b10..-1.47% + * 0b11..-3.33% + */ +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXRISETUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXRISETUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0_MASK (0xC000000U) +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0_SHIFT (26U) +/*! TXRESTUNE0 - USB Source Impedance Adjustment + * 0b00..Source impedance is increased by approximately 3.01 ohm + * 0b01..00, design default + * 0b10..Source impedance is decreased by approximately 1.32 ohm + * 0b11..Source impedance is decreased by approximately 3.71 ohm + */ +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXRESTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXRESTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_MASK (0x30000000U) +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_SHIFT (28U) +/*! TXPREEMPAMPTUNE0 - HS Transmitter Pre-Emphasis Current Control + * 0b00..HS Transmitter pre-emphasis is disabled. + * 0b01..HS Transmitter pre-emphasis circuit sources 1x pre-emphasis current. + * 0b10..HS Transmitter pre-emphasis circuit sources 2x pre-emphasis current. + * 0b11..HS Transmitter pre-emphasis circuit sources 3x pre-emphasis current. + */ +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_MASK (0x40000000U) +#define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_SHIFT (30U) +/*! TXPREEMPPULSETUNE0 - HS Transmitter Pre-Emphasis Duration Control + * 0b0..Design default. Long pre-emphasis current duration + * 0b1..Short pre-emphasis current duration + */ +#define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USB__USBNC_OTG1 base address */ +#define USB__USBNC_OTG1_BASE (0x4C100200u) +/** Peripheral USB__USBNC_OTG1 base pointer */ +#define USB__USBNC_OTG1 ((USBNC_Type *)USB__USBNC_OTG1_BASE) +/** Peripheral USB__USBNC_OTG2 base address */ +#define USB__USBNC_OTG2_BASE (0x4C200200u) +/** Peripheral USB__USBNC_OTG2 base pointer */ +#define USB__USBNC_OTG2 ((USBNC_Type *)USB__USBNC_OTG2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { USB__USBNC_OTG1_BASE, USB__USBNC_OTG2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { USB__USBNC_OTG1, USB__USBNC_OTG2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[4]; + __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */ + __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */ + uint8_t RESERVED_3[72]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< eMMC Boot, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ + uint8_t RESERVED_4[48]; + __I uint32_t CQVER; /**< Command Queuing Version, offset: 0x100 */ + __IO uint32_t CQCAP; /**< Command Queuing Capabilities, offset: 0x104 */ + __IO uint32_t CQCFG; /**< Command Queuing Configuration, offset: 0x108 */ + __IO uint32_t CQCTL; /**< Command Queuing Control, offset: 0x10C */ + __IO uint32_t CQIS; /**< Command Queuing Interrupt Status, offset: 0x110 */ + __IO uint32_t CQISTE; /**< Command Queuing Interrupt Status Enable, offset: 0x114 */ + __IO uint32_t CQISGE; /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */ + __IO uint32_t CQIC; /**< Command Queuing Interrupt Coalescing, offset: 0x11C */ + __IO uint32_t CQTDLBA; /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */ + __IO uint32_t CQTDLBAU; /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */ + __IO uint32_t CQTDBR; /**< Command Queuing Task Doorbell, offset: 0x128 */ + __IO uint32_t CQTCN; /**< Command Queuing Task Completion Notification, offset: 0x12C */ + __I uint32_t CQDQS; /**< Command Queuing Device Queue Status, offset: 0x130 */ + __I uint32_t CQDPT; /**< Command Queuing Device Pending Tasks, offset: 0x134 */ + __IO uint32_t CQTCLR; /**< Command Queuing Task Clear, offset: 0x138 */ + uint8_t RESERVED_5[4]; + __IO uint32_t CQSSC1; /**< Command Queuing Send Status Configuration 1, offset: 0x140 */ + __IO uint32_t CQSSC2; /**< Command Queuing Send Status Configuration 2, offset: 0x144 */ + __I uint32_t CQCRDCT; /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */ + uint8_t RESERVED_6[4]; + __IO uint32_t CQRMEM; /**< Command Queuing Response Mode Error Mask, offset: 0x150 */ + __I uint32_t CQTERRI; /**< Command Queuing Task Error Information, offset: 0x154 */ + __I uint32_t CQCRI; /**< Command Queuing Command Response Index, offset: 0x158 */ + __I uint32_t CQCRA; /**< Command Queuing Command Response Argument, offset: 0x15C */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +/*! @{ */ + +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +/*! DS_ADDR - System address */ +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ + +/*! @name BLK_ATT - Block Attributes */ +/*! @{ */ + +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Transfer block size + * 0b0000000000000..No data transfer + * 0b0000000000001..1 byte + * 0b0000000000010..2 bytes + * 0b0000000000011..3 bytes + * 0b0000000000100..4 bytes + * 0b0000111111111..511 bytes + * 0b0001000000000..512 bytes + * 0b0100000000000..2048 bytes + * 0b1000000000000..4096 bytes + */ +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) + +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT - Blocks count for current transfer + * 0b0000000000000000..Stop count + * 0b0000000000000001..1 block + * 0b0000000000000010..2 blocks + * 0b1111111111111111..65535 blocks + */ +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ + +/*! @name CMD_ARG - Command Argument */ +/*! @{ */ + +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +/*! CMDARG - Command argument */ +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ + +#define USDHC_CMD_XFR_TYP_DMAEN_MASK (0x1U) +#define USDHC_CMD_XFR_TYP_DMAEN_SHIFT (0U) +/*! DMAEN - DMAEN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK) + +#define USDHC_CMD_XFR_TYP_BCEN_MASK (0x2U) +#define USDHC_CMD_XFR_TYP_BCEN_SHIFT (1U) +/*! BCEN - BCEN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK) + +#define USDHC_CMD_XFR_TYP_AC12EN_MASK (0x4U) +#define USDHC_CMD_XFR_TYP_AC12EN_SHIFT (2U) +/*! AC12EN - AC12EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK) + +#define USDHC_CMD_XFR_TYP_DDR_EN_MASK (0x8U) +#define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT (3U) +/*! DDR_EN - DDR_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK) + +#define USDHC_CMD_XFR_TYP_DTDSEL_MASK (0x10U) +#define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT (4U) +/*! DTDSEL - DTDSEL + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK) + +#define USDHC_CMD_XFR_TYP_MSBSEL_MASK (0x20U) +#define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT (5U) +/*! MSBSEL - MSBSEL + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK) + +#define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK (0x40U) +#define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT (6U) +/*! NIBBLE_POS - NIBBLE_POS + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK) + +#define USDHC_CMD_XFR_TYP_AC23EN_MASK (0x80U) +#define USDHC_CMD_XFR_TYP_AC23EN_SHIFT (7U) +/*! AC23EN - AC23EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK) + +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response type select + * 0b00..No response + * 0b01..Response length 136 + * 0b10..Response length 48 + * 0b11..Response length 48, check busy after response + */ +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) + +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC check enable + * 0b0..Disables command CRC check + * 0b1..Enables command CRC check + */ +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) + +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command index check enable + * 0b0..Disable command index check + * 0b1..Enables command index check + */ +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) + +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data present select + * 0b0..No data present + * 0b1..Data present + */ +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) + +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command type + * 0b00..Normal other commands + * 0b01..Suspend CMD52 for writing bus suspend in CCCR + * 0b10..Resume CMD52 for writing function select in CCCR + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + */ +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) + +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +/*! CMDINX - Command index */ +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ + +/*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ + +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +/*! CMDRSP0 - Command response 0 */ +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ + +/*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ + +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +/*! CMDRSP1 - Command response 1 */ +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ + +/*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ + +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +/*! CMDRSP2 - Command response 2 */ +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ + +/*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ + +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +/*! CMDRSP3 - Command response 3 */ +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ + +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +/*! DATCONT - Data content */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ + +/*! @name PRES_STATE - Present State */ +/*! @{ */ + +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command inhibit (CMD) + * 0b0..Can issue command using only CMD line + * 0b1..Cannot issue command + */ +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) + +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit Data (DATA) + * 0b0..Can issue command that uses the DATA line + * 0b1..Cannot issue command that uses the DATA line + */ +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) + +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data line active + * 0b0..DATA line inactive + * 0b1..DATA line active + */ +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) + +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD clock stable + * 0b0..Clock is changing frequency and not stable. + * 0b1..Clock is stable. + */ +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) + +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write transfer active + * 0b0..No valid data + * 0b1..Transferring data + */ +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) + +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read transfer active + * 0b0..No valid data + * 0b1..Transferring data + */ +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) + +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer write enable + * 0b0..Write disable + * 0b1..Write enable + */ +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) + +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer read enable + * 0b0..Read disable + * 0b1..Read enable + */ +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) + +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode, and eMMC HS200 mode) + * 0b0..Fixed or well tuned sampling clock + * 0b1..Sampling clock needs re-tuning + */ +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) + +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tap select change done + * 0b0..Delay cell select change is not finished. + * 0b1..Delay cell select change is finished. + */ +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) + +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card inserted + * 0b0..Power on reset or no card + * 0b1..Card inserted + */ +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) + +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card detect pin level + * 0b0..No card present (CD_B = 1) + * 0b1..Card present (CD_B = 0) + */ +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) + +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write protect switch pin level + * 0b0..Write protected (WP = 1) + * 0b1..Write enabled (WP = 0) + */ +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) + +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +/*! CLSL - CMD line signal level */ +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) + +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] line signal level + * 0b00000001..Data 0 line signal level + * 0b00000010..Data 1 line signal level + * 0b00000100..Data 2 line signal level + * 0b00001000..Data 3 line signal level + * 0b00010000..Data 4 line signal level + * 0b00100000..Data 5 line signal level + * 0b01000000..Data 6 line signal level + * 0b10000000..Data 7 line signal level + */ +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ + +/*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ + +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data transfer width + * 0b00..1-bit mode + * 0b01..4-bit mode + * 0b10..8-bit mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) + +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as card detection pin + * 0b0..DATA3 does not monitor card insertion + * 0b1..DATA3 as card detection pin + */ +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) + +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian mode + * 0b00..Big endian mode + * 0b01..Half word big endian mode + * 0b10..Little endian mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) + +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA select + * 0b00..No DMA or simple DMA is selected. + * 0b01..ADMA1 is selected. + * 0b10..ADMA2 is selected. + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) + +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop at block gap request + * 0b0..Transfer + * 0b1..Stop + */ +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) + +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue request + * 0b0..No effect + * 0b1..Restart + */ +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) + +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read wait control + * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set + * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set + */ +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) + +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt at block gap + * 0b0..Disables interrupt at block gap + * 0b1..Enables interrupt at block gap + */ +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) + +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +/*! RD_DONE_NO_8CLK - Read performed number 8 clock */ +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) + +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup event enable on card interrupt + * 0b0..Disables wakeup event enable on card interrupt + * 0b1..Enables wakeup event enable on card interrupt + */ +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) + +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup event enable on SD card insertion + * 0b0..Disable wakeup event enable on SD card insertion + * 0b1..Enable wakeup event enable on SD card insertion + */ +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) + +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup event enable on SD card removal + * 0b0..Disables wakeup event enable on SD card removal + * 0b1..Enables wakeup event enable on SD card removal + */ +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) + +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD - Non-exact block read + * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + */ +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ + +/*! @name SYS_CTRL - System Control */ +/*! @{ */ + +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) + +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +/*! SDCLKFS - SDCLK frequency select */ +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) + +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data timeout counter value + * 0b0000..SDCLK x 2 32 + * 0b0001..SDCLK x 2 33 + * 0b0010..SDCLK x 2 18 + * 0b0011..SDCLK x 2 19 + * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except HS200, HS400, SDR104 mode + * 0b1110..SDCLK x 2 30, recommend to use for HS200 and SDR104 mode + * 0b1111..SDCLK x 2 31, recommend to use for HS400 mode + */ +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) + +#define USDHC_SYS_CTRL_RST_FIFO_MASK (0x400000U) +#define USDHC_SYS_CTRL_RST_FIFO_SHIFT (22U) +/*! RST_FIFO - Reset the async FIFO */ +#define USDHC_SYS_CTRL_RST_FIFO(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK) + +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +/*! IPP_RST_N - Hardware reset */ +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) + +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software reset for all + * 0b0..No reset + * 0b1..Reset + */ +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) + +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software reset for CMD line + * 0b0..No reset + * 0b1..Reset + */ +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) + +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software reset for data line + * 0b0..No reset + * 0b1..Reset + */ +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) + +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +/*! INITA - Initialization active */ +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) + +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +/*! RSTT - Reset tuning */ +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ + +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command complete + * 0b0..Command not complete + * 0b1..Command complete + */ +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) + +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer complete + * 0b0..Transfer does not complete + * 0b1..Transfer complete + */ +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) + +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block gap event + * 0b0..No block gap event + * 0b1..Transaction stopped at block gap + */ +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) + +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA interrupt + * 0b0..No DMA interrupt + * 0b1..DMA interrupt is generated. + */ +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) + +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer write ready + * 0b0..Not ready to write buffer + * 0b1..Ready to write buffer + */ +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) + +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer read ready + * 0b0..Not ready to read buffer + * 0b1..Ready to read buffer + */ +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) + +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card insertion + * 0b0..Card state unstable or removed + * 0b1..Card inserted + */ +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) + +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card removal + * 0b0..Card state unstable or inserted + * 0b1..Card removed + */ +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) + +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card interrupt + * 0b0..No card interrupt + * 0b1..Generate card interrupt + */ +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) + +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode) + * 0b0..Re-tuning is not required. + * 0b1..Re-tuning should be performed. + */ +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) + +#define USDHC_INT_STATUS_TP_MASK (0x2000U) +#define USDHC_INT_STATUS_TP_SHIFT (13U) +/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode) */ +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) + +#define USDHC_INT_STATUS_CQI_MASK (0x4000U) +#define USDHC_INT_STATUS_CQI_SHIFT (14U) +/*! CQI - Command queuing interrupt */ +#define USDHC_INT_STATUS_CQI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK) + +#define USDHC_INT_STATUS_ERR_INT_STATUS_MASK (0x8000U) +#define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT (15U) +/*! ERR_INT_STATUS - Error Interrupt Status */ +#define USDHC_INT_STATUS_ERR_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK) + +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command timeout error + * 0b0..No error + * 0b1..Time out + */ +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) + +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC error + * 0b0..No error + * 0b1..CRC error generated + */ +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) + +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command end bit error + * 0b0..No error + * 0b1..End bit error generated + */ +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) + +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command index error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) + +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data timeout error + * 0b0..No error + * 0b1..Time out + */ +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) + +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) + +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data end bit error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) + +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) + +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode) */ +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) + +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ + +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command complete status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) + +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer complete status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) + +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block gap event status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) + +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA interrupt status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) + +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer write ready status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) + +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer read ready status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) + +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card insertion status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) + +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card removal status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) + +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card interrupt status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) + +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-tuning event status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) + +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U) +/*! TPSEN - Tuning pass status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) + +#define USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U) +/*! CQISEN - Command queuing status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK) + +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command timeout error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) + +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) + +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command end bit error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) + +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command index error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) + +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data timeout error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) + +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) + +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data end bit error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) + +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) + +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) + +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ + +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command complete interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer complete interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block gap event interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer write ready interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer read ready interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card insertion interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card removal interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-tuning event interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U) +/*! TPIEN - Tuning pass interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U) +/*! CQIIEN - Command queuing signal enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command timeout error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command end bit error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command index error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data timeout error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data end bit error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA error interrupt enable + * 0b0..Masked + * 0b1..Enable + */ +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 not executed + * 0b0..Executed + * 0b1..Not executed + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 timeout error + * 0b0..No error + * 0b1..Time out + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (2U) +/*! AC12CE - Auto CMD12 / 23 CRC error + * 0b0..No CRC error + * 0b1..CRC error met in Auto CMD12/23 response + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U) +/*! AC12EBE - Auto CMD12 / 23 end bit error + * 0b0..No error + * 0b1..End bit error generated + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 index error + * 0b0..No error + * 0b1..Error, the CMD index in response is not CMD12/23 + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command not issued by Auto CMD12 error + * 0b0..No error + * 0b1..Not issued + */ +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +/*! EXECUTE_TUNING - Execute tuning + * 0b0..Tuning procedure is aborted + * 0b1..Start tuning procedure + */ +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample clock select + * 0b0..Fixed clock is used to sample data + * 0b1..Tuned clock is used to sample data + */ +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ + +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +/*! SDR50_SUPPORT - SDR50 support */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +/*! SDR104_SUPPORT - SDR104 support */ +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +/*! DDR50_SUPPORT - DDR50 support */ +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b0..SDR50 does not support tuning + * 0b1..SDR50 supports tuning + */ +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) + +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max block length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) + +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA support + * 0b0..Advanced DMA not supported + * 0b1..Advanced DMA supported + */ +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) + +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High speed support + * 0b0..High speed not supported + * 0b1..High speed supported + */ +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) + +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA support + * 0b0..DMA not supported + * 0b1..DMA supported + */ +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) + +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / resume support + * 0b0..Not supported + * 0b1..Supported + */ +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) + +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage support 3.3 V + * 0b0..3.3 V not supported + * 0b1..3.3 V supported + */ +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) + +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage support 3.0 V + * 0b0..3.0 V not supported + * 0b1..3.0 V supported + */ +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) + +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage support 1.8 V + * 0b0..1.8 V not supported + * 0b1..1.8 V supported + */ +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ + +/*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ + +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +/*! RD_WML - Read watermark level */ +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) + +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +/*! WR_WML - Write watermark level */ +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +/*! @} */ + +/*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ + +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA enable + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) + +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block count enable + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) + +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 enable + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) + +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +/*! DDR_EN - Dual data rate mode selection */ +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) + +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data transfer direction select + * 0b0..Write (Host to card) + * 0b1..Read (Card to host) + */ +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) + +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single block select + * 0b0..Single block + * 0b1..Multiple blocks + */ +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) + +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +/*! NIBBLE_POS - Nibble position indication */ +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) + +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +/*! AC23EN - Auto CMD23 enable */ +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) + +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) + * 0b0..Not tuned or tuning completed + * 0b1..Execute tuning + */ +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) + +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Clock selection + * 0b0..Fixed clock is used to sample data / cmd + * 0b1..Tuned clock is used to sample data / cmd + */ +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) + +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) + * 0b0..Disable auto tuning + * 0b1..Enable auto tuning + */ +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) + +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) + * 0b0..Feedback clock comes from the loopback CLK + * 0b1..Feedback clock comes from the ipp_card_clk_out + */ +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + +#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) +#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) +/*! HS400_MODE - Enable HS400 mode */ +#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) + +#define USDHC_MIX_CTRL_EN_HS400_MODE_MASK (0x8000000U) +#define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT (27U) +/*! EN_HS400_MODE - Enable enhance HS400 mode */ +#define USDHC_MIX_CTRL_EN_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK) +/*! @} */ + +/*! @name FORCE_EVENT - Force Event */ +/*! @{ */ + +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +/*! FEVTAC12NE - Force event auto command 12 not executed */ +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +/*! FEVTAC12TOE - Force event auto command 12 time out error */ +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +/*! FEVTAC12CE - Force event auto command 12 CRC error */ +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +/*! FEVTAC12EBE - Force event Auto Command 12 end bit error */ +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +/*! FEVTAC12IE - Force event Auto Command 12 index error */ +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */ +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) + +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +/*! FEVTCTOE - Force event command time out error */ +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +/*! FEVTCCE - Force event command CRC error */ +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +/*! FEVTCEBE - Force event command end bit error */ +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +/*! FEVTCIE - Force event command index error */ +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +/*! FEVTDTOE - Force event data time out error */ +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +/*! FEVTDCE - Force event data CRC error */ +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +/*! FEVTDEBE - Force event data end bit error */ +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +/*! FEVTAC12E - Force event Auto Command 12 error */ +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) + +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +/*! FEVTTNE - Force tuning error */ +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +/*! FEVTDMAE - Force event DMA error */ +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +/*! FEVTCINT - Force event card interrupt */ +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ + +/*! @name ADMA_ERR_STATUS - ADMA Error Status */ +/*! @{ */ + +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +/*! ADMAES - ADMA error state (when ADMA error is occurred) */ +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) + +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA length mismatch error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) + +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA descriptor error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ + +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +/*! ADS_ADDR - ADMA system address */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ + +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +/*! DLL_CTRL_ENABLE - DLL and delay chain */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +/*! DLL_CTRL_RESET - DLL reset */ +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +/*! DLL_CTRL_GATE_UPDATE - DLL gate update */ +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */ +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name DLL_STATUS - DLL Status */ +/*! @{ */ + +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +/*! DLL_STS_SLV_LOCK - Slave delay-line lock status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +/*! DLL_STS_REF_LOCK - Reference DLL lock status */ +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +/*! DLL_STS_SLV_SEL - Slave delay line select status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +/*! DLL_STS_REF_SEL - Reference delay line select taps */ +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +/*! NXT_ERR - NXT error */ +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +/*! TAP_SEL_PRE - TAP_SEL_PRE */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +/*! PRE_ERR - PRE error */ +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ + +/*! @name STROBE_DLL_CTRL - Strobe DLL control */ +/*! @{ */ + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) +/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) +/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +/*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name STROBE_DLL_STATUS - Strobe DLL status */ +/*! @{ */ + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) +/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) +/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) +/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) +/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ + +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage selection + * 0b0..Change the voltage to high voltage range, around 3.0 V + * 0b1..Change the voltage to low voltage range , around 1.8 V + */ +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) + +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN - Check busy enable + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) + +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON - Force CLK + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active + */ +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) + +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet + */ +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) + +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP + * 0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only. + * 0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write. + */ +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ + +/*! @name MMC_BOOT - eMMC Boot */ +/*! @{ */ + +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK - DTOCV_ACK + * 0b0000..SDCLK x 2^32 + * 0b0001..SDCLK x 2^33 + * 0b0010..SDCLK x 2^18 + * 0b0011..SDCLK x 2^19 + * 0b0100..SDCLK x 2^20 + * 0b0101..SDCLK x 2^21 + * 0b0110..SDCLK x 2^22 + * 0b0111..SDCLK x 2^23 + * 0b1110..SDCLK x 2^30 + * 0b1111..SDCLK x 2^31 + */ +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) + +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK - BOOT ACK + * 0b0..No ack + * 0b1..Ack + */ +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) + +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE - Boot mode + * 0b0..Normal boot + * 0b1..Alternative boot + */ +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) + +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN - Boot enable + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) + +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +/*! AUTO_SABG_EN - Auto stop at block gap */ +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) + +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Time out + * 0b0..Enable time out + * 0b1..Disable time out + */ +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) + +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */ +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ + +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card interrupt detection test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) + +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK (0x30U) +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT (4U) +/*! TUNING_BIT_EN - Tuning bit enable + * 0b00..Enable Tuning circuit for DATA[3:0] + * 0b01..Enable Tuning circuit for DATA[7:0] + * 0b10..Enable Tuning circuit for DATA[0] + * 0b11..Invalid + */ +#define USDHC_VEND_SPEC2_TUNING_BIT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) + +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN - Tuning command enable + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) + +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) +/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */ +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) + +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) +/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */ +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) + +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 + * 0b0..Disable + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. + */ +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) +#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) +/*! EN_32K_CLK - Select the clock source for host card detection. + * 0b0..Use the peripheral clock (ipg_clk) for card detection. + * 0b1..Use the low power clock (ipg_clk_lp) for card detection. + */ +#define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) + +#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK (0xFFFF0000U) +#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT (16U) +/*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */ +#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK) +/*! @} */ + +/*! @name TUNING_CTRL - Tuning Control */ +/*! @{ */ + +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +/*! TUNING_START_TAP - Tuning start */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) + +#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U) +#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U) +/*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */ +#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK) + +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +/*! TUNING_COUNTER - Tuning counter */ +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) + +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +/*! TUNING_STEP - TUNING_STEP */ +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) + +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +/*! TUNING_WINDOW - Data window */ +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) + +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +/*! STD_TUNING_EN - Standard tuning circuit and procedure enable */ +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ + +/*! @name CQVER - Command Queuing Version */ +/*! @{ */ + +#define USDHC_CQVER_VERSION_SUFFIX_MASK (0xFU) +#define USDHC_CQVER_VERSION_SUFFIX_SHIFT (0U) +/*! VERSION_SUFFIX - eMMC version suffix */ +#define USDHC_CQVER_VERSION_SUFFIX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK) + +#define USDHC_CQVER_MINOR_VN_MASK (0xF0U) +#define USDHC_CQVER_MINOR_VN_SHIFT (4U) +/*! MINOR_VN - eMMC minor version number */ +#define USDHC_CQVER_MINOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK) + +#define USDHC_CQVER_MAJOR_VN_MASK (0xF00U) +#define USDHC_CQVER_MAJOR_VN_SHIFT (8U) +/*! MAJOR_VN - eMMC major version number */ +#define USDHC_CQVER_MAJOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK) +/*! @} */ + +/*! @name CQCAP - Command Queuing Capabilities */ +/*! @{ */ + +#define USDHC_CQCAP_ITCFVAL_MASK (0x3FFU) +#define USDHC_CQCAP_ITCFVAL_SHIFT (0U) +/*! ITCFVAL - Internal timer clock frequency value */ +#define USDHC_CQCAP_ITCFVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK) + +#define USDHC_CQCAP_ITCFMUL_MASK (0xF000U) +#define USDHC_CQCAP_ITCFMUL_SHIFT (12U) +/*! ITCFMUL - Internal timer clock frequency multiplier + * 0b0001..0.001 MHz + * 0b0010..0.01 MHz + * 0b0011..0.1 MHz + * 0b0100..1 MHz + * 0b0101..10 MHz + * 0b0110-0b1001..Reserved + */ +#define USDHC_CQCAP_ITCFMUL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK) +/*! @} */ + +/*! @name CQCFG - Command Queuing Configuration */ +/*! @{ */ + +#define USDHC_CQCFG_CQUE_MASK (0x1U) +#define USDHC_CQCFG_CQUE_SHIFT (0U) +/*! CQUE - Command queuing enable */ +#define USDHC_CQCFG_CQUE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK) + +#define USDHC_CQCFG_TDS_MASK (0x100U) +#define USDHC_CQCFG_TDS_SHIFT (8U) +/*! TDS - Task descriptor size + * 0b0..Task descriptor size is 64 bits + * 0b1..Task descriptor size is 128 bits + */ +#define USDHC_CQCFG_TDS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK) + +#define USDHC_CQCFG_DCMDE_MASK (0x1000U) +#define USDHC_CQCFG_DCMDE_SHIFT (12U) +/*! DCMDE - Direct command (DCMD) enable + * 0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor + * 0b1..Task descriptor in slot #31 is a DCMD Task Descriptor + */ +#define USDHC_CQCFG_DCMDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK) +/*! @} */ + +/*! @name CQCTL - Command Queuing Control */ +/*! @{ */ + +#define USDHC_CQCTL_HALT_MASK (0x1U) +#define USDHC_CQCTL_HALT_SHIFT (0U) +/*! HALT - Halt */ +#define USDHC_CQCTL_HALT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK) + +#define USDHC_CQCTL_CLEAR_MASK (0x100U) +#define USDHC_CQCTL_CLEAR_SHIFT (8U) +/*! CLEAR - Clear all tasks */ +#define USDHC_CQCTL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK) +/*! @} */ + +/*! @name CQIS - Command Queuing Interrupt Status */ +/*! @{ */ + +#define USDHC_CQIS_HAC_MASK (0x1U) +#define USDHC_CQIS_HAC_SHIFT (0U) +/*! HAC - Halt complete interrupt */ +#define USDHC_CQIS_HAC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK) + +#define USDHC_CQIS_TCC_MASK (0x2U) +#define USDHC_CQIS_TCC_SHIFT (1U) +/*! TCC - Task complete interrupt */ +#define USDHC_CQIS_TCC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK) + +#define USDHC_CQIS_RED_MASK (0x4U) +#define USDHC_CQIS_RED_SHIFT (2U) +/*! RED - Response error detected interrupt */ +#define USDHC_CQIS_RED(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK) + +#define USDHC_CQIS_TCL_MASK (0x8U) +#define USDHC_CQIS_TCL_SHIFT (3U) +/*! TCL - Task cleared */ +#define USDHC_CQIS_TCL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK) +/*! @} */ + +/*! @name CQISTE - Command Queuing Interrupt Status Enable */ +/*! @{ */ + +#define USDHC_CQISTE_HAC_STE_MASK (0x1U) +#define USDHC_CQISTE_HAC_STE_SHIFT (0U) +/*! HAC_STE - Halt complete status enable + * 0b0..CQIS[HAC] is disabled + * 0b1..CQIS[HAC] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_HAC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK) + +#define USDHC_CQISTE_TCC_STE_MASK (0x2U) +#define USDHC_CQISTE_TCC_STE_SHIFT (1U) +/*! TCC_STE - Task complete status enable + * 0b0..CQIS[TCC] is disabled + * 0b1..CQIS[TCC] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_TCC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK) + +#define USDHC_CQISTE_RED_STE_MASK (0x4U) +#define USDHC_CQISTE_RED_STE_SHIFT (2U) +/*! RED_STE - Response error detected status enable + * 0b0..CQIS[RED]is disabled + * 0b1..CQIS[RED] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_RED_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK) + +#define USDHC_CQISTE_TCL_STE_MASK (0x8U) +#define USDHC_CQISTE_TCL_STE_SHIFT (3U) +/*! TCL_STE - Task cleared status enable + * 0b0..CQIS[TCL] is disabled + * 0b1..CQIS[TCL] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_TCL_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK) +/*! @} */ + +/*! @name CQISGE - Command Queuing Interrupt Signal Enable */ +/*! @{ */ + +#define USDHC_CQISGE_HAC_SGE_MASK (0x1U) +#define USDHC_CQISGE_HAC_SGE_SHIFT (0U) +/*! HAC_SGE - Halt complete signal enable */ +#define USDHC_CQISGE_HAC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK) + +#define USDHC_CQISGE_TCC_SGE_MASK (0x2U) +#define USDHC_CQISGE_TCC_SGE_SHIFT (1U) +/*! TCC_SGE - Task complete signal enable */ +#define USDHC_CQISGE_TCC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK) + +#define USDHC_CQISGE_RED_SGE_MASK (0x4U) +#define USDHC_CQISGE_RED_SGE_SHIFT (2U) +/*! RED_SGE - Response error detected signal enable */ +#define USDHC_CQISGE_RED_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK) + +#define USDHC_CQISGE_TCL_SGE_MASK (0x8U) +#define USDHC_CQISGE_TCL_SGE_SHIFT (3U) +/*! TCL_SGE - Task cleared signal enable */ +#define USDHC_CQISGE_TCL_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK) +/*! @} */ + +/*! @name CQIC - Command Queuing Interrupt Coalescing */ +/*! @{ */ + +#define USDHC_CQIC_ICTOVAL_MASK (0x7FU) +#define USDHC_CQIC_ICTOVAL_SHIFT (0U) +/*! ICTOVAL - Interrupt coalescing timeout value */ +#define USDHC_CQIC_ICTOVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK) + +#define USDHC_CQIC_ICTOVALWEN_MASK (0x80U) +#define USDHC_CQIC_ICTOVALWEN_SHIFT (7U) +/*! ICTOVALWEN - Interrupt coalescing timeout value write enable */ +#define USDHC_CQIC_ICTOVALWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK) + +#define USDHC_CQIC_ICCTH_MASK (0x1F00U) +#define USDHC_CQIC_ICCTH_SHIFT (8U) +/*! ICCTH - Interrupt coalescing counter threshold */ +#define USDHC_CQIC_ICCTH(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK) + +#define USDHC_CQIC_ICCTHWEN_MASK (0x8000U) +#define USDHC_CQIC_ICCTHWEN_SHIFT (15U) +/*! ICCTHWEN - Interrupt coalescing counter threshold write enable */ +#define USDHC_CQIC_ICCTHWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK) + +#define USDHC_CQIC_ICCTR_MASK (0x10000U) +#define USDHC_CQIC_ICCTR_SHIFT (16U) +/*! ICCTR - Counter and timer reset */ +#define USDHC_CQIC_ICCTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK) + +#define USDHC_CQIC_ICSB_MASK (0x100000U) +#define USDHC_CQIC_ICSB_SHIFT (20U) +/*! ICSB - Interrupt coalescing status + * 0b0..No task completions have occurred since last counter reset (IC counter =0) + * 0b1..At least one task completion has been counted (IC counter >0) + */ +#define USDHC_CQIC_ICSB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK) + +#define USDHC_CQIC_ICENDIS_MASK (0x80000000U) +#define USDHC_CQIC_ICENDIS_SHIFT (31U) +/*! ICENDIS - Interrupt coalescing enable/disable */ +#define USDHC_CQIC_ICENDIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK) +/*! @} */ + +/*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */ +/*! @{ */ + +#define USDHC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFU) +#define USDHC_CQTDLBA_TDLBA_SHIFT (0U) +/*! TDLBA - Task descriptor list base address */ +#define USDHC_CQTDLBA_TDLBA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK) +/*! @} */ + +/*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */ +/*! @{ */ + +#define USDHC_CQTDLBAU_TDLBAU_MASK (0xFFFFFFFFU) +#define USDHC_CQTDLBAU_TDLBAU_SHIFT (0U) +/*! TDLBAU - Task descriptor list base address */ +#define USDHC_CQTDLBAU_TDLBAU(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK) +/*! @} */ + +/*! @name CQTDBR - Command Queuing Task Doorbell */ +/*! @{ */ + +#define USDHC_CQTDBR_TDBR_MASK (0xFFFFFFFFU) +#define USDHC_CQTDBR_TDBR_SHIFT (0U) +/*! TDBR - Task doorbell */ +#define USDHC_CQTDBR_TDBR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK) +/*! @} */ + +/*! @name CQTCN - Command Queuing Task Completion Notification */ +/*! @{ */ + +#define USDHC_CQTCN_TCN_MASK (0xFFFFFFFFU) +#define USDHC_CQTCN_TCN_SHIFT (0U) +/*! TCN - Task complete notification */ +#define USDHC_CQTCN_TCN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK) +/*! @} */ + +/*! @name CQDQS - Command Queuing Device Queue Status */ +/*! @{ */ + +#define USDHC_CQDQS_DQS_MASK (0xFFFFFFFFU) +#define USDHC_CQDQS_DQS_SHIFT (0U) +/*! DQS - Device queue status */ +#define USDHC_CQDQS_DQS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK) +/*! @} */ + +/*! @name CQDPT - Command Queuing Device Pending Tasks */ +/*! @{ */ + +#define USDHC_CQDPT_DPT_MASK (0xFFFFFFFFU) +#define USDHC_CQDPT_DPT_SHIFT (0U) +/*! DPT - Device pending tasks */ +#define USDHC_CQDPT_DPT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK) +/*! @} */ + +/*! @name CQTCLR - Command Queuing Task Clear */ +/*! @{ */ + +#define USDHC_CQTCLR_TCLR_MASK (0xFFFFFFFFU) +#define USDHC_CQTCLR_TCLR_SHIFT (0U) +/*! TCLR - Task clear */ +#define USDHC_CQTCLR_TCLR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK) +/*! @} */ + +/*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */ +/*! @{ */ + +#define USDHC_CQSSC1_CIT_MASK (0xFFFFU) +#define USDHC_CQSSC1_CIT_SHIFT (0U) +/*! CIT - Send status command idle timer */ +#define USDHC_CQSSC1_CIT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK) + +#define USDHC_CQSSC1_CBC_MASK (0xF0000U) +#define USDHC_CQSSC1_CBC_SHIFT (16U) +/*! CBC - Send status command block counter */ +#define USDHC_CQSSC1_CBC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK) +/*! @} */ + +/*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */ +/*! @{ */ + +#define USDHC_CQSSC2_SSC2_MASK (0xFFFFU) +#define USDHC_CQSSC2_SSC2_SHIFT (0U) +/*! SSC2 - Send queue status RCA */ +#define USDHC_CQSSC2_SSC2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK) +/*! @} */ + +/*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */ +/*! @{ */ + +#define USDHC_CQCRDCT_CRDCT_MASK (0xFFFFFFFFU) +#define USDHC_CQCRDCT_CRDCT_SHIFT (0U) +/*! CRDCT - Direct command last response */ +#define USDHC_CQCRDCT_CRDCT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK) +/*! @} */ + +/*! @name CQRMEM - Command Queuing Response Mode Error Mask */ +/*! @{ */ + +#define USDHC_CQRMEM_RMEM_MASK (0xFFFFFFFFU) +#define USDHC_CQRMEM_RMEM_SHIFT (0U) +/*! RMEM - Response mode error mask + * 0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored + * 0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated + */ +#define USDHC_CQRMEM_RMEM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK) +/*! @} */ + +/*! @name CQTERRI - Command Queuing Task Error Information */ +/*! @{ */ + +#define USDHC_CQTERRI_RMECI_MASK (0x3FU) +#define USDHC_CQTERRI_RMECI_SHIFT (0U) +/*! RMECI - Response mode error command index */ +#define USDHC_CQTERRI_RMECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK) + +#define USDHC_CQTERRI_RMETID_MASK (0x1F00U) +#define USDHC_CQTERRI_RMETID_SHIFT (8U) +/*! RMETID - Response mode error task ID */ +#define USDHC_CQTERRI_RMETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK) + +#define USDHC_CQTERRI_RMEFV_MASK (0x8000U) +#define USDHC_CQTERRI_RMEFV_SHIFT (15U) +/*! RMEFV - Response mode error fields valid */ +#define USDHC_CQTERRI_RMEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK) + +#define USDHC_CQTERRI_DTECI_MASK (0x3F0000U) +#define USDHC_CQTERRI_DTECI_SHIFT (16U) +/*! DTECI - Data transfer error command index */ +#define USDHC_CQTERRI_DTECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK) + +#define USDHC_CQTERRI_DTETID_MASK (0x1F000000U) +#define USDHC_CQTERRI_DTETID_SHIFT (24U) +/*! DTETID - Data transfer error task ID */ +#define USDHC_CQTERRI_DTETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK) + +#define USDHC_CQTERRI_DTEFV_MASK (0x80000000U) +#define USDHC_CQTERRI_DTEFV_SHIFT (31U) +/*! DTEFV - Data transfer error fields valid */ +#define USDHC_CQTERRI_DTEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK) +/*! @} */ + +/*! @name CQCRI - Command Queuing Command Response Index */ +/*! @{ */ + +#define USDHC_CQCRI_LCMDRI_MASK (0x3FU) +#define USDHC_CQCRI_LCMDRI_SHIFT (0U) +/*! LCMDRI - Last command response index */ +#define USDHC_CQCRI_LCMDRI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK) +/*! @} */ + +/*! @name CQCRA - Command Queuing Command Response Argument */ +/*! @{ */ + +#define USDHC_CQCRA_LCMDRA_MASK (0xFFFFFFFFU) +#define USDHC_CQCRA_LCMDRA_SHIFT (0U) +/*! LCMDRA - Last command response argument */ +#define USDHC_CQCRA_LCMDRA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x42850000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x42860000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Peripheral USDHC3 base address */ +#define USDHC3_BASE (0x428B0000u) +/** Peripheral USDHC3 base pointer */ +#define USDHC3 ((USDHC_Type *)USDHC3_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< WDOG Control and Status, offset: 0x0 */ + __IO uint32_t CNT; /**< WDOG Counter, offset: 0x4 */ + __IO uint32_t TOVAL; /**< WDOG Timeout Value, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window, offset: 0xC */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name CS - WDOG Control and Status */ +/*! @{ */ + +#define WDOG_CS_STOP_MASK (0x1U) +#define WDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) + +#define WDOG_CS_WAIT_MASK (0x2U) +#define WDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) + +#define WDOG_CS_DBG_MASK (0x4U) +#define WDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) + +#define WDOG_CS_TST_MASK (0x18U) +#define WDOG_CS_TST_SHIFT (3U) +/*! TST - WDOG Test + * 0b00..Disable WDOG Test mode + * 0b01..Enable WDOG User mode + * 0b10-0b11..Enable WDOG Test mode + */ +#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) + +#define WDOG_CS_UPDATE_MASK (0x20U) +#define WDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Updates Allowed + * 0b0..Updates not allowed + * 0b1..Updates allowed + */ +#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) + +#define WDOG_CS_INT_MASK (0x40U) +#define WDOG_CS_INT_SHIFT (6U) +/*! INT - WDOG Interrupt + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) + +#define WDOG_CS_EN_MASK (0x80U) +#define WDOG_CS_EN_SHIFT (7U) +/*! EN - WDOG Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) + +#define WDOG_CS_CLK_MASK (0x300U) +#define WDOG_CS_CLK_SHIFT (8U) +/*! CLK - WDOG Clock + * 0b00..IPG + * 0b01..LPO + * 0b10..INT + * 0b11..EXT + */ +#define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) + +#define WDOG_CS_RCS_MASK (0x400U) +#define WDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Unsuccessful + * 0b1..Successful + */ +#define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) + +#define WDOG_CS_ULK_MASK (0x800U) +#define WDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock Status + * 0b0..Locked + * 0b1..Unlocked + */ +#define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) + +#define WDOG_CS_PRES_MASK (0x1000U) +#define WDOG_CS_PRES_SHIFT (12U) +/*! PRES - WDOG Prescaler + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) + +#define WDOG_CS_CMD32EN_MASK (0x2000U) +#define WDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Command 32 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) + +#define WDOG_CS_FLG_MASK (0x4000U) +#define WDOG_CS_FLG_SHIFT (14U) +/*! FLG - WDOG Interrupt Flag + * 0b0..No interrupt occurred + * 0b1..An interrupt occurred + */ +#define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) + +#define WDOG_CS_WIN_MASK (0x8000U) +#define WDOG_CS_WIN_SHIFT (15U) +/*! WIN - WDOG Window + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) +/*! @} */ + +/*! @name CNT - WDOG Counter */ +/*! @{ */ + +#define WDOG_CNT_CNTLOW_MASK (0xFFU) +#define WDOG_CNT_CNTLOW_SHIFT (0U) +/*! CNTLOW - Counter Low Byte */ +#define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) + +#define WDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define WDOG_CNT_CNTHIGH_SHIFT (8U) +/*! CNTHIGH - Counter High Byte */ +#define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) +/*! @} */ + +/*! @name TOVAL - WDOG Timeout Value */ +/*! @{ */ + +#define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define WDOG_TOVAL_TOVALLOW_SHIFT (0U) +/*! TOVALLOW - Timeout Value Low */ +#define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) + +#define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) +/*! TOVALHIGH - Timeout Value High */ +#define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ + +/*! @name WIN - Watchdog Window */ +/*! @{ */ + +#define WDOG_WIN_WINLOW_MASK (0xFFU) +#define WDOG_WIN_WINLOW_SHIFT (0U) +/*! WINLOW - Low Byte */ +#define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) + +#define WDOG_WIN_WINHIGH_MASK (0xFF00U) +#define WDOG_WIN_WINHIGH_SHIFT (8U) +/*! WINHIGH - High Byte */ +#define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x442D0000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x442E0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x42490000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +/** Peripheral WDOG4 base address */ +#define WDOG4_BASE (0x424A0000u) +/** Peripheral WDOG4 base pointer */ +#define WDOG4 ((WDOG_Type *)WDOG4_BASE) +/** Peripheral WDOG5 base address */ +#define WDOG5_BASE (0x424B0000u) +/** Peripheral WDOG5 base pointer */ +#define WDOG5 ((WDOG_Type *)WDOG5_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE, WDOG4_BASE, WDOG5_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { WDOG1, WDOG2, WDOG3, WDOG4, WDOG5 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn, WDOG4_IRQn, WDOG5_IRQn } +/* Extra definition */ +#define WDOG_UPDATE_KEY (0xD928C520U) +#define WDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MIMX9131_H_ */ + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131_features.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131_features.h new file mode 100644 index 00000000000..76ab6eb787e --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131_features.h @@ -0,0 +1,671 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MIMX9131_FEATURES_H_ +#define _MIMX9131_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (1) +/* @brief BBNSM availability on the SoC. */ +#define FSL_FEATURE_SOC_BBNSM_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (4) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (1) +/* @brief ENET_QOS availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_QOS_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (2) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief ISI availability on the SoC. */ +#define FSL_FEATURE_SOC_ISI_COUNT (1) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (8) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (2) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (8) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (4) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief RGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_RGPIO_COUNT (4) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (2) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (6) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (3) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (5) + +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + +/* FLEXCAN module features */ + +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1) +/* @brief Init memory base 1 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80) +/* @brief Init memory size 1 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60) +/* @brief Init memory base 2 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xC20) +/* @brief Init memory size 2 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0x25E0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (64) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) \ + (((x) == DMA4) ? (64) : \ + (((x) == DMA3) ? (31) : (-1))) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Has register bit fields CR[CLM]. */ +#define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief eDMA3 has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (0) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (1) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (1) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (1) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) \ + (((x) == EDMA4_2__TCD) ? (0) : \ + (((x) == EDMA3_1__TCD) ? (1) : (-1))) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (1) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (3) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (1) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) +/* @brief Support Interrupt Coalesce for each instance */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) +/* @brief Queue Size for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3) +/* @brief Has AVB Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1) +/* @brief Has Timer Pulse Width control for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) +/* @brief Has Extend MDIO Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) +/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) +/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ +#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) +/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) +/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) +/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ +#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) +/* @brief ENET Has Extra Clock Gate.(RW610). */ +#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) + +/* ENET_QOS module features */ + +/* @brief ENET QOS Queue Tx checksum offload support bit map. */ +#define FSL_FEATURE_ENET_QOS_TX_OFFLOAD_QUEUE_SUPPORT_BITMAP (0x1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) + +/* RGPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief There is ICR registers */ +#define FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG (1) +/* @brief There is PIDR register */ +#define FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief SOC doesn't support slave IBI/MR/HJ. */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* IOMUXC1 module features */ + +/* @brief Has SDK API function for IOMUXC1 setting. */ +#define FSL_FEATURE_IOMUXC1_HAS_SDK_SUPPORT (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) + +/* LPIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_LPIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (8) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (8) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1) +/* @brief CLKDIV factor in Medium, High and Low Quality modes */ +#define FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR (93) +/* @brief CLKDIV factor in Very Low Quality modes */ +#define FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR (43) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (0) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) + +/* SAI module features */ + +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ + (((x) == SAI1) ? (64) : \ + (((x) == SAI2) ? (128) : \ + (((x) == SAI3) ? (128) : (-1)))) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ + (((x) == SAI1) ? (2) : \ + (((x) == SAI2) ? (1) : \ + (((x) == SAI3) ? (1) : (-1)))) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (64) + +/* TPM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (4) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (1) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (1) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (1) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (1) +/* @brief Whether TRIG register has effect. */ +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0) +/* @brief Has global time base enable. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) +/* @brief Has global time base sync. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC (1) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Whether POL register has effect. */ +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (0) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) +/* @brief Has pause level select. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (1) +/* @brief Whether 32 bits counter has effect. */ +#define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC domain number (reset value of HWCFG0[NDID]). */ +#define FSL_FEATURE_TRDC_DOMAIN_COUNT (16) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (1) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (1) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (1) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (1) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (1) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief WDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) + +/* CACHE module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (64) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (64) +/* @brief Has NONCACHEABLE section. */ +#define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0) + +/* MEMORY module features */ + +/* @brief Memory map doesn't have offset between subsystems. */ +#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (0) + +#endif /* _MIMX9131_FEATURES_H_ */ + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/SConscript new file mode 100644 index 00000000000..43869fedcc6 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('drivers/*.c') + +CPPPATH = [cwd, cwd + '/drivers'] +CPPDEFINES = [ + {'CPU_MIMX9131DVVXJ': 1} +] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/all_lib_device_MIMX9131.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/all_lib_device_MIMX9131.cmake new file mode 100644 index 00000000000..3dd91b836a6 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/all_lib_device_MIMX9131.cmake @@ -0,0 +1,64 @@ +list(APPEND CMAKE_MODULE_PATH + ${CMAKE_CURRENT_LIST_DIR}/. + ${CMAKE_CURRENT_LIST_DIR}/../../CMSIS/Core_AArch64/Include + ${CMAKE_CURRENT_LIST_DIR}/../../components/i2c + ${CMAKE_CURRENT_LIST_DIR}/../../components/lists + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/device/phyrtl8211f + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/mdio + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/mdio/enet + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/mdio/enet_qos + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager + ${CMAKE_CURRENT_LIST_DIR}/../../components/uart + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/cache/armv8-a + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/common + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/enet + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/enet_qos + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexcan + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lptmr + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/tpm + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpi2c + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpuart + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mu1 + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/rgpio + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/sai + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/assert + ${CMAKE_CURRENT_LIST_DIR}/../../utilities + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/misc_utilities + ${CMAKE_CURRENT_LIST_DIR}/drivers +) + + +# Copy the cmake components into projects +# include(driver_lpi2c) +# include(driver_lpi2c_edma) +# include(driver_lpi2c_freertos) +# include(driver_lpuart_dma) +# include(driver_lpuart_edma) +# include(driver_lpuart_freertos) +# include(component_lpi2c_adapter) +# include(component_lpuart_adapter) +# include(component_lists) +# include(component_serial_manager) +# include(component_serial_manager_uart) +# include(device_startup) +# include(device_system) +# include(driver_cache_armv8a) +# include(driver_common) +# include(driver_enet) +# include(driver_flexcan) +# include(driver_lptmr) +# include(driver_tpm) +# include(driver_rgpio) +# include(driver_lpuart) +# include(driver_mdio-enet) +# include(driver_mu1) +# include(driver_phy-device-rtl8211f) +# include(driver_sai) +# include(middleware_freertos-kernel_aarch64) +# include(middleware_freertos-kernel_extension) +# include(middleware_freertos-kernel_heap_4) +# include(utilities_misc_utilities) +# include(utility_assert) +# include(utility_debug_console) +# include(utility_debug_console_lite) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_CMSIS.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_CMSIS.cmake new file mode 100644 index 00000000000..5c14b183da7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_CMSIS.cmake @@ -0,0 +1,15 @@ +#Description: device_CMSIS; user_visible: False +include_guard(GLOBAL) +message("device_CMSIS component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +if(${MCUX_DEVICE} STREQUAL "MIMX9131") + include(CMSIS_Include_core_ca OPTIONAL) +endif() diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_system.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_system.cmake new file mode 100644 index 00000000000..e59c2802ab1 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_system.cmake @@ -0,0 +1,14 @@ +#Description: device_system; user_visible: False +include_guard(GLOBAL) +message("device_system component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/system_MIMX9131.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +#include(device_CMSIS) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_clock.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_clock.cmake new file mode 100644 index 00000000000..e91de205335 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_clock.cmake @@ -0,0 +1,15 @@ +include_guard() +message("driver_clock component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common) + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_iomuxc.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_iomuxc.cmake new file mode 100644 index 00000000000..71c55a6a05c --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_iomuxc.cmake @@ -0,0 +1,10 @@ +include_guard() +message("driver_iomuxc component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(driver_common) + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_memory.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_memory.cmake new file mode 100644 index 00000000000..f8778e3fa0e --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_memory.cmake @@ -0,0 +1,10 @@ +include_guard() +message("driver_memory component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(driver_common) + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_reset.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_reset.cmake new file mode 100644 index 00000000000..9b3c82d5719 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_reset.cmake @@ -0,0 +1,10 @@ +#Description: Reset Driver; user_visible: False +include_guard(GLOBAL) +message("driver_reset component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.c b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.c new file mode 100644 index 00000000000..ccc9609fb36 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.c @@ -0,0 +1,149 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/* ROM initializes PLLs with default frequencies except audio/video/ext */ +volatile uint32_t g_clockSourceFreq[kCLOCK_Ext + 1] = { + 24000000U, /* kCLOCK_Osc24M */ + 2000000000U, /* kCLOCK_ArmPll */ + 2000000000U, /* kCLOCK_ArmPllOut */ + 1000000000U, /* kCLOCK_DramPll */ + 1000000000U, /* kCLOCK_DramPllOut */ + 4000000000U, /* kCLOCK_SysPll1 */ + 1000000000U, /* kCLOCK_SysPll1Pfd0 */ + 500000000U, /* kCLOCK_SysPll1Pfd0Div2 */ + 800000000U, /* kCLOCK_SysPll1Pfd1 */ + 400000000U, /* kCLOCK_SysPll1Pfd1Div2 */ + 625000000U, /* kCLOCK_SysPll1Pfd2 */ + 312500000U, /* kCLOCK_SysPll1Pfd2Div2 */ + 0U, /* kCLOCK_AudioPll1 */ + 0U, /* kCLOCK_AudioPll1Out */ + 0U, /* kCLOCK_VideoPll1 */ + 0U, /* kCLOCK_VideoPll1Out */ + 0U /* kCLOCK_Ext */ +}; + +const clock_name_t s_clockSourceName[][4] = { + /*SRC0, SRC1, SRC2, SRC3, */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Arm A55 Periph */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Arm A55 MTR BUS */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Arm A55 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* M33 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Sentinel */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Bus Wakeup */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Bus Aon */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Wakeup Axi */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Swo Trace */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* M33 Systick */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Flexio1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Flexio2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpit1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpit2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lptmr1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lptmr2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Flexspi1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Can1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Can2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart7 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart8 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c7 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c8 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi7 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi8 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Usdhc1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Usdhc2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Usdhc3 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Sai1 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Sai2 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Sai3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_AudioPll1Out}, /* Ccm Cko1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_VideoPll1Out}, /* Ccm Cko2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_AudioPll1Out}, /* Ccm Cko3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_VideoPll1Out}, /* Ccm Cko4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Hsio */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Hsio Usb Test 60M */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Hsio Acscan 80M */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd2}, /* Hsio Acscan 480M */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Nic */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Nic Apb */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Ml Apb */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Ml */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Media Axi */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Media Apb */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Media Ldb */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Media Disp Pix */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Cam Pix */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Mipi Test Byte */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Mipi Phy Cfg */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Dram Alt */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Dram Apb */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Adc */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Pdm */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Tstmr1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Tstmr2 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Mqs1 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Mqs2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Audio XCVR */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Spdif */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Enet */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Enet Timer1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Enet Timer2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Enet Ref */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Enet Ref Phy */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c1 Slow */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c2 Slow */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Usb Phy Burunin */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd2} /* Pal Came Scan */ +}; + +uint32_t CLOCK_GetIpFreq(clock_root_t name) +{ + clock_name_t clock; + uint32_t mux; + uint32_t div; + + mux = CLOCK_GetRootClockMux(name); + div = CLOCK_GetRootClockDiv(name); + + clock = CLOCK_GetRootClockSource(name, mux); + assert(clock <= kCLOCK_Ext); + + return g_clockSourceFreq[clock] / div; +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.h new file mode 100644 index 00000000000..52d6e812008 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.h @@ -0,0 +1,1279 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @brief CLOCK driver version. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 1)) + +/*! + * @brief CCM reg macros to map corresponding registers. + */ +#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) +#define CCM_REG(root) CCM_REG_OFF(root, 0U) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY \ + (250000000UL) /* When using Overdrive Voltage, the maximum frequency of cm33 is 250 MHz */ +#endif + +/*! LPM_SETTING + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM_SETTING_0 (0U) +#define CCM_LPCG_LPM_SETTING_1 (1U) +#define CCM_LPCG_LPM_SETTING_2 (2U) +#define CCM_LPCG_LPM_SETTING_3 (3U) +#define CCM_LPCG_LPM_SETTING_4 (4U) + +/******************************************************************************* + * PLL Definitions + ******************************************************************************/ + +/*! @brief PLL initialzation data. */ +typedef struct _fracn_pll_init +{ + uint32_t rdiv; + uint32_t mfi; + uint32_t mfn; + uint32_t mfd; + uint32_t odiv; +} fracn_pll_init_t; + +/*! @brief PLL PFD initialzation data. */ +typedef struct _fracn_pll_pfd_init +{ + uint32_t mfi; + uint32_t mfn; + bool div2_en; +} fracn_pll_pfd_init_t; + +/*! + * @brief PLL init. + * + * @param pll PLL base addr. + * @param pll_cfg PLL initailization data. + */ +static inline void CLOCK_PllInit(PLL_Type *pll, const fracn_pll_init_t *pll_cfg) +{ + /* Bypass PLL */ + pll->CTRL.SET = PLL_CTRL_CLKMUX_BYPASS_MASK; + /* Disable output and PLL */ + pll->CTRL.CLR = PLL_CTRL_CLKMUX_EN_MASK | PLL_CTRL_POWERUP_MASK; + /* Set rdiv, mfi, and odiv */ + pll->DIV.RW = PLL_DIV_RDIV(pll_cfg->rdiv) | PLL_DIV_MFI(pll_cfg->mfi) | PLL_DIV_ODIV(pll_cfg->odiv); + /* Disable spread spectrum modulation */ + pll->SPREAD_SPECTRUM.CLR = PLL_SPREAD_SPECTRUM_ENABLE_MASK; + /* Set mfn and mfd */ + pll->NUMERATOR.RW = PLL_NUMERATOR_MFN(pll_cfg->mfn); + pll->DENOMINATOR.RW = PLL_DENOMINATOR_MFD(pll_cfg->mfd); + + /* Power up for locking */ + pll->CTRL.SET = PLL_CTRL_POWERUP_MASK; + while ((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) == 0UL) + { + } + + /* Enable PLL and clean bypass*/ + pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK; + pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK; + __DSB(); + __ISB(); +} + +/*! + * @brief PLL PFD init. + * + * @param pll PLL base addr. + * @param pfd_n The PFD index number. + * @param pfd_cfg PLL PFD initailization data. + */ +static inline void CLOCK_PllPfdInit(PLL_Type *pll, uint32_t pfd_n, const fracn_pll_pfd_init_t *pfd_cfg) +{ + /* Bypass DFS*/ + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_BYPASS_EN_MASK; + /* Disable output and DFS */ + pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_CLKOUT_EN_MASK | PLL_DFS_ENABLE_MASK; + /* Set mfi and mfn */ + pll->DFS[pfd_n].DFS_DIV.RW = PLL_DFS_MFI(pfd_cfg->mfi) | PLL_DFS_MFN(pfd_cfg->mfn); + /* Enable output and DFS*/ + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_EN_MASK; + /* Enable div2 */ + if (pfd_cfg->div2_en) + { + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_DIVBY2_EN_MASK; + } + /* Enable DFS for locking*/ + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_ENABLE_MASK; + while (((pll->DFS_STATUS & PLL_DFS_STATUS_DFS_OK_MASK) & (1UL << pfd_n)) == 0UL) + { + } + /* Clean bypass */ + pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_BYPASS_EN_MASK; + __DSB(); + __ISB(); +} + +/******************************************************************************* + * Clock Source Definitions + ******************************************************************************/ + +/*! + * @brief Clock name. + */ +typedef enum _clock_name +{ + kCLOCK_Osc24M = 0, /*!< 24MHz Oscillator. */ + kCLOCK_ArmPll = 1, /* ARM PLL */ + kCLOCK_ArmPllOut = 2, /* ARM PLL Out */ + kCLOCK_DramPll = 3, /* DRAM PLL */ + kCLOCK_DramPllOut = 4, /* DRAM PLL Out */ + kCLOCK_SysPll1 = 5, /* SYSTEM PLL1 */ + kCLOCK_SysPll1Pfd0 = 6, /* SYSTEM PLL1 PFD0 */ + kCLOCK_SysPll1Pfd0Div2 = 7, /* SYSTEM PLL1 PFD0 DIV2 */ + kCLOCK_SysPll1Pfd1 = 8, /* SYSTEM PLL1 PFD1 */ + kCLOCK_SysPll1Pfd1Div2 = 9, /* SYSTEM PLL1 PFD1 DIV2 */ + kCLOCK_SysPll1Pfd2 = 10, /* SYSTEM PLL1 PFD2 */ + kCLOCK_SysPll1Pfd2Div2 = 11, /* SYSTEM PLL1 PFD2 DIV2 */ + kCLOCK_AudioPll1 = 12, /* AUDIO PLL1 */ + kCLOCK_AudioPll1Out = 13, /* AUDIO PLL1 Out */ + kCLOCK_VideoPll1 = 14, /* VEDIO PLL1 */ + kCLOCK_VideoPll1Out = 15, /* VEDIO PLL1 Out */ + kCLOCK_Ext = 16, /* Ext */ +} clock_name_t; + +extern const clock_name_t s_clockSourceName[][4]; +/******************************************************************************* + * Clock Root Definitions + ******************************************************************************/ + +/*! @brief Clock root configuration */ +typedef struct _clock_root_config_t +{ + bool clockOff; + uint8_t mux; /*!< See #clock_root_mux_source_t for details. */ + uint8_t div; /*!< it's the actual divider */ +} clock_root_config_t; + +/*! + * @brief Root clock index + */ +typedef enum _clock_root +{ + kCLOCK_Root_A55Periph = 0, /*!< CLOCK Root Arm A55 Periph. */ + kCLOCK_Root_A55MtrBus = 1, /*!< CLOCK Root Arm A55 MTR BUS. */ + kCLOCK_Root_A55 = 2, /*!< CLOCK Root Arm A55. */ + kCLOCK_Root_M33 = 3, /*!< CLOCK Root M33. */ + kCLOCK_Root_Sentinel = 4, /*!< CLOCK Root Sentinel. */ + kCLOCK_Root_BusWakeup = 5, /*!< CLOCK Root Bus Wakeup. */ + kCLOCK_Root_BusAon = 6, /*!< CLOCK Root Bus Aon. */ + kCLOCK_Root_WakeupAxi = 7, /*!< CLOCK Root Wakeup Axi. */ + kCLOCK_Root_SwoTrace = 8, /*!< CLOCK Root Swo Trace. */ + kCLOCK_Root_M33Systick = 9, /*!< CLOCK Root M33 Systick. */ + kCLOCK_Root_Flexio1 = 10, /*!< CLOCK Root Flexio1. */ + kCLOCK_Root_Flexio2 = 11, /*!< CLOCK Root Flexio2. */ + kCLOCK_Root_Lpit1 = 12, /*!< CLOCK Root Lpit1. */ + kCLOCK_Root_Lpit2 = 13, /*!< CLOCK Root Lpit2. */ + kCLOCK_Root_Lptmr1 = 14, /*!< CLOCK Root Lptmr1. */ + kCLOCK_Root_Lptmr2 = 15, /*!< CLOCK Root Lptmr2. */ + kCLOCK_Root_Tpm1 = 16, /*!< CLOCK Root Tpm1. */ + kCLOCK_Root_Tpm2 = 17, /*!< CLOCK Root Tpm2. */ + kCLOCK_Root_Tpm3 = 18, /*!< CLOCK Root Tpm3. */ + kCLOCK_Root_Tpm4 = 19, /*!< CLOCK Root Tpm4. */ + kCLOCK_Root_Tpm5 = 20, /*!< CLOCK Root Tpm5. */ + kCLOCK_Root_Tpm6 = 21, /*!< CLOCK Root Tpm6. */ + kCLOCK_Root_Flexspi1 = 22, /*!< CLOCK Root Flexspi1. */ + kCLOCK_Root_Can1 = 23, /*!< CLOCK Root Can1. */ + kCLOCK_Root_Can2 = 24, /*!< CLOCK Root Can2. */ + kCLOCK_Root_Lpuart1 = 25, /*!< CLOCK Root Lpuart1. */ + kCLOCK_Root_Lpuart2 = 26, /*!< CLOCK Root Lpuart2. */ + kCLOCK_Root_Lpuart3 = 27, /*!< CLOCK Root Lpuart3. */ + kCLOCK_Root_Lpuart4 = 28, /*!< CLOCK Root Lpuart4. */ + kCLOCK_Root_Lpuart5 = 29, /*!< CLOCK Root Lpuart5. */ + kCLOCK_Root_Lpuart6 = 30, /*!< CLOCK Root Lpuart6. */ + kCLOCK_Root_Lpuart7 = 31, /*!< CLOCK Root Lpuart7. */ + kCLOCK_Root_Lpuart8 = 32, /*!< CLOCK Root Lpuart8. */ + kCLOCK_Root_Lpi2c1 = 33, /*!< CLOCK Root Lpi2c1. */ + kCLOCK_Root_Lpi2c2 = 34, /*!< CLOCK Root Lpi2c2. */ + kCLOCK_Root_Lpi2c3 = 35, /*!< CLOCK Root Lpi2c3. */ + kCLOCK_Root_Lpi2c4 = 36, /*!< CLOCK Root Lpi2c4. */ + kCLOCK_Root_Lpi2c5 = 37, /*!< CLOCK Root Lpi2c5. */ + kCLOCK_Root_Lpi2c6 = 38, /*!< CLOCK Root Lpi2c6. */ + kCLOCK_Root_Lpi2c7 = 39, /*!< CLOCK Root Lpi2c7. */ + kCLOCK_Root_Lpi2c8 = 40, /*!< CLOCK Root Lpi2c8. */ + kCLOCK_Root_Lpspi1 = 41, /*!< CLOCK Root Lpspi1. */ + kCLOCK_Root_Lpspi2 = 42, /*!< CLOCK Root Lpspi2. */ + kCLOCK_Root_Lpspi3 = 43, /*!< CLOCK Root Lpspi3. */ + kCLOCK_Root_Lpspi4 = 44, /*!< CLOCK Root Lpspi4. */ + kCLOCK_Root_Lpspi5 = 45, /*!< CLOCK Root Lpspi5. */ + kCLOCK_Root_Lpspi6 = 46, /*!< CLOCK Root Lpspi6. */ + kCLOCK_Root_Lpspi7 = 47, /*!< CLOCK Root Lpspi7. */ + kCLOCK_Root_Lpspi8 = 48, /*!< CLOCK Root Lpspi8. */ + kCLOCK_Root_I3c1 = 49, /*!< CLOCK Root I3c1. */ + kCLOCK_Root_I3c2 = 50, /*!< CLOCK Root I3c2. */ + kCLOCK_Root_Usdhc1 = 51, /*!< CLOCK Root Usdhc1. */ + kCLOCK_Root_Usdhc2 = 52, /*!< CLOCK Root Usdhc2. */ + kCLOCK_Root_Usdhc3 = 53, /*!< CLOCK Root Usdhc3. */ + kCLOCK_Root_Sai1 = 54, /*!< CLOCK Root Sai1. */ + kCLOCK_Root_Sai2 = 55, /*!< CLOCK Root Sai2. */ + kCLOCK_Root_Sai3 = 56, /*!< CLOCK Root Sai3. */ + kCLOCK_Root_CcmCko1 = 57, /*!< CLOCK Root Ccm Cko1. */ + kCLOCK_Root_CcmCko2 = 58, /*!< CLOCK Root Ccm Cko2. */ + kCLOCK_Root_CcmCko3 = 59, /*!< CLOCK Root Ccm Cko3. */ + kCLOCK_Root_CcmCko4 = 60, /*!< CLOCK Root Ccm Cko4. */ + kCLOCK_Root_Hsio = 61, /*!< CLOCK Root Hsio. */ + kCLOCK_Root_HsioUsbTest60M = 62, /*!< CLOCK Root Hsio Usb Test 60M. */ + kCLOCK_Root_HsioAcscan80M = 63, /*!< CLOCK Root Hsio Acscan 80M. */ + kCLOCK_Root_HsioAcscan480M = 64, /*!< CLOCK Root Hsio Acscan 480M. */ + kCLOCK_Root_Nic = 65, /*!< CLOCK Root Nic. */ + kCLOCK_Root_NicApb = 66, /*!< CLOCK Root Nic Apb. */ + kCLOCK_Root_MlApb = 67, /*!< CLOCK Root Ml Apb. */ + kCLOCK_Root_Ml = 68, /*!< CLOCK Root Ml. */ + kCLOCK_Root_MediaAxi = 69, /*!< CLOCK Root Media Axi. */ + kCLOCK_Root_MediaApb = 70, /*!< CLOCK Root Media Apb. */ + kCLOCK_Root_MediaLdb = 71, /*!< CLOCK Root Media Ldb. */ + kCLOCK_Root_MediaDispPix = 72, /*!< CLOCK Root Media Disp Pix. */ + kCLOCK_Root_CamPix = 73, /*!< CLOCK Root Cam Pix. */ + kCLOCK_Root_MipiTestByte = 74, /*!< CLOCK Root Mipi Test Byte. */ + kCLOCK_Root_MipiPhyCfg = 75, /*!< CLOCK Root Mipi Phy Cfg. */ + kCLOCK_Root_DramAlt = 76, /*!< CLOCK Root Dram Alt. */ + kCLOCK_Root_DramApb = 77, /*!< CLOCK Root Dram Apb. */ + kCLOCK_Root_Adc = 78, /*!< CLOCK Root Adc. */ + kCLOCK_Root_Pdm = 79, /*!< CLOCK Root Pdm. */ + kCLOCK_Root_Tstmr1 = 80, /*!< CLOCK Root Tstmr1. */ + kCLOCK_Root_Tstmr2 = 81, /*!< CLOCK Root Tstmr2. */ + kCLOCK_Root_Mqs1 = 82, /*!< CLOCK Root MQS1. */ + kCLOCK_Root_Mqs2 = 83, /*!< CLOCK Root MQS2. */ + kCLOCK_Root_AudioXCVR = 84, /*!< CLOCK Root Audio XCVR. */ + kCLOCK_Root_Spdif = 85, /*!< CLOCK Root Spdif. */ + kCLOCK_Root_Enet = 86, /*!< CLOCK Root Enet. */ + kCLOCK_Root_EnetTimer1 = 87, /*!< CLOCK Root Enet Timer1. */ + kCLOCK_Root_EnetTimer2 = 88, /*!< CLOCK Root Enet Timer2. */ + kCLOCK_Root_EnetRef = 89, /*!< CLOCK Root Enet Ref. */ + kCLOCK_Root_EnetRefPhy = 90, /*!< CLOCK Root Enet Ref Phy. */ + kCLOCK_Root_I3c1Slow = 91, /*!< CLOCK Root I3c1Slow. */ + kCLOCK_Root_I3c2Slow = 92, /*!< CLOCK Root I3c2Slow. */ + kCLOCK_Root_UsbPhyBurunin = 93, /*!< CLOCK Root Usb Phy Burunin. */ + kCLOCK_Root_PalCameScan = 94, /*!< CLOCK Root Pal Came Scan. */ +} clock_root_t; + +/*! + * @brief The enumerator of clock roots' clock source mux value. + */ +typedef enum _clock_root_mux_source +{ + /* ARM A55 Periph */ + kCLOCK_A55PERIPH_ClockRoot_MuxOsc24M = 0U, + kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* ARM A55 MTR BUS */ + kCLOCK_A55MTRBUS_ClockRoot_MuxOsc24M = 0U, + kCLOCK_A55MTRBUS_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_A55MTRBUS_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_A55MTRBUS_ClockRoot_MuxVideoPll1Out = 3U, + + /* ARM A55 */ + kCLOCK_A55_ClockRoot_MuxOsc24M = 0U, + kCLOCK_A55_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_A55_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_A55_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* M33 */ + kCLOCK_M33_ClockRoot_MuxOsc24M = 0U, + kCLOCK_M33_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_M33_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_M33_ClockRoot_MuxVideoPll1Out = 3U, + + /* Sentinel */ + kCLOCK_SENTINEL_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SENTINEL_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_SENTINEL_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_SENTINEL_ClockRoot_MuxVideoPll1Out = 3U, + + /* Bus Wakeup */ + kCLOCK_BUSWAKEUP_ClockRoot_MuxOsc24M = 0U, + kCLOCK_BUSWAKEUP_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_BUSWAKEUP_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_BUSWAKEUP_ClockRoot_MuxVideoPll1Out = 3U, + + /* Bus Aon */ + kCLOCK_BUSAON_ClockRoot_MuxOsc24M = 0U, + kCLOCK_BUSAON_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_BUSAON_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_BUSAON_ClockRoot_MuxVideoPll1Out = 3U, + + /* Wakeup Axi */ + kCLOCK_WAKEUPAXI_ClockRoot_MuxOsc24M = 0U, + kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Swo Trace */ + kCLOCK_SWOTRACE_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SWOTRACE_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_SWOTRACE_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_SWOTRACE_ClockRoot_MuxVideoPll1Out = 3U, + + /* M33 Systick */ + kCLOCK_M33SYSTICK_ClockRoot_MuxOsc24M = 0U, + kCLOCK_M33SYSTICK_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_M33SYSTICK_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_M33SYSTICK_ClockRoot_MuxVideoPll1Out = 3U, + + /* Flexio1 */ + kCLOCK_FLEXIO1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_FLEXIO1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Flexio2 */ + kCLOCK_FLEXIO2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_FLEXIO2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpit1 */ + kCLOCK_LPIT1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPIT1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPIT1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPIT1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpit2 */ + kCLOCK_LPIT2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPIT2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPIT2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPIT2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lptmr1 */ + kCLOCK_LPTMR1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPTMR1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lptmr2 */ + kCLOCK_LPTMR2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPTMR2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Tpm1 */ + kCLOCK_TPM1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM1_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM1_ClockRoot_MuxExt = 3U, + + /* Tpm2 */ + kCLOCK_TPM2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM2_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM2_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM2_ClockRoot_MuxExt = 3U, + + /* Tpm3 */ + kCLOCK_TPM3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM3_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM3_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM3_ClockRoot_MuxExt = 3U, + + /* Tpm4 */ + kCLOCK_TPM4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM4_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM4_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM4_ClockRoot_MuxExt = 3U, + + /* Tpm5 */ + kCLOCK_TPM5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM5_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM5_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM5_ClockRoot_MuxExt = 3U, + + /* Tpm6 */ + kCLOCK_TPM6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM6_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM6_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM6_ClockRoot_MuxExt = 3U, + + /* Flexspi1 */ + kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Can1 */ + kCLOCK_CAN1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CAN1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_CAN1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_CAN1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Can2 */ + kCLOCK_CAN2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CAN2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_CAN2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_CAN2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart1 */ + kCLOCK_LPUART1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart2 */ + kCLOCK_LPUART2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart3 */ + kCLOCK_LPUART3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART3_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart4 */ + kCLOCK_LPUART4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart5 */ + kCLOCK_LPUART5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART5_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart6 */ + kCLOCK_LPUART6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART6_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart7 */ + kCLOCK_LPUART7_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART7_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart8 */ + kCLOCK_LPUART8_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART8_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c1 */ + kCLOCK_LPI2C1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c2 */ + kCLOCK_LPI2C2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c3 */ + kCLOCK_LPI2C3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C3_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c4 */ + kCLOCK_LPI2C4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c5 */ + kCLOCK_LPI2C5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C5_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c6 */ + kCLOCK_LPI2C6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C6_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c7 */ + kCLOCK_LPI2C7_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C7_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c8 */ + kCLOCK_LPI2C8_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C8_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi1 */ + kCLOCK_LPSPI1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi2 */ + kCLOCK_LPSPI2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi3 */ + kCLOCK_LPSPI3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI3_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi4 */ + kCLOCK_LPSPI4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpispi5 */ + kCLOCK_LPSPI5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI5_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi6 */ + kCLOCK_LPSPI6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI6_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi7 */ + kCLOCK_LPSPI7_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI7_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi8 */ + kCLOCK_LPSPI8_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI8_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c1 */ + kCLOCK_I3C1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C1_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c2 */ + kCLOCK_I3C2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Usdhc1 */ + kCLOCK_Usdhc1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Usdhc2 */ + kCLOCK_Usdhc2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Usdhc3 */ + kCLOCK_Usdhc3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Sai1 */ + kCLOCK_SAI1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SAI1_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SAI1_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SAI1_ClockRoot_MuxExt = 3U, + + /* Sai2 */ + kCLOCK_SAI2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SAI2_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SAI2_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SAI2_ClockRoot_MuxExt = 3U, + + /* Sai3 */ + kCLOCK_SAI3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SAI3_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SAI3_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SAI3_ClockRoot_MuxExt = 3U, + + /* Ccm Cko1 */ + kCLOCK_CCMCKO1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO1_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO1_ClockRoot_MuxAudioPll1Out = 3U, + + /* Ccm Cko2 */ + kCLOCK_CCMCKO2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO2_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO2_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Ccm Cko3 */ + kCLOCK_CCMCKO3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO3_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO3_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO3_ClockRoot_MuxAudioPll1Out = 3U, + + /* Ccm Cko4 */ + kCLOCK_CCMCKO4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO4_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO4_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio */ + kCLOCK_HSIO_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIO_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIO_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIO_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio Usb Test 60M */ + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio Acscan 80M */ + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio Acscan 480M */ + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxVideoPll1Out = 3U, + + /* Nic */ + kCLOCK_NIC_ClockRoot_MuxOsc24M = 0U, + kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Nic Apb */ + kCLOCK_NICAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_NICAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_NICAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_NICAPB_ClockRoot_MuxVideoPll1Out = 3U, + + /* Ml Apb */ + kCLOCK_MLAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MLAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_MLAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_MLAPB_ClockRoot_MuxVideoPll1Out = 3U, + + /* Ml */ + kCLOCK_ML_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ML_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_ML_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_ML_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Media Axi */ + kCLOCK_MEDIAAXI_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Media Apb */ + kCLOCK_MEDIAAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIAAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_MEDIAAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_MEDIAAPB_ClockRoot_MuxVideoPll1Out = 3U, + + /* Media Ldb */ + kCLOCK_MEDIALDB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIALDB_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MEDIALDB_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MEDIALDB_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Media Disp Pix */ + kCLOCK_MEDIADISPPIX_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIADISPPIX_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MEDIADISPPIX_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MEDIADISPPIX_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Cam Pix */ + kCLOCK_CAMPIX_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CAMPIX_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_CAMPIX_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_CAMPIX_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Mipi Test Byte */ + kCLOCK_MIPITESTBYTE_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MIPITESTBYTE_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MIPITESTBYTE_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MIPITESTBYTE_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Mipi Phy Cfg */ + kCLOCK_MIPIPHYCFG_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MIPIPHYCFG_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MIPIPHYCFG_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MIPIPHYCFG_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Dram Alt */ + kCLOCK_DRAMALT_ClockRoot_MuxOsc24M = 0U, + kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Dram Apb */ + kCLOCK_DRAMAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Adc */ + kCLOCK_ADC_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ADC_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ADC_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ADC_ClockRoot_MuxVideoPll1Out = 3U, + + /* Pdm */ + kCLOCK_PDM_ClockRoot_MuxOsc24M = 0U, + kCLOCK_PDM_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_PDM_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_PDM_ClockRoot_MuxExt = 3U, + + /* Tstmr1 */ + kCLOCK_TSTMR1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TSTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_TSTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_TSTMR1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Tstmr2 */ + kCLOCK_TSTMR2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TSTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_TSTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_TSTMR2_ClockRoot_MuxVideoPll1Out = 3U, + + /* MQS1 */ + kCLOCK_MQS1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MQS1_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MQS1_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MQS1_ClockRoot_MuxExt = 3U, + + /* MQS2 */ + kCLOCK_MQS2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MQS2_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MQS2_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MQS2_ClockRoot_MuxExt = 3U, + + /* Audio XCVR */ + kCLOCK_AUDIOXCVR_ClockRoot_MuxOsc24M = 0U, + kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Spdif */ + kCLOCK_SPDIF_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SPDIF_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SPDIF_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SPDIF_ClockRoot_MuxExt = 3U, + + /* Enet */ + kCLOCK_ENET_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Enet Timer1 */ + kCLOCK_ENETTSTMR1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETTSTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETTSTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETTSTMR1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Enet Timer2 */ + kCLOCK_ENETTSTMR2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETTSTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETTSTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETTSTMR2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Enet Ref */ + kCLOCK_ENETREF_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Enet Ref Phy */ + kCLOCK_ENETREFPHY_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETREFPHY_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETREFPHY_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETREFPHY_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c1 Slow */ + kCLOCK_I3C1SLOW_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C1SLOW_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C1SLOW_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C1SLOW_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c2 Slow */ + kCLOCK_I3C2SLOW_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C2SLOW_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C2SLOW_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C2SLOW_ClockRoot_MuxVideoPll1Out = 3U, + + /* Usb Phy Burunin */ + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxOsc24M = 0U, + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxVideoPll1Out = 3U, + + /* Pal Came Scan */ + kCLOCK_PALCAMESCAN_ClockRoot_MuxOsc24M = 0U, + kCLOCK_PALCAMESCAN_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_PALCAMESCAN_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_PALCAMESCAN_ClockRoot_MuxSysPll1Pfd2 = 3U, +} clock_root_mux_source_t; + +/******************************************************************************* + * Clock Gate Definitions + ******************************************************************************/ + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_Off = CCM_LPCG_LPM_SETTING_0, + kCLOCK_On = CCM_LPCG_LPM_SETTING_4, +} clock_gate_value_t; + +/*! + * @brief Clock LPCG index (Clock Gating Channel) + */ +typedef enum _clock_lpcg +{ + kCLOCK_A55 = 0, + kCLOCK_Cm33 = 1, + kCLOCK_Arm_Trout = 2, + kCLOCK_Sentinel = 3, + kCLOCK_Sim_Wakeup = 4, + kCLOCK_Sim_Aon = 5, + kCLOCK_Sim_Mega = 6, + kCLOCK_Anadig = 7, + kCLOCK_Src = 8, + kCLOCK_Ccm = 9, + kCLOCK_Gpc = 10, + kCLOCK_Adc1 = 11, + kCLOCK_Wdog1 = 12, + kCLOCK_Wdog2 = 13, + kCLOCK_Wdog3 = 14, + kCLOCK_Wdog4 = 15, + kCLOCK_Wdog5 = 16, + kCLOCK_Sema1 = 17, + kCLOCK_Sema2 = 18, + kCLOCK_Mu_A = 19, + kCLOCK_Mu_B = 20, + kCLOCK_Edma1 = 21, + kCLOCK_Edma2 = 22, + kCLOCK_Romcp_A55 = 23, + kCLOCK_Romcp_M33 = 24, + kCLOCK_Flexspi1 = 25, + kCLOCK_Aon_Trdc = 26, + kCLOCK_Wkup_Trdc = 27, + kCLOCK_Ocotp = 28, + kCLOCK_Bbsm_Hp = 29, + kCLOCK_Bbsm = 30, + kCLOCK_Cstrace = 31, + kCLOCK_Csswo = 32, + kCLOCK_Iomuxc = 33, + kCLOCK_Gpio1 = 34, + kCLOCK_Gpio2 = 35, + kCLOCK_Gpio3 = 36, + kCLOCK_Gpio4 = 37, + kCLOCK_Flexio1 = 38, + kCLOCK_Flexio2 = 39, + kCLOCK_Lpit1 = 40, + kCLOCK_Lpit2 = 41, + kCLOCK_Lptmr1 = 42, + kCLOCK_Lptmr2 = 43, + kCLOCK_Tpm1 = 44, + kCLOCK_Tpm2 = 45, + kCLOCK_Tpm3 = 46, + kCLOCK_Tpm4 = 47, + kCLOCK_Tpm5 = 48, + kCLOCK_Tpm6 = 49, + kCLOCK_Can1 = 50, + kCLOCK_Can2 = 51, + kCLOCK_Lpuart1 = 52, + kCLOCK_Lpuart2 = 53, + kCLOCK_Lpuart3 = 54, + kCLOCK_Lpuart4 = 55, + kCLOCK_Lpuart5 = 56, + kCLOCK_Lpuart6 = 57, + kCLOCK_Lpuart7 = 58, + kCLOCK_Lpuart8 = 59, + kCLOCK_Lpi2c1 = 60, + kCLOCK_Lpi2c2 = 61, + kCLOCK_Lpi2c3 = 62, + kCLOCK_Lpi2c4 = 63, + kCLOCK_Lpi2c5 = 64, + kCLOCK_Lpi2c6 = 65, + kCLOCK_Lpi2c7 = 66, + kCLOCK_Lpi2c8 = 67, + kCLOCK_Lpspi1 = 68, + kCLOCK_Lpspi2 = 69, + kCLOCK_Lpspi3 = 70, + kCLOCK_Lpspi4 = 71, + kCLOCK_Lpspi5 = 72, + kCLOCK_Lpspi6 = 73, + kCLOCK_Lpspi7 = 74, + kCLOCK_Lpspi8 = 75, + kCLOCK_I3c1 = 76, + kCLOCK_I3c2 = 77, + kCLOCK_Usdhc1 = 78, + kCLOCK_Usdhc2 = 79, + kCLOCK_Usdhc3 = 80, + kCLOCK_Sai1 = 81, + kCLOCK_Sai2 = 82, + kCLOCK_Sai3 = 83, + kCLOCK_Ssi_W2ao = 84, + kCLOCK_Ssi_Ao2w = 85, + kCLOCK_Mipi_Csi = 86, + kCLOCK_Mipi_Dsi = 87, + kCLOCK_Lvds = 88, + kCLOCK_Lcdif = 89, + kCLOCK_Pxp = 90, + kCLOCK_Isi = 91, + kCLOCK_Nic_Media = 92, + kCLOCK_Ddr_Dfi = 93, + kCLOCK_Ddr_Ctl = 94, + kCLOCK_Ddr_Dfi_Ctl = 95, + kCLOCK_Ddr_Ssi = 96, + kCLOCK_Ddr_Bypass = 97, + kCLOCK_Ddr_Apb = 98, + kCLOCK_Ddr_Drampll = 99, + kCLOCK_Ddr_Clk_Ctl = 100, + kCLOCK_Nic_Central = 101, + kCLOCK_Gic600 = 102, + kCLOCK_Nic_Apb = 103, + kCLOCK_Usb_Controller = 104, + kCLOCK_Usb_Test_60m = 105, + kCLOCK_Hsio_Trout_24m = 106, + kCLOCK_Pdm = 107, + kCLOCK_Mqs1 = 108, + kCLOCK_Mqs2 = 109, + kCLOCK_Aud_Xcvr = 110, + kCLOCK_Nicmix_Mecc = 111, + kCLOCK_Spdif = 112, + kCLOCK_Ssi_Ml2nic = 113, + kCLOCK_Ssi_Med2nic = 114, + kCLOCK_Ssi_Hsio2nic = 115, + kCLOCK_Ssi_W2nic = 116, + kCLOCK_Ssi_Nic2w = 117, + kCLOCK_Ssi_Nic2ddr = 118, + kCLOCK_Hsio_32k = 119, + kCLOCK_Enet1 = 120, + kCLOCK_Enet_Qos = 121, + kCLOCK_Sys_Cnt = 122, + kCLOCK_Tstmr1 = 123, + kCLOCK_Tstmr2 = 124, + kCLOCK_Tmc = 125, + kCLOCK_Pmro = 126, + kCLOCK_IpInvalid, +} clock_lpcg_t; + +#define clock_ip_name_t clock_lpcg_t + +/*! @brief Clock ip name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Edma1, kCLOCK_Edma2 \ + } + +/* + * ! @brief Clock ip name array for MU. + * clock of MU1_MUA, MU2_MUA is enabled by same LPCG42(Gate signal is clk_enable_mu_a) + */ +#define MU_CLOCKS \ + { \ + kCLOCK_Mu_A, kCLOCK_Mu_A \ + } + +/*! @brief Clock ip name array for LCDIFV3. */ +#define LCDIFV3_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lcdif \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6, \ + kCLOCK_Lpi2c7, kCLOCK_Lpi2c8 \ + } + +/*! @brief Clock ip name array for LPIT. */ +#define LPIT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpit1, kCLOCK_Lpit2 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6, \ + kCLOCK_Lpspi7, kCLOCK_Lpspi8 \ + } + +/*! @brief Clock ip name array for TPM. */ +#define TPM_CLOCKS \ + { \ + kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6, \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexspi1 \ + } + +/*! @brief Clock ip name array for TMU. */ +#define TMU_CLOCKS \ + { \ + kCLOCK_Tmc, \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, \ + } + +/*! @brief Clock ip name array for PDM. */ +#define PDM_CLOCKS \ + { \ + kCLOCK_Pdm \ + } + +/*! @brief Clock ip name array for ENET QOS. */ +#define ENETQOS_CLOCKS \ + { \ + kCLOCK_Enet_Qos \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet1 \ + } + +/*! @brief Clock ip name array for I3C. */ +#define I3C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_I3c1, kCLOCK_I3c2 \ + } + +/*! @brief Clock ip name array for SEMA42. */ +#define SEMA42_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sema1, kCLOCK_Sema2 \ + } + +/******************************************************************************* + * Clock Root APIs + ******************************************************************************/ + +/*! + * @brief Set CCM Root Clock MUX node to certain value. + * + * @param root Which root clock node to set, see \ref clock_root_t. + * @param src Clock mux value to set, different mux has different value range. See \ref clock_root_mux_source_t. + */ +static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src) +{ + assert(src < 8U); + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = + (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~(CCM_CLOCK_ROOT_MUX_MASK)) | CCM_CLOCK_ROOT_MUX(src); + __DSB(); + __ISB(); +} + +/*! + * @brief Get CCM Root Clock MUX value. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root) +{ + return (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_MUX_MASK) >> CCM_CLOCK_ROOT_MUX_SHIFT; +} + +/*! + * @brief Get CCM Root Clock Source. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @param src Clock mux value to get, see \ref clock_root_mux_source_t. + * @return Clock source + */ +static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src) +{ + return s_clockSourceName[root][src]; +} + +/*! + * @brief Set CCM Root Clock DIV certain value. + * + * @param root Which root clock to set, see \ref clock_root_t. + * @param div Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint8_t div) +{ + assert(div); + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = + (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~CCM_CLOCK_ROOT_DIV_MASK) | + CCM_CLOCK_ROOT_DIV((uint32_t)div - 1UL); + __DSB(); + __ISB(); +} + +/*! + * @brief Get CCM DIV node value. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @return divider set for this root + */ +static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root) +{ + return ((CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_DIV_MASK) >> CCM_CLOCK_ROOT_DIV_SHIFT) + + 1UL; +} + +/*! + * @brief Power Off Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + */ +static inline void CLOCK_PowerOffRootClock(clock_root_t root) +{ + if (0UL == (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_OFF_MASK)) + { + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.SET = CCM_CLOCK_ROOT_OFF_MASK; + __DSB(); + __ISB(); + } +} + +/*! + * @brief Power On Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + */ +static inline void CLOCK_PowerOnRootClock(clock_root_t root) +{ + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.CLR = CCM_CLOCK_ROOT_OFF_MASK; + __DSB(); + __ISB(); +} + +/*! + * @brief Configure Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + * @param config root clock config, see \ref clock_root_config_t + */ +static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config) +{ + assert(config); + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = CCM_CLOCK_ROOT_MUX(config->mux) | + CCM_CLOCK_ROOT_DIV((uint32_t)config->div - 1UL) | + (config->clockOff ? CCM_CLOCK_ROOT_OFF(config->clockOff) : 0UL); + __DSB(); + __ISB(); +} + +/******************************************************************************* + * Clock Gate APIs + ******************************************************************************/ + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_lpcg_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + CCM_CTRL->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_CPULPM_MODE(1U); + CCM_CTRL->LPCG[name].LPM_CUR = CCM_LPCG_LPM_CUR_LPM_SETTING_CUR(value); + __DSB(); + __ISB(); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_lpcg_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_On); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_lpcg_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_Off); +} + +/******************************************************************************* + * Other APIs + ******************************************************************************/ + +/* + * Setup a variable for clock source frequencies + */ +extern volatile uint32_t g_clockSourceFreq[kCLOCK_Ext + 1]; + +/*! + * @brief Gets the clock frequency for a specific IP module. + * + * This function gets the IP module clock frequency. + * + * @param name Which root clock to get, see \ref clock_root_t. + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetIpFreq(clock_root_t name); + +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_iomuxc.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_iomuxc.h new file mode 100644 index 00000000000..c1a7bc8d6a4 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_iomuxc.h @@ -0,0 +1,796 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 1.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PAD_DAP_TDI__JTAG_MUX_TDI 0x543c0000, 0x00, 0x543c03d8, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__MQS2_LEFT 0x543c0000, 0x01, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__CAN2_TX 0x543c0000, 0x03, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x543c0000, 0x04, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__GPIO3_IO28 0x543c0000, 0x05, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__LPUART5_RX 0x543c0000, 0x06, 0x543c0488, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x543c0004, 0x00, 0x543c03dc, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x543c0004, 0x04, 0x0, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x543c0004, 0x05, 0x0, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x543c0004, 0x06, 0x0, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x543c0008, 0x00, 0x543c03d4, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x543c0008, 0x04, 0x0, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x543c0008, 0x05, 0x0, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x543c0008, 0x06, 0x543c0484, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x543c000c, 0x00, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x543c000c, 0x01, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x543c000c, 0x03, 0x543c0364, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x543c000c, 0x04, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x543c000c, 0x05, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x543c000c, 0x06, 0x543c048c, 0x00, 0x543c01bc +#define IOMUXC_PAD_GPIO_IO00__GPIO2_IO0 0x543c0010, 0x00, 0x0, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPI2C3_SDA 0x543c0010, 0x01, 0x543c03f4, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x543c0010, 0x02, 0x543c04bc, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x543c0010, 0x03, 0x0, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPSPI6_PCS0 0x543c0010, 0x04, 0x0, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPUART5_TX 0x543c0010, 0x05, 0x543c048c, 0x01, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPI2C5_SDA 0x543c0010, 0x06, 0x543c0404, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x543c0010, 0x07, 0x543c036c, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO01__GPIO2_IO1 0x543c0014, 0x00, 0x0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPI2C3_SCL 0x543c0014, 0x01, 0x543c03f0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x543c0014, 0x02, 0x543c0490, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x543c0014, 0x03, 0x0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPSPI6_SIN 0x543c0014, 0x04, 0x0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPUART5_RX 0x543c0014, 0x05, 0x543c0488, 0x01, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPI2C5_SCL 0x543c0014, 0x06, 0x543c0400, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x543c0014, 0x07, 0x543c0370, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO02__GPIO2_IO3 0x543c0018, 0x00, 0x0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPI2C4_SDA 0x543c0018, 0x01, 0x543c03fc, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x543c0018, 0x02, 0x543c04c0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x543c0018, 0x03, 0x0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPSPI6_SOUT 0x543c0018, 0x04, 0x0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPUART5_CTS_B 0x543c0018, 0x05, 0x543c0484, 0x01, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPI2C6_SDA 0x543c0018, 0x06, 0x543c040c, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__FLEXIO1_FLEXIO3 0x543c0018, 0x07, 0x543c0374, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO03__GPIO2_IO3 0x543c001c, 0x00, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPI2C4_SCL 0x543c001c, 0x01, 0x543c03f8, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x543c001c, 0x02, 0x543c04b8, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x543c001c, 0x03, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPSPI6_SCK 0x543c001c, 0x04, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPUART5_RTS_B 0x543c001c, 0x05, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPI2C6_SCL 0x543c001c, 0x06, 0x543c0408, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x543c001c, 0x07, 0x543c0378, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO04__GPIO2_IO4 0x543c0020, 0x00, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__TPM3_CH0 0x543c0020, 0x01, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__PDM_CLK 0x543c0020, 0x02, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x543c0020, 0x03, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__LPSPI7_PCS0 0x543c0020, 0x04, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__LPUART6_TX 0x543c0020, 0x05, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__LPI2C6_SDA 0x543c0020, 0x06, 0x543c040c, 0x01, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x543c0020, 0x07, 0x543c037c, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO05__GPIO2_IO5 0x543c0024, 0x00, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__TPM4_CH0 0x543c0024, 0x01, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x543c0024, 0x02, 0x543c04c4, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x543c0024, 0x03, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__LPSPI7_SIN 0x543c0024, 0x04, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__LPUART6_RX 0x543c0024, 0x05, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__LPI2C6_SCL 0x543c0024, 0x06, 0x543c0408, 0x01, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x543c0024, 0x07, 0x543c0380, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO06__GPIO2_IO6 0x543c0028, 0x00, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__TPM5_CH0 0x543c0028, 0x01, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x543c0028, 0x02, 0x543c04c8, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x543c0028, 0x03, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__LPSPI7_SOUT 0x543c0028, 0x04, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__LPUART6_CTS_B 0x543c0028, 0x05, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__LPI2C7_SDA 0x543c0028, 0x06, 0x543c0414, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x543c0028, 0x07, 0x543c0384, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO07__GPIO2_IO7 0x543c002c, 0x00, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPSPI3_PCS1 0x543c002c, 0x01, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x543c002c, 0x02, 0x543c0494, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x543c002c, 0x03, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPSPI7_SCK 0x543c002c, 0x04, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPUART6_RTS_B 0x543c002c, 0x05, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPI2C7_SCL 0x543c002c, 0x06, 0x543c0410, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x543c002c, 0x07, 0x543c0388, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO08__GPIO2_IO8 0x543c0030, 0x00, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__LPSPI3_PCS0 0x543c0030, 0x01, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x543c0030, 0x02, 0x543c0498, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x543c0030, 0x03, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__TPM6_CH0 0x543c0030, 0x04, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__LPUART7_TX 0x543c0030, 0x05, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__LPI2C7_SDA 0x543c0030, 0x06, 0x543c0414, 0x01, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x543c0030, 0x07, 0x543c038c, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO09__GPIO2_IO9 0x543c0034, 0x00, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__LPSPI3_SIN 0x543c0034, 0x01, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x543c0034, 0x02, 0x543c049c, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x543c0034, 0x03, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__TPM3_EXTCLK 0x543c0034, 0x04, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__LPUART7_RX 0x543c0034, 0x05, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__LPI2C7_SCL 0x543c0034, 0x06, 0x543c0410, 0x01, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x543c0034, 0x07, 0x543c0390, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO10__GPIO2_IO10 0x543c0038, 0x00, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__LPSPI3_SOUT 0x543c0038, 0x01, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x543c0038, 0x02, 0x543c04a0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x543c0038, 0x03, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__TPM4_EXTCLK 0x543c0038, 0x04, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__LPUART7_CTS_B 0x543c0038, 0x05, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__LPI2C8_SDA 0x543c0038, 0x06, 0x543c041c, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x543c0038, 0x07, 0x543c0394, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO11__GPIO2_IO11 0x543c003c, 0x00, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__LPSPI3_SCK 0x543c003c, 0x01, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x543c003c, 0x02, 0x543c04a4, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x543c003c, 0x03, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__TPM5_EXTCLK 0x543c003c, 0x04, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__LPUART7_RTS_B 0x543c003c, 0x05, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__LPI2C8_SCL 0x543c003c, 0x06, 0x543c0418, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x543c003c, 0x07, 0x543c0398, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO12__GPIO2_IO12 0x543c0040, 0x00, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__TPM3_CH2 0x543c0040, 0x01, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x543c0040, 0x02, 0x543c04cc, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x543c0040, 0x03, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__LPSPI8_PCS0 0x543c0040, 0x04, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__LPUART8_TX 0x543c0040, 0x05, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__LPI2C8_SDA 0x543c0040, 0x06, 0x543c041c, 0x01, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__SAI3_RX_SYNC 0x543c0040, 0x07, 0x543c04dc, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO13__GPIO2_IO13 0x543c0044, 0x00, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__TPM4_CH2 0x543c0044, 0x01, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x543c0044, 0x02, 0x543c04d0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x543c0044, 0x03, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__LPSPI8_SIN 0x543c0044, 0x04, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__LPUART8_RX 0x543c0044, 0x05, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__LPI2C8_SCL 0x543c0044, 0x06, 0x543c0418, 0x01, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x543c0044, 0x07, 0x543c039c, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO14__GPIO2_IO14 0x543c0048, 0x00, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPUART3_TX 0x543c0048, 0x01, 0x543c0474, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x543c0048, 0x02, 0x543c04a8, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x543c0048, 0x03, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPSPI8_SOUT 0x543c0048, 0x04, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPUART8_CTS_B 0x543c0048, 0x05, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPUART4_TX 0x543c0048, 0x06, 0x543c0480, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x543c0048, 0x07, 0x543c03a0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO15__GPIO2_IO15 0x543c004c, 0x00, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPUART3_RX 0x543c004c, 0x01, 0x543c0470, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x543c004c, 0x02, 0x543c04ac, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x543c004c, 0x03, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPSPI8_SCK 0x543c004c, 0x04, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPUART8_RTS_B 0x543c004c, 0x05, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPUART4_RX 0x543c004c, 0x06, 0x543c047c, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x543c004c, 0x07, 0x543c03a4, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO16__GPIO2_IO16 0x543c0050, 0x00, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__SAI3_TX_BCLK 0x543c0050, 0x01, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x543c0050, 0x02, 0x543c04cc, 0x01, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x543c0050, 0x03, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__LPUART3_CTS_B 0x543c0050, 0x04, 0x543c046c, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__LPSPI4_PCS2 0x543c0050, 0x05, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__LPUART4_CTS_B 0x543c0050, 0x06, 0x543c0478, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x543c0050, 0x07, 0x543c03a8, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO17__GPIO2_IO17 0x543c0054, 0x00, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__SAI3_MCLK 0x543c0054, 0x01, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x543c0054, 0x02, 0x543c04b0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x543c0054, 0x03, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__LPUART3_RTS_B 0x543c0054, 0x04, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__LPSPI4_PCS1 0x543c0054, 0x05, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__LPUART4_RTS_B 0x543c0054, 0x06, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x543c0054, 0x07, 0x543c03ac, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO18__GPIO2_IO18 0x543c0058, 0x00, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__SAI3_RX_BCLK 0x543c0058, 0x01, 0x543c04d8, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x543c0058, 0x02, 0x543c04b4, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x543c0058, 0x03, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__LPSPI5_PCS0 0x543c0058, 0x04, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__LPSPI4_PCS0 0x543c0058, 0x05, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__TPM5_CH2 0x543c0058, 0x06, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x543c0058, 0x07, 0x543c03b0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO19__GPIO2_IO19 0x543c005c, 0x00, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__SAI3_RX_SYNC 0x543c005c, 0x01, 0x543c04dc, 0x01, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x543c005c, 0x02, 0x543c04d0, 0x01, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x543c005c, 0x03, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__LPSPI5_SIN 0x543c005c, 0x04, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__LPSPI4_SIN 0x543c005c, 0x05, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__TPM6_CH2 0x543c005c, 0x06, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__SAI3_TX_DATA0 0x543c005c, 0x07, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO20__GPIO2_IO20 0x543c0060, 0x00, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__SAI3_RX_DATA0 0x543c0060, 0x01, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x543c0060, 0x02, 0x543c04c4, 0x01, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x543c0060, 0x03, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__LPSPI5_SOUT 0x543c0060, 0x04, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__LPSPI4_SOUT 0x543c0060, 0x05, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__TPM3_CH1 0x543c0060, 0x06, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x543c0060, 0x07, 0x543c03b4, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO21__GPIO2_IO21 0x543c0064, 0x00, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__SAI3_TX_DATA0 0x543c0064, 0x01, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__PDM_CLK 0x543c0064, 0x02, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x543c0064, 0x03, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__LPSPI5_SCK 0x543c0064, 0x04, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__LPSPI4_SCK 0x543c0064, 0x05, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__TPM4_CH1 0x543c0064, 0x06, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__SAI3_RX_BCLK 0x543c0064, 0x07, 0x543c04d8, 0x01, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO22__GPIO2_IO22 0x543c0068, 0x00, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__USDHC3_CLK 0x543c0068, 0x01, 0x543c04e8, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__SPDIF_IN 0x543c0068, 0x02, 0x543c04e4, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x543c0068, 0x03, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__TPM5_CH1 0x543c0068, 0x04, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__TPM6_EXTCLK 0x543c0068, 0x05, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__LPI2C5_SDA 0x543c0068, 0x06, 0x543c0404, 0x01, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x543c0068, 0x07, 0x543c03b8, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO23__GPIO2_IO23 0x543c006c, 0x00, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__USDHC3_CMD 0x543c006c, 0x01, 0x543c04ec, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__SPDIF_OUT 0x543c006c, 0x02, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x543c006c, 0x03, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__TPM6_CH1 0x543c006c, 0x04, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__LPI2C5_SCL 0x543c006c, 0x06, 0x543c0400, 0x01, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x543c006c, 0x07, 0x543c03bc, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO24__GPIO2_IO24 0x543c0070, 0x00, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__USDHC3_DATA0 0x543c0070, 0x01, 0x543c04f0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x543c0070, 0x03, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__TPM3_CH3 0x543c0070, 0x04, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__JTAG_MUX_TDO 0x543c0070, 0x05, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__LPSPI6_PCS1 0x543c0070, 0x06, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x543c0070, 0x07, 0x543c03c0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO25__GPIO2_IO25 0x543c0074, 0x00, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__USDHC3_DATA1 0x543c0074, 0x01, 0x543c04f4, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__CAN2_TX 0x543c0074, 0x02, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x543c0074, 0x03, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__TPM4_CH3 0x543c0074, 0x04, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__JTAG_MUX_TCK 0x543c0074, 0x05, 0x543c03d4, 0x01, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__LPSPI7_PCS1 0x543c0074, 0x06, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x543c0074, 0x07, 0x543c03c4, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO26__GPIO2_IO26 0x543c0078, 0x00, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__USDHC3_DATA2 0x543c0078, 0x01, 0x543c04f8, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x543c0078, 0x02, 0x543c04c8, 0x01, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x543c0078, 0x03, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__TPM5_CH3 0x543c0078, 0x04, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__JTAG_MUX_TDI 0x543c0078, 0x05, 0x543c03d8, 0x01, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__LPSPI8_PCS1 0x543c0078, 0x06, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__SAI3_TX_SYNC 0x543c0078, 0x07, 0x543c04e0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO27__GPIO2_IO27 0x543c007c, 0x00, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__USDHC3_DATA3 0x543c007c, 0x01, 0x543c04fc, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__CAN2_RX 0x543c007c, 0x02, 0x543c0364, 0x01, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x543c007c, 0x03, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__TPM6_CH3 0x543c007c, 0x04, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__JTAG_MUX_TMS 0x543c007c, 0x05, 0x543c03dc, 0x01, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__LPSPI5_PCS1 0x543c007c, 0x06, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x543c007c, 0x07, 0x543c03c8, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO28__GPIO2_IO28 0x543c0080, 0x00, 0x0, 0x00, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO28__LPI2C3_SDA 0x543c0080, 0x01, 0x543c03f4, 0x01, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO28__CAN1_TX 0x543c0080, 0x02, 0x0, 0x00, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x543c0080, 0x07, 0x0, 0x00, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO29__GPIO2_IO29 0x543c0084, 0x00, 0x0, 0x00, 0x543c0234 +#define IOMUXC_PAD_GPIO_IO29__LPI2C3_SCL 0x543c0084, 0x01, 0x543c03f0, 0x01, 0x543c0234 +#define IOMUXC_PAD_GPIO_IO29__CAN1_RX 0x543c0084, 0x02, 0x543c0360, 0x00, 0x543c0234 +#define IOMUXC_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x543c0084, 0x07, 0x0, 0x00, 0x543c0234 +#define IOMUXC_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x543c0088, 0x00, 0x0, 0x00, 0x543c0238 +#define IOMUXC_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x543c0088, 0x04, 0x0, 0x00, 0x543c0238 +#define IOMUXC_PAD_CCM_CLKO1__GPIO3_IO26 0x543c0088, 0x05, 0x0, 0x00, 0x543c0238 +#define IOMUXC_PAD_CCM_CLKO2__GPIO3_IO27 0x543c008c, 0x05, 0x0, 0x00, 0x543c023c +#define IOMUXC_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x543c008c, 0x00, 0x0, 0x00, 0x543c023c +#define IOMUXC_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x543c008c, 0x04, 0x543c03c8, 0x01, 0x543c023c +#define IOMUXC_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x543c0090, 0x00, 0x0, 0x00, 0x543c0240 +#define IOMUXC_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x543c0090, 0x04, 0x0, 0x00, 0x543c0240 +#define IOMUXC_PAD_CCM_CLKO3__GPIO4_IO28 0x543c0090, 0x05, 0x0, 0x00, 0x543c0240 +#define IOMUXC_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x543c0094, 0x00, 0x0, 0x00, 0x543c0244 +#define IOMUXC_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x543c0094, 0x04, 0x0, 0x00, 0x543c0244 +#define IOMUXC_PAD_CCM_CLKO4__GPIO4_IO29 0x543c0094, 0x05, 0x0, 0x00, 0x543c0244 +#define IOMUXC_PAD_ENET1_MDC__ENET1_MDC 0x543c0098, 0x00, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__LPUART3_DCB_B 0x543c0098, 0x01, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__I3C2_SCL 0x543c0098, 0x02, 0x543c03cc, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x543c0098, 0x03, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x543c0098, 0x04, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__GPIO4_IO0 0x543c0098, 0x05, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__LPI2C1_SCL 0x543c0098, 0x06, 0x543c03e0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x543c009c, 0x00, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__LPUART3_RIN_B 0x543c009c, 0x01, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__I3C2_SDA 0x543c009c, 0x02, 0x543c03d0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x543c009c, 0x03, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x543c009c, 0x04, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__GPIO4_IO1 0x543c009c, 0x05, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__LPI2C1_SDA 0x543c009c, 0x06, 0x543c03e4, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x543c00a0, 0x00, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__CAN2_TX 0x543c00a0, 0x02, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x543c00a0, 0x03, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x543c00a0, 0x04, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__GPIO4_IO3 0x543c00a0, 0x05, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__LPI2C1_SCL 0x543c00a0, 0x06, 0x543c03e8, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x543c00a4, 0x00, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x543c00a4, 0x01, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__CAN2_RX 0x543c00a4, 0x02, 0x543c0364, 0x02, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x543c00a4, 0x03, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x543c00a4, 0x04, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__GPIO4_IO3 0x543c00a4, 0x05, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__LPI2C2_SDA 0x543c00a4, 0x06, 0x543c03ec, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x543c00a8, 0x00, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__LPUART3_RTS_B 0x543c00a8, 0x01, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__I3C2_PUR 0x543c00a8, 0x02, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x543c00a8, 0x03, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x543c00a8, 0x04, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__GPIO4_IO4 0x543c00a8, 0x05, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__I3C2_PUR_B 0x543c00a8, 0x06, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x543c00ac, 0x00, 0x0, 0x00, 0x543c025c +#define IOMUXC_PAD_ENET1_TD0__LPUART3_TX 0x543c00ac, 0x01, 0x543c0474, 0x01, 0x543c025c +#define IOMUXC_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x543c00ac, 0x04, 0x0, 0x00, 0x543c025c +#define IOMUXC_PAD_ENET1_TD0__GPIO4_IO5 0x543c00ac, 0x05, 0x0, 0x00, 0x543c025c +#define IOMUXC_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x543c00b0, 0x00, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x543c00b0, 0x01, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x543c00b0, 0x04, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__GPIO4_IO6 0x543c00b0, 0x05, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x543c00b0, 0x02, 0x543c043c, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x543c00b4, 0x00, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x543c00b4, 0x01, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x543c00b4, 0x04, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__GPIO4_IO7 0x543c00b4, 0x05, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__LPSPI2_SIN 0x543c00b4, 0x02, 0x543c0440, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x543c00b8, 0x00, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x543c00b8, 0x01, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x543c00b8, 0x03, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x543c00b8, 0x04, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__GPIO4_IO8 0x543c00b8, 0x05, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x543c00b8, 0x02, 0x543c0434, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x543c00bc, 0x00, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x543c00bc, 0x01, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x543c00bc, 0x04, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__GPIO4_IO9 0x543c00bc, 0x05, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__LPSPI2_SOUT 0x543c00bc, 0x02, 0x543c0444, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x543c00c0, 0x00, 0x0, 0x00, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD0__LPUART3_RX 0x543c00c0, 0x01, 0x543c0470, 0x01, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x543c00c0, 0x04, 0x0, 0x00, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD0__GPIO4_IO10 0x543c00c0, 0x05, 0x0, 0x00, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x543c00c4, 0x00, 0x0, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__LPUART3_CTS_B 0x543c00c4, 0x01, 0x543c046c, 0x01, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__LPTMR2_ALT1 0x543c00c4, 0x03, 0x543c0448, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x543c00c4, 0x04, 0x0, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__GPIO4_IO11 0x543c00c4, 0x05, 0x0, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x543c00c8, 0x00, 0x0, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD2__LPTMR2_ALT2 0x543c00c8, 0x03, 0x543c044c, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x543c00c8, 0x04, 0x0, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD2__GPIO4_IO12 0x543c00c8, 0x05, 0x0, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x543c00cc, 0x00, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x543c00cc, 0x02, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__LPTMR2_ALT3 0x543c00cc, 0x03, 0x543c0450, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x543c00cc, 0x04, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__GPIO4_IO13 0x543c00cc, 0x05, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET2_MDC__ENET2_MDC 0x543c00d0, 0x00, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__LPUART4_DCB_B 0x543c00d0, 0x01, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__SAI2_RX_SYNC 0x543c00d0, 0x02, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x543c00d0, 0x04, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__GPIO4_IO14 0x543c00d0, 0x05, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x543c00d0, 0x06, 0x543c04bc, 0x01, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDIO__ENET2_MDIO 0x543c00d4, 0x00, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__LPUART4_RIN_B 0x543c00d4, 0x01, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x543c00d4, 0x02, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x543c00d4, 0x04, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__GPIO4_IO15 0x543c00d4, 0x05, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x543c00d4, 0x06, 0x543c0490, 0x01, 0x543c0284 +#define IOMUXC_PAD_ENET2_TD3__SAI2_RX_DATA0 0x543c00d8, 0x02, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x543c00d8, 0x04, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__GPIO4_IO16 0x543c00d8, 0x05, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x543c00d8, 0x06, 0x543c04c0, 0x01, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x543c00d8, 0x00, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x543c00dc, 0x00, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__ENET2_TX_CLK2 0x543c00dc, 0x01, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x543c00dc, 0x04, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__GPIO4_IO17 0x543c00dc, 0x05, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x543c00dc, 0x06, 0x543c04b8, 0x01, 0x543c028c +#define IOMUXC_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x543c00e0, 0x00, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__LPUART4_RTS_B 0x543c00e0, 0x01, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x543c00e0, 0x04, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__GPIO4_IO18 0x543c00e0, 0x05, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x543c00e0, 0x06, 0x543c0494, 0x01, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x543c00e4, 0x00, 0x0, 0x00, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__LPUART4_TX 0x543c00e4, 0x01, 0x543c0480, 0x01, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x543c00e4, 0x04, 0x0, 0x00, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__GPIO4_IO19 0x543c00e4, 0x05, 0x0, 0x00, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x543c00e4, 0x06, 0x543c0498, 0x01, 0x543c0294 +#define IOMUXC_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x543c00e8, 0x00, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x543c00e8, 0x01, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x543c00e8, 0x02, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x543c00e8, 0x04, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__GPIO4_IO20 0x543c00e8, 0x05, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x543c00e8, 0x06, 0x543c049c, 0x01, 0x543c0298 +#define IOMUXC_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x543c00ec, 0x00, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__ENET2_TX_ER 0x543c00ec, 0x01, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__SAI2_TX_BCLK 0x543c00ec, 0x02, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x543c00ec, 0x04, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__GPIO4_IO21 0x543c00ec, 0x05, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x543c00ec, 0x06, 0x543c04a0, 0x01, 0x543c029c +#define IOMUXC_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x543c00f0, 0x00, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x543c00f0, 0x01, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x543c00f0, 0x02, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x543c00f0, 0x04, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__GPIO4_IO22 0x543c00f0, 0x05, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x543c00f0, 0x06, 0x543c04a4, 0x01, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x543c00f4, 0x00, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__ENET2_RX_ER 0x543c00f4, 0x01, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x543c00f4, 0x04, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__GPIO4_IO23 0x543c00f4, 0x05, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x543c00f4, 0x06, 0x543c04a8, 0x01, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x543c00f8, 0x00, 0x0, 0x00, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__LPUART4_RX 0x543c00f8, 0x01, 0x543c047c, 0x01, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x543c00f8, 0x04, 0x0, 0x00, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__GPIO4_IO24 0x543c00f8, 0x05, 0x0, 0x00, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x543c00f8, 0x06, 0x543c04ac, 0x01, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x543c00fc, 0x00, 0x0, 0x00, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__SPDIF_IN 0x543c00fc, 0x01, 0x543c04e4, 0x01, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x543c00fc, 0x04, 0x0, 0x00, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__GPIO4_IO25 0x543c00fc, 0x05, 0x0, 0x00, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x543c00fc, 0x06, 0x543c04b0, 0x01, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x543c0100, 0x00, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__LPUART4_CTS_B 0x543c0100, 0x01, 0x543c0478, 0x01, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__SAI2_MCLK 0x543c0100, 0x02, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__MQS2_RIGHT 0x543c0100, 0x03, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x543c0100, 0x04, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__GPIO4_IO26 0x543c0100, 0x05, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x543c0100, 0x06, 0x543c04b4, 0x01, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x543c0104, 0x00, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__SPDIF_OUT 0x543c0104, 0x01, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__SPDIF_IN 0x543c0104, 0x02, 0x543c04e4, 0x02, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__MQS2_LEFT 0x543c0104, 0x03, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x543c0104, 0x04, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__GPIO4_IO27 0x543c0104, 0x05, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x543c0108, 0x04, 0x543c038c, 0x01, 0x543c02b8 +#define IOMUXC_PAD_SD1_CLK__GPIO3_IO8 0x543c0108, 0x05, 0x0, 0x00, 0x543c02b8 +#define IOMUXC_PAD_SD1_CLK__USDHC1_CLK 0x543c0108, 0x00, 0x0, 0x00, 0x543c02b8 +#define IOMUXC_PAD_SD1_CLK__LPSPI2_SCK 0x543c0108, 0x03, 0x543c043c, 0x01, 0x543c02b8 +#define IOMUXC_PAD_SD1_CMD__USDHC1_CMD 0x543c010c, 0x00, 0x0, 0x00, 0x543c02bc +#define IOMUXC_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x543c010c, 0x04, 0x543c0390, 0x01, 0x543c02bc +#define IOMUXC_PAD_SD1_CMD__GPIO3_IO9 0x543c010c, 0x05, 0x0, 0x00, 0x543c02bc +#define IOMUXC_PAD_SD1_CMD__LPSPI2_SIN 0x543c010c, 0x03, 0x543c0440, 0x01, 0x543c02bc +#define IOMUXC_PAD_SD1_DATA0__USDHC1_DATA0 0x543c0110, 0x00, 0x0, 0x00, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x543c0110, 0x04, 0x543c0394, 0x01, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA0__GPIO3_IO10 0x543c0110, 0x05, 0x0, 0x00, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA0__LPSPI2_PCS0 0x543c0110, 0x03, 0x543c0434, 0x01, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA1__USDHC1_DATA1 0x543c0114, 0x00, 0x0, 0x00, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x543c0114, 0x04, 0x543c0398, 0x01, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__GPIO3_IO11 0x543c0114, 0x05, 0x0, 0x00, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x543c0114, 0x06, 0x0, 0x00, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__LPSPI2_SOUT 0x543c0114, 0x03, 0x543c0444, 0x01, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA2__USDHC1_DATA2 0x543c0118, 0x00, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x543c0118, 0x04, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__GPIO3_IO12 0x543c0118, 0x05, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x543c0118, 0x06, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__LPSPI2_PCS1 0x543c0118, 0x03, 0x543c0438, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA3__USDHC1_DATA3 0x543c011c, 0x00, 0x0, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x543c011c, 0x01, 0x0, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x543c011c, 0x04, 0x543c039c, 0x01, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__GPIO3_IO13 0x543c011c, 0x05, 0x0, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__LPSPI1_PCS1 0x543c011c, 0x03, 0x543c0424, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA4__USDHC1_DATA4 0x543c0120, 0x00, 0x0, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x543c0120, 0x01, 0x0, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x543c0120, 0x04, 0x543c03a0, 0x01, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__GPIO3_IO14 0x543c0120, 0x05, 0x0, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__LPSPI1_PCS0 0x543c0120, 0x03, 0x543c0420, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA5__USDHC1_DATA5 0x543c0124, 0x00, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x543c0124, 0x01, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__USDHC1_RESET_B 0x543c0124, 0x02, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x543c0124, 0x04, 0x543c03a4, 0x01, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__GPIO3_IO15 0x543c0124, 0x05, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__LPSPI1_SIN 0x543c0124, 0x03, 0x543c042c, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA6__USDHC1_DATA6 0x543c0128, 0x00, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x543c0128, 0x01, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__USDHC1_CD_B 0x543c0128, 0x02, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x543c0128, 0x04, 0x543c03a8, 0x01, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__GPIO3_IO16 0x543c0128, 0x05, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__LPSPI1_SCK 0x543c0128, 0x03, 0x543c0428, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA7__USDHC1_DATA7 0x543c012c, 0x00, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x543c012c, 0x01, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__USDHC1_WP 0x543c012c, 0x02, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x543c012c, 0x04, 0x543c03ac, 0x01, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__GPIO3_IO17 0x543c012c, 0x05, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__LPSPI1_SOUT 0x543c012c, 0x03, 0x543c0430, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_STROBE__USDHC1_STROBE 0x543c0130, 0x00, 0x0, 0x00, 0x543c02e0 +#define IOMUXC_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x543c0130, 0x01, 0x0, 0x00, 0x543c02e0 +#define IOMUXC_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x543c0130, 0x04, 0x543c03b0, 0x01, 0x543c02e0 +#define IOMUXC_PAD_SD1_STROBE__GPIO3_IO18 0x543c0130, 0x05, 0x0, 0x00, 0x543c02e0 +#define IOMUXC_PAD_SD2_VSELECT__USDHC2_VSELECT 0x543c0134, 0x00, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__USDHC2_WP 0x543c0134, 0x01, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__LPTMR2_ALT3 0x543c0134, 0x02, 0x543c0450, 0x01, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x543c0134, 0x04, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__GPIO3_IO19 0x543c0134, 0x05, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x543c0134, 0x06, 0x543c0368, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD3_CLK__USDHC3_CLK 0x543c0138, 0x00, 0x543c04e8, 0x01, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x543c0138, 0x01, 0x0, 0x00, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__LPUART1_CTS_B 0x543c0138, 0x02, 0x543c0454, 0x00, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x543c0138, 0x04, 0x543c03b4, 0x01, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__GPIO3_IO20 0x543c0138, 0x05, 0x0, 0x00, 0x543c02e8 +#define IOMUXC_PAD_SD3_CMD__USDHC3_CMD 0x543c013c, 0x00, 0x543c04ec, 0x01, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x543c013c, 0x01, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__LPUART1_RTS_B 0x543c013c, 0x02, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x543c013c, 0x04, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__GPIO3_IO21 0x543c013c, 0x05, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_DATA0__USDHC3_DATA0 0x543c0140, 0x00, 0x543c04f0, 0x01, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x543c0140, 0x01, 0x0, 0x00, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__LPUART2_CTS_B 0x543c0140, 0x02, 0x543c0460, 0x00, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x543c0140, 0x04, 0x543c03b8, 0x01, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__GPIO3_IO22 0x543c0140, 0x05, 0x0, 0x00, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA1__USDHC3_DATA1 0x543c0144, 0x00, 0x543c04f4, 0x01, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x543c0144, 0x01, 0x0, 0x00, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__LPUART2_RTS_B 0x543c0144, 0x02, 0x0, 0x00, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x543c0144, 0x04, 0x543c03bc, 0x01, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__GPIO3_IO23 0x543c0144, 0x05, 0x0, 0x00, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA2__USDHC3_DATA2 0x543c0148, 0x00, 0x543c04f8, 0x01, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__LPI2C4_SDA 0x543c0148, 0x02, 0x543c03fc, 0x01, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x543c0148, 0x01, 0x0, 0x00, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x543c0148, 0x04, 0x543c03c0, 0x01, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__GPIO3_IO24 0x543c0148, 0x05, 0x0, 0x00, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA3__USDHC3_DATA3 0x543c014c, 0x00, 0x543c04fc, 0x01, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x543c014c, 0x01, 0x0, 0x00, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__LPI2C4_SCL 0x543c014c, 0x02, 0x543c03f8, 0x01, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x543c014c, 0x04, 0x543c03c4, 0x01, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__GPIO3_IO25 0x543c014c, 0x05, 0x0, 0x00, 0x543c02fc +#define IOMUXC_PAD_SD2_CD_B__USDHC2_CD_B 0x543c0150, 0x00, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x543c0150, 0x01, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__I3C2_SCL 0x543c0150, 0x02, 0x543c03cc, 0x01, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x543c0150, 0x04, 0x543c036c, 0x01, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__GPIO3_IO0 0x543c0150, 0x05, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__LPI2C1_SCL 0x543c0150, 0x03, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CLK__USDHC2_CLK 0x543c0154, 0x00, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x543c0154, 0x01, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__I2C1_SDA 0x543c0154, 0x03, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__I3C2_SDA 0x543c0154, 0x02, 0x543c03d0, 0x01, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x543c0154, 0x04, 0x543c0370, 0x01, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__GPIO3_IO1 0x543c0154, 0x05, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x543c0154, 0x06, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__LPI2C1_SDA 0x543c0154, 0x03, 0x543c03e4, 0x01, 0x543c0304 +#define IOMUXC_PAD_SD2_CMD__USDHC2_CMD 0x543c0158, 0x00, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x543c0158, 0x01, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__I3C2_PUR 0x543c0158, 0x02, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__I3C2_PUR_B 0x543c0158, 0x03, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x543c0158, 0x04, 0x543c0374, 0x01, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__GPIO3_IO2 0x543c0158, 0x05, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x543c0158, 0x06, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_DATA0__USDHC2_DATA0 0x543c015c, 0x00, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x543c015c, 0x01, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__CAN2_TX 0x543c015c, 0x02, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x543c015c, 0x04, 0x543c0378, 0x01, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__GPIO3_IO3 0x543c015c, 0x05, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__LPUART1_TX 0x543c015c, 0x03, 0x543c045c, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x543c015c, 0x06, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA1__USDHC2_DATA1 0x543c0160, 0x00, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x543c0160, 0x01, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__CAN2_RX 0x543c0160, 0x02, 0x543c0364, 0x03, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x543c0160, 0x04, 0x543c037c, 0x01, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__GPIO3_IO4 0x543c0160, 0x05, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__LPUART1_RX 0x543c0160, 0x03, 0x543c0458, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x543c0160, 0x06, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA2__USDHC2_DATA2 0x543c0164, 0x00, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x543c0164, 0x01, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__MQS2_RIGHT 0x543c0164, 0x02, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x543c0164, 0x04, 0x543c0380, 0x01, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__GPIO3_IO5 0x543c0164, 0x05, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__LPUART2_TX 0x543c0164, 0x03, 0x543c0468, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x543c0164, 0x06, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA3__USDHC2_DATA3 0x543c0168, 0x00, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__LPTMR2_ALT1 0x543c0168, 0x01, 0x543c0448, 0x01, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__MQS2_LEFT 0x543c0168, 0x02, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x543c0168, 0x04, 0x543c0384, 0x01, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__GPIO3_IO6 0x543c0168, 0x05, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__LPUART2_RX 0x543c0168, 0x03, 0x543c0464, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x543c0168, 0x06, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_RESET_B__USDHC2_RESET_B 0x543c016c, 0x00, 0x0, 0x00, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__LPTMR2_ALT2 0x543c016c, 0x01, 0x543c044c, 0x01, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x543c016c, 0x04, 0x543c0388, 0x01, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__GPIO3_IO7 0x543c016c, 0x05, 0x0, 0x00, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x543c016c, 0x06, 0x0, 0x00, 0x543c031c +#define IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL 0x543c0170, 0x00, 0x543c03e0, 0x02, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__I3C1_SCL 0x543c0170, 0x01, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__LPUART1_DCB_B 0x543c0170, 0x02, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__TPM2_CH0 0x543c0170, 0x03, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__GPIO1_IO0 0x543c0170, 0x05, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA 0x543c0174, 0x00, 0x543c03e4, 0x02, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__I3C1_SDA 0x543c0174, 0x01, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__LPUART1_RIN_B 0x543c0174, 0x02, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__TPM2_CH1 0x543c0174, 0x03, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__GPIO1_IO1 0x543c0174, 0x05, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL 0x543c0178, 0x00, 0x543c03e8, 0x01, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__I3C1_PUR 0x543c0178, 0x01, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__LPUART2_DCB_B 0x543c0178, 0x02, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__TPM2_CH2 0x543c0178, 0x03, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__SAI1_RX_SYNC 0x543c0178, 0x04, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__GPIO1_IO3 0x543c0178, 0x05, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__I3C1_PUR_B 0x543c0178, 0x06, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA 0x543c017c, 0x00, 0x543c03ec, 0x01, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__LPUART2_RIN_B 0x543c017c, 0x02, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__TPM2_CH3 0x543c017c, 0x03, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__SAI1_RX_BCLK 0x543c017c, 0x04, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__GPIO1_IO3 0x543c017c, 0x05, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_UART1_RXD__LPUART1_RX 0x543c0180, 0x00, 0x543c0458, 0x01, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__ELE_UART_RX 0x543c0180, 0x01, 0x0, 0x00, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__LPSPI2_SIN 0x543c0180, 0x02, 0x543c0440, 0x02, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__TPM1_CH0 0x543c0180, 0x03, 0x0, 0x00, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__GPIO1_IO4 0x543c0180, 0x05, 0x0, 0x00, 0x543c0330 +#define IOMUXC_PAD_UART1_TXD__LPUART1_TX 0x543c0184, 0x00, 0x543c045c, 0x01, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__ELE_UART_TX 0x543c0184, 0x01, 0x0, 0x00, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__LPSPI2_PCS0 0x543c0184, 0x02, 0x543c0434, 0x02, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__TPM1_CH1 0x543c0184, 0x03, 0x0, 0x00, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__GPIO1_IO5 0x543c0184, 0x05, 0x0, 0x00, 0x543c0334 +#define IOMUXC_PAD_UART2_RXD__LPUART2_RX 0x543c0188, 0x00, 0x543c0464, 0x01, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__LPUART1_CTS_B 0x543c0188, 0x01, 0x543c0454, 0x01, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__LPSPI2_SOUT 0x543c0188, 0x02, 0x543c0444, 0x02, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__TPM1_CH2 0x543c0188, 0x03, 0x0, 0x00, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__SAI1_MCLK 0x543c0188, 0x04, 0x543c04d4, 0x00, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__GPIO1_IO6 0x543c0188, 0x05, 0x0, 0x00, 0x543c0338 +#define IOMUXC_PAD_UART2_TXD__LPUART2_TX 0x543c018c, 0x00, 0x543c0468, 0x01, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__LPUART1_RTS_B 0x543c018c, 0x01, 0x0, 0x00, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__LPSPI2_SCK 0x543c018c, 0x02, 0x543c043c, 0x02, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__TPM1_CH3 0x543c018c, 0x03, 0x0, 0x00, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__GPIO1_IO7 0x543c018c, 0x05, 0x0, 0x00, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__SAI3_TX_SYNC 0x543c018c, 0x07, 0x543c04e0, 0x02, 0x543c033c +#define IOMUXC_PAD_PDM_CLK__PDM_CLK 0x543c0190, 0x00, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__MQS1_LEFT 0x543c0190, 0x01, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__LPTMR1_ALT1 0x543c0190, 0x04, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__GPIO1_IO8 0x543c0190, 0x05, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__CAN1_TX 0x543c0190, 0x06, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x543c0194, 0x00, 0x543c04c4, 0x02, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x543c0194, 0x01, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x543c0194, 0x02, 0x543c0424, 0x01, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x543c0194, 0x03, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x543c0194, 0x04, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x543c0194, 0x05, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX 0x543c0194, 0x06, 0x543c0360, 0x01, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x543c0198, 0x00, 0x543c04c8, 0x02, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x543c0198, 0x02, 0x543c0438, 0x01, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x543c0198, 0x03, 0x0, 0x00, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x543c0198, 0x04, 0x0, 0x00, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x543c0198, 0x05, 0x0, 0x00, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x543c0198, 0x06, 0x543c0368, 0x01, 0x543c0348 +#define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x543c019c, 0x00, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x543c019c, 0x01, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__LPSPI1_PCS0 0x543c019c, 0x02, 0x543c0420, 0x01, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__LPUART2_DTR_B 0x543c019c, 0x03, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__MQS1_LEFT 0x543c019c, 0x04, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__GPIO1_IO11 0x543c019c, 0x05, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXC__SAI1_TX_BCLK 0x543c01a0, 0x00, 0x0, 0x00, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__LPUART2_CTS_B 0x543c01a0, 0x01, 0x543c0460, 0x01, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__LPSPI1_SIN 0x543c01a0, 0x02, 0x543c042c, 0x01, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__LPUART1_DSR_B 0x543c01a0, 0x03, 0x0, 0x00, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__CAN1_RX 0x543c01a0, 0x04, 0x543c0360, 0x02, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__GPIO1_IO12 0x543c01a0, 0x05, 0x0, 0x00, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x543c01a4, 0x00, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__LPUART2_RTS_B 0x543c01a4, 0x01, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__LPSPI1_SCK 0x543c01a4, 0x02, 0x543c0428, 0x01, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__LPUART1_DTR_B 0x543c01a4, 0x03, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__CAN1_TX 0x543c01a4, 0x04, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__GPIO1_IO13 0x543c01a4, 0x05, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__SAI1_MCLK 0x543c01a4, 0x06, 0x543c04d4, 0x01, 0x543c0354 +#define IOMUXC_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x543c01a8, 0x00, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__SAI1_MCLK 0x543c01a8, 0x01, 0x543c04d4, 0x02, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__LPSPI1_SOUT 0x543c01a8, 0x02, 0x543c0430, 0x01, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__LPUART2_DSR_B 0x543c01a8, 0x03, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__MQS1_RIGHT 0x543c01a8, 0x04, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__GPIO1_IO14 0x543c01a8, 0x05, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x543c01ac, 0x00, 0x0, 0x00, 0x543c035c +#define IOMUXC_PAD_WDOG_ANY__GPIO1_IO15 0x543c01ac, 0x05, 0x0, 0x00, 0x543c035c +/*@}*/ + +#define IOMUXC_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_MUX_MODE_SHIFT)) & IOMUXC_PAD_MUX_MODE_MASK) +#define IOMUXC_PAD_SION_MASK (0x10U) +#define IOMUXC_PAD_SION_SHIFT (4U) +#define IOMUXC_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_SION_SHIFT)) & IOMUXC_PAD_SION_MASK) + +#define IOMUXC_PAD_DSE_MASK (0x7EU) +#define IOMUXC_PAD_DSE_SHIFT (1U) +#define IOMUXC_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_DSE_SHIFT)) & IOMUXC_PAD_DSE_MASK) +#define IOMUXC_PAD_FSEL1_MASK (0x180U) +#define IOMUXC_PAD_FSEL1_SHIFT (7U) +#define IOMUXC_PAD_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_FSEL1_SHIFT)) & IOMUXC_PAD_FSEL1_MASK) +#define IOMUXC_PAD_PU_MASK (0x200U) +#define IOMUXC_PAD_PU_SHIFT (9U) +#define IOMUXC_PAD_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PU_SHIFT)) & IOMUXC_PAD_PU_MASK) +#define IOMUXC_PAD_PD_MASK (0x400U) +#define IOMUXC_PAD_PD_SHIFT (10U) +#define IOMUXC_PAD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PD_SHIFT)) & IOMUXC_PAD_PD_MASK) +#define IOMUXC_PAD_OD_MASK (0x800U) +#define IOMUXC_PAD_OD_SHIFT (11U) +#define IOMUXC_PAD_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_OD_SHIFT)) & IOMUXC_PAD_OD_MASK) +#define IOMUXC_PAD_HYS_MASK (0x1000U) +#define IOMUXC_PAD_HYS_SHIFT (11U) +#define IOMUXC_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_HYS_SHIFT)) & IOMUXC_PAD_HYS_MASK) +#define IOMUXC_PAD_APC_MASK (0xFF000000U) +#define IOMUXC_PAD_APC_SHIFT (24U) +#define IOMUXC_PAD_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_APC_SHIFT)) & IOMUXC_PAD_APC_MASK) + +#define SECURE_ADDR_MASK (0x10000000U) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +#define IOMUXC_REG_ADDR(x) (x) +#else +#define IOMUXC_REG_ADDR(x) ((x) & (~SECURE_ADDR_MASK)) +#endif + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * @param muxRegister The pin mux register + * @param muxMode The pin mux mode + * @param inputRegister The select input register + * @param inputDaisy The input daisy + * @param configRegister The config register + * @param inputOn The software input on + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + if (muxRegister != 0U) + { + *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(muxRegister)) = + IOMUXC_PAD_MUX_MODE(muxMode) | IOMUXC_PAD_SION(inputOnfield); + } + + if (inputRegister != 0U) + { + *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(inputRegister)) = inputDaisy; + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * @param muxRegister The pin mux register + * @param muxMode The pin mux mode + * @param inputRegister The select input register + * @param inputDaisy The input daisy + * @param configRegister The config register + * @param configValue The pin config value + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister != 0U) + { + *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(configRegister)) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/fsl_device_registers.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/fsl_device_registers.h new file mode 100644 index 00000000000..92a7a677bbb --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/fsl_device_registers.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMX9131CVVXJ) || defined(CPU_MIMX9131DVVXJ)) + +#define MIMX9131_SERIES + +/* CMSIS-style register definitions */ +#include "MIMX9131.h" +/* CPU specific feature definitions */ +#include "MIMX9131_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.c b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.c new file mode 100644 index 00000000000..618f49a25ec --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.c @@ -0,0 +1,82 @@ +/* +** ################################################################### +** Processors: MIMX9131CVVXJ +** MIMX9131DVVXJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** +** Reference manual: IMX91RM Rev.1 +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMX9131 + * @version 1.0 + * @date 2024-11-15 + * @brief Device specific configuration file for MIMX9131 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + __ASM volatile("mov x0, #(3 << 20) \n\t" + "msr cpacr_el1, x0"); +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SystemInitHook(); + + ARM_TIMER_GetFreq(&SystemCoreClock); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.h new file mode 100644 index 00000000000..c825d695612 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.h @@ -0,0 +1,101 @@ +/* +** ################################################################### +** Processors: MIMX9131CVVXJ +** MIMX9131DVVXJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** +** Reference manual: IMX91RM Rev.1 +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMX9131 + * @version 1.0 + * @date 2024-11-15 + * @brief Device specific configuration file for MIMX9131 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMX9131_H_ +#define _SYSTEM_MIMX9131_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Define clock source values */ +#define DEFAULT_SYSTEM_CLOCK 24000000U /* Default System clock value */ + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMX9131_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/devices/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/SConscript new file mode 100644 index 00000000000..3f8f39acae7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.c new file mode 100644 index 00000000000..c0d2d9d670b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.c @@ -0,0 +1,58 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache.h" +#include "cache_armv8a.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_armv8a" +#endif + +/*! + * brief Invalidates all instruction caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void ICACHE_InvalidateByRange(uintptr_t address, size_t size_byte) +{ + icache_invalidate_range(address, size_byte); +} + +/*! + * brief Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void DCACHE_InvalidateByRange(uintptr_t address, size_t size_byte) +{ + dcache_invalidate_range(address, size_byte); +} + +/*! + * brief Cleans all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned. + */ +void DCACHE_CleanByRange(uintptr_t address, size_t size_byte) +{ + dcache_clean_range(address, size_byte); +} + +/*! + * brief Cleans and Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned and invalidated. + */ +void DCACHE_CleanInvalidateByRange(uintptr_t address, size_t size_byte) +{ + dcache_clean_invalidate_range(address, size_byte); +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.h new file mode 100644 index 00000000000..0ecab0ba68b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.h @@ -0,0 +1,83 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_armv8a + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 1.0.0. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @name Unified Cache Control for all caches + * Mainly used for many drivers for easy cache operation. + *@{ + */ + +/*! + * brief Invalidates all instruction caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void ICACHE_InvalidateByRange(uintptr_t address, size_t size_byte); + +/*! + * brief Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void DCACHE_InvalidateByRange(uintptr_t address, size_t size_byte); + +/*! + * brief Cleans all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned. + */ +void DCACHE_CleanByRange(uintptr_t address, size_t size_byte); + +/*! + * brief Cleans and Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned and invalidated. + */ +void DCACHE_CleanInvalidateByRange(uintptr_t address, size_t size_byte); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/SConscript new file mode 100644 index 00000000000..62321b37009 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('fsl_common.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.c new file mode 100644 index 00000000000..d0dcc4b69fa --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + if ((alignbytes == 0U) || (alignbytes >= SIZE_MAX)) + { + return NULL; + } + + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.h new file mode 100644 index 00000000000..31a594bdc02 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022,2024-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) + +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) + +/*! @name Driver version */ +/*! @{ */ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ + +/*! @name Debug console type definition. */ +/*! @{ */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ +/*! @} */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */ + kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */ + kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */ + kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */ + kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ + kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ + kStatusGroup_GLIKEY = 168, /*!< Group number for GLIKEY status codes. */ + kStatusGroup_AON_POWER = 169, /*!< Group number for AON_POWER status codes. */ + kStatusGroup_AON_COMMON = 170, /*!< Group number for AON_COMMON status codes. */ + kStatusGroup_ENDAT3 = 171, /*!< Group number for ENDAT3 status codes. */ + kStatusGroup_HIPERFACE = 172, /*!< Group number for HIPERFACE status codes. */ + kStatusGroup_NPX = 173, /*!< Group number for NPX status codes. */ + kStatusGroup_ELA_CSEC = 174, /*!< Group number for ELA_CSEC status codes. */ + kStatusGroup_FLEXIO_T_FORMAT= 175, /*!< Group number for T-format status codes. */ + kStatusGroup_FLEXIO_A_FORMAT= 176, /*!< Group number for A-format status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +#ifdef __ZEPHYR__ +#include +#else +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +/*! Computes the minimum of \a a and \a b. */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +/*! Computes the maximum of \a a and \a b. */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/*! @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif +#endif /* __ZEPHYR__ */ + +/*! @name UINT16_MAX/UINT32_MAX value */ +/*! @{ */ +#if !defined(UINT16_MAX) +/*! Max value of uint16_t type. */ +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +/*! Max value of uint32_t type. */ +#define UINT32_MAX ((uint32_t)-1) +#endif +/*! @} */ + +/*! Macro to get upper 32 bits of a 64-bit value */ +#if !defined(UINT64_H) +#define UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL)) +#endif + +/*! Macro to get lower 32 bits of a 64-bit value */ +#if !defined(UINT64_L) +#define UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL)) +#endif + +/*! + * @def SUPPRESS_FALL_THROUGH_WARNING() + * + * For switch case code block, if case section ends without "break;" statement, there wil be + * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + * case section which misses "break;"statement. + */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); +#endif + +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XTENSA__) +#include "fsl_common_dsp.h" +#elif defined(__riscv) +#include "fsl_common_riscv.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* FSL_COMMON_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.c new file mode 100644 index 00000000000..28e3dc89d24 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.c @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021,2023,2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + + if (((int32_t)irq + 16) < 0) + { + return MSDK_INVALID_IRQ_HANDLER; + } + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/* Use WDT. */ +void MSDK_EnableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +uint32_t MSDK_GetCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#endif /* defined(DWT) */ + +#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT)) +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV X0, %0" : : "r"(count)); + __ASM volatile( + "loop%=: \n" + " SUB X0, X0, #1 \n" + " CMP X0, #0 \n" + + " BNE loop%= \n" + : + : + : "r0"); +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop%=: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop%= \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + MSDK_EnableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += MSDK_GetCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < MSDK_GetCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > MSDK_GetCpuCycleCount()) + { + } +#else +#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55)) + /* + * Cortex-A53/A55 execution throughput: + * - SUB/CMP: 2 instructions per cycle + * - BNE: 1 instruction per cycle + * So, each loop takes 2 CPU cycles. + */ + count = count / 2U; +#elif (__CORTEX_M == 7) + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} + +#if defined(FSL_FEATURE_MEASURE_CRITICAL_SECTION) && FSL_FEATURE_MEASURE_CRITICAL_SECTION +/* Use shall define their own IDs, FSL_FEATURE_CRITICAL_SECTION_MAX_ID and FSL_FEATURE_CRITICAL_SECTION_INVALID_ID + for the critical sections if want to use the critical section measurement. + */ +#ifndef FSL_FEATURE_CRITICAL_SECTION_MAX_ID +#define FSL_FEATURE_CRITICAL_SECTION_MAX_ID 0xFFU +#endif + +#ifndef FSL_FEATURE_CRITICAL_SECTION_INVALID_ID +#define FSL_FEATURE_CRITICAL_SECTION_INVALID_ID 0U +#endif + +typedef struct +{ + uint32_t id; /*!< The id of the critical section, defined by user. */ + uint32_t startTime; /*!< The timestamp for the start of the critical section. */ + uint32_t dur_max[FSL_FEATURE_CRITICAL_SECTION_MAX_ID]; /*!< The maximum duration of the section's previous executions. */ + uint32_t execution_times[FSL_FEATURE_CRITICAL_SECTION_MAX_ID]; /*!< How many times the section is executed. */ + getTimestamp_t getTimestamp; /*!< Function to get the current time stamp. */ +} critical_section_measurement_t; + +static critical_section_measurement_t s_critical_section_measurement_context; + +/*! + * brief Initialize the context of the critical section measurement and assign + * the function to get the current timestamp. + * + * param func The function to get the current timestamp. + */ +void InitCriticalSectionMeasurementContext(getTimestamp_t func) +{ + assert(func != NULL); + + (void)memset(&s_critical_section_measurement_context, 0, sizeof(critical_section_measurement_t)); + + s_critical_section_measurement_context.getTimestamp = func; +} + +/*! + * brief Disable the global IRQ with critical section ID + * + * Extended function of DisableGlobalIRQ. Apart from the standard operation, also check + * the id of the protected critical section and mark the begining for timer. + * User is required to provided the primask register for the EnableGlobalIRQEx. + * + * param id The id for critical section. + * return Current primask value. + */ +uint32_t DisableGlobalIRQEx(uint32_t id) +{ + uint32_t primask = DisableGlobalIRQ(); + if (primask != 0U) + { +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Check for the critical section id. */ + assert(id != FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); + assert(id < FSL_FEATURE_CRITICAL_SECTION_MAX_ID); + assert(s_critical_section_measurement_context.id == FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); +#endif + if (s_critical_section_measurement_context.getTimestamp != NULL) + { + s_critical_section_measurement_context.id = id; + s_critical_section_measurement_context.startTime = s_critical_section_measurement_context.getTimestamp(); + } + } + return primask; +} + +/*! + * brief Enable the global IRQ and calculate the execution time of critical section + * + * Extended function of EnableGlobalIRQ. Apart from the standard operation, also + * marks the exit of the critical section and calculate the execution time for the section. + * User is required to use the DisableGlobalIRQEx and EnableGlobalIRQEx in pair. + * + * param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQEx(). + */ +void EnableGlobalIRQEx(uint32_t primask) +{ + if (primask != 0U) + { +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Check for the critical section id. */ + assert(s_critical_section_measurement_context.id != FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); + assert(s_critical_section_measurement_context.id < FSL_FEATURE_CRITICAL_SECTION_MAX_ID); +#endif + if (s_critical_section_measurement_context.getTimestamp != NULL) + { + /* Calculate the critical section duration. */ + uint32_t dur = s_critical_section_measurement_context.getTimestamp() - s_critical_section_measurement_context.startTime; + if (dur > s_critical_section_measurement_context.dur_max[s_critical_section_measurement_context.id]) + { + s_critical_section_measurement_context.dur_max[s_critical_section_measurement_context.id] = dur; + } + s_critical_section_measurement_context.execution_times[s_critical_section_measurement_context.id]++; + } +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Exit the critical section, set the id to invalid. In this case when entering critical + section again DisableGlobalIRQEx has to be called first to avoid assertion. */ + s_critical_section_measurement_context.id = FSL_FEATURE_CRITICAL_SECTION_INVALID_ID; +#endif + } + EnableGlobalIRQ(primask); +} +#endif /* FSL_FEATURE_MEASURE_CRITICAL_SECTION */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.h new file mode 100644 index 00000000000..55544c17bab --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.h @@ -0,0 +1,1184 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/*! + * @def SDK_ATOMIC_LOCAL_ADD(addr, val) + * Add value \a val from the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SUB(addr, val) + * Subtract value \a val to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SET(addr, bits) + * Set the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits) + * Clear the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) + * Toggle the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) + * For the variable at address \a address, clear the bits specifiled by \a clearBits + * and set the bits specifiled by \a setBits. + + * @def SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) + * For the variable at address \a address, check whether the value equal to \a expected. If value same as \a expected + * then update \a newValue to address and return \b true , else return \b false . + * + * @def SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) + * For the variable at address \a address, set as \a newValue value and return old value. + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) + +#define SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalCompareAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(expected), (uint8_t)(newValue)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalCompareAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(expected), (uint16_t)(newValue)) : \ + _SDK_AtomicLocalCompareAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(expected), (uint32_t)(newValue)))) + +#define SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalTestAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(newValue)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalTestAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(newValue)) : \ + _SDK_AtomicLocalTestAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(newValue)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) -= (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) \ + _SDK_AtomicLocalCompareAndSet((uint32_t *)addr, (uint32_t)expected, (uint32_t)newValue) + +#define SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) \ + _SDK_AtomicTestAndSet((uint32_t *)addr, (uint32_t)newValue) + +#endif +/*! @} */ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/*! @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/*! @} */ + +/*! @name Alignment variable definition macros */ +/*! @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! + * @name Non-cacheable region definition macros + * + * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable + * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + * + * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + * + * @{ + */ + +/*! + * @def AT_NONCACHEABLE_SECTION(var) + * Define a variable \a var, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) + * Define a variable \a var, and place it in non-cacheable section, the start address + * of the variable is aligned to \a alignbytes. + * + * @def AT_NONCACHEABLE_SECTION_INIT(var) + * Define a variable \a var with initial value, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) + * Define a variable \a var with initial value, and place it in non-cacheable section, + * the start address of the variable is aligned to \a alignbytes. + */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#if defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +#define MCUX_CS "//" +#else +#define MCUX_CS "@" +#endif + +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/*! @} */ + +/*! + * @name Cache line region definition macros + * + * For initialized non-zero cache line variables, please use "AT_CACHE_LINE_SECTION_INIT(var) ={xx};" + * For zero-inited cache line variables, please use "AT_CACHE_LINE_SECTION(var);" + * + * @note This section is applicable to cached memory only, say external sdram, cached ocram, etc. + * Please avoid to use this section for none-cached memory, say TCM. + * So only those targets, which utilize the cached memory, say flexspi_nor_sdram_debug, support + * this kind of section. + * @{ + */ + +/*! + * @def AT_CACHE_LINE_SECTION(var) + * Define a variable \a var, which is cache line size aligned and be placed in CacheLineData section. + * + * @def AT_CACHE_LINE_SECTION_INIT(var) + * Define a variable \a var with initial value, which is cache line size aligned and be placed in CacheLineData.init section. + */ + +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define CACHE_LINE_DATA SDK_L1DCACHE_ALIGN +#elif defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define CACHE_LINE_DATA SDK_L2CACHE_ALIGN +#endif + +#if (defined(__ICCARM__)) +#define AT_CACHE_LINE_SECTION(var) CACHE_LINE_DATA(var) @"CacheLineData" +#define AT_CACHE_LINE_SECTION_INIT(var) CACHE_LINE_DATA(var) @"CacheLineData.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if (defined(__CC_ARM)) +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData"), zero_init)) CACHE_LINE_DATA(var) +#else +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData"))) CACHE_LINE_DATA(var) +#endif +#define AT_CACHE_LINE_SECTION_INIT(var) __attribute__((section("CacheLineData.init"))) CACHE_LINE_DATA(var) + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData,\"aw\",%nobits @"))) CACHE_LINE_DATA(var) +#define AT_CACHE_LINE_SECTION_INIT(var) __attribute__((section("CacheLineData.init"))) CACHE_LINE_DATA(var) + +#else +#error Toolchain not supported. +#endif + +/*! @} */ + +/*! + * @name Time sensitive region + * @{ + */ + +/*! + * @def AT_QUICKACCESS_SECTION_CODE(func) + * Place function in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA(var) + * Place data in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) + * Place data in a section which can be accessed quickly by core, and the variable + * address is set to align with \a alignbytes. + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +/*! + * @name Ram Function + * @{ + * + * @def RAMFUNCTION_SECTION_CODE(func) + * Place function in ram. + */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +/*! + * @def MSDK_REG_SECURE_ADDR(x) + * Convert the register address to the one used in secure mode. + * + * @def MSDK_REG_NONSECURE_ADDR(x) + * Convert the register address to the one used in non-secure mode. + */ + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +#define MSDK_REG_SECURE_ADDR(x) ((uintptr_t)(x) | (0x1UL << 28)) +#define MSDK_REG_NONSECURE_ADDR(x) ((uintptr_t)(x) & ~(0x1UL << 28)) +#else +#define MSDK_REG_SECURE_ADDR(x) (x) +#define MSDK_REG_NONSECURE_ADDR(x) (x) +#endif + +/*! + * @brief Invalid IRQ handler address. + */ +#define MSDK_INVALID_IRQ_HANDLER UINT32_MAX + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) +void IRQSTEER_EnableInterrupt(int32_t instIdx, IRQn_Type irq); +void IRQSTEER_DisableInterrupt(int32_t instIdx, IRQn_Type irq); +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) + int32_t irqsteerInstIdx = (int32_t)((interrupt + 1 - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) / FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM); + + IRQSTEER_EnableInterrupt(irqsteerInstIdx, interrupt); +#else + status = kStatus_Fail; +#endif + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) + int32_t irqsteerInstIdx = (int32_t)((interrupt - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) / FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM); + + IRQSTEER_DisableInterrupt(irqsteerInstIdx, interrupt); +#else + status = kStatus_Fail; +#endif + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to Enable. + * @param priNum Priority number set to interrupt controller register. + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); + GIC_EnableIRQ(interrupt); +#else + NVIC_SetPriority(interrupt, priNum); + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Set the IRQ priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); +#else + NVIC_SetPriority(interrupt, priNum); +#endif + } + + return status; +} + +/*! + * @brief Clear the pending IRQ flag. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The flag which IRQ to clear. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_ClearPendingIRQ(interrupt); +#else + NVIC_ClearPendingIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t mask; + +#if defined(CPSR_I_Msk) + mask = __get_CPSR() & CPSR_I_Msk; +#elif defined(DAIF_I_BIT) + mask = __get_DAIF() & DAIF_I_BIT; +#else + mask = __get_PRIMASK(); +#endif + __disable_irq(); + + return mask; +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#elif defined(DAIF_I_BIT) + if (0UL == primask) + { + __enable_irq(); + } +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address, if the input @p irq is invalid, then + * return value is @ref MSDK_INVALID_IRQ_HANDLER. + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/*! + * @brief Enable the counter to get CPU cycles. + */ +void MSDK_EnableCpuCycleCounter(void); + +/*! + * @brief Get the current CPU cycle count. + * + * @return Current CPU cycle count. + */ +uint32_t MSDK_GetCpuCycleCount(void); +#endif + +#if defined(FSL_FEATURE_MEASURE_CRITICAL_SECTION) && (FSL_FEATURE_MEASURE_CRITICAL_SECTION != 0) +typedef uint32_t (*getTimestamp_t)(void); /*!< Function to get the current time stamp. */ + +/*! + * @rief Initialize the context of the critical section measurement and assign + * the function to get the current timestamp. + * + * @param getTimestamp The function to get the current timestamp. + */ +void InitCriticalSectionMeasurementContext(getTimestamp_t func); + +/*! + * @brief Disable the global IRQ with critical section ID + * + * Extended function of DisableGlobalIRQ. Apart from the standard operation, also check + * the id of the protected critical section and mark the begining for timer. + * User is required to provided the primask register for the EnableGlobalIRQEx. + * + * @param id The id for critical section. + * @return Current primask value. + */ +uint32_t DisableGlobalIRQEx(uint32_t id); + +/*! + * @brief Enable the global IRQ and calculate the execution time of critical section + * + * Extended function of EnableGlobalIRQ. Apart from the standard operation, also + * marks the exit of the critical section and calculate the execution time for the section. + * User is required to use the DisableGlobalIRQEx and EnableGlobalIRQEx in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQEx(). + */ +void EnableGlobalIRQEx(uint32_t primask); +#endif + + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ +static inline bool _SDK_AtomicLocalCompareAndSet1Byte(volatile uint8_t *addr, uint8_t expected, uint8_t newValue) +{ + uint8_t s_actual; + + do + { + s_actual = __LDREXB(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXB((newValue), (addr))); + + return true; +} + +static inline bool _SDK_AtomicLocalCompareAndSet2Byte(volatile uint16_t *addr, uint16_t expected, uint16_t newValue) +{ + uint16_t s_actual; + + do + { + s_actual = __LDREXH(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXH((newValue), (addr))); + + return true; +} + +static inline bool _SDK_AtomicLocalCompareAndSet4Byte(volatile uint32_t *addr, uint32_t expected, uint32_t newValue) +{ + uint32_t s_actual; + + do + { + s_actual = __LDREXW(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXW((newValue), (addr))); + + return true; +} + +static inline uint8_t _SDK_AtomicLocalTestAndSet1Byte(volatile uint8_t *addr, uint8_t newValue) +{ + uint8_t s_old; + + do + { + s_old = __LDREXB(addr); + } while (__STREXB((newValue), (addr))); + + return s_old; +} + +static inline uint16_t _SDK_AtomicLocalTestAndSet2Byte(volatile uint16_t *addr, uint16_t newValue) +{ + uint16_t s_old; + + do + { + s_old = __LDREXH(addr); + } while (__STREXH((newValue), (addr))); + + return s_old; +} + +static inline uint32_t _SDK_AtomicLocalTestAndSet4Byte(volatile uint32_t *addr, uint32_t newValue) +{ + uint32_t s_old; + + do + { + s_old = __LDREXW(addr); + } while (__STREXW((newValue), (addr))); + + return s_old; +} + +#else +static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue) +{ + uint32_t s_atomicOldInt; + uint32_t s_actual; + + s_atomicOldInt = DisableGlobalIRQ(); + + s_actual = *addr; + if (s_actual == expected) + { + *addr = newValue; + EnableGlobalIRQ(s_atomicOldInt); + return true; + } + else + { + EnableGlobalIRQ(s_atomicOldInt); + return false; + } +} + +static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue) +{ + uint32_t s_atomicOldInt = DisableGlobalIRQ(); + + uint32_t oldValue = (uint32_t)(*addr); + *addr = newValue; + + EnableGlobalIRQ(s_atomicOldInt); + return oldValue; +} + +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.c new file mode 100644 index 00000000000..19919494737 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.c @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_dsc" +#endif + +#define COMMON_INTC_TYPE_REG_INDEX(x) (((uint8_t)(x)) >> 3U) +#define COMMON_INTC_TYPE_BIT_INDEX(x) ((((uint8_t)(x)) & 0x7U) << 1U) + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Interrupt priority table. */ +static uint16_t s_intPrioTable[(NUMBER_OF_INT_IRQ - 1U) / 8U + 1U] = {0U}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t EnableIRQWithPriority(IRQn_Type irq, uint8_t priNum) +{ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t prioMask; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + prioMask = ((uint16_t)3U << bitIndex); + /* Valid priority number is 0-3 */ + priNum = priNum & 0x03U; + + if (0U == priNum) + { + priNum = SDK_DSC_DEFAULT_INT_PRIO; + } + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + /* Save the priority in s_intPrioTable */ + reg = s_intPrioTable[regIndex]; + reg = (reg & ~prioMask) | (priNum << bitIndex); + + s_intPrioTable[regIndex] = reg; + + /* Set new priority in interrupt controller register. */ + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + reg = (reg & ~prioMask) | (priNum << bitIndex); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +status_t DisableIRQ(IRQn_Type irq) +{ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + reg = reg & (~((uint16_t)3U << bitIndex)); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +status_t EnableIRQ(IRQn_Type irq) +{ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t prioMask; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + prioMask = ((uint16_t)3U << bitIndex); + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + /* If priority in s_intPrioTable is 0, use SDK_DSC_DEFAULT_INT_PRIO. */ + if (0U == (s_intPrioTable[regIndex] & prioMask)) + { + s_intPrioTable[regIndex] = (s_intPrioTable[regIndex] & ~prioMask) | (SDK_DSC_DEFAULT_INT_PRIO << bitIndex); + } + + /* Set the interrupt priority with the priority in s_intPrioTable. */ + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + reg = (reg & ~prioMask) | (s_intPrioTable[regIndex] & prioMask); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +/* + * brief Set the IRQ priority. + * + * note The parameter priNum is range in 1~3, and its value is **NOT** + * directly map to interrupt priority. + * + * - Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3 + * - Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2 + * + * User should check chip's RM to get its corresponding interrupt priority + */ +status_t IRQ_SetPriority(IRQn_Type irq, uint8_t priNum) +{ + /* + * If the interrupt is already enabled, the new priority will be set + * to the register. If interrupt is not enabled, the new priority is + * only saved in priority table s_intPrioTable, when interrupt enabled, + * the priority value is set to register. + */ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t prioMask; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + prioMask = ((uint16_t)3U << bitIndex); + + /* Valid priority number is 0-3 */ + priNum = priNum & 0x03U; + + if (0U == priNum) + { + priNum = SDK_DSC_DEFAULT_INT_PRIO; + } + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + /* Save the priority in s_intPrioTable */ + reg = s_intPrioTable[regIndex]; + reg = (reg & ~prioMask) | (priNum << bitIndex); + + s_intPrioTable[regIndex] = reg; + + /* + * If interrupt already enabled, set new priority + * in interrupt controller register. + */ + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + + if (0U != (reg & prioMask)) + { + reg = (reg & (~prioMask)) | (priNum << bitIndex); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + } + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +/*! + * brief Delay core cycles. + * Please note that, this API uses software loop for delay, the actual delayed + * time depends on core clock frequency, where the function is located (ram or flash), + * flash clock, possible interrupt. + * + * param u32Num Number of core clock cycle which needs to be delayed. + */ +void SDK_DelayCoreCycles(uint32_t u32Num) +{ + /* + * if(u32Num < 22) + * { + * ActualDelayCycle = 21; + * } + * else + * { + * ActualDelayCycle = 35 + ((u32Num-22)/8) * 8 = 13 + u32Num - ((u32Num-22)%8) + * } + */ + + /* JSR - 4 cycles + * RTS - 8 cycles + */ + + asm { + cmp.l #21,A // 2 cycle + bls ret // 5 cycles when jump occurs. 3 cycles when jump doesn't occur + nop // 1 cycle + nop // 1 cycle + sub.l #22, A // 2 cycle + asrr.l #3, A // 2 cycle + bra test // 5 cycle + + loop: + dec.l A // 1 cycle + + test: + tst.l A // 1 cycle + nop // 1 cycle + bne loop // 5 cycles when jump occurs. 3 cycles when jump doesn't occur + + ret: + nop // 1 cycle + nop // 1 cycle + } +} + +/*! + * brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * param delayTime_us Delay time in unit of microsecond. + * param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + while(delayTime_us > 0) + { + uint32_t us, count; + + /* USEC_TO_COUNT(fixed-point) supports maximum 4294us, use 4000UL here */ + if(delayTime_us > 4000UL) + { + us = 4000UL; + } + else + { + us = delayTime_us; + } + delayTime_us -= us; + + count = USEC_TO_COUNT(us, coreClock_Hz); + SDK_DelayCoreCycles(count); + } +} + +/*! + * brief Covert us to count with fixed-point calculation. + * + * note u32Us must not be greater than 4294 + * + * param u32Us Time in us + * param u32Hz Clock frequency in Hz + * return The count value + */ +uint32_t SDK_CovertUsToCount(uint32_t u32Us, uint32_t u32Hz) +{ + /* + * Hz * us / 1000000UL = (Hz / 1000000UL) * us + * = (i + r/1000000UL) * us + * = i * us + r * us / 1000000UL + */ + + assert(u32Us <= 4294UL); + assert(u32Hz != 0U); + + uint32_t i, r; + + i = u32Hz / 1000000UL; + r = u32Hz - i * 1000000UL; + + return i * u32Us + (r * u32Us / 1000000UL); +} + +/*! + * brief Covert count to us with fixed-point calculation. + * + * note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * param u32Count Count value + * param u32Hz Clock frequency in Hz + * return The us value + */ +uint32_t SDK_CovertCountToUs(uint32_t u32Count, uint32_t u32Hz) +{ + /* + * count * 1000000UL / hz + * + * i1 = count / hz + * r1 = count - i1 * hz + * sum = i1 * 1000000UL + * + * count = r1 * 10UL + * i2 = count / hz + * r2 = count - i2 * hz + * sum += i2 * 100000UL + * + * count = r2 * 10UL + * i3 = count / hz + * r3 = count - i3 * hz + * sum += i3 * 10000UL; + * + * count = r3 * 10UL + * i4 = count / hz + * r4 = count - i4 * hz + * sum += i4 * 1000UL; + * + * count = r4 * 10UL + * i5 = count / hz + * r5 = count - i5 * hz + * sum += i5 * 100UL; + * + * count = r5 * 10UL + * i6 = count / hz + * r6 = count - i6 * hz + * sum += i6 * 10UL; + * + * count = r6 * 10UL + * i7 = count / hz + * r7 = count - i7 * hz + * sum += i7 * 1UL; + * + */ + assert(u32Hz != 0U); + assert(u32Hz <= 429496729UL); + + uint32_t j; + + uint32_t i, r, sum = 0UL, c = 1UL; + + for (j = 0U; j < 7U; j++) + { + i = u32Count / u32Hz; + r = u32Count - i * u32Hz; + sum += i * 1000000UL / c; + + c *= 10UL; + u32Count = r * 10UL; + } + + return sum; +} + +/*! + * brief Covert ms to count with fixed-point calculation. + * + * note u32Ms must not be greater than 42949UL @ u32Hz = 100M + * + * param u32Ms Time in us + * param u32Hz Clock frequency in Hz + * return The count value + */ +uint32_t SDK_CovertMsToCount(uint32_t u32Ms, uint32_t u32Hz) +{ + /* + * Hz * ms / 1000UL = (Hz / 1000UL) * ms + * = (i + r/1000UL) * ms + * = i * ms + r * ms / 1000UL + */ + + assert(u32Ms <= 42949UL); + assert(u32Hz != 0U); + + uint32_t i, r; + + i = u32Hz / 1000UL; + r = u32Hz - i * 1000UL; + + return i * u32Ms + (r * u32Ms / 1000UL); +} + +/*! + * brief Covert count to ms with fixed-point calculation. + * + * note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * param u32Count Count value + * param u32Hz Clock frequency in Hz + * return The us value + */ +uint32_t SDK_CovertCountToMs(uint32_t u32Count, uint32_t u32Hz) +{ + /* + * count * 1000UL / hz + * + * i1 = count / hz + * r1 = count - i1 * hz * + * sum = i1 * 1000UL + * + * count = r1 * 10UL + * i2 = count / hz + * r2 = count - i2 * hz + * sum += i2 * 100UL + * + * count = r2 * 10UL + * i3 = count / hz + * r3 = count - i3 * hz + * sum += i3 * 10L; + * + * count = r3 * 10UL + * i4 = count / hz + * r4 = count - i4 * hz + * sum += i4 * 1UL; + * + */ + assert(u32Hz != 0U); + assert(u32Hz <= 429496729UL); + + uint32_t j; + + uint32_t i, r, sum = 0UL, c = 1UL; + + for (j = 0U; j < 4U; j++) + { + i = u32Count / u32Hz; + r = u32Count - i * u32Hz; + sum += i * 1000UL / c; + + c *= 10UL; + u32Count = r * 10UL; + } + + return sum; +} + +/*! + * brief Delay at least for some time in millisecond unit. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * param delayTime_ms Delay time in unit of millisecond. + * param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastMs(uint32_t delayTime_ms, uint32_t coreClock_Hz) +{ + while(delayTime_ms > 0) + { + uint32_t ms, count; + + /* MSEC_TO_COUNT(fixed-point) supports maximum 42949ms @ 100MHz, use 1000UL here */ + if(delayTime_ms > 1000UL) + { + ms = 1000UL; + } + else + { + ms = delayTime_ms; + } + delayTime_ms -= ms; + + count = MSEC_TO_COUNT(ms, coreClock_Hz); + SDK_DelayCoreCycles(count); + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.h new file mode 100644 index 00000000000..3659d4b23a9 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_DSC_H_ +#define FSL_COMMON_DSC_H_ + +#include "fsl_device_registers.h" +#include "Cpu.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#ifndef bool +typedef uint8_t bool; +#define true 1 +#define false 0 +#endif + +/*! @name Timer utilities */ +/*! @{ */ +#if FSL_FEATURE_SOC_HAS_FPU +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) ((float)clockFreqInHz * ((float))us / 1000000UL) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) ((float)count * 1000000UL / (float)clockFreqInHz) +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) ((float)clockFreqInHz * ((float))ms / 1000UL) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) ((float)count * 1000UL / (float)clockFreqInHz) + +#else +/*! Macro to convert a microsecond period to raw count value */ +/* To avoid overflow, us is maximum to 4294us */ +#define USEC_TO_COUNT(us, clockFreqInHz) SDK_CovertUsToCount(us, clockFreqInHz) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) SDK_CovertCountToUs(count, clockFreqInHz) +/*! Macro to convert a millisecond period to raw count value */ +/* To avoid overflow, ms is maximum to 42949ms @ clockFreqInHz = 100MHz */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) SDK_CovertMsToCount(ms, clockFreqInHz) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) SDK_CovertCountToMs(count, clockFreqInHz) +#endif +/*! @} */ + +#define SDK_ISR_EXIT_BARRIER + +/*! @name Alignment variable definition macros */ +/*! @{ */ +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! @} */ + +/*! @brief Default DSC interrupt priority number. */ +#define SDK_DSC_DEFAULT_INT_PRIO 1U + +/*! @brief Set base core IRQ priority, that core will response the interrupt request with priority >= base IRQ priority. + */ +#define SetIRQBasePriority(x) __EI##x() + +/*! + * @brief Read register value. + * + * Example: + * val = PeriphReadReg(OCCS->OSCTL2); + * + * @param reg Register name. + * + * @return The value of register. + */ +#define PeriphReadReg(reg) (reg) + +/*! + * @brief Write data to register. + * + * Example: + * PeriphWriteReg(OCCS->OSCTL2, 0x278U); + * + * @param reg Register name. + * @param data Data wrote to register. + */ +#define PeriphWriteReg(reg, data) (reg) = (data) + +/*! + * @brief Set specified bits in register. + * + * Example: + * PeriphSetBits(OCCS->OSCTL2, 0x12U); + * + * @param reg Register name. + * @param bitMask Bits mask, set bits will be set in the register. + */ +#define PeriphSetBits(reg, bitMask) (reg) |= (bitMask) + +/*! + * @brief Clear specified bits in register. + * + * Example: + * PeriphClearBits(OCCS->OSCTL2, 0x12U); + * + * @param reg Register name. + * @param bitMask Bits mask, set bits will be cleared in the register. + */ +#define PeriphClearBits(reg, bitMask) (reg) &= (~(bitMask)) + +/*! + * @brief Invert specified bits in register. + * + * Example: + * PeriphInvertBits(OCCS->OSCTL2, 0x12U); + * + * @param reg Register name. + * @param bitMask Bits mask, set bits will be inverted in the register. + */ +#define PeriphInvertBits(reg, bitMask) (reg) ^= (bitMask) + +/*! + * @brief Get specified bits in register. + * + * Example: + * val = PeriphGetBits(OCCS->OSCTL2, 0x23U); + * + * @param reg Register name. + * @param bitMask Bits mask, specify the getting bits. + * + * @return The value of specified bits. + */ +#define PeriphGetBits(reg, bitMask) ((reg) & (bitMask)) + +/*! + * @brief Write group of bits to register. + * + * Example: + * PeriphWriteBitGroup(OCCS->DIVBY, OCCS_DIVBY_COD_MASK, OCCS_DIVBY_COD(23U)); + * PeriphWriteBitGroup(OCCS->DIVBY, OCCS_DIVBY_COD_MASK | OCCS_DIVBY_PLLDB_MASK, \ + * OCCS_DIVBY_COD(23U) | OCCS_DIVBY_PLLDB(49U)); + * + * @param reg Register name. + * @param bitMask Bits mask, mask of the group of bits. + * @param bitValue This value will be written into the bit group specified by parameter bitMask. + */ +#define PeriphWriteBitGroup(reg, bitMask, bitValue) (reg) = ((reg) & ~(bitMask)) | ((bitValue) & (bitMask)) + +/*! + * @brief Clear (acknowledge) flags which are active-high and are cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeClearFlags(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FFLAG(2)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param flagMask The selected flags(cleared-by-write-one) which are supposed to be cleared. + */ +#define PeriphSafeClearFlags(reg, allFlagsMask, flagMask) \ + (reg) = ((reg) & (~(allFlagsMask))) | ((flagMask) & (allFlagsMask)) + +/*! + * @brief Clear selected bits without modifying (acknowledge) bit flags which are active-high and are + * cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeClearBits(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF(2)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param bitMask The selected bits which are supposed to be cleared. + */ +#define PeriphSafeClearBits(reg, allFlagsMask, bitMask) (reg) = ((reg) & (~((allFlagsMask) | (bitMask)))) + +/*! + * @brief Set selected bits without modifying (acknowledge) bit flags which are active-high and are + * cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeSetBits(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF(2)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param bitMask The selected bits which are supposed to be set. + */ +#define PeriphSafeSetBits(reg, allFlagsMask, bitMask) \ + (reg) = ((reg) & (~(allFlagsMask))) | ((bitMask) & (~(allFlagsMask))) + +/*! + * @brief Write group of bits without modifying (acknowledge) bit flags which are active-high and are + * cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeWriteBitGroup(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF_MASK, PWM_FSTS_FHALF(3U)); + * PeriphSafeWriteBitGroup(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF_MASK | PWM_FSTS_FFULL_MASK, \ + * PWM_FSTS_FHALF(3U) | PWM_FSTS_FFULL(2U)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param bitMask Bits mask, mask of the group of bits. + * @param bitValue This value will be written into the bit group specified by parameter bitMask. + */ +#define PeriphSafeWriteBitGroup(reg, allFlagsMask, bitMask, bitValue) \ + (reg) = ((reg) & (~((allFlagsMask) | (bitMask)))) | ((bitValue) & (bitMask) & (~(allFlagsMask))) + +/*! + * @brief Get IP register byte address with uint32_t type. + * + * This macro is useful when a register byte address is required, especially in SDM mode. + * Example: + * SDK_GET_REGISTER_BYTE_ADDR(ADC_Type, ADC, RSLT[0]); + * + * @param ipType IP register mapping struct type. + * @param ipBase IP instance base pointer, WORD address. + * @param regName Member register name of IP register mapping struct. + */ +#define SDK_GET_REGISTER_BYTE_ADDR(ipType, ipBase, regName) \ + ((2UL * ((uint32_t)(ipBase))) + ((uint32_t)(uint8_t *)&(((ipType *)0)->regName))) + +/* Macros for compatibility. */ +#define MSDK_REG_SECURE_ADDR(x) (x) +#define MSDK_REG_NONSECURE_ADDR(x) (x) + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t. + */ +#include "fsl_clock.h" + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Disable the global IRQ + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t ret; + if ((INTC->CTRL & INTC_CTRL_INT_DIS_MASK) != 0U) + { + ret = 0U; + } + else + { + INTC->CTRL |= INTC_CTRL_INT_DIS_MASK; + ret = 1U; + } + return ret; +} + +/*! + * @brief Enable the global IRQ + */ +static inline void EnableGlobalIRQ(uint32_t irqSts) +{ + if (irqSts != 0U) + { + INTC->CTRL &= ~INTC_CTRL_INT_DIS_MASK; + } + else + { + INTC->CTRL |= INTC_CTRL_INT_DIS_MASK; + } +} + +/*! + * @brief Check if currently core is able to response IRQ + */ +static inline bool isIRQAllowed(void) +{ + bool ret = true; + uint16_t srReg; + + if (0U != (INTC->CTRL | INTC_CTRL_INT_DIS_MASK)) + { + ret = false; + } + + asm {move.w SR, srReg} + ; + if (0U != (srReg & 0x300U)) + { + ret = false; + } + return ret; +} + +/*! + * @name Interrupt + * + * DSC interrupt controller uses the same bit-filed to control interrupt enable + * status and priority, to provide compatible APIs, SDK uses a interrupt priority + * table, thus application could control the interrupt + * enable/disable, and interrupt priority independently. Also, the API + * @ref EnableIRQWithPriority could be used to enable the interrupt and set the priority + * at the same time. + * + * API implementation: + * + * 1. When calling @ref EnableIRQ, if the interrupt priority in priority table is + * valid, then set the interrupt priority level to the value in priority table + * If interrupt priority in priority table is invalid, then set the interrupt + * priority level to @ref SDK_DSC_DEFAULT_INT_PRIO. + * + * 2. When calling @ref IRQ_SetPriority, if the interrupt is already enabled, new + * priority is set to interrupt controller, meanwhile the priority table is + * updated accordingly. If the interrupt is not enabled, new priority value is + * saved to priority table , and takes effect when calling @ref EnableIRQ. + * + * The interrupt functions configure INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @{ + */ + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * @note The parameter @p priNum is range in 1~3, and its value is **NOT** + * directly map to interrupt priority. + * + * - Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3 + * - Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2 + * + * User should check chip's RM to get its corresponding interrupt priority. + * + * When @p priNum set as 0, then @ref SDK_DSC_DEFAULT_INT_PRIO is set instead. + * When @p priNum set as number larger than 3, then only the 2 LSB take effect, + * for example, setting @p priNum to 5 is the same with setting it to 1. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to enable. + * @param priNum Priority number set to interrupt controller register. + * Larger number means higher priority. + * The allowed range is 1~3, and its value is **NOT** directly map to interrupt priority. + * In other words, the same priority number means different interrupt priority levels + * for different IRQ, please check reference manual for the relationship. + * When pass in 0, then @ref SDK_DSC_DEFAULT_INT_PRIO is set to priority register. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t EnableIRQWithPriority(IRQn_Type irq, uint8_t priNum); + +/*! + * @brief Disable specific interrupt. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to disable. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t DisableIRQ(IRQn_Type irq); + +/*! + * @brief Enable specific interrupt. + * + * The recommended workflow is calling @ref IRQ_SetPriority first, then call + * @ref EnableIRQ. If @ref IRQ_SetPriority is not called first, then the interrupt + * is enabled with default priority value @ref SDK_DSC_DEFAULT_INT_PRIO. + * + * Another recommended workflow is calling @ref EnableIRQWithPriority directly, + * it is the same with calling @ref IRQ_SetPriority + @ref EnableIRQ. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to enable. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t EnableIRQ(IRQn_Type irq); + +/*! + * @brief Set the IRQ priority. + * + * @note The parameter @p priNum is range in 1~3, and its value is **NOT** + * directly map to interrupt priority. + * + * - Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3 + * - Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2 + * + * User should check chip's RM to get its corresponding interrupt priority + * + * When @p priNum set as 0, then @ref SDK_DSC_DEFAULT_INT_PRIO is set instead. + * When @p priNum set as number larger than 3, then only the 2 LSB take effect, + * for example, setting @p priNum to 5 is the same with setting it to 1. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * Larger number means higher priority, 0 means disable the interrupt. + * The allowed range is 0~3, and its value is **NOT** directly map to interrupt priority. + * In other words, the same priority number means different interrupt priority levels + * for different IRQ, please check reference manual for the relationship. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t IRQ_SetPriority(IRQn_Type irq, uint8_t priNum); + +/*! @} */ + +/*! + * @brief Delay core cycles. + * Please note that, this API uses software loop for delay, the actual delayed + * time depends on core clock frequency, where the function is located (ram or flash), + * flash clock, possible interrupt. + * + * @param u32Num Number of core clock cycle which needs to be delayed. + */ +void SDK_DelayCoreCycles(uint32_t u32Num); + +/*! + * @brief Covert us to count with fixed-point calculation. + * + * @note u32Us must not be greater than 4294 + * + * @param u32Us Time in us + * @param u32Hz Clock frequency in Hz + * @return The count value + */ +uint32_t SDK_CovertUsToCount(uint32_t u32Us, uint32_t u32Hz); + +/*! + * @brief Covert count to us with fixed-point calculation. + * + * @note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * @param u32Count Count value + * @param u32Hz Clock frequency in Hz + * @return The us value + */ +uint32_t SDK_CovertCountToUs(uint32_t u32Count, uint32_t u32Hz); + +/*! + * @brief Covert ms to count with fixed-point calculation. + * + * @note u32Ms must not be greater than 42949UL @ u32Hz = 100M + * + * @param u32Ms Time in us + * @param u32Hz Clock frequency in Hz + * @return The count value + */ +uint32_t SDK_CovertMsToCount(uint32_t u32Ms, uint32_t u32Hz); + +/*! + * @brief Covert count to ms with fixed-point calculation. + * + * @note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * @param u32Count Count value + * @param u32Hz Clock frequency in Hz + * @return The us value + */ +uint32_t SDK_CovertCountToMs(uint32_t u32Count, uint32_t u32Hz); + +/*! + * @brief Delay at least for some time in millisecond unit. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_ms Delay time in unit of millisecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastMs(uint32_t delayTime_ms, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_COMMON_DSC_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.c new file mode 100644 index 00000000000..8a1ea9e1fdf --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_dsp" +#endif + +extern uint32_t xthal_get_ccount(void); + +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + + /* Calculate the count ticks. */ + count += xthal_get_ccount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < xthal_get_ccount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > xthal_get_ccount()) + { + } + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.h new file mode 100644 index 00000000000..c3662abade7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_DSP_H_ +#define FSL_COMMON_DSP_H_ + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/*! @} */ + +#define SDK_ISR_EXIT_BARRIER + +/*! @name Alignment variable definition macros */ +/*! @{ */ +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif + +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/*! @{ */ + +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) + +/*! @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func + +#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ + +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func + +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/*! @} */ + +/* Macros for compatibility. */ +#define NVIC_SetPriorityGrouping(value) do {} while(0) +#define NVIC_GetPriorityGrouping() do {} while(0) +#define NVIC_SetPriority(irq, value) do {} while(0) +#define NVIC_GetPriority(irq) do {} while(0) +#define NVIC_EnableIRQ(value) do {} while(0) +#define NVIC_GetEnableIRQ(value) do {} while(0) +#define NVIC_DisableIRQ(value) do {} while(0) +#define NVIC_GetPendingIRQ(value) do {} while(0) +#define NVIC_SetPendingIRQ(value) do {} while(0) +#define NVIC_ClearPendingIRQ(value) do {} while(0) +#define NVIC_GetActive(value) do {} while(0) +#define MSDK_REG_SECURE_ADDR(x) (x) +#define MSDK_REG_NONSECURE_ADDR(x) (x) + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable the global IRQ + * + * Empty function for build compatibility. + * + * @return Always return 0; + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + return 0; +} + +/*! + * @brief Enable the global IRQ + * + * Empty function for build compatibility. + * + * @param primask Not used. + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_COMMON_DSP_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.c new file mode 100644 index 00000000000..c3e9bd556a1 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.c @@ -0,0 +1,45 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_riscv" +#endif + +static void DelayLoop(uint32_t count) +{ + __ASM volatile( + " mv a0, %0 \n" + "loop%=: \n" + " addi a0, a0, -1 \n" + " bgtz a0, loop%= \n" + : + : "r"(count) + :); +} + +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + + /* + * Add is 1 cycle. + * Branch is 2 cycle. + */ + count = count / 3U; + + DelayLoop((uint32_t)count); + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.h new file mode 100644 index 00000000000..2366783b646 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.h @@ -0,0 +1,148 @@ +/* + * Copyright 2024-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_RISCV_H_ +#define FSL_COMMON_RISCV_H_ + +#include "riscv_interrupt.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/*! @} */ + +#define SDK_ISR_EXIT_BARRIER + +/*! @name Alignment variable definition macros */ +/*! @{ */ +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! + * @def MSDK_REG_SECURE_ADDR(x) + * Convert the register address to the one used in secure mode. + * + * @def MSDK_REG_NONSECURE_ADDR(x) + * Convert the register address to the one used in unsecure mode. + */ +#define MSDK_REG_SECURE_ADDR(x) ((typeof(x))((uintptr_t)(x) | (0x1UL << 28))) +#define MSDK_REG_NONSECURE_ADDR(x) ((typeof(x))((uintptr_t)(x) & ~(0x1UL << 28))) + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global IRQ. + * + * @return The global IRQ control register value before been disabled. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + return csr_read_clear(CSR_MSTATUS, CSR_MSTATUS_MIE); +} + +/*! + * @brief Enable the global IRQ + * + * Enable the global interrupt by setting the global IRQ control register. + * Generally this value is the return value of DisableGlobalIRQ. + * + * @param intCtrl The global interrupt control register value. + */ +static inline void EnableGlobalIRQ(uint32_t intCtrl) +{ + csr_set(CSR_MSTATUS, intCtrl); +} + +/*! + * @brief Enable M-mode interrupt. + * + * @param mask M-mode interrupt mask. + */ +static inline void EnableMachineModeInt(ezhv_mie_mask_t mask) +{ + csr_set(CSR_MIE, mask); +} + +/*! + * @brief Disable M-mode interrupt. + * + * @param mask M-mode interrupt mask. + */ +static inline void DisableMachineModeInt(ezhv_mie_mask_t mask) +{ + csr_clear(CSR_MIE, mask); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/SConscript new file mode 100644 index 00000000000..fa6cdfab67b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('fsl_lpuart.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.c new file mode 100644 index 00000000000..8e9fa360b93 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.c @@ -0,0 +1,2786 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart.h" + +#include + +#define memset rt_memset + +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpuart_c_ref_1$ + * (osr > 3) (false) can't be not covered, because osr(osrTemp) is increased from 4U. + * + * $Justification fsl_lpuart_c_ref_2$ + * The flag is cleared successfully during test. + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart" +#endif + +/* LPUART transfer state. */ +enum +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +#if defined(LPUART_RSTS) +#define LPUART_RESETS_ARRAY LPUART_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Check whether the RX ring buffer is full. + * + * @userData handle LPUART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); +/*! + * @brief Write to TX register using non-blocking method in 9bit or 10bit mode. + * + * The 10bit of data will be writen to TX register DATA. + * Please make sure data 10bit is valid and other bit is 0. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); +/*! + * @brief Read RX register using non-blocking method in 9bit or 10bit mode. + * + * This function reads 10bit data from the RX register directly and stores to 16bit data. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); +/*! + * @brief LPUART_TransferHandleIDLEIsReady handle function. + * This function handles when IDLE is ready. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleReceiveDataIsFull handle function. + * This function handles when receive data is full. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleSendDataIsEmpty handle function. + * This function handles when send data is empty. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleTransmissionIsComplete handle function. + * This function handles Transmission complete and the interrupt is enabled. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART peripheral base address. */ +static LPUART_Type** const s_lpuartBases[] = LPUART_BASE_PTRS; +/* Array of LPUART handle. */ +void *s_lpuartHandle[ARRAY_SIZE(s_lpuartBases)]; +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) +static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS; +#endif +#if defined(LPUART_TX_IRQS) +const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS; +#endif +#else +#if defined(LPUART_RX_TX_IRQS) +const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; +#endif +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of LPUART clock name. */ +static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; + +#if defined(LPUART_PERIPH_CLOCKS) +/* Array of LPUART functional clock name. */ +static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* LPUART ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)] = {[0 ...(ARRAY_SIZE(s_lpuartBases) - 1)] = + (lpuart_isr_t)DefaultISR}; +#else +lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)]; +#endif + +#if defined(LPUART_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpuartResets[] = LPUART_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the LPUART instance from peripheral base address. + * + * param base LPUART peripheral base address. + * return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 1U; instance < ARRAY_SIZE(s_lpuartBases); instance++) + { + if (MSDK_REG_SECURE_ADDR(*(s_lpuartBases[instance])) == MSDK_REG_SECURE_ADDR(base)) + { + return instance; + } + } + + assert(instance < ARRAY_SIZE(s_lpuartBases)); + + return instance; +} + +/*! + * @brief Set the LPUART instance to peripheral base address. + * + * @param instance LPUART instance. + * @param base LPUART peripheral base address. + */ +void LPUART_SetInstance(uint32_t instance, LPUART_Type *base) +{ + if (instance >= ARRAY_SIZE(s_lpuartBases) || !instance) + { + return; + } + *(s_lpuartBases[instance]) = base; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * userData handle LPUART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + size_t size; + size_t tmpRxRingBufferSize = handle->rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; + + if (tmpRxRingBufferTail > tmpRxRingBufferHead) + { + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); + } + else + { + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (uint8_t)(base->DATA & 0x7FU); + } + else + { + data[i] = (uint8_t)base->DATA; + } +#else + data[i] = (uint8_t)(base->DATA); +#endif + } +} + +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = (uint16_t)(base->DATA & 0x03FFU); + } +} + +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + assert(0U < config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->rxFifoWatermark); +#endif + + status_t status = kStatus_Success; + uint32_t temp; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* Avoid MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); + tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : + (config->baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPUART_GetInstance(base); + + /* Enable lpuart clock */ + (void)CLOCK_EnableClock(s_lpuartClock[instance]); +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPUART_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpuartResets[LPUART_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_1$ + */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | + LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + +#if defined(FSL_FEATURE_LPUART_HAS_CTRL_SWAP) && FSL_FEATURE_LPUART_HAS_CTRL_SWAP + if (config->swapTxdRxd == true) + { + temp |= LPUART_CTRL_SWAP_MASK; + } + else + { + temp &= ~LPUART_CTRL_SWAP_MASK; + } +#endif + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (true == config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (true == config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (true == config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (true == config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (true == config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; + } + + return status; +} +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shift out */ + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = LPUART_GetInstance(base); + + /* Disable lpuart clock */ + (void)CLOCK_DisableClock(s_lpuartClock[instance]); + +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0U; + config->rxFifoWatermark = 0U; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +#if defined(FSL_FEATURE_LPUART_HAS_CTRL_SWAP) && FSL_FEATURE_LPUART_HAS_CTRL_SWAP + config->swapTxdRxd = false; +#endif +} + +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(0U < baudRate_Bps); + + status_t status = kStatus_Success; + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* Avoid MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); + + tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_1$ + */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + + return status; +} + +/*! + * brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base LPUART peripheral base address. + * param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */ + temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK); + temp |= (uint32_t)LPUART_CTRL_M_MASK; + base->CTRL = temp; + } + else + { + /* Clear LPUART_CTRL_M. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK; + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT + /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */ + base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK; +#endif +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base LPUART peripheral base address. + * param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address) +{ + assert(base != NULL); + + uint32_t temp = base->DATA & 0xFFFFFC00UL; + temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT)); + base->DATA = temp; +} + +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + + /* Check int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD |= baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Set int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL |= mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + + /* Clear int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD &= ~baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Clear int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Clear int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL &= ~mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + /* Check int enable bits in base->CTRL */ + uint32_t temp = (uint32_t)(base->CTRL & (uint32_t)kLPUART_AllInterruptEnable); + + /* Check int enable bits in base->BAUD */ + temp = (temp & ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable) | ((base->BAUD & LPUART_BAUD_RXEDGIE_MASK) >> 8U); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp = (temp & ~(uint32_t)kLPUART_LinBreakInterruptEnable) | ((base->BAUD & LPUART_BAUD_LBKDIE_MASK) >> 8U); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + temp = + (temp & ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable)) | + (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + + return temp; +} + +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16U; +#endif + /* Only keeps the status bits */ + temp &= (uint32_t)kLPUART_AllFlags; + return temp; +} + +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; + + /* Only deal with the clearable flags */ + mask &= (uint32_t)kLPUART_AllClearFlags; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Status bits in FIFO register */ + if ((mask & ((uint32_t)kLPUART_TxFifoOverflowFlag | (uint32_t)kLPUART_RxFifoUnderflowFlag)) != 0U) + { + /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case + they are written 1 accidentally. */ + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | + LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; + } +#endif + /* Status bits in STAT register */ + /* First get the STAT register value and mask all the bits that not represent status, then OR with the status bit + * that is to be W1C */ + temp = (base->STAT & 0x3E000000UL) | mask; + base->STAT = temp; + /* If some flags still pending. */ + if (0U != (mask & LPUART_GetStatusFlags(base))) + { + status = kStatus_LPUART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the data to be sent out to bus. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} +/*! + * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + const uint16_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint8_t *dataAddress = data; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + + if (kStatus_Success == status) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(dataAddress) = (uint8_t)(base->DATA & 0x7FU); + dataAddress++; + } + else + { + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; + } +#else + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; +#endif + } + else + { + break; + } + } + + return status; +} +/*! + * brief Reads the receiver data register in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint16_t *dataAddress = data; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + if (kStatus_Success == status) + { + *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU); + dataAddress++; + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + handle->is16bitData = false; + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr[instance] = LPUART_TransferHandleIRQ; + +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) + (void)EnableIRQ(s_lpuartRxIRQ[instance]); +#endif +#if defined(LPUART_TX_IRQS) + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#endif +#else +#if defined(LPUART_RX_TX_IRQS) + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif +#endif +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + if (!handle->is16bitData) + { + handle->rxRingBufferSize = ringBufferSize; + } + else + { + handle->rxRingBufferSize = ringBufferSize / 2U; + } + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable the interrupt to accept the data when user need the ring buffer. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kLPUART_RxIdle) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->txData); + assert(0U != xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + if (!handle->is16bitData) + { + handle->txData = xfer->txData; + } + else + { + handle->txData16 = xfer->txData16; + } + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kLPUART_TxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable transmitter interrupt. */ + base->CTRL |= (uint32_t)LPUART_CTRL_TIE_MASK; + EnableGlobalIRQ(irqMask); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_TIE_MASK | LPUART_CTRL_TCIE_MASK); + EnableGlobalIRQ(irqMask); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmptxDataSize = handle->txDataSize; + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + status = kStatus_NoTransferInProgress; + } + else + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + *count = handle->txDataSizeAll - tmptxDataSize - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U) + { + *count = handle->txDataSizeAll - tmptxDataSize; + } + else + { + *count = handle->txDataSizeAll - tmptxDataSize - 1U; + } +#endif + } + + return status; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->rxData); + assert(0U != xfer->dataSize); + + uint32_t i; + status_t status; + uint32_t irqMask; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (NULL != handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable LPUART RX IRQ, protect ring buffer. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (0U != bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + if (!handle->is16bitData) + { + xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + } + else + { + xfer->rxData16[bytesCurrentReceived] = handle->rxRingBuffer16[handle->rxRingBufferTail]; + } + bytesCurrentReceived++; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (0U != bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kLPUART_RxBusy; + } + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Re-enable LPUART RX IRQ. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Enable RX interrupt. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + /* Return the how many bytes have read. */ + if (NULL != receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Disable RX interrupt. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmprxDataSize = handle->rxDataSize; + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxDataSizeAll - tmprxDataSize; + } + + return status; +} + +static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint32_t irqMask; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t count; + uint8_t tempCount; + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((0U != handle->rxDataSize) && (0U != count)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, invoke rx idle callback.*/ + if (0U == (handle->rxDataSize)) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_IDLE_MASK); + + /* If rxDataSize is 0, disable rx ready, overrun and idle line interrupt.*/ + if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + /* Invoke callback if callback is not NULL and rxDataSize is not 0. */ + else if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + else + { + /* Avoid MISRA 15.7 */ + } +} + +static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + uint16_t tpmRxRingBufferHead; + uint32_t tpmData; + uint32_t irqMask; + + /* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((0U != handle->rxDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (NULL != handle->rxRingBuffer) + { + while (0U != count) + { + count--; + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + tpmRxRingBufferHead = handle->rxRingBufferHead; + tpmData = base->DATA; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU); + } + else + { + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } + } +#else + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } +#endif + + /* Increase handle->rxRingBufferHead. */ + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK | LPUART_CTRL_ILIE_MASK); + EnableGlobalIRQ(irqMask); + } + else + { + /* Avoid MISRA C-2012 15.7 voiation */ + return; + } +} + +static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + uint32_t irqMask; +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((0U != handle->txDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + if (!handle->is16bitData) + { + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData = &handle->txData[tempCount]; + } + else + { + LPUART_WriteNonBlocking16bit(base, handle->txData16, tempCount); + handle->txData16 = &handle->txData16[tempCount]; + } + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (0U == handle->txDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable TX register empty interrupt and enable transmission completion interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK) | LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + } + } +} + +static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint32_t irqMask; + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + irqMask = DisableGlobalIRQ(); + /* Disable transmission complete interrupt. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + + /* Trigger callback. */ + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } +} + +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle) +{ + assert(NULL != irqHandle); + + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); + + lpuart_handle_t *handle = (lpuart_handle_t *)irqHandle; + + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (NULL != (handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleIDLEReady(base, handle); + } + /* Receive data register full */ + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleReceiveDataFull(base, handle); + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleSendDataEmpty(base, handle); + } + + /* Transmission complete and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && + (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleTransmissionComplete(base, handle); + } +} + +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle) +{ + /* To be implemented by User. */ +} + +void LPUART_DriverIRQHandler(uint32_t instance) +{ + if (instance < ARRAY_SIZE(s_lpuartBases)) + { + s_lpuartIsr[instance](*(s_lpuartBases[instance]), s_lpuartHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_DriverIRQHandler(void); +void LPUART0_LPUART1_RX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_LPUART1_TX_DriverIRQHandler(void); +void LPUART0_LPUART1_TX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_LPUART1_DriverIRQHandler(void); +void LPUART0_LPUART1_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_DriverIRQHandler(void); +void LPUART0_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_RX_DriverIRQHandler(void); +void LPUART0_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_DriverIRQHandler(void); +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_DriverIRQHandler(void); +void LPUART1_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART1_RX_DriverIRQHandler(void); +void LPUART1_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART1_DriverIRQHandler(void); +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_DriverIRQHandler(void); +void LPUART2_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART2_RX_DriverIRQHandler(void); +void LPUART2_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART2_DriverIRQHandler(void); +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_DriverIRQHandler(void); +void LPUART3_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART3_RX_DriverIRQHandler(void); +void LPUART3_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART3_DriverIRQHandler(void); +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_DriverIRQHandler(void); +void LPUART4_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART4_RX_DriverIRQHandler(void); +void LPUART4_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART4_DriverIRQHandler(void); +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_DriverIRQHandler(void); +void LPUART5_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART5_RX_DriverIRQHandler(void); +void LPUART5_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART5_DriverIRQHandler(void); +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_DriverIRQHandler(void); +void LPUART6_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART6_RX_DriverIRQHandler(void); +void LPUART6_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART6_DriverIRQHandler(void); +void LPUART6_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_DriverIRQHandler(void); +void LPUART7_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART7_RX_DriverIRQHandler(void); +void LPUART7_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART7_DriverIRQHandler(void); +void LPUART7_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_DriverIRQHandler(void); +void LPUART8_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART8_RX_DriverIRQHandler(void); +void LPUART8_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART8_DriverIRQHandler(void); +void LPUART8_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART9) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART9_TX_DriverIRQHandler(void); +void LPUART9_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART9_RX_DriverIRQHandler(void); +void LPUART9_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART9_DriverIRQHandler(void); +void LPUART9_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART10) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART10_TX_DriverIRQHandler(void); +void LPUART10_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART10_RX_DriverIRQHandler(void); +void LPUART10_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART10_DriverIRQHandler(void); +void LPUART10_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART11) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART11_TX_DriverIRQHandler(void); +void LPUART11_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART11_RX_DriverIRQHandler(void); +void LPUART11_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART11_DriverIRQHandler(void); +void LPUART11_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART12) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART12_TX_DriverIRQHandler(void); +void LPUART12_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART12_RX_DriverIRQHandler(void); +void LPUART12_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART12_DriverIRQHandler(void); +void LPUART12_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_DriverIRQHandler(void); +void M4_0_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4_0__LPUART)](CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_DriverIRQHandler(void); +void M4_1_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4_1__LPUART)](CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void); +void M4_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4__LPUART)](CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_DriverIRQHandler(void); +void DMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART0)](DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_DriverIRQHandler(void); +void DMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART1)](DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_DriverIRQHandler(void); +void DMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART2)](DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_DriverIRQHandler(void); +void DMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART3)](DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_DriverIRQHandler(void); +void DMA_UART4_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART4)](DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void); +void ADMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART0)](ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void); +void ADMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART1)](ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void); +void ADMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART2)](ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void); +void ADMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART3)](ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.h new file mode 100644 index 00000000000..9bf98b000e7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.h @@ -0,0 +1,1150 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_H_ +#define FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART driver version. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) +/*! @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the LPUART driver. */ +enum +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ + kStatus_LPUART_Timeout = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. bit 23 */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. bit 22 */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. bit 21 */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. bit 20 */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. bit 27 */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. bit 26 */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. bit 25 */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. bit 24 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_Match1InterruptEnable = (LPUART_CTRL_MA1IE_MASK), /*!< Parity error flag. bit 15 */ + kLPUART_Match2InterruptEnable = (LPUART_CTRL_MA2IE_MASK), /*!< Parity error flag. bit 14 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */ +#endif + + kLPUART_AllInterruptEnable = kLPUART_RxActiveEdgeInterruptEnable | kLPUART_TxDataRegEmptyInterruptEnable | + kLPUART_TransmissionCompleteInterruptEnable | kLPUART_RxDataRegFullInterruptEnable | + kLPUART_IdleLineInterruptEnable | kLPUART_RxOverrunInterruptEnable | + kLPUART_NoiseErrorInterruptEnable | kLPUART_FramingErrorInterruptEnable | + kLPUART_ParityErrorInterruptEnable +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakInterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_Match1InterruptEnable | kLPUART_Match2InterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowInterruptEnable | kLPUART_RxFifoUnderflowInterruptEnable +#endif + , +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */ + kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive + data buffer is full. bit 21 */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected. bit 20 */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register. bit 19 */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets. bit 18 */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection. bit 16 */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled. bit 31 */ +#endif + kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active + edge detected. bit 30 */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = + LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */ + kLPUART_DataMatch2Flag = + LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = + (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty. bit 7 */ + kLPUART_RxFifoEmptyFlag = + (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */ +#endif + + kLPUART_AllClearFlags = kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | + kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , + + kLPUART_AllFlags = + kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_TxDataRegEmptyFlag | + kLPUART_TransmissionCompleteFlag | kLPUART_RxDataRegFullFlag | kLPUART_RxActiveFlag | kLPUART_NoiseErrorFlag | + kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag | kLPUART_TxFifoEmptyFlag | kLPUART_RxFifoEmptyFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +#if defined(FSL_FEATURE_LPUART_HAS_CTRL_SWAP) && FSL_FEATURE_LPUART_HAS_CTRL_SWAP + bool swapTxdRxd; /*!< Swap TXD and RXD pins */ +#endif +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + uint16_t *rxData16; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + const uint16_t *txData16; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + union + { + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + const uint16_t *volatile txData16; /*!< Address of remaining data to send. */ + }; + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + union + { + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + uint16_t *volatile rxData16; /*!< Address of remaining data to receive. */ + }; + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + union + { + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + uint16_t *rxRingBuffer16; /*!< Start address of the receiver ring buffer. */ + }; + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif + bool is16bitData; /*!< 16bit data bits flag, only used for 9bit or 10bit data */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART handle. */ +extern void *s_lpuartHandle[]; + +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +extern const IRQn_Type s_lpuartTxIRQ[]; +#else +extern const IRQn_Type s_lpuartIRQ[]; +#endif + +/* LPUART ISR for transactional APIs. */ +extern lpuart_isr_t s_lpuartIsr[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/*! @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); +/*! @} */ + +/*! + * @name Module configuration + * @{ + */ +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base LPUART peripheral base address. + * @param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable); + +/*! + * @brief Set the LPUART address. + * + * This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address + * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being + * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one + * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in + * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with + * unmatched address. + * + * @note Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base LPUART peripheral base address. + * @param address1 LPUART slave address1. + * @param address2 LPUART slave address2. + */ +static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2) +{ + /* Configure match address. */ + uint32_t address = ((uint32_t)address2 << 16U) | (uint32_t)address1 | 0x1000100UL; + base->MATCH = address; +} + +/*! + * @brief Enable the LPUART match address feature. + * + * @param base LPUART peripheral base address. + * @param match1 true to enable match address1, false to disable. + * @param match2 true to enable match address2, false to disable. + */ +static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2) +{ + /* Configure match address1 enable bit. */ + if (match1) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN1_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN1_MASK; + } + /* Configure match address2 enable bit. */ + if (match2) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN2_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN2_MASK; + } +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_RXWATER_MASK) | LPUART_WATER_RXWATER(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water); +} +#endif + +/*! + * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. + * + * This function Enable 16bit Data transmit in lpuart_handle_t. + * + * @param handle LPUART handle pointer. + * @param enable true to enable, false to disable. + */ +static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable) +{ + handle->is16bitData = enable; +} +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); +/*! @} */ + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @name DMA Configuration + * @{ + */ +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uintptr_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} +/*! @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Set the LPUART instance to peripheral base address. + * + * @note Add this function to support remap LPUART base address. + * @param instance LPUART instance. + * @param base LPUART peripheral base address. + */ +void LPUART_SetInstance(uint32_t instance, LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + uint8_t result; + /* + * $Branch Coverage Justification$ + * (ctrl & LPUART_CTRL_M7_MASK) == 0U) false is not covered. + * If ctrl & LPUART_CTRL_M7_MASK is 0, it can't be !0 in next judge. + */ + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) && + ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); + + if (isSevenDataBits) + { + result = (uint8_t)(base->DATA & 0x7FU); + } + else + { + result = (uint8_t)base->DATA; + } + + return result; +#else + return (uint8_t)(base->DATA); +#endif +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Gets the rx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +} +#endif + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base LPUART peripheral base address. + * @param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address); + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle); + +/*! + * @brief LPUART driver IRQ handler common entry. + * + * This function provides the common IRQ request entry for LPUART. + * + * @param instance LPUART instance. + */ +void LPUART_DriverIRQHandler(uint32_t instance); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.c new file mode 100644 index 00000000000..5d75e6bdd7c --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.c @@ -0,0 +1,434 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_lpuart_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_dma" +#endif + +/*base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(lpuartPrivateHandle->handle->txDmaHandle->base, + lpuartPrivateHandle->handle->txDmaHandle->channel); + + /* Enable tx complete interrupt */ + LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); +} + +static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param) +{ + assert(handle != NULL); + assert(param != NULL); + + lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param; + + /* Disable LPUART RX DMA. */ + LPUART_EnableRxDMA(lpuartPrivateHandle->base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(lpuartPrivateHandle->handle->rxDmaHandle->base, + lpuartPrivateHandle->handle->rxDmaHandle->channel); + + lpuartPrivateHandle->handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (lpuartPrivateHandle->handle->callback != NULL) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * + * note This function disables all LPUART interrupts. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_dma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txDmaHandle User-requested DMA handle for TX DMA transfer. + * param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleDMA(LPUART_Type *base, + lpuart_dma_handle_t *handle, + lpuart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + assert(handle != NULL); + + uint32_t instance = LPUART_GetInstance(base); + + (void)memset(handle, 0, sizeof(lpuart_dma_handle_t)); + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, DMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + DMA transfer because the water mark is 2. + */ + if (rxDmaHandle != NULL) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + /* Set LPUART_TransferDMAHandleIRQ as DMA IRQ handler */ + s_lpuartIsr[instance] = LPUART_TransferDMAHandleIRQ; + /* Disable all LPUART internal interrupts */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable); + /* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif + + /* Configure TX. */ + if (txDmaHandle != NULL) + { + DMA_SetCallback(txDmaHandle, LPUART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle != NULL) + { + DMA_SetCallback(rxDmaHandle, LPUART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + status_t status; + dma_transfer_config_t xferConfig; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + uint32_t address = LPUART_GetDataRegisterAddress(base); + DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), + xfer->dataSize, kDMA_MemoryToPeripheral); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt); + DMA_StartTransfer(handle->txDmaHandle); + + /* Enable LPUART TX DMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_dma_handle_t structure. + * param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_RxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + status_t status; + dma_transfer_config_t xferConfig; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + uint32_t address = LPUART_GetDataRegisterAddress(base); + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), xfer->data, sizeof(uint8_t), + xfer->dataSize, kDMA_PeripheralToMemory); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt); + DMA_StartTransfer(handle->rxDmaHandle); + + /* Enable LPUART RX DMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * param base LPUART peripheral base address + * param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + + /* Disable LPUART TX DMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, + (uint32_t)kDMA_TransactionsDoneFlag); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base LPUART peripheral base address + * param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + + /* Disable LPUART RX DMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, + (uint32_t)kDMA_TransactionsDoneFlag); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief LPUART DMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * param base LPUART peripheral base address. + * param lpuartDmaHandle LPUART handle pointer. + */ +void LPUART_TransferDMAHandleIRQ(LPUART_Type *base, void *lpuartDmaHandle) +{ + assert(lpuartDmaHandle != NULL); + + if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U) + { + lpuart_dma_handle_t *handle = (lpuart_dma_handle_t *)lpuartDmaHandle; + + /* Disable tx complete interrupt */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txState = (uint8_t)kLPUART_TxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.h new file mode 100644 index 00000000000..992163bbcf4 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_DMA_H_ +#define FSL_LPUART_DMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_dma.h" + +/*! + * @addtogroup lpuart_dma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART DMA driver version. */ +#define FSL_LPUART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_dma_handle lpuart_dma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_dma_transfer_callback_t)(LPUART_Type *base, + lpuart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART DMA handle + */ +struct _lpuart_dma_handle +{ + lpuart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * + * @note This function disables all LPUART interrupts. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleDMA(LPUART_Type *base, + lpuart_dma_handle_t *handle, + lpuart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_dma_handle_t structure. + * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base LPUART peripheral base address + * @param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base LPUART peripheral base address + * @param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART DMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * @note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * @param base LPUART peripheral base address. + * @param lpuartDmaHandle LPUART handle pointer. + */ +void LPUART_TransferDMAHandleIRQ(LPUART_Type *base, void *lpuartDmaHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_DMA_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.c new file mode 100644 index 00000000000..8c761a2feb9 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.c @@ -0,0 +1,469 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_edma.h" +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpuart_edma_c_ref_1$ + * The EDMA handle is only used by the LPUART EDMA driver, with the LPUART EDMA driver workflow, + * the callback is only called when EDMA transfer done. + * + * $Justification fsl_lpuart_edma_c_ref_2$ + * This function only handles the kLPUART_TransmissionCompleteFlag event. + * + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma" +#endif + +/*base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle); + + /* Enable tx complete interrupt */ + LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(NULL != param); + + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_edma_c_ref_1$ + */ + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (NULL != lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * + * note This function disables all LPUART interrupts. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = LPUART_GetInstance(base); + + s_lpuartEdmaPrivateHandle[instance].base = base; + s_lpuartEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (NULL != rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + /* Set LPUART_TransferEdmaHandleIRQ as DMA IRQ handler */ + s_lpuartIsr[instance] = LPUART_TransferEdmaHandleIRQ; + /* Disable all LPUART internal interrupts */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable); + /* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif + + /* Configure TX. */ + if (NULL != txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (NULL != rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success if succeed, others fail. + * retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * param base LPUART peripheral base address. + * param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle) +{ + assert(lpuartEdmaHandle != NULL); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_edma_c_ref_2$ + */ + if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U) + { + lpuart_edma_handle_t *handle = (lpuart_edma_handle_t *)lpuartEdmaHandle; + + /* Disable tx complete interrupt */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txState = (uint8_t)kLPUART_TxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.h new file mode 100644 index 00000000000..1190ed36e86 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_EDMA_H_ +#define FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART EDMA driver version. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART eDMA handle + */ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * + * @note This function disables all LPUART interrupts. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * @note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * @param base LPUART peripheral base address. + * @param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_EDMA_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/SConscript new file mode 100644 index 00000000000..3f8f39acae7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.c new file mode 100644 index 00000000000..aa946a35bd2 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rgpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rgpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +#endif /* FSL_FEATURE_SOC_PORT_COUNT */ + +static RGPIO_Type *const s_rgpioBases[] = RGPIO_BASE_PTRS; + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets the RGPIO instance according to the RGPIO base + * + * param base RGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * retval RGPIO instance + */ +uint32_t RGPIO_GetInstance(RGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_rgpioBases); instance++) + { + if (MSDK_REG_SECURE_ADDR(s_rgpioBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_rgpioBases)); + + return instance; +} + +/*! + * brief Initializes a RGPIO pin used by the board. + * + * To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the RGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * param pin RGPIO port pin number + * param config RGPIO pin configuration pointer + */ +void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config) +{ + assert(NULL != config); + + if (config->pinDirection == kRGPIO_DigitalInput) + { + base->PDDR &= ~(1UL << pin); + } + else + { + RGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1UL << pin); + } +} + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! + * brief Reads the RGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * retval The current RGPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t RGPIO_PortGetInterruptFlags(RGPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = RGPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +/*! + * brief Clears multiple RGPIO pin interrupt status flags. + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * param mask RGPIO pin number macro + */ +void RGPIO_PortClearInterruptFlags(RGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = RGPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#endif /* FSL_FEATURE_SOC_PORT_COUNT */ + +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The RGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * param mask RGPIO pin number macro + */ +void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute) +{ + base->GACR = ((uint32_t)attribute << RGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << RGPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << RGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << RGPIO_GACR_ACB3_SHIFT); +} +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets the FGPIO instance according to the RGPIO base + * + * param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * retval FGPIO instance + */ +uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_fgpioBases); instance++) + { + if (MSDK_REG_SECURE_ADDR(s_fgpioBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_fgpioBases)); + + return instance; +} + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +void FGPIO_PortInit(FGPIO_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param pin FGPIO port pin number + * param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config) +{ + assert(NULL != config); + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + + if (config->pinDirection == kRGPIO_DigitalInput) + { + base->PDDR &= ~(1UL << pin); + } + else + { + FGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1UL << pin); + } +} + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! + * brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +/*! + * brief Clears the multiple FGPIO pin interrupt status flag. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#endif /* FSL_FEATURE_SOC_PORT_COUNT */ + +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, rgpio_checker_attribute_t attribute) +{ + base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | + (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT); +} +#endif + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.h new file mode 100644 index 00000000000..2241e6a17c0 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.h @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_RGPIO_H_ +#define FSL_RGPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rgpio + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief RGPIO driver version 2.1.0. */ +#define FSL_RGPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @} */ + +/*! @brief RGPIO direction definition */ +typedef enum _rgpio_pin_direction +{ + kRGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kRGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} rgpio_pin_direction_t; + +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! @brief RGPIO checker attribute */ +typedef enum _rgpio_checker_attribute +{ + kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = + 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = + 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = + 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = + 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = + 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = + 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = + 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = + 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ + kRGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ +} rgpio_checker_attribute_t; +#endif + +#if defined(FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG) && FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG +/*! @brief Configures the interrupt generation condition. */ +typedef enum _rgpio_interrupt_sel +{ + kRGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */ + kRGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */ + kRGPIO_InterruptOutput2 = 0x2U, /*!< Interrupt/DMA request/trigger output 2. */ + kRGPIO_InterruptOutput3 = 0x3U, /*!< Interrupt/DMA request/trigger output 3. */ +} rgpio_interrupt_sel_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef enum _rgpio_interrupt_config +{ + kRGPIO_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ + kRGPIO_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kRGPIO_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kRGPIO_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ + kRGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kRGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kRGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ + kRGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kRGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kRGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kRGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kRGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ + kRGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kRGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +} rgpio_interrupt_config_t; +#endif + +/*! + * @brief The RGPIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, leave the outputConfig unused. + * Note that in some use cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig(). + */ +typedef struct _rgpio_pin_config +{ + rgpio_pin_direction_t pinDirection; /*!< RGPIO direction, input or output */ + /* Output configurations; ignore if configured as an input pin */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ +} rgpio_pin_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup rgpio_driver + * @{ + */ + +/*! @name RGPIO Configuration */ +/*! @{ */ + +/*! + * @brief Initializes a RGPIO pin used by the board. + * + * To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the RGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO port pin number + * @param config RGPIO pin configuration pointer + */ +void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config); + +/*! + * @brief Gets the RGPIO instance according to the RGPIO base + * + * @param base RGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval RGPIO instance + */ +uint32_t RGPIO_GetInstance(RGPIO_Type *base); +/*! @} */ + +/*! @name RGPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO pin number + * @param output RGPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinWrite. + */ +static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output) +{ + RGPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortSet. + */ +static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 0. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClear. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple RGPIO pins. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple RGPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortToggle. + */ +static inline void RGPIO_TogglePinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortToggle(base, mask); +} +/*! @} */ + +/*! @name RGPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the RGPIO port. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO pin number + * @retval RGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} + +/*! + * @brief Reads the current input value of the RGPIO port. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinRead. + */ +static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin) +{ + return RGPIO_PinRead(base, pin); +} + +#if defined(FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE) && FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE +/*! + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number mask + * @param enable RGPIO digital input enable/disable flag. + */ +static inline void RGPIO_EnablePortInput(RGPIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PIDR &= ~mask; + } + else + { + base->PIDR |= mask; + } +} +#endif + +/*! @} */ + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! @name RGPIO Interrupt */ +/*! @{ */ + +/*! + * @brief Reads the RGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @retval The current RGPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t RGPIO_PortGetInterruptFlags(RGPIO_Type *base); + +/*! + * @brief Reads the RGPIO port interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortGetInterruptFlags. + */ +static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base) +{ + return RGPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears multiple RGPIO pin interrupt status flags. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +void RGPIO_PortClearInterruptFlags(RGPIO_Type *base, uint32_t mask); + +/*! + * @brief Clears multiple RGPIO pin interrupt status flags. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClearInterruptFlags. + */ +static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortClearInterruptFlags(base, mask); +} +#endif +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The RGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute); +#endif + +#if defined(FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG) && FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG +/*! + * @brief Configures the gpio pin interrupt/DMA request. + * + * @param base RGPIO peripheral base pointer. + * @param pin RGPIO pin number. + * @param sel RGPIO pin interrupt selection(0-3). + * @param config RGPIO pin interrupt configuration. + */ +static inline void RGPIO_SetPinInterruptConfig(RGPIO_Type *base, + uint32_t pin, + rgpio_interrupt_sel_t sel, + rgpio_interrupt_config_t config) +{ + base->ICR[pin] = + (base->ICR[pin] & ~(RGPIO_ICR_IRQC_MASK | RGPIO_ICR_IRQS_MASK)) | RGPIO_ICR_IRQC(config) | RGPIO_ICR_IRQS(sel); +} + +/*! + * @brief Sets the gpio interrupt configuration in ICR register for multiple pins. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro. + * @param sel RGPIO pin interrupt selection(0-3). + * @param config RGPIO pin interrupt configuration. + */ +static inline void _SetMultipleInterruptPinsConfig(RGPIO_Type *base, + uint32_t mask, + rgpio_interrupt_sel_t sel, + rgpio_interrupt_config_t config) +{ + if (0U != (mask & 0xFFFFU)) + { + base->GICLR = + ((uint32_t)sel << RGPIO_ICR_IRQS_SHIFT) | ((uint32_t)config << RGPIO_ICR_IRQC_SHIFT) | (mask & 0xFFFFU); + } + mask = mask >> 16; + if (0U != mask) + { + base->GICHR = + ((uint32_t)sel << RGPIO_ICR_IRQS_SHIFT) | ((uint32_t)config << RGPIO_ICR_IRQC_SHIFT) | (mask & 0xFFFFU); + } +} + +/*! + * @brief Reads the whole gpio status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base RGPIO peripheral base pointer. + * @param sel RGPIO pin interrupt selection(0-3). + * @return Current gpio interrupt status flags, for example, 0x00010001 means the + * pin 0 and 16 have the interrupt. + */ +static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel) +{ + return base->ISFR[(uint8_t)sel]; +} + +/*! + * @brief Clears the multiple pin interrupt status flag. + * + * @param base RGPIO peripheral base pointer. + * @param sel RGPIO pin interrupt selection(0-3). + * @param mask RGPIO pin number macro. + */ +static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel, uint32_t mask) +{ + base->ISFR[(uint8_t)sel] = mask; +} +#endif + +/*! @} */ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduces the FGPIO feature. + * + * The FGPIO registers are aliased to the IOPORT interface. + * Accesses via the IOPORT interface occur in parallel with any instruction fetches and + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*! @{ */ + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * @brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base); + +/*! + * @brief Initializes the FGPIO peripheral. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortInit. + */ +static inline void FGPIO_Init(FGPIO_Type *base) +{ + FGPIO_PortInit(base); +} +#endif +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * @code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config); + +/*! + * @brief Gets the FGPIO instance according to the RGPIO base + * + * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval FGPIO instance + */ +uint32_t FGPIO_GetInstance(FGPIO_Type *base); +/*! @} */ + +/*! @name FGPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinWrite. + */ +static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + FGPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortSet. + */ +static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClear. + */ +static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortToggle. + */ +static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortToggle(base, mask); +} +/*! @} */ + +/*! @name FGPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the FGPIO port. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @retval FGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} + +/*! + * @brief Reads the current input value of the FGPIO port. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinRead + */ +static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +{ + return FGPIO_PinRead(base, pin); +} +/*! @} */ + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! @name FGPIO Interrupt */ +/*! @{ */ + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortGetInterruptFlags. + */ +static inline uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +{ + return FGPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClearInterruptFlags. + */ +static inline void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortClearInterruptFlags(base, mask); +} +#endif +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, rgpio_checker_attribute_t attribute); +#endif + +/*! @} */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_RGPIO_H_*/ diff --git a/bsp/nxp/imx/imx91/drivers/serial.c b/bsp/nxp/imx/imx91/drivers/serial.c new file mode 100644 index 00000000000..4ac9096aa1b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/serial.c @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + */ + +#include +#include +#include +#include + +#include "serial.h" + +#include "MIMX9131.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +struct hw_uart_device +{ + struct rt_serial_device serial; /* Select serial device */ + const char *device_name; /* serial device name */ + + LPUART_Type *uart_ptr; + rt_base_t uart_base; + int instance; + int irqn; + + clock_root_t clock_root; /* clock root */ + clock_root_mux_source_t clock_mux; /* clock mux */ + clock_ip_name_t clock_ip_name; /* clock control gate */ +}; + +#ifdef BSP_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = { + .device_name = "uart1", + .uart_ptr = RT_NULL, + .uart_base = LPUART1_BASE, + .instance = 1, + .irqn = LPUART1_IRQn, + .clock_root = kCLOCK_Root_Lpuart1, + .clock_mux = kCLOCK_LPUART1_ClockRoot_MuxOsc24M, + .clock_ip_name = kCLOCK_Lpuart1, +}; +#endif + +static struct hw_uart_device *hw_uart_devices[] = { +#ifdef BSP_USING_UART1 + &_uart1_device, +#endif +}; + +static void rt_hw_uart_isr(int irqn, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart = RT_NULL; + static lpuart_config_t config; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + LPUART_GetDefaultConfig(&config); + + // baud rate + config.baudRate_Bps = cfg->baud_rate; + + // data bits + switch (cfg->data_bits) + { + case DATA_BITS_8: + config.dataBitsCount = kLPUART_EightDataBits; + break; + case DATA_BITS_7: +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + config.dataBitsCount = kLPUART_SevenDataBits; + break; +#endif + default: + config.dataBitsCount = kLPUART_EightDataBits; + break; + } + + // parity bit + switch (cfg->parity) + { + case PARITY_NONE: + config.parityMode = kLPUART_ParityDisabled; + break; + case PARITY_ODD: + config.parityMode = kLPUART_ParityOdd; + break; + case PARITY_EVEN: + config.parityMode = kLPUART_ParityEven; + break; + default: + config.parityMode = kLPUART_ParityDisabled; + break; + } + + // stop bits +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + switch (cfg->stop_bits) + { + case STOP_BITS_1: + config.stopBitCount = kLPUART_OneStopBit; + break; + case STOP_BITS_2: + config.stopBitCount = kLPUART_TwoStopBit; + break; + default: + config.stopBitCount = kLPUART_OneStopBit; + break; + } +#endif + + // LSB/MSB + if (cfg->bit_order == BIT_ORDER_LSB) + { + config.isMsb = false; + } + else + { + config.isMsb = true; + } + + // hardware flow control +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + if (cfg->flowcontrol == RT_SERIAL_FLOWCONTROL_NONE) + { + // disable hardware flow control + config.enableRxRTS = false; + config.enableTxCTS = false; + } + else + { + // enable hardware flow control + config.enableRxRTS = true; + config.enableTxCTS = true; + } +#endif + + // enable TX and RX + config.enableTx = serial->parent.flag & RT_DEVICE_FLAG_WRONLY; + config.enableRx = serial->parent.flag & RT_DEVICE_FLAG_RDONLY; + + // Set UART clock source and clock divider + CLOCK_SetRootClockMux(uart->clock_root, uart->clock_mux); + CLOCK_SetRootClockDiv(uart->clock_root, 1U); + + // Initialize the LPUART module with the configuration structure and clock source + LPUART_Init(uart->uart_ptr, &config, CLOCK_GetIpFreq(uart->clock_root)); + + // Install interrupt handler + rt_hw_interrupt_install(uart->irqn, rt_hw_uart_isr, serial, "uart"); + rt_hw_interrupt_mask(uart->irqn); + + // Enable RX interrupt + LPUART_EnableInterrupts(uart->uart_ptr, kLPUART_RxDataRegFullInterruptEnable); + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + rt_hw_interrupt_mask(uart->irqn); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + rt_hw_interrupt_umask(uart->irqn); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + while (!(LPUART_GetStatusFlags(uart->uart_ptr) & kLPUART_TxDataRegEmptyFlag)) + { + __NOP(); + } + + LPUART_WriteByte(uart->uart_ptr, c); + + return 1; +} + +#ifdef BSP_USING_EARLY_CONSOLE +LPUART_Type *earlycon_base = RT_NULL; + +void rt_hw_earlycon_set(void *base) +{ + earlycon_base = (LPUART_Type *)base; +} + +void rt_hw_earlycon_ioremap(void) +{ + earlycon_base = rt_ioremap_early((void *)LPUART1, LPUART1_SIZE); +} + +void rt_hw_earlycon_putc(char c) +{ + LPUART_WriteByte(earlycon_base, c); + while (!(LPUART_GetStatusFlags(earlycon_base) & kLPUART_TxDataRegEmptyFlag)) + ; +} + +static void rt_hw_earlycon_print(const char *str, int print_newline) +{ + int has_cr = 0; + int has_lf = 0; + while (*str) + { + if (*str == '\r') + { + has_cr = 1; + } + else if (*str == '\n') + { + has_lf = 1; + } + rt_hw_earlycon_putc(*str++); + } + if (!has_cr && print_newline) + { + rt_hw_earlycon_putc('\r'); + } + if (!has_lf && print_newline) + { + rt_hw_earlycon_putc('\n'); + } +} + +void rt_hw_earlycon_puts(const char *str) +{ + rt_hw_earlycon_print(str, 1); +} + +void rt_hw_earlycon_print_hex(const char *str, rt_base_t hex) +{ + rt_hw_earlycon_print(str, 0); + rt_hw_earlycon_putc('0'); + rt_hw_earlycon_putc('x'); + for (int i = 60; i >= 0; i -= 4) + { + rt_base_t h = (hex >> i) & 0xF; + rt_hw_earlycon_putc(h < 10 ? '0' + h : 'A' + h - 10); + } + rt_hw_earlycon_putc('\r'); + rt_hw_earlycon_putc('\n'); +} +#endif + +void rt_hw_console_putc(char c) +{ +#if defined(BSP_USING_UART1) + uart_putc(&_uart1_device.serial, c); +#endif +} + +void rt_hw_console_output(const char *str) +{ +#if defined(BSP_USING_UART1) + int has_cr = 0; + int has_lf = 0; + while (*str) + { + if (*str == '\r') + { + has_cr = 1; + } + else if (*str == '\n') + { + has_lf = 1; + } + rt_hw_console_putc(*str++); + } + if (!has_cr) + { + rt_hw_console_putc('\r'); + } + if (!has_lf) + { + rt_hw_console_putc('\n'); + } +#endif +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + uint32_t flags = LPUART_GetStatusFlags(uart->uart_ptr); + if (flags & kLPUART_RxDataRegFullFlag) + { + ch = LPUART_ReadByte(uart->uart_ptr); + } + else + { + ch = -1; + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = { + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +int rt_hw_uart_init(void) +{ + struct serial_configure config; + + /* setup default serial configure */ + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + /* Remap CCM controller to virtual address */ + CCM_CTRL = rt_ioremap((void *)CCM_CTRL_BASE, CCM_CTRL_SIZE); + + for (int i = 0; i < RT_ARRAY_SIZE(hw_uart_devices); i++) + { + if (hw_uart_devices[i] != RT_NULL) + { + hw_uart_devices[i]->serial.ops = &_uart_ops; + hw_uart_devices[i]->serial.config = config; + + /* Remap LPUART instance to virtual address */ + hw_uart_devices[i]->uart_ptr = rt_ioremap((void *)hw_uart_devices[i]->uart_base, LPUART1_SIZE); + + /* Update LPUART instance */ + LPUART_SetInstance(hw_uart_devices[i]->instance, hw_uart_devices[i]->uart_ptr); + + rt_hw_serial_register(&hw_uart_devices[i]->serial, hw_uart_devices[i]->device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, hw_uart_devices[i]); + } + } + + return 0; +} diff --git a/bsp/nxp/imx/imx91/drivers/serial.h b/bsp/nxp/imx/imx91/drivers/serial.h new file mode 100644 index 00000000000..93f53bc1a9d --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/serial.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include "board.h" + +#include + +int rt_hw_uart_init(void); + +#ifdef BSP_USING_EARLY_CONSOLE +void rt_hw_earlycon_ioremap(void); +void rt_hw_earlycon_putc(char c); +void rt_hw_earlycon_puts(const char *str); +void rt_hw_earlycon_print_hex(const char *str, rt_base_t hex); +#else +static inline void rt_hw_earlycon_ioremap(void) {} +static inline void rt_hw_earlycon_putc(char c) {} +static inline void rt_hw_earlycon_puts(const char *str) {} +static inline void rt_hw_earlycon_print_hex(const char *str, rt_base_t hex) {} +#endif + +void rt_hw_console_putc(char c); +void rt_hw_console_output(const char *str); + +#endif + + diff --git a/bsp/nxp/imx/imx91/rtconfig.h b/bsp/nxp/imx/imx91/rtconfig.h new file mode 100644 index 00000000000..6e279d91c8c --- /dev/null +++ b/bsp/nxp/imx/imx91/rtconfig.h @@ -0,0 +1,468 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 16 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 8192 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 8192 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_THREADSAFE_PRINTF +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ + +/* AArch64 Architecture Configuration */ + +#define ARCH_TEXT_OFFSET 0x0 +#define ARCH_RAM_OFFSET 0x80000000 +#define ARCH_SECONDARY_CPU_STACK_SIZE 4096 +#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_USING_GENERIC_CPUID +#define ARCH_HEAP_SIZE 0x2000000 +#define ARCH_INIT_PAGE_SIZE 0x8000000 +/* end of AArch64 Architecture Configuration */ +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define RT_USING_HW_ATOMIC +#define ARCH_ARM_BOOTWITH_FLUSH_CACHE +#define RT_USING_CPU_FFS +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define ARCH_ARM_CORTEX_A +#define RT_NO_USING_GIC +#define ARCH_ARM_CORTEX_A55 +#define RT_BACKTRACE_FUNCTION_NAME +#define ARCH_ARMV8 +#define ARCH_USING_ASID +#define ARCH_USING_HW_THREAD_SELF +#define ARCH_USING_IRQ_CTX_LIST + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 8092 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +#define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +/* end of Utilities */ + +/* Memory management */ + +#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000 +#define RT_PAGE_MAX_ORDER 11 + +/* Debugging */ + +/* end of Debugging */ +/* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define BOARD_IMX91 +#define SOC_MIMX91X1D + +/* Hardware Drivers Config */ + +#define BSP_USING_EARLY_CONSOLE +#define BSP_USING_UART1 +#define BSP_USING_GIC +#define BSP_USING_GICV3 +#define KERNEL_ASPACE_START 0x1000000 +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/imx/imx91/rtconfig.py b/bsp/nxp/imx/imx91/rtconfig.py new file mode 100644 index 00000000000..b162a6a6a28 --- /dev/null +++ b/bsp/nxp/imx/imx91/rtconfig.py @@ -0,0 +1,58 @@ +import os + +# toolchains options +ARCH = 'aarch64' +CPU = 'cortex-a' +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..') + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# only support GNU GCC compiler. +PLATFORM = 'gcc' +EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + CPP = PREFIX + 'cpp' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=armv8-a -mtune=cortex-a55' + DEVICE += ' -fno-omit-frame-pointer -ffunction-sections -fdata-sections' + CPPFLAGS = ' -E -P -x assembler-with-cpp' + CFLAGS = DEVICE + ' -Wall -Wno-cpp' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + CPPFLAGS += ' -O0 -ggdb' + else: + CFLAGS += ' -O2 -ggdb' + CPPFLAGS += ' -O2 -ggdb' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + SIZE + ' $TARGET \n' + DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > disasm.txt\n' From a5e0bfd36a14a2667bedfb90220c2d6d00ebc894 Mon Sep 17 00:00:00 2001 From: lct1001 <2739960959@qq.com> Date: Wed, 10 Dec 2025 09:34:21 +0800 Subject: [PATCH 06/20] components:libc:cplusplus:os/utest:Some comments have been initially added. Some comments have been initially added as a bignner task. components/libc/cplusplus/os/cxx_Semaphore.cpp components/libc/cplusplus/os/cxx_Thread.cpp components/libc/cplusplus/utest/tc_atomic.cpp components/libc/cplusplus/utest/tc_smartptr.cpp components/libc/cplusplus/utest/tc_thread.cpp Signed-off-by:Liu Chengtao<2739960959@qq.com> --- .../libc/cplusplus/os/cxx_Semaphore.cpp | 16 ++++++ components/libc/cplusplus/os/cxx_Thread.cpp | 46 ++++++++++++++++- components/libc/cplusplus/utest/tc_atomic.cpp | 49 ++++++++++++------- .../libc/cplusplus/utest/tc_smartptr.cpp | 15 +++++- components/libc/cplusplus/utest/tc_thread.cpp | 31 ++++++++++-- 5 files changed, 132 insertions(+), 25 deletions(-) diff --git a/components/libc/cplusplus/os/cxx_Semaphore.cpp b/components/libc/cplusplus/os/cxx_Semaphore.cpp index 672eeb04afe..e0dbeb158a8 100644 --- a/components/libc/cplusplus/os/cxx_Semaphore.cpp +++ b/components/libc/cplusplus/os/cxx_Semaphore.cpp @@ -11,11 +11,21 @@ using namespace rtthread; +/** + * @brief Semaphore class constructor. + * @param name Semaphore name + * @param count Initial semaphore count + */ Semaphore::Semaphore(const char *name, int32_t count) { rt_sem_init(&mID, name, count, RT_IPC_FLAG_FIFO); } +/** + * @brief Wait on the semaphore. + * @param millisec Timeout in milliseconds (-1 for infinite wait). + * @return true if the semaphore was successfully taken, false on timeout. + */ bool Semaphore::wait(int32_t millisec) { rt_int32_t tick; @@ -28,11 +38,17 @@ bool Semaphore::wait(int32_t millisec) return rt_sem_take(&mID, tick) == RT_EOK; } +/** + * @brief Release the semaphore. + */ void Semaphore::release(void) { rt_sem_release(&mID); } +/** + * @brief Detach the semaphore when the object is destroyed. + */ Semaphore::~Semaphore() { rt_sem_detach(&mID); diff --git a/components/libc/cplusplus/os/cxx_Thread.cpp b/components/libc/cplusplus/os/cxx_Thread.cpp index f3484bb1f49..dc444c255bf 100644 --- a/components/libc/cplusplus/os/cxx_Thread.cpp +++ b/components/libc/cplusplus/os/cxx_Thread.cpp @@ -11,6 +11,13 @@ using namespace rtthread; +/** + * @brief Thread class constructor with parameters for stack size, priority, tick, and name. + * @param stack_size Stack size in bytes + * @param priority Thread priority + * @param tick Time slice in ticks + * @param name Thread name + */ Thread::Thread(rt_uint32_t stack_size, rt_uint8_t priority, rt_uint32_t tick, @@ -27,6 +34,15 @@ Thread::Thread(rt_uint32_t stack_size, tick); } +/** + * @brief Thread class constructor with entry function and parameters. + * @param entry The entry function pointer for the thread. + * @param p The parameter to pass to the entry function. + * @param stack_size The size of the thread stack in bytes. + * @param priority The priority of the thread. + * @param tick The time slice (tick) for the thread. + * @param name The name of the thread. + */ Thread::Thread(void (*entry)(void *p), void *p, rt_uint32_t stack_size, @@ -45,12 +61,19 @@ Thread::Thread(void (*entry)(void *p), tick); } +/** + * @brief Detach the event and delete the thread when the object is destroyed. + */ Thread::~Thread() { rt_event_detach(&_event); rt_thread_delete(_thread); } +/** + * @brief Start the thread execution. + * @return true if the thread was successfully started. + */ bool Thread::start() { if (rt_thread_startup(_thread) == RT_EOK) @@ -61,6 +84,10 @@ bool Thread::start() return started; } +/** + * @brief Make the thread sleep for a specified duration. + * @param millisec Duration in milliseconds. + */ void Thread::sleep(int32_t millisec) { rt_int32_t tick; @@ -73,6 +100,9 @@ void Thread::sleep(int32_t millisec) rt_thread_delay(tick); } +/** + * @brief Function to run the thread's entry function. + */ void Thread::func(Thread *pThis) { if (pThis->_entry != RT_NULL) @@ -87,22 +117,34 @@ void Thread::func(Thread *pThis) rt_event_send(&pThis->_event, 1); } +/** + * @brief Default run function that can be overridden by subclasses. + */ void Thread::run(void *parameter) { /* please overload this method */ } +/** + * @brief Wait for the thread to complete with a timeout. + * @param millisec Timeout in milliseconds. + * @return RT_EOK if the thread completed within the timeout, error code otherwise. + */ rt_err_t Thread::wait(int32_t millisec) { return join(millisec); } +/** + * @brief Join the thread with a timeout. + * @param millisec Timeout in milliseconds. + * @return RT_EOK if the thread completed within the timeout, error code otherwise. + */ rt_err_t Thread::join(int32_t millisec) { if (started) { rt_int32_t tick; - if (millisec < 0) tick = -1; else @@ -114,4 +156,4 @@ rt_err_t Thread::join(int32_t millisec) { return -RT_ENOSYS; } -} +} \ No newline at end of file diff --git a/components/libc/cplusplus/utest/tc_atomic.cpp b/components/libc/cplusplus/utest/tc_atomic.cpp index 8b5bdbd9bad..ae7c3b88410 100644 --- a/components/libc/cplusplus/utest/tc_atomic.cpp +++ b/components/libc/cplusplus/utest/tc_atomic.cpp @@ -20,7 +20,7 @@ */ static void test_atomic_load_store_int32(void) { - constexpr int kRound = 10000000; + constexpr int kRound = 10000000; std::atomic thread_count(0); std::atomic count(100); uassert_int_equal(count.load(), 100); @@ -56,7 +56,7 @@ static void test_atomic_load_store_int32(void) */ static void test_atomic_load_store_int64(void) { - constexpr int kRound = 10000000; + constexpr int kRound = 10000000; std::atomic thread_count(0); std::atomic count(100); uassert_int_equal(count.load(), 100); @@ -112,7 +112,7 @@ static void test_atomic_basic_int32(void) val.fetch_and(14); uassert_int_equal(val.load(), 10); - val.fetch_or(11); //1010 + val.fetch_or(11); /* 1010 */ uassert_int_equal(val.load(), 11); val.fetch_xor(4); @@ -121,9 +121,9 @@ static void test_atomic_basic_int32(void) val.exchange(1); uassert_int_equal(val.load(), 1); - int32_t x = 2; - int32_t y = 3; - bool exchanged = val.compare_exchange_strong(x, y); + int32_t x = 2; + int32_t y = 3; + bool exchanged = val.compare_exchange_strong(x, y); uassert_false(exchanged); uassert_int_equal(val.load(), 1); uassert_int_equal(x, 1); @@ -159,7 +159,7 @@ static void test_atomic_basic_int64(void) val.fetch_and(14); uassert_int_equal(val.load(), 10); - val.fetch_or(11); //1010 + val.fetch_or(11); /* 1010 */ uassert_int_equal(val.load(), 11); val.fetch_xor(4); @@ -168,9 +168,9 @@ static void test_atomic_basic_int64(void) val.exchange(1); uassert_int_equal(val.load(), 1); - int64_t x = 2; - int64_t y = 3; - bool exchanged = val.compare_exchange_strong(x, y); + int64_t x = 2; + int64_t y = 3; + bool exchanged = val.compare_exchange_strong(x, y); uassert_false(exchanged); uassert_int_equal(val.load(), 1); uassert_int_equal(x, 1); @@ -191,7 +191,7 @@ static void test_atomic_bool(void) flag.exchange(false); uassert_false(flag.load()); bool expected = false; - bool desired = true; + bool desired = true; uassert_true(flag.compare_exchange_strong(expected, desired)); uassert_true(flag.load()); } @@ -201,7 +201,7 @@ static void test_atomic_bool(void) */ static void test_atomic_pointer(void) { - int a = 1, b = 2; + int a = 1, b = 2; std::atomic ptr(&a); ptr.store(&b); uassert_int_equal(*ptr.load(), 2); @@ -217,7 +217,7 @@ static void test_memory_order(void) { std::atomic x(0); std::atomic y(0); - // Simple test for memory order + /* Simple test for memory order */ x.store(1, std::memory_order_release); y.store(2, std::memory_order_release); uassert_int_equal(x.load(std::memory_order_acquire), 1); @@ -230,25 +230,36 @@ static void test_memory_order(void) static void test_compare_exchange_weak(void) { std::atomic val(1); - int expected = 1; - int desired = 2; + int expected = 1; + int desired = 2; while (!val.compare_exchange_weak(expected, desired)) { - expected = 1; // reset + /* Reset */ + expected = 1; } uassert_int_equal(val.load(), 2); } - +/** + * @brief Test case initialization function. + * @return RT_EOK on success. + */ static rt_err_t utest_tc_init(void) { return RT_EOK; } +/** + * @brief Test case cleanup function. + * @return RT_EOK on success. + */ static rt_err_t utest_tc_cleanup(void) { return RT_EOK; } +/** + * @brief Main test case function that runs the test. + */ static void testcase(void) { /* Test load and store operations for int32_t atomic variables in multi-threaded environment */ @@ -268,4 +279,6 @@ static void testcase(void) /* Test compare_exchange_weak operation */ UTEST_UNIT_RUN(test_compare_exchange_weak); } -UTEST_TC_EXPORT(testcase, "components.libc.cpp.atomic_tc", utest_tc_init, utest_tc_cleanup, 10); + +/* Export the test case with initialization and cleanup functions and a timeout of 10 ticks. */ +UTEST_TC_EXPORT(testcase, "components.libc.cpp.atomic_tc", utest_tc_init, utest_tc_cleanup, 10); \ No newline at end of file diff --git a/components/libc/cplusplus/utest/tc_smartptr.cpp b/components/libc/cplusplus/utest/tc_smartptr.cpp index 1a9fa7eb116..c75149c8507 100644 --- a/components/libc/cplusplus/utest/tc_smartptr.cpp +++ b/components/libc/cplusplus/utest/tc_smartptr.cpp @@ -35,16 +35,27 @@ static void test_shared_ptr(void) uassert_int_equal(p1.use_count(), 2); } +/** + * @brief Test case initialization function. + * @return RT_EOK on success. + */ static rt_err_t utest_tc_init(void) { return RT_EOK; } +/** + * @brief Test case cleanup function. + * @return RT_EOK on success. + */ static rt_err_t utest_tc_cleanup(void) { return RT_EOK; } +/** + * @brief Main test case function that runs the test. + */ static void testcase(void) { /* Test unique_ptr basic operations */ @@ -52,4 +63,6 @@ static void testcase(void) /* Test shared_ptr basic operations */ UTEST_UNIT_RUN(test_shared_ptr); } -UTEST_TC_EXPORT(testcase, "components.libc.cpp.smartptr_tc", utest_tc_init, utest_tc_cleanup, 10); + +/* Export the test case with initialization and cleanup functions and a timeout of 10 ticks. */ +UTEST_TC_EXPORT(testcase, "components.libc.cpp.smartptr_tc", utest_tc_init, utest_tc_cleanup, 10); \ No newline at end of file diff --git a/components/libc/cplusplus/utest/tc_thread.cpp b/components/libc/cplusplus/utest/tc_thread.cpp index c60a9ab6025..2f81da5c416 100644 --- a/components/libc/cplusplus/utest/tc_thread.cpp +++ b/components/libc/cplusplus/utest/tc_thread.cpp @@ -12,25 +12,34 @@ #include "utest.h" #include + +/** + * @brief Function to test thread functionality. + */ static void test_thread(void) { int count = 0; - auto func = [&]() mutable - { + + /* Lambda function to increment the count. */ + auto func = [&]() mutable { for (int i = 0; i < 100; ++i) { ++count; } }; + /* Create and run a thread executing the lambda function. */ std::thread t1(func); + /* Wait for the thread to finish execution. */ t1.join(); + /* Verify if the count is as expected after the first thread execution. */ if (count != 100) { uassert_false(1); } + /* Create and run another thread executing the same lambda function. */ std::thread t2(func); t2.join(); @@ -39,21 +48,35 @@ static void test_thread(void) uassert_false(1); } + /* If both assertions passed, the test is successful. */ uassert_true(1); } + +/** + * @brief Test case initialization function. + * @return RT_EOK on success. + */ static rt_err_t utest_tc_init(void) { return RT_EOK; } - +/** + * @brief Test case cleanup function. + * @return RT_EOK on success. + */ static rt_err_t utest_tc_cleanup(void) { return RT_EOK; } +/** + * @brief Main test case function that runs the test. + */ static void testcase(void) { UTEST_UNIT_RUN(test_thread); } -UTEST_TC_EXPORT(testcase, "components.libc.cpp.thread_tc", utest_tc_init, utest_tc_cleanup, 10); + +/* Export the test case with initialization and cleanup functions and a timeout of 10 ticks. */ +UTEST_TC_EXPORT(testcase, "components.libc.cpp.thread_tc", utest_tc_init, utest_tc_cleanup, 10); \ No newline at end of file From b404016e595a09f8221272f5d7c713fdccaeb14e Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Fri, 12 Dec 2025 16:12:31 +0800 Subject: [PATCH 07/20] [dm][pmdomain] make DM Kconfig import Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/Kconfig | 1 + components/drivers/pmdomain/Kconfig | 6 ++++++ components/drivers/pmdomain/SConscript | 15 +++++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 components/drivers/pmdomain/Kconfig create mode 100644 components/drivers/pmdomain/SConscript diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index de082cd6ad4..84ffcad62fa 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -32,6 +32,7 @@ rsource "block/Kconfig" rsource "scsi/Kconfig" rsource "regulator/Kconfig" rsource "reset/Kconfig" +rsource "pmdomain/Kconfig" rsource "thermal/Kconfig" rsource "virtio/Kconfig" rsource "nvmem/Kconfig" diff --git a/components/drivers/pmdomain/Kconfig b/components/drivers/pmdomain/Kconfig new file mode 100644 index 00000000000..3d899f74633 --- /dev/null +++ b/components/drivers/pmdomain/Kconfig @@ -0,0 +1,6 @@ +if RT_USING_DM +menu "Power Management (PM) Domains device drivers" + + osource "$(SOC_DM_PMDOMAIN_DIR)/Kconfig" +endmenu +endif diff --git a/components/drivers/pmdomain/SConscript b/components/drivers/pmdomain/SConscript new file mode 100644 index 00000000000..957416cfca9 --- /dev/null +++ b/components/drivers/pmdomain/SConscript @@ -0,0 +1,15 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_DM']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = [] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') From 1e61fbdf2a93643b2c79321b3c4b255aa0a66496 Mon Sep 17 00:00:00 2001 From: GUI <39894654+GuEe-GUI@users.noreply.github.com> Date: Sat, 13 Dec 2025 16:32:25 +0800 Subject: [PATCH 08/20] [dm][hwcache] support hwcache (#11049) Some ARCH not has std cache ops, such as RISC-V Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/Kconfig | 1 + components/drivers/hwcache/Kconfig | 9 ++ components/drivers/hwcache/SConscript | 15 ++ components/drivers/hwcache/hwcache.c | 139 +++++++++++++++++++ components/drivers/include/drivers/hwcache.h | 48 +++++++ components/drivers/include/rtdevice.h | 4 + 6 files changed, 216 insertions(+) create mode 100644 components/drivers/hwcache/Kconfig create mode 100644 components/drivers/hwcache/SConscript create mode 100644 components/drivers/hwcache/hwcache.c create mode 100644 components/drivers/include/drivers/hwcache.h diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 84ffcad62fa..87e37864bd0 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -30,6 +30,7 @@ rsource "ata/Kconfig" rsource "nvme/Kconfig" rsource "block/Kconfig" rsource "scsi/Kconfig" +rsource "hwcache/Kconfig" rsource "regulator/Kconfig" rsource "reset/Kconfig" rsource "pmdomain/Kconfig" diff --git a/components/drivers/hwcache/Kconfig b/components/drivers/hwcache/Kconfig new file mode 100644 index 00000000000..6936dd1ff30 --- /dev/null +++ b/components/drivers/hwcache/Kconfig @@ -0,0 +1,9 @@ +menuconfig RT_USING_HWCACHE + bool "Using Hardware Cache device drivers" + depends on RT_USING_DM + depends on RT_USING_CACHE + default n + +if RT_USING_HWCACHE + osource "$(SOC_DM_HWCACHE_DIR)/Kconfig" +endif diff --git a/components/drivers/hwcache/SConscript b/components/drivers/hwcache/SConscript new file mode 100644 index 00000000000..6d16ba02e6b --- /dev/null +++ b/components/drivers/hwcache/SConscript @@ -0,0 +1,15 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_HWCACHE']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['hwcache.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/drivers/hwcache/hwcache.c b/components/drivers/hwcache/hwcache.c new file mode 100644 index 00000000000..65029bf66ec --- /dev/null +++ b/components/drivers/hwcache/hwcache.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include + +#define DBG_TAG "rtdm.hwcache" +#define DBG_LVL DBG_INFO +#include + +struct rt_hwcache_ops *rt_dm_cpu_dcache_ops = RT_NULL; +struct rt_hwcache_ops *rt_dm_cpu_icache_ops = RT_NULL; + +static void hwcache_enable(struct rt_hwcache_ops *ops) +{ + if (ops && ops->enable) + { + ops->enable(); + } +} + +static void hwcache_disable(struct rt_hwcache_ops *ops) +{ + if (ops && ops->enable) + { + ops->enable(); + } +} + +static rt_base_t hwcache_status(struct rt_hwcache_ops *ops) +{ + if (ops && ops->status) + { + return ops->status(); + } + + return 0; +} + +static void hwcache_ops(struct rt_hwcache_ops *ops, int op, void *addr, int size) +{ + if (ops) + { + if (op == RT_HW_CACHE_FLUSH) + { + if (ops->flush) + { + ops->flush(addr, size); + } + } + else if (op == RT_HW_CACHE_INVALIDATE) + { + if (ops->invalidate) + { + ops->invalidate(addr, size); + } + } + } +} + +void rt_hwcache_icache_enable(void) +{ + hwcache_enable(rt_dm_cpu_icache_ops); +} + +void rt_hwcache_icache_disable(void) +{ + hwcache_disable(rt_dm_cpu_icache_ops); +} + +rt_base_t rt_hwcache_icache_status(void) +{ + return hwcache_status(rt_dm_cpu_icache_ops); +} + +void rt_hwcache_icache_ops(int ops, void *addr, int size) +{ + hwcache_ops(rt_dm_cpu_icache_ops, ops, addr, size); +} + +void rt_hwcache_dcache_enable(void) +{ + hwcache_enable(rt_dm_cpu_dcache_ops); +} + +void rt_hwcache_dcache_disable(void) +{ + hwcache_disable(rt_dm_cpu_dcache_ops); +} + +rt_base_t rt_hwcache_dcache_status(void) +{ + return hwcache_status(rt_dm_cpu_dcache_ops); +} + +void rt_hwcache_dcache_ops(int ops, void *addr, int size) +{ + hwcache_ops(rt_dm_cpu_dcache_ops, ops, addr, size); +} + +#ifdef RT_USING_OFW +RT_OFW_STUB_RANGE_EXPORT(hwcache, _hwcache_ofw_start, _hwcache_ofw_end); + +static rt_err_t ofw_hwcache_init(void) +{ + struct rt_ofw_node *cache_np; + + rt_ofw_foreach_allnodes(cache_np) + { + rt_ofw_stub_probe_range(cache_np, &_hwcache_ofw_start, &_hwcache_ofw_end); + } + + return RT_EOK; +} +#else +static rt_err_t ofw_hwcache_init(void) +{ + return RT_EOK; +} +#endif /* !RT_USING_OFW */ + +rt_err_t rt_hwcache_init(void) +{ + rt_err_t err; + + LOG_D("init start"); + + err = ofw_hwcache_init(); + + LOG_D("init end"); + + return err; +} diff --git a/components/drivers/include/drivers/hwcache.h b/components/drivers/include/drivers/hwcache.h new file mode 100644 index 00000000000..048dd303bdb --- /dev/null +++ b/components/drivers/include/drivers/hwcache.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __HWCACHE_H__ +#define __HWCACHE_H__ + +#include +#include +#include + +struct rt_hwcache_ops +{ + const char *name; + + void (*enable)(void); + void (*disable)(void); + + rt_base_t (*status)(void); + + void (*flush)(void *vaddr, rt_size_t size); + void (*invalidate)(void *vaddr, rt_size_t size); +}; + +extern struct rt_hwcache_ops *rt_dm_cpu_dcache_ops; +extern struct rt_hwcache_ops *rt_dm_cpu_icache_ops; + +#define RT_HWCACHE_OFW_DECLARE(name, ids, handler) RT_OFW_STUB_EXPORT(name, ids, hwcache, handler) + +void rt_hwcache_icache_enable(void); +void rt_hwcache_icache_disable(void); +rt_base_t rt_hwcache_icache_status(void); +void rt_hwcache_icache_ops(int ops, void *addr, int size); + +void rt_hwcache_dcache_enable(void); +void rt_hwcache_dcache_disable(void); +rt_base_t rt_hwcache_dcache_status(void); +void rt_hwcache_dcache_ops(int ops, void *addr, int size); + +rt_err_t rt_hwcache_init(void); + +#endif /* __HWCACHE_H__ */ diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index d55a41f30b7..89af4b933c0 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -130,6 +130,10 @@ extern "C" { #include "drivers/thermal.h" #endif /* RT_USING_THERMAL */ +#ifdef RT_USING_HWCACHE +#include "drivers/hwcache.h" +#endif /* RT_USING_HWCACHE */ + #ifdef RT_USING_NVMEM #include "drivers/nvmem.h" #endif /* RT_USING_NVMEM */ From 5c38e7502eb1aa5dd54b368954bad833c60833ef Mon Sep 17 00:00:00 2001 From: GUI <39894654+GuEe-GUI@users.noreply.github.com> Date: Sat, 13 Dec 2025 16:33:05 +0800 Subject: [PATCH 09/20] [dm][pinctrl] Set pinctrl default auto in platform bus. (#11052) Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/core/platform.c | 8 ++++++++ components/drivers/serial/dev_serial.c | 5 ----- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/components/drivers/core/platform.c b/components/drivers/core/platform.c index d308dd08065..48b7077a03d 100644 --- a/components/drivers/core/platform.c +++ b/components/drivers/core/platform.c @@ -18,6 +18,7 @@ #ifdef RT_USING_CLK #include #endif +#include #include #include #include @@ -122,6 +123,13 @@ static rt_err_t platform_probe(rt_device_t dev) struct rt_ofw_node *np = dev->ofw_node; #endif +#ifdef RT_USING_PINCTRL + if (rt_pin_ctrl_confs_apply_by_name(dev, RT_NULL)) + { + rt_pin_ctrl_confs_apply(dev, 0); + } +#endif + #ifdef RT_USING_CLK if ((err = rt_ofw_clk_set_defaults(dev->ofw_node))) { diff --git a/components/drivers/serial/dev_serial.c b/components/drivers/serial/dev_serial.c index 3ebe3063ace..45bf97c3289 100644 --- a/components/drivers/serial/dev_serial.c +++ b/components/drivers/serial/dev_serial.c @@ -664,11 +664,6 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) /* get open flags */ dev->open_flag = oflag & 0xff; -#ifdef RT_USING_PINCTRL - /* initialize iomux in DM */ - rt_pin_ctrl_confs_apply_by_name(dev, RT_NULL); -#endif - /* initialize the Rx/Tx structure according to open flag */ if (serial->serial_rx == RT_NULL) { From 1b8e3732b99708ee09ac29dda679c4c435b3b551 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Sat, 13 Dec 2025 01:24:54 +0800 Subject: [PATCH 10/20] [dm][core] Update the OFW CLk init flow The clock should init before common platform devices. Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/core/platform_ofw.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/components/drivers/core/platform_ofw.c b/components/drivers/core/platform_ofw.c index dbe091935e9..38065dd3eb5 100644 --- a/components/drivers/core/platform_ofw.c +++ b/components/drivers/core/platform_ofw.c @@ -267,6 +267,12 @@ static int platform_ofw_device_probe(void) if (ofw_node_root) { + if ((node = rt_ofw_find_node_by_path("/clocks"))) + { + platform_ofw_device_probe_once(node); + rt_ofw_node_put(node); + } + rt_ofw_node_get(ofw_node_root); err = platform_ofw_device_probe_once(ofw_node_root); @@ -279,12 +285,6 @@ static int platform_ofw_device_probe(void) rt_ofw_node_put(node); } - if ((node = rt_ofw_find_node_by_path("/clocks"))) - { - platform_ofw_device_probe_once(node); - rt_ofw_node_put(node); - } - rt_ofw_node_get(ofw_node_chosen); if ((node = rt_ofw_get_child_by_compatible(ofw_node_chosen, "simple-framebuffer"))) { From ea5e21833e414381afdf189c39d473596c8947bb Mon Sep 17 00:00:00 2001 From: lhxj <2743257167@qq.com> Date: Fri, 12 Dec 2025 19:09:13 +0800 Subject: [PATCH 11/20] Most test cases in `src/utest` lack standardized functional documentation, as tracked in issue [#10895](https://github.com/RT-Thread/rt-thread/issues/10895). This leads to high maintenance costs, difficulty for new contributors, and inefficient code reviews. Solution: This patch adds the full, standardized documentation block to `sched_mtx_tc.c`, `sched_sem_tc.c`, `sched_thread_tc.c`, `sched_timed_mtx_tc.c` and `sched_timed_sem_tc.c` following the approved template. The documentation details: - Test Objectives and tested APIs - Test Scenarios - Verification Metrics - Dependencies - Test Execution command and Expected Results This makes the test case's purpose and behavior immediately clear to future maintainers and reviewers. Relates to [#10895](https://github.com/RT-Thread/rt-thread/issues/10895) Signed-off-by: lhxj <2743257167@qq.com> --- src/utest/sched_mtx_tc.c | 49 +++++++++++++++++++++++++++++++ src/utest/sched_sem_tc.c | 53 ++++++++++++++++++++++++++++++++++ src/utest/sched_thread_tc.c | 51 ++++++++++++++++++++++++++++++++ src/utest/sched_timed_mtx_tc.c | 47 ++++++++++++++++++++++++++++++ src/utest/sched_timed_sem_tc.c | 49 +++++++++++++++++++++++++++++++ 5 files changed, 249 insertions(+) diff --git a/src/utest/sched_mtx_tc.c b/src/utest/sched_mtx_tc.c index dbd6af873a8..bc62084b2d3 100644 --- a/src/utest/sched_mtx_tc.c +++ b/src/utest/sched_mtx_tc.c @@ -6,7 +6,56 @@ * Change Logs: * Date Author Notes * 2024-01-17 Shell the first version + * 2025-12-12 lhxj Add standardized utest documentation block */ + +/** + * Test Case Name: Scheduler Mutex Stress Test (core.scheduler_mutex) + * + * Test Objectives: + * - Validate the stability of the Mutex subsystem under high contention (Stress Test). + * - Ensure priority inheritance (if supported) or basic blocking/waking works correctly. + * - In multi-core systems, verify data consistency and spinlock mechanisms when multiple cores contend for a single kernel object simultaneously. + * - List specific functions or APIs to be tested: + * - rt_mutex_take() + * - rt_mutex_release() + * - rt_thread_create() + * + * Test Scenarios: + * - **Stress Test (mutex_stress_tc):** + * 1. Create `RT_CPUS_NR` threads (e.g., 4 threads in a Quad-Core setup). + * 2. Assign **staggered priorities** to these threads (`priority_base + i % range`) to simulate contention between high and low priority tasks. + * 3. All tester threads execute a tight loop: attempting to take and immediately release the *same* global mutex (`_racing_lock`). + * - In SMP, this simulates true parallel contention. + * 4. The main test thread sleeps for `TEST_SECONDS` (30s), periodically printing progress. + * 5. After time is up, signal threads to exit (`_exit_flag`) and wait for them using a semaphore (`_thr_exit_sem`). + * + * Verification Metrics: + * - **Pass:** The system must remain responsive (no deadlocks, hard faults, or RCU stalls) during the 30-second run. + * - **Pass:** The main thread must successfully wait for all tester threads to exit (`rt_sem_take` returns `RT_EOK`). + * - **Pass:** `uassert_true(1)` is executed periodically, confirming the main loop is alive. + * + * Dependencies: + * - Hardware requirements (e.g., specific peripherals) + * - No specific peripherals required, but Multi-core CPU recommended for SMP testing. + * (This is met by the qemu-virt64-riscv BSP). + * - Software configuration (e.g., kernel options, driver initialization) + * - `RT_USING_UTEST` must be enabled (`RT-Thread Utestcases`). + * - `Scheduler Test` must be enabled (`RT-Thread Utestcases` -> `Kernel Core` -> 'Scheduler Test'). + * - (Optional) Enable SMP for parallel testing: + * - Go to `RT-Thread Kernel` -> `Enable SMP (Symmetric multiprocessing)`. + * - Set `Number of CPUs` to > 1 (e.g., 4). + * - Environmental assumptions + * - Requires sufficient heap memory to allocate stacks for `RT_CPUS_NR` threads. + * - Run the test case from the msh prompt: + * `utest_run core.scheduler_mutex` + * + * Expected Results: + * - The test continues for approximately 30 seconds. + * - The console logs periodic success assertions. + * - Final Output: `[ PASSED ] [ result ] testcase (core.scheduler_mutex)` + */ + #include #include #include "utest.h" diff --git a/src/utest/sched_sem_tc.c b/src/utest/sched_sem_tc.c index bfc9aac91f0..4a2fd00f2bc 100644 --- a/src/utest/sched_sem_tc.c +++ b/src/utest/sched_sem_tc.c @@ -6,7 +6,60 @@ * Change Logs: * Date Author Notes * 2024-01-17 Shell the first version + * 2025-12-12 lhxj Add standardized utest documentation block */ + +/** + * Test Case Name: Priority Based Semaphore Synchronization Test (core.scheduler_sem) + * + * Test Objectives: + * - Verify the stability and correctness of the scheduler under high concurrency. + * - Verify thread synchronization and execution order using Semaphore chains across different priority levels. + * - Verify SMP (Symmetric Multiprocessing) load balancing and atomic operations in a multi-core environment. + * - List specific functions or APIs to be tested: + * - rt_sem_init + * - rt_sem_take + * - rt_sem_release + * - rt_thread_create + * - rt_thread_startup + * - rt_atomic_add + * + * Test Scenarios: + * - **Semaphore Chained Scheduling:** + * 1. Initialize a "thread matrix" where threads are created across multiple priority levels (`TEST_LEVEL_COUNTS`). + * 2. For each priority level, create multiple concurrent threads (`RT_CPUS_NR * 2`). + * 3. Establish a dependency chain (Ring Topology): + * - **Level 0 threads:** Notify Level 1, then wait for their own resource. + * - **Middle Level threads:** Wait for their resource (notified by Level N-1), then notify Level N+1. + * - **Last Level threads:** Wait for their resource, print status (CPU ID), delay, then notify Level 0. + * 4. Each thread increments an atomic load counter for the specific CPU it is running on. + * 5. The main test thread waits for all sub-threads to signal completion via `_thr_exit_sem`. + * + * Verification Metrics: + * - **Pass:** All created threads must complete their execution loops without deadlocking. + * - **Pass:** The sum of execution counts across all CPUs (`_load_average`) must equal the calculated expected total (`KERN_TEST_CONFIG_LOOP_TIMES * TEST_LEVEL_COUNTS * KERN_TEST_CONCURRENT_THREADS`). + * + * Dependencies: + * - Hardware requirements + * - No specific peripherals required, but multi-core CPU is recommended for SMP verification. + * (This is met by the qemu-virt64-riscv BSP). + * - Software configuration + * - `RT_USING_UTEST` must be enabled (`RT-Thread Utestcases`). + * - `Scheduler Test` must be enabled (`RT-Thread Utestcases` -> `Kernel Core` -> 'Scheduler Test'). + * - (Optional) Enable SMP for parallel testing (Highly Recommended): + * - Go to `RT-Thread Kernel` -> `Enable SMP (Symmetric multiprocessing)`. + * - Set `Number of CPUs` to > 1 (e.g., 2 or 4). + * - Environmental assumptions + * - The system must support enough valid priority levels (`RT_THREAD_PRIORITY_MAX`) to accommodate `TEST_LEVEL_COUNTS`. + * - Run the test case from the msh prompt: + * `utest_run core.scheduler_sem` + * + * Expected Results: + * - The console should print character patterns (e.g., `*0*1...`) indicating thread activity on specific CPUs. + * - The final load statistics per CPU should be printed. + * - Final Output: `[ PASSED ] [ result ] testcase (core.scheduler_sem)` + */ + #define __RT_IPC_SOURCE__ #include diff --git a/src/utest/sched_thread_tc.c b/src/utest/sched_thread_tc.c index 42fedea2f3e..9c3f74eef9b 100644 --- a/src/utest/sched_thread_tc.c +++ b/src/utest/sched_thread_tc.c @@ -6,7 +6,58 @@ * Change Logs: * Date Author Notes * 2024-01-25 Shell init ver. + * 2025-12-12 lhxj Add standardized utest documentation block */ + +/** + * Test Case Name: Scheduler Thread Stability Test (core.scheduler_thread) + * + * Test Objectives: + * - Verify the stability of the scheduler during intensive context switching. + * - Test the interaction between `rt_thread_suspend` and `rt_thread_resume` within critical sections. + * - Verify scheduler robustness in multi-core environments (using `RT_CPUS_NR`) ensuring no deadlocks or race conditions occur during thread state transitions. + * - List specific functions or APIs to be tested: + * - rt_thread_create + * - rt_thread_startup + * - rt_thread_suspend + * - rt_thread_resume + * - rt_enter_critical / rt_exit_critical_safe + * - rt_atomic_add + * + * Test Scenarios: + * - **Multi-threaded Ping-Pong Context Switching:** + * 1. Initialize a semaphore `_thr_exit_sem` for completion synchronization. + * 2. Create `TEST_THREAD_COUNT` pairs of threads (based on `RT_CPUS_NR`). + * 3. Each thread pair performs a "ping-pong" operation in a loop (100,000 iterations): + * - Thread A enters critical section, suspends self, resumes Thread B, exits critical section. + * - Thread B enters critical section, suspends self, resumes Thread A, exits critical section. + * 4. An atomic counter `_progress_counter` tracks execution progress, triggering `uassert_true` at intervals. + * 5. The main test thread waits for all worker threads to signal completion via the semaphore. + * + * Verification Metrics: + * - **Pass:** All created threads complete their execution loops without system hangs or crashes. + * - **Pass:** The progress counter increments as expected, validating thread execution flow. + * + * Dependencies: + * - Hardware requirements (e.g., specific peripherals) + * - No specific peripherals required. + * (This is met by the qemu-virt64-riscv BSP). + * - Software configuration (e.g., kernel options, driver initialization) + * - `RT_USING_UTEST` must be enabled (`RT-Thread Utestcases`). + * - `Scheduler Test` must be enabled (`RT-Thread Utestcases` -> `Kernel Core` -> 'Scheduler Test'). + * - (Optional) Enable SMP for parallel testing: + * - Go to `RT-Thread Kernel` -> `Enable SMP (Symmetric multiprocessing)`. + * - Set `Number of CPUs` to > 1 (e.g., 4). + * - Environmental assumptions + * - `UTEST_THR_STACK_SIZE` is sufficient for the test threads. + * - Run the test case from the msh prompt: + * `utest_run core.scheduler_thread` + * + * Expected Results: + * - The test proceeds through multiple loops of thread suspension and resumption. + * - Final Output: `[ PASSED ] [ result ] testcase (core.scheduler_thread)` + */ + #define __RT_KERNEL_SOURCE__ #include #include "utest.h" diff --git a/src/utest/sched_timed_mtx_tc.c b/src/utest/sched_timed_mtx_tc.c index 363b152df2f..1b4b24b6d48 100644 --- a/src/utest/sched_timed_mtx_tc.c +++ b/src/utest/sched_timed_mtx_tc.c @@ -6,7 +6,54 @@ * Change Logs: * Date Author Notes * 2024-01-25 Shell init ver. + * 2025-12-12 lhxj Add standardized utest documentation block */ + +/** + * Test Case Name: Timed Mutex Race Condition Test (core.scheduler_timed_mtx) + * + * Test Objectives: + * - Verify mutex behavior when a timeout race condition occurs between the timeout timer (scheduler) and mutex release. + * - Ensure strict round-robin ownership (Producer <-> Consumer) is maintained despite timeouts. + * - Validate that `rt_mutex_take_interruptible` correctly handles timeouts returning `-RT_ETIMEOUT`. + * - Ensure a thread does not hold the mutex if it reports a timeout. + * - List specific functions or APIs to be tested: + * - rt_mutex_take_interruptible + * - rt_mutex_take + * - rt_mutex_release + * - rt_tick_get + * + * Test Scenarios: + * - **Timeout vs Release Race:** + * 1. Create a Producer thread and a Consumer thread. + * 2. Producer acquires the mutex, aligns execution to the system tick edge (`_wait_until_edge`) with random latency, and releases the mutex. + * 3. Consumer attempts to acquire the mutex with a short timeout (1 tick) using `rt_mutex_take_interruptible`. + * 4. Verify that if Consumer times out, it does not hold the mutex. + * 5. Verify that if Consumer acquires the mutex, strict ownership order (Producer -> Consumer) was followed using magic flags. + * 6. Repeat for `TEST_LOOP_TICKS`. + * + * Verification Metrics: + * - **Pass:** The mutex ownership sequence (Consumer -> Producer -> Consumer) is never violated. + * - **Pass:** `rt_mutex_get_owner` returns NULL or not the current thread if `rt_mutex_take_interruptible` returns `-RT_ETIMEOUT`. + * - **Pass:** Both threads complete their loops and signal exit without asserting failure. + * + * Dependencies: + * - Hardware requirements (e.g., specific peripherals) + * - No specific hardware requirements. + * (This is met by the qemu-virt64-riscv BSP). + * - Software configuration (e.g., kernel options, driver initialization) + * - `RT_USING_UTEST` must be enabled (`RT-Thread Utestcases`). + * - `Scheduler Test` must be enabled (`RT-Thread Utestcases` -> `Kernel Core` -> 'Scheduler Test'). + * - Environmental assumptions + * - No specific environmental assumptions. + * - Run the test case from the msh prompt: + * `utest_run core.scheduler_timed_mtx` + * + * Expected Results: + * - The test logs "Total failed times: X(in Y)" indicating valid timeouts handled correctly. + * - Final Output: `[ PASSED ] [ result ] testcase (core.scheduler_timed_mtx)` + */ + #define __RT_KERNEL_SOURCE__ #include #include diff --git a/src/utest/sched_timed_sem_tc.c b/src/utest/sched_timed_sem_tc.c index b11b5080b77..147b7c238f4 100644 --- a/src/utest/sched_timed_sem_tc.c +++ b/src/utest/sched_timed_sem_tc.c @@ -6,7 +6,56 @@ * Change Logs: * Date Author Notes * 2024-01-25 Shell init ver. + * 2025-12-12 lhxj Add standardized utest documentation block */ + +/** + * Test Case Name: Scheduler Timed Semaphore Race Test (core.scheduler_timed_sem) + * + * Test Objectives: + * - Verify IPC (Semaphore) behavior under tight timing conditions (tick edge). + * - Stress test the race condition where a timeout routine and a producer thread + * race to wake up a sleeping consumer. + * - Ensure the scheduler handles interruptible semaphore takes correctly without + * returning unexpected error codes during high-contention/edge-case timing. + * - List specific functions or APIs to be tested: + * - rt_sem_take_interruptible + * - rt_sem_release + * - rt_tick_get + * - rt_thread_create + * + * Test Scenarios: + * - **Producer-Consumer Tick Edge Race:** + * 1. Initialize two semaphores (`_ipc_sem`, `_thr_exit_sem`). + * 2. Create two threads: a Producer (priority +1) and a Consumer (priority +1). + * 3. **Producer Loop:** Wait specifically for the RT-Thread tick count to change (tick edge), + * add a small random latency, and then release `_ipc_sem`. + * 4. **Consumer Loop:** Attempt to take `_ipc_sem` with a timeout of exactly 1 tick. + * 5. Track "failed times" (valid timeouts) versus "unexpected errors" (assert failure). + * 6. Run this loop for `TEST_SECONDS` (10 seconds). + * + * Verification Metrics: + * - **Pass:** The test completes the duration without triggering `uassert_true(0)`. + * - **Pass:** Consumer receives either `RT_EOK` (success) or `-RT_ETIMEOUT` (expected race loss). + * - **Fail:** Consumer receives any error code other than `RT_EOK` or `-RT_ETIMEOUT`. + * + * Dependencies: + * - Hardware requirements + * - No specific peripheral required. + * (This is met by the qemu-virt64-riscv BSP). + * - Software configuration + * - `RT_USING_UTEST` must be enabled (`RT-Thread Utestcases`). + * - `Scheduler Test` must be enabled (`RT-Thread Utestcases` -> `Kernel Core` -> 'Scheduler Test'). + * - Environmental assumptions + * - System tick must be running. + * - Run the test case from the msh prompt: + * `utest_run core.scheduler_timed_sem` + * + * Expected Results: + * - The system logs "Total failed times: X(in Y)" (Timeouts are allowed/counted, not fatal). + * - Final Output: `[ PASSED ] [ result ] testcase (core.scheduler_timed_sem)` + */ + #define __RT_KERNEL_SOURCE__ #include #include From 8dad5f5779ae364d6afb53f5f98c9dc15a348537 Mon Sep 17 00:00:00 2001 From: Chuan Date: Sun, 14 Dec 2025 21:57:30 +0800 Subject: [PATCH 12/20] [utest][mm_api]Add standardized documentation for MM API Test --- examples/utest/testcases/mm/mm_api_tc.c | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/examples/utest/testcases/mm/mm_api_tc.c b/examples/utest/testcases/mm/mm_api_tc.c index 6ddb39189de..d7fcdffb00c 100644 --- a/examples/utest/testcases/mm/mm_api_tc.c +++ b/examples/utest/testcases/mm/mm_api_tc.c @@ -7,6 +7,41 @@ * Date Author Notes * 2022-12-14 WangXiaoyao the first version * 2023-03-20 WangXiaoyao Format & add more testcases for API under mm_aspace.h + * 2025-12-14 ChuanN-sudo Add standardized utest documentation block + */ + +/** + * Test Case Name: MM API Test + * + * Test Objectives: + * - Verify I/O remapping functionality with cached memory access. + * - Test memory mapping flag creation and extraction mechanisms. + * - Validate address space management operations. + * - Test core APIs: rt_pages_alloc(), rt_ioremap_cached(), rt_iounmap(), rt_pages_free(), + * rt_pages_free(), MMF_CREATE(), MMF_GET_CNTL(), MMF_GET_ALIGN(). + * + * Test Scenarios: + * - Address Space Test (aspace_tc): Tests memory address space management APIs. + * - I/O Remap Test (ioremap_tc): Allocates physical pages, maps to virtual address with cache, verifies data consistency, and cleans up resources. + * - Flag Test (flag_tc): Creates memory mapping flags with different parameters and validates control bits and alignment values extraction. + * + * Verification Metrics: + * - I/O remapping should correctly map physical to virtual addresses. + * - Cached memory access should maintain data consistency between physical and virtual addresses. + * - Memory mapping flags should correctly encode and decode control bits and alignment values. + * - Flag creation with alignment should set MMF_REQUEST_ALIGN bit and store alignment value. + * - Flag creation without alignment should not set alignment-related bits. + * + Dependencies: + * - Hardware requirements: QEMU emulator or any hardware platform that supports RT-Thread with MMU. + * - Software configuration: + * - RT_UTEST_MM_API must be enabled (enable via: RT-Thread Utestcases -> RT-Thread Utestcases -> Memory Management Subsystem Testcase -> Enable Utest for MM API). + * - RT_USING_SMART must be enabled (enable via: Enable RT-Thread Kernel -> RT-Thread Smart (microkernel on kernel/userland)). + * - Environmental Assumptions: MMU support must be available on the target platform. + + * Expected Results: + * - Final output: "[ PASSED ] [ result ] testcase (testcases.mm.api_tc)" + * - No assertion failures during test execution. */ #include "common.h" From b3429e33604676eea87c04b6921368f7ee5963f7 Mon Sep 17 00:00:00 2001 From: bernard Date: Sat, 13 Dec 2025 21:42:29 +0800 Subject: [PATCH 13/20] [rust] Tidy core defaults and migrate docs to README --- components/rust/{README_cn.md => README_zh.md} | 0 components/rust/core/src/api/libloading.rs | 2 +- components/rust/core/src/lib.rs | 2 +- components/rust/core/src/panic.rs | 2 +- components/rust/core/src/thread.rs | 4 ++-- components/rust/docs/1.tools/{tools.md => README.md} | 0 components/rust/docs/1.tools/{tools_cn.md => README_zh.md} | 0 .../rust/docs/2.applications/{application.md => README.md} | 0 .../docs/2.applications/{application_cn.md => README_zh.md} | 0 .../rust/docs/3.components/{component.md => README.md} | 0 .../docs/3.components/{component_cn.md => README_zh.md} | 0 components/rust/docs/4.modules/{modules.md => README.md} | 0 .../rust/docs/4.modules/{modules_cn.md => README_zh.md} | 0 components/rust/docs/5.rt-macro/{rt-macros.md => README.md} | 0 .../rust/docs/5.rt-macro/{rt-macros_cn.md => README_zh.md} | 0 components/rust/examples/modules/example_lib/src/lib.rs | 6 +++--- 16 files changed, 8 insertions(+), 8 deletions(-) rename components/rust/{README_cn.md => README_zh.md} (100%) rename components/rust/docs/1.tools/{tools.md => README.md} (100%) rename components/rust/docs/1.tools/{tools_cn.md => README_zh.md} (100%) rename components/rust/docs/2.applications/{application.md => README.md} (100%) rename components/rust/docs/2.applications/{application_cn.md => README_zh.md} (100%) rename components/rust/docs/3.components/{component.md => README.md} (100%) rename components/rust/docs/3.components/{component_cn.md => README_zh.md} (100%) rename components/rust/docs/4.modules/{modules.md => README.md} (100%) rename components/rust/docs/4.modules/{modules_cn.md => README_zh.md} (100%) rename components/rust/docs/5.rt-macro/{rt-macros.md => README.md} (100%) rename components/rust/docs/5.rt-macro/{rt-macros_cn.md => README_zh.md} (100%) diff --git a/components/rust/README_cn.md b/components/rust/README_zh.md similarity index 100% rename from components/rust/README_cn.md rename to components/rust/README_zh.md diff --git a/components/rust/core/src/api/libloading.rs b/components/rust/core/src/api/libloading.rs index 438f1fb40b8..90b33cc92d3 100644 --- a/components/rust/core/src/api/libloading.rs +++ b/components/rust/core/src/api/libloading.rs @@ -150,7 +150,7 @@ impl Library { let h = self.handle; forget(self); let rc = libc::dlclose(h); - if rc == 1 { + if rc == 0 { Ok(()) } else { Err(DlError::Close(rc)) diff --git a/components/rust/core/src/lib.rs b/components/rust/core/src/lib.rs index 2787b7240a4..01e4b34102b 100644 --- a/components/rust/core/src/lib.rs +++ b/components/rust/core/src/lib.rs @@ -77,7 +77,7 @@ pub enum RTTError { FileSetLengthErr, FileSyncErr, - FuncUnDefine, + FuncUndefined, } pub type RTResult = Result; diff --git a/components/rust/core/src/panic.rs b/components/rust/core/src/panic.rs index 371f86fdb62..b45ad7d1a34 100644 --- a/components/rust/core/src/panic.rs +++ b/components/rust/core/src/panic.rs @@ -24,7 +24,7 @@ fn panic(info: &core::panic::PanicInfo) -> ! { } #[linkage = "weak"] -#[unsafe(no_mangle)] +#[no_mangle] fn __rust_panic() -> ! { /* Default weak panic handler: loops forever to halt execution. */ print!("Entered weak panic handler: system will halt."); diff --git a/components/rust/core/src/thread.rs b/components/rust/core/src/thread.rs index 35e03f3c3aa..791fd46da7d 100644 --- a/components/rust/core/src/thread.rs +++ b/components/rust/core/src/thread.rs @@ -28,7 +28,7 @@ impl Thread { pub fn new() -> ThreadBuilder { ThreadBuilder { - th_name: "uname".into(), + th_name: "Unnamed".into(), th_stack_size: 4096, th_priority: 10, th_ticks: 10, @@ -151,4 +151,4 @@ impl ThreadBuilder { func, ) } -} \ No newline at end of file +} diff --git a/components/rust/docs/1.tools/tools.md b/components/rust/docs/1.tools/README.md similarity index 100% rename from components/rust/docs/1.tools/tools.md rename to components/rust/docs/1.tools/README.md diff --git a/components/rust/docs/1.tools/tools_cn.md b/components/rust/docs/1.tools/README_zh.md similarity index 100% rename from components/rust/docs/1.tools/tools_cn.md rename to components/rust/docs/1.tools/README_zh.md diff --git a/components/rust/docs/2.applications/application.md b/components/rust/docs/2.applications/README.md similarity index 100% rename from components/rust/docs/2.applications/application.md rename to components/rust/docs/2.applications/README.md diff --git a/components/rust/docs/2.applications/application_cn.md b/components/rust/docs/2.applications/README_zh.md similarity index 100% rename from components/rust/docs/2.applications/application_cn.md rename to components/rust/docs/2.applications/README_zh.md diff --git a/components/rust/docs/3.components/component.md b/components/rust/docs/3.components/README.md similarity index 100% rename from components/rust/docs/3.components/component.md rename to components/rust/docs/3.components/README.md diff --git a/components/rust/docs/3.components/component_cn.md b/components/rust/docs/3.components/README_zh.md similarity index 100% rename from components/rust/docs/3.components/component_cn.md rename to components/rust/docs/3.components/README_zh.md diff --git a/components/rust/docs/4.modules/modules.md b/components/rust/docs/4.modules/README.md similarity index 100% rename from components/rust/docs/4.modules/modules.md rename to components/rust/docs/4.modules/README.md diff --git a/components/rust/docs/4.modules/modules_cn.md b/components/rust/docs/4.modules/README_zh.md similarity index 100% rename from components/rust/docs/4.modules/modules_cn.md rename to components/rust/docs/4.modules/README_zh.md diff --git a/components/rust/docs/5.rt-macro/rt-macros.md b/components/rust/docs/5.rt-macro/README.md similarity index 100% rename from components/rust/docs/5.rt-macro/rt-macros.md rename to components/rust/docs/5.rt-macro/README.md diff --git a/components/rust/docs/5.rt-macro/rt-macros_cn.md b/components/rust/docs/5.rt-macro/README_zh.md similarity index 100% rename from components/rust/docs/5.rt-macro/rt-macros_cn.md rename to components/rust/docs/5.rt-macro/README_zh.md diff --git a/components/rust/examples/modules/example_lib/src/lib.rs b/components/rust/examples/modules/example_lib/src/lib.rs index 5f81c1553fd..79fe384e6ad 100644 --- a/components/rust/examples/modules/example_lib/src/lib.rs +++ b/components/rust/examples/modules/example_lib/src/lib.rs @@ -11,7 +11,7 @@ /* Bring rt-rust's println! macro into scope */ use rt_rust::println; use core::ffi::{c_char, CStr}; -#[unsafe(no_mangle)] +#[no_mangle] pub extern "C" fn rust_mylib_println(s: *const c_char) { if s.is_null() { println!(""); @@ -24,7 +24,7 @@ pub extern "C" fn rust_mylib_println(s: *const c_char) { } } -#[unsafe(no_mangle)] +#[no_mangle] pub extern "C" fn rust_mylib_add(a: usize, b: usize) -> usize { a + b -} \ No newline at end of file +} From 6178907fe0a18faed280795ee02a5bc88a576513 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Tue, 9 Dec 2025 12:00:48 +0800 Subject: [PATCH 14/20] [finsh][cmd] add 'console' command to config console Signed-off-by: GuEe-GUI <2991707448@qq.com> --- .../applications/console.c | 27 --------- components/finsh/cmd.c | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 27 deletions(-) diff --git a/bsp/qemu-virt64-aarch64/applications/console.c b/bsp/qemu-virt64-aarch64/applications/console.c index b69b9b3b978..3f8be481891 100644 --- a/bsp/qemu-virt64-aarch64/applications/console.c +++ b/bsp/qemu-virt64-aarch64/applications/console.c @@ -31,30 +31,3 @@ static int console_init() return status; } INIT_ENV_EXPORT(console_init); - -static int console(int argc, char **argv) -{ - rt_err_t result = RT_EOK; - - if (argc > 1) - { - if (!rt_strcmp(argv[1], "set")) - { - rt_kprintf("console change to %s\n", argv[2]); - rt_console_set_device(argv[2]); - } - else - { - rt_kprintf("Unknown command. Please enter 'console' for help\n"); - result = -RT_ERROR; - } - } - else - { - rt_kprintf("Usage: \n"); - rt_kprintf("console set - change console by name\n"); - result = -RT_ERROR; - } - return result; -} -MSH_CMD_EXPORT(console, set console name); diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index c88895d6eea..48bbfc833aa 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -32,6 +32,7 @@ * 2022-07-02 Stanley Lwin add list command * 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable * 2024-02-09 Bernard fix the version command + * 2023-02-25 GuEe-GUI add console */ #include @@ -60,6 +61,61 @@ static long version(void) } MSH_CMD_EXPORT(version, show RT-Thread version information); +#if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE) +#if !defined(RT_USING_POSIX) && defined(RT_USING_POSIX_STDIO) +#include +#endif + +static int console(int argc, char **argv) +{ + if (argc > 1) + { + if (!rt_strcmp(argv[1], "set")) + { + if (argc < 3) + { + goto _help; + } + + rt_kprintf("console change to %s\n", argv[2]); + rt_console_set_device(argv[2]); + +#ifdef RT_USING_POSIX + { + rt_device_t dev = rt_device_find(argv[2]); + + if (dev != RT_NULL) + { + console_set_iodev(dev); + } + } +#elif !defined(RT_USING_POSIX_STDIO) + finsh_set_device(argv[2]); +#else + rt_posix_stdio_init(); +#endif /* RT_USING_POSIX */ + } + else + { + goto _help; + } + } + else + { + goto _help; + } + + return RT_EOK; + +_help: + rt_kprintf("Usage: \n"); + rt_kprintf("console set - change console by name\n"); + + return -RT_ERROR; +} +MSH_CMD_EXPORT(console, console setting); +#endif /* RT_USING_DEVICE && RT_USING_CONSOLE */ + rt_inline void object_split(int len) { while (len--) rt_kprintf("-"); From 3daf62e800f41d1d21c30d227e1629c358bb0f5f Mon Sep 17 00:00:00 2001 From: Yaochenger <1516081466@qq.com> Date: Wed, 9 Jul 2025 15:33:48 +0800 Subject: [PATCH 15/20] [add] add gd32w553h-eval bsp --- .github/ALL_BSP_COMPILE.json | 3 +- bsp/gd32/risc-v/gd32vw553h-eval/.config | 1428 +++++++++++++++++ bsp/gd32/risc-v/gd32vw553h-eval/Kconfig | 12 + bsp/gd32/risc-v/gd32vw553h-eval/README.md | 181 +++ bsp/gd32/risc-v/gd32vw553h-eval/SConscript | 16 + bsp/gd32/risc-v/gd32vw553h-eval/SConstruct | 71 + .../gd32vw553h-eval/applications/SConscript | 11 + .../gd32vw553h-eval/applications/main.c | 35 + bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig | 90 ++ .../risc-v/gd32vw553h-eval/board/SConscript | 27 + bsp/gd32/risc-v/gd32vw553h-eval/board/board.c | 71 + bsp/gd32/risc-v/gd32vw553h-eval/board/board.h | 24 + .../gd32vw553h-eval/board/gd32vw55x_libopt.h | 63 + .../board/linker_scripts/link.lds | 200 +++ .../risc-v/gd32vw553h-eval/board/trap_gcc.S | 45 + .../risc-v/gd32vw553h-eval/figures/board.png | Bin 0 -> 1011893 bytes .../risc-v/gd32vw553h-eval/figures/env.png | Bin 0 -> 13234 bytes .../gd32vw553h-eval/figures/programmer.png | Bin 0 -> 55778 bytes .../risc-v/gd32vw553h-eval/openocd_gdlink.cfg | 42 + bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h | 417 +++++ bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py | 73 + bsp/gd32/risc-v/libraries/Kconfig | 6 + .../risc-v/libraries/gd32_drivers/drv_gpio.c | 71 +- .../risc-v/libraries/gd32_drivers/drv_gpio.h | 16 +- .../risc-v/libraries/gd32_drivers/drv_usart.c | 73 +- .../risc-v/libraries/gd32_drivers/drv_usart.h | 23 +- 26 files changed, 2946 insertions(+), 52 deletions(-) create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/.config create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/Kconfig create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/README.md create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/SConscript create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/SConstruct create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/applications/SConscript create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/applications/main.c create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/board.c create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/board.h create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/gd32vw55x_libopt.h create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/trap_gcc.S create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/figures/board.png create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/figures/env.png create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/figures/programmer.png create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/openocd_gdlink.cfg create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index f2703450484..3dae5e30fca 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -398,7 +398,8 @@ "k210", "wch/risc-v/ch32v208w-r0", "wch/risc-v/ch32v307v-r1", - "wch/risc-v/yd-ch32v307vct6" + "wch/risc-v/yd-ch32v307vct6", + "gd32/risc-v/gd32vw553h-eval" ] }, { diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/.config b/bsp/gd32/risc-v/gd32vw553h-eval/.config new file mode 100644 index 00000000000..d0575487ef0 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/.config @@ -0,0 +1,1428 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +# CONFIG_RT_USING_DEBUG is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER=y +CONFIG_PKG_GD32_RISCV_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/gd32/gd32-riscv-series" +CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_GD32_RISCV_SERIES_DRIVER_VER="latest" +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_GD32=y +CONFIG_SOC_GD32VW553H=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_SERIES_GD32VW55x=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/Kconfig b/bsp/gd32/risc-v/gd32vw553h-eval/Kconfig new file mode 100644 index 00000000000..07edfefc341 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/README.md b/bsp/gd32/risc-v/gd32vw553h-eval/README.md new file mode 100644 index 00000000000..53589e4c007 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/README.md @@ -0,0 +1,181 @@ +# GD32VW553H_EVAL 开发板BSP说明 + +## 1 简介 + +GD32VW553H_EVAL是-兆易创新推出的一款GD32VW系列的评估板。开发板外观如下图所示： + +![board](figures/board.png) + +GD32VW553系列双模无线MCU,支持Wi-Fi 6及Bluetooth LE 5.2无线连接，集成了高达4MB Flash及320KB SRAM，另有32KB可配置指令高速缓存(I-Cache)，大幅提升了CPU处理效率。不仅具备出色的无线性能，芯片还配置了丰富的通用有线接口，包含3个U(S)ART、2个I2C、1个SPI以及1个四线制QSPI等, 以及多达29个可编程 GPIO 管脚。内置2个32位通用定时器、2个16位通用定时器、4个16位基本定时器、1个PWM高级定时器和1个12位ADC。供电电压1.8V - 3.6V，并提供了85℃ - 105℃宽温选择，以满足工控互联、照明设备以及插座面板等高温场景应用所需。 + +面向实时处理和高效通信需求，GD32VW553系列MCU采用了全新的开源指令集架构RISC-V处理器内核，主频可达160MHz，还配备了高级DSP硬件加速器、双精度浮点单元(FPU)以及指令扩展接口等资源，以出色的微架构设计实现了极佳的能效比，并提供了灵活的可扩展性。 + +## 2 快速上手 + +### 2.1 环境准备 + +#### 2.1.1 工具链 + +首先需要准备BSP编译所需的工具链，[工具链下载链接](https://www.gigadevice.com.cn/product/mcu/mcus-product-selector/gd32vw553hmq6)，在该链接下载应用软件选项中的GD32 Embedded Builder。 + +工具链的相对路径如下： + +> GD32EmbeddedBuilder_v1.5.2.30854\Tools\RISC-V Embedded GCC\8.2.0-2.2-20190521-0004\bin + +#### 2.1.2 下载工具 + +GD32VW553可以使用GD官方工具GD32AllInOneProgrammer下载，[GD32AllInOneProgrammer下载链接](https://www.gd32mcu.com/cn/download?kw=GD32+All-In-One+Programmer&lan=cn)，编译出的固件可使用该软件下载。 + +#### 2.1.3 RT-Thread ENV工具 + +RT-Thread的BSP可以使用官方env工具编译，env使用请自行学习，[env下载链接](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)。 + +#### 2.2 固件编译 + +使用USB数据线连接板载的GD-Link与串口。 + +在BSP根路径下使用env工具打开BSP，示例如下： + +![board](figures/env.png) + +然后执行pkgs --update命令添加当前BSP所需要的驱动库，示例如下（如果长时间未使用env，可首先 + +行pkgs --upgrade更新软件包的链接索引） + +```powershell +(.venv) RTT@RSH-PC0001 E:\rt-thread\bsp\gd32\risc-v\gd32vw553h-eval +$ pkgs --upgrade +Error message:[Errno 2] No such file or directory: 'E:\\env-windows-v2.0.0\\env-windows\\tools\\bin\\..\\..\\tools\\scripts\\cmds\\.config' +open .config failed +[Use Github server - auto decision based on IP location] +Begin to upgrade env packages. +remote: Enumerating objects: 768, done. +remote: Counting objects: 100% (374/374), done. +remote: Compressing objects: 100% (16/16), done. +Receiving objects: 96% (738/768) +Receiving objects: 100% (768/768), 142.23 KiB | 5.69 MiB/s, done. +Resolving deltas: 100% (462/462), completed with 70 local objects. +From https://github.com/RT-Thread/packages + * branch HEAD -> FETCH_HEAD +==============================> Env packages upgrade done +(.venv) RTT@RSH-PC0001 E:\rt-thread\bsp\gd32\risc-v\gd32vw553h-eval +$ pkgs --update +``` + +接下来需要设置工具链字段，示例如下（使用时将下述路径调整为自己的工具链路径）： + +```powershell +(.venv) RTT@RSH-PC0001 E:\rt-thread\bsp\gd32\risc-v\gd32vw553h-eval +$ set RTT_EXEC_PATH=E:\GD32\GD32VW5\GD32EmbeddedBuilder_v1.5.4_Rel\Tools\RISC-V Embedded GCC\8.2.0-2.2-20190521-0004\bin +``` + +接下来执行scons -j128命令编译工程，示例如下： + +```powershell +(.venv) RTT@RSH-PC0001 E:\rt-thread\bsp\gd32\risc-v\gd32vw553h-eval +$ scons -j128 +``` + +成功编译会输出下述日志，并在BSP根路径生成**rtthread.bin**固件，该固件即下文需要烧录的固件。 + +```powershell +LINK rtthread.elf +Memory region Used Size Region Size %age Used + flash: 66388 B 4 MB 1.58% + ram: 288 KB 288 KB 100.00% +riscv-none-embed-objcopy -O binary rtthread.elf rtthread.bin +riscv-none-embed-size rtthread.elf + text data bss dec hex filename + 65152 1200 7612 73964 120ec rtthread.elf +scons: done building targets. +``` + +#### 2.3 固件烧录 + +固件烧录需要使用上述的GD32AllInOneProgrammer软件，烧录说明位于烧录软件下的Doc文件夹，或在线搜索使用方法，下述是烧录的示例： + +![board](figures/programmer.png) + +> 需要注意的是使用上述软件烧录时需要将boot1置为高电平，烧录结束后重新设置为低电平，手动调整板载的boot跳线帽。 + +#### 2.4 运行结果 + +烧录完毕后，使用串口连接自己的串口终端软件，即可通过串口与开发板交互，示例如下： + +```shell + \ | / +- RT - Thread Operating System + / | \ 5.2.1 build Dec 12 2025 14:51:49 + 2006 - 2024 Copyright by RT-Thread team +Hello GD32VW553H +msh > +msh >ps +thread pri status sp stack size max used left tick error tcb addr +-------- --- ------- ---------- ---------- ------ ---------- ------- ---------- +tshell 20 running 0x000002d0 0x00001000 31% 0x00000009 OK 0x20002598 +tidle0 31 ready 0x00000220 0x00000400 53% 0x00000019 OK 0x20000654 +timer 4 suspend 0x00000290 0x00000400 64% 0x00000009 EINTRPT 0x20000ba8 +main 10 suspend 0x00000280 0x00001000 17% 0x00000013 EINTRPT 0x200012b8 +msh > +``` + +#### 2.5 配置工程 + + BSP 默认只开启了 GPIO 和 串口0的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 +3. 输入`pkgs --update`命令更新软件包。 +4. 输入`scons `命令重新编译工程。 + +## 3 调试下载（VSCode） + +首先在BSP根目录下执行下述命令，生成VSCode工程所需文件。 + +> scons --target=vs + +在VSCode安装扩展插件Cortex-Debug，版本v1.4.4。 + +完成上述工作后，点击运行和调试选项，创建一个launch.json配置文件，配置文件示例如下： + +```json +{ + "version": "0.2.0", + "configurations": + [ + { + "name": "Cortex Debug", + "cwd": "${workspaceFolder}", + "executable": "${workspaceFolder}/rtthread.elf", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "E:/GD32/GD32VW5/Tools/GD32EmbeddedBuilder_v1.5.2.30854/Tools/OpenOCD/xpack-openocd-0.11.0-3/bin/openocd", + "configFiles": + [ + "${workspaceFolder}/openocd_gdlink.cfg" + ], + "runToEntryPoint": "main", + "showDevDebugOutput": "raw", + "toolchainPrefix": "E:/GD32/GD32VW5/Tools/GD32EmbeddedBuilder_v1.5.2.30854/Tools/RISC-V Embedded GCC/8.2.0-2.2-20190521-0004/bin/riscv-none-embed" + } + ] +} +``` + +上述文件中的部分字段需要根据用户环境进行修改，格式需与示例一致： + +- "serverpath”：该字段需要改为用户的openocd所在路径，openocd工具位于GD32EmbeddedBuilder工具包中。 +- "toolchainPrefix"：该字段需修改为用户的工具链所在路径，工具链位于GD32EmbeddedBuilder工具包中。 + +完成上述配置后即可点击调试选项进行调试，调试时boot管脚均置为低电平即可，调试时同样会进行固件下载。 + +## 4 注意事项 + +- Cortex-Debug插件优先选用v1.4.4版本，高版本可能会出现与GDB版本不匹配的问题。 + +## 联系人信息 + +维护人: + +- [MuChenger](https://github.com/MuChenger), 邮箱：<1516081466@qq.com> \ No newline at end of file diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/SConscript b/bsp/gd32/risc-v/gd32vw553h-eval/SConscript new file mode 100644 index 00000000000..945e23289ad --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/SConscript @@ -0,0 +1,16 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = str(Dir('#')) + +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/SConstruct b/bsp/gd32/risc-v/gd32vw553h-eval/SConstruct new file mode 100644 index 00000000000..0b74a2510a3 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/SConstruct @@ -0,0 +1,71 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "gd32-riscv-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +gd32_library = 'GD32VW55x_Firmware_Library' +rtconfig.BSP_LIBRARY_TYPE = gd32_library + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/applications/SConscript b/bsp/gd32/risc-v/gd32vw553h-eval/applications/SConscript new file mode 100644 index 00000000000..ef1c39fd832 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, ] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/applications/main.c b/bsp/gd32/risc-v/gd32vw553h-eval/applications/main.c new file mode 100644 index 00000000000..706c3d03bb6 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/applications/main.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-04 BruceOu first implementation + * 2025-07-10 WangShun fix for GD32VW553H_EVAL + */ + +#include +#include +#include +#include + +/* LED1 ~ LED3 pin: PA4 PA5 PA6 */ +#define LED1_PIN GET_PIN(A, 4) + +int main(void) +{ + rt_kprintf("Hello GD32VW553H\n"); + /* set LED1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig new file mode 100644 index 00000000000..6bb5df41373 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig @@ -0,0 +1,90 @@ +menu "Hardware Drivers Config" + +config SOC_SERIES_GD32VW55x + bool + default y + +config SOC_GD32VW553H + bool + select SOC_SERIES_GD32VW55x + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default n + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 + select RT_SERIAL_USING_DMA + default n + endif + + source "$(BSP_DIR)/../libraries/gd32_drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu + diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript b/bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript new file mode 100644 index 00000000000..71fadebe66f --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript @@ -0,0 +1,27 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +trap_gcc.S +''') + +path = [cwd] + +# add startup txt path +startup_path_prefix = os.getcwd() + '/../' + +if rtconfig.PLATFORM in ['gcc']: + src += [startup_path_prefix + '/packages/gd32-riscv-series-latest/GD32VW55x/RISCV/env_Eclipse/start.S'] + src += [startup_path_prefix + '/packages/gd32-riscv-series-latest/GD32VW55x/RISCV/env_Eclipse/entry.S'] + +CPPDEFINES = ['GD32VW553H_EVAL'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/board.c b/bsp/gd32/risc-v/gd32vw553h-eval/board/board.c new file mode 100644 index 00000000000..7f9307fdb91 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/board.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-04 BruceOu first implementation + */ + +#include +#include +#include +#include "board.h" + +#ifdef RT_USING_SERIAL +#include +#endif + +/* System Tick Configuration */ +void systick_config(void) +{ + SysTimer_SetControlValue(SysTimer_MTIMECTL_CMPCLREN_Msk); + SysTimer_SetCompareValue(((uint32_t) SystemCoreClock / 4) / RT_TICK_PER_SECOND); + __ECLIC_SetTrigIRQ(CLIC_INT_TMR, ECLIC_POSTIVE_EDGE_TRIGGER); + eclic_irq_enable(CLIC_INT_TMR, 0, 0); +} + +void rt_hw_board_init(void) +{ +extern void _init(void); + _init(); + systick_config(); + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END); +#endif + +} + + void eclic_mtip_handler(void) + { + /* clear value */ + ECLIC_ClearPendingIRQ(CLIC_INT_TMR); + SysTimer_SetLoadValue(0); + + /* enter interrupt */ + rt_interrupt_enter(); + /* tick increase */ + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + } + +/******************** end of file *******************/ diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/board.h b/bsp/gd32/risc-v/gd32vw553h-eval/board/board.h new file mode 100644 index 00000000000..a34e184df76 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/board.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-04 BruceOu first implementation + */ + +#ifndef __BOARD__ +#define __BOARD__ +#include "gd32vw55x.h" +#include "drv_gpio.h" +extern void *_end; +extern void *_heap_end; +#define HEAP_BEGIN &_end +#define HEAP_END &_heap_end + +void rt_hw_board_init(void); + +#endif /* __BOARD__ */ + +/******************** end of file *******************/ diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/gd32vw55x_libopt.h b/bsp/gd32/risc-v/gd32vw553h-eval/board/gd32vw55x_libopt.h new file mode 100644 index 00000000000..77347a31d13 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/gd32vw55x_libopt.h @@ -0,0 +1,63 @@ +/*! + \file gd32vw55x_libopt.h + \brief library optional for gd32vw55x + + \version 2025-02-12, V1.4.0, demo for GD32VW55x +*/ + +/* + Copyright (c) 2024, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VW55X_LIBOPT_H +#define GD32VW55X_LIBOPT_H + +#include "gd32vw55x_adc.h" +#include "gd32vw55x_cau.h" +#include "gd32vw55x_crc.h" +#include "gd32vw55x_dbg.h" +#include "gd32vw55x_dma.h" +#include "gd32vw55x_eclic.h" +#include "gd32vw55x_efuse.h" +#include "gd32vw55x_exti.h" +#include "gd32vw55x_fmc.h" +#include "gd32vw55x_fwdgt.h" +#include "gd32vw55x_gpio.h" +#include "gd32vw55x_hau.h" +#include "gd32vw55x_i2c.h" +#include "gd32vw55x_pkcau.h" +#include "gd32vw55x_pmu.h" +#include "gd32vw55x_qspi.h" +#include "gd32vw55x_rcu.h" +#include "gd32vw55x_rtc.h" +#include "gd32vw55x_spi.h" +#include "gd32vw55x_syscfg.h" +#include "gd32vw55x_timer.h" +#include "gd32vw55x_trng.h" +#include "gd32vw55x_usart.h" +#include "gd32vw55x_wwdgt.h" + +#endif /* GD32VW55X_LIBOPT_H */ diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds b/bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds new file mode 100644 index 00000000000..82516919c27 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds @@ -0,0 +1,200 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 4096k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 288K + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 32k + ram (wxa!ri) : ORIGIN = 0x20008000, LENGTH = 256K +*/ +} + + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 4K; + + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash + + .ilalign : + { + . = ALIGN(4); + PROVIDE( _ilm_lma = . ); + } >flash AT>flash + + .ialign : + { + PROVIDE( _ilm = . ); + } >flash AT>flash + + .text : + { + *(.rodata .rodata.*) + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + } >flash AT>flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash + + . = ALIGN(4); + + PROVIDE (__etext = .); + PROVIDE (_etext = .);/*0x80022c8*/ + PROVIDE (etext = .);/*0x80022c8*/ + PROVIDE( _eilm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash + + . = ALIGN(4); + PROVIDE( _eilm = . ); + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash + + + .data : + { + *(.rdata) + + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram + + . = ALIGN(8); + PROVIDE( _end = . ); /*0X2000,0340*/ + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE( __rt_rvstack = .); + } >ram AT>ram +} diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/trap_gcc.S b/bsp/gd32/risc-v/gd32vw553h-eval/board/trap_gcc.S new file mode 100644 index 00000000000..3e6e070ae44 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/trap_gcc.S @@ -0,0 +1,45 @@ +#include "cpuport.h" +#include "riscv_encoding.h" + +.macro SAVE_CSR_CONTEXT + csrrwi x0, CSR_PUSHMCAUSE, 11 + csrrwi x0, CSR_PUSHMEPC, 12 + csrrwi x0, CSR_PUSHMSUBM, 13 +.endm + +.macro RESTORE_CSR_CONTEXT + LOAD x5, 13*REGBYTES(sp) + csrw CSR_MSUBM, x5 + LOAD x5, 12*REGBYTES(sp) + csrw CSR_MEPC, x5 + LOAD x5, 11*REGBYTES(sp) + csrw CSR_MCAUSE, x5 +.endm + +.macro DISABLE_MIE + csrc CSR_MSTATUS, MSTATUS_MIE +.endm + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + csrr a0, mcause + csrr a1, mepc + mv a2, sp + + SAVE_CSR_CONTEXT + + csrrw ra, CSR_JALMNXTI, ra + + + DISABLE_MIE + RESTORE_CSR_CONTEXT + + li t0, 0x08 + csrc mstatus, t0 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/figures/board.png b/bsp/gd32/risc-v/gd32vw553h-eval/figures/board.png new file mode 100644 index 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zjg~nRRuVXY?=$8nMtb5mm^@Gu8xk++nVdN2C;*CQM{jUx69Ncw0*u+1MKFq+3_V`j{v zebR^DYc5>(AX)lou;)J&I7iptcjZrZ!eF5%X@Qy{8=fU-XBzdKS|b_yUVGy?$_VVH0RDirv0EeNE}A7 zdsEW74baH#C`HI172o-sVN%b+o7j~e-6f0j{NZ?QuhiJCB=E&M#z3P=n&&6A@9LSo zIaSx=W6I}Z{oX80WBrsa!o-6L&Z%puEimFOy3=ffJQjCAsHruD{a$rw{LOvpHG&CB z)9;24i|w9<_vNv{;a{7%+r?l{tx+(0RjL3 literal 0 HcmV?d00001 diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/openocd_gdlink.cfg b/bsp/gd32/risc-v/gd32vw553h-eval/openocd_gdlink.cfg new file mode 100644 index 00000000000..1791376ba7d --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/openocd_gdlink.cfg @@ -0,0 +1,42 @@ +# +# GigaDevice GD32VW55x target +# +adapter driver cmsis-dap + +adapter speed 8000000 +reset_config trst_only +adapter srst pulse_width 100 + +transport select jtag + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10307a6d + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0 + + +# Work-area is a space in RAM used for flash programming +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x5000 +} + +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME gd32vw55x 0x08000000 0x400000 0 0 $_TARGETNAME +riscv set_reset_timeout_sec 1 +init + +halt diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h new file mode 100644 index 00000000000..d84ae18f2ef --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h @@ -0,0 +1,417 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice options */ + +/* end of kservice options */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +#define PKG_USING_GD32_RISCV_SERIES_DRIVER +#define PKG_USING_GD32_RISCV_SERIES_DRIVER_LATEST_VERSION +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_GD32 +#define SOC_GD32VW553H + +/* Hardware Drivers Config */ + +#define SOC_SERIES_GD32VW55x + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py new file mode 100644 index 00000000000..79d8de523e7 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py @@ -0,0 +1,73 @@ +import os + +# toolchains options +ARCH='risc-v' +CPU='bumblebee' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:/Program Files (x86)/GNU Tools RISC-V Embedded/8 2019.08-2/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +CORE = 'risc-v' +BUILD = 'debug' +MAP_FILE = 'rtthread.map' +LINK_FILE = './board/linker_scripts/link.lds' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv-none-embed-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=rv32imafdc -mcmodel=medany -msmall-data-limit=8 -mdiv -mabi=ilp32d -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections ' + + # C Compilation Parameters + CFLAGS = DEVICE + ' -std=gnu11 -DUSE_STDPERIPH_DRIVE -save-temps=obj' + # Assembly Compilation Parameters + AFLAGS = DEVICE + '-c'+ ' -x assembler-with-cpp' + # Linking Parameters + LFLAGS = DEVICE + ' -nostartfiles -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs ' + ' -T ' + LINK_FILE + ' -Wl,-Map=' + MAP_FILE + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -g3' + AFLAGS += ' -g3' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/gd32/risc-v/libraries/Kconfig b/bsp/gd32/risc-v/libraries/Kconfig index 682e10d342f..ac4edcc7a68 100644 --- a/bsp/gd32/risc-v/libraries/Kconfig +++ b/bsp/gd32/risc-v/libraries/Kconfig @@ -7,3 +7,9 @@ config SOC_GD32VF103V select SOC_FAMILY_GD32 select RT_USING_HW_ATOMIC +config SOC_GD32VW553H + bool + select SOC_SERIES_GD32VW + select SOC_FAMILY_GD32 + select RT_USING_HW_ATOMIC + diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c index 8d3df301d42..ade2d7b405b 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -183,7 +183,17 @@ const struct pin_index *get_pin(rt_uint8_t pin) static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { const struct pin_index *index = RT_NULL; - rt_uint32_t pin_mode = 0; + +#if defined(SOC_SERIES_GD32VF103V) + rt_uint32_t pin_mode = GPIO_MODE_OUT_PP; +#elif defined(SOC_SERIES_GD32VW55x) + rt_uint32_t pin_mode = GPIO_MODE_OUTPUT; + rt_uint32_t pin_pull_up_down = GPIO_PUPD_NONE; + rt_uint32_t pin_otype = GPIO_OTYPE_PP; + rt_uint32_t pin_speed = GPIO_OSPEED_25MHZ; +#else +#error "not support soc" +#endif index = get_pin(pin); if (index == RT_NULL) @@ -194,35 +204,74 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) /* GPIO Periph clock enable */ rcu_periph_clock_enable(index->clk); - pin_mode = GPIO_MODE_OUT_PP; - switch(mode) { case PIN_MODE_OUTPUT: /* output setting */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_OUT_PP; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_OUTPUT; +#else +#error "not support soc" +#endif break; case PIN_MODE_OUTPUT_OD: /* output setting: od. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_OUT_OD; +#elif defined(SOC_SERIES_GD32VW55x) + pin_otype = GPIO_OTYPE_OD; +#else +#error "not support soc" +#endif break; case PIN_MODE_INPUT: /* input setting: not pull. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_IN_FLOATING; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_INPUT; +#else +#error "not support soc" +#endif break; case PIN_MODE_INPUT_PULLUP: /* input setting: pull up. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_IPU; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_INPUT; + pin_pull_up_down = GPIO_PUPD_PULLUP; +#else +#error "not support soc" +#endif break; case PIN_MODE_INPUT_PULLDOWN: /* input setting: pull down. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_IPD; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_INPUT; + pin_pull_up_down = GPIO_PUPD_PULLDOWN; +#else +#error "not support soc" +#endif break; default: break; } +#if defined(SOC_SERIES_GD32VF103V) gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); +#elif defined(SOC_SERIES_GD32VW55x) + gpio_mode_set(index->gpio_periph, pin_mode, pin_pull_up_down, index->pin); + gpio_output_options_set(index->gpio_periph, pin_otype, pin_speed, index->pin); +#else +#error "not support soc" +#endif /* SOC_SERIES_GD32VW55x */ + + } /** @@ -329,6 +378,7 @@ static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_hw_interrupt_enable(level); return RT_EOK; } + if (pin_irq_hdr_tab[hdr_index].pin != -1) { rt_hw_interrupt_enable(level); @@ -433,14 +483,22 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_ return -RT_EINVAL; } +#if defined(SOC_SERIES_GD32VF103V) rcu_periph_clock_enable(RCU_AF); - +#elif defined(SOC_SERIES_GD32VW55x) + rcu_periph_clock_enable(RCU_SYSCFG); +#else +#endif /* enable and set interrupt priority */ eclic_irq_enable(irqmap->irqno, 5U, 0U); /* connect EXTI line to GPIO pin */ +#if defined(SOC_SERIES_GD32VF103V) gpio_exti_source_select(index->port_src, index->pin_src); - +#elif defined(SOC_SERIES_GD32VW55x) + syscfg_exti_line_config(index->port_src, index->pin_src); +#else +#endif /* configure EXTI line */ exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_interrupt_flag_clear((exti_line_enum)(index->pin)); @@ -572,3 +630,4 @@ int rt_hw_pin_init(void) INIT_BOARD_EXPORT(rt_hw_pin_init); #endif + diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h index 3bfc37b3638..d415309a950 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,15 +21,27 @@ extern "C" { #if defined SOC_SERIES_GD32VF103V #include "gd32vf103_gpio.h" +#elif defined SOC_SERIES_GD32VW55x +#include "gd32vw55x_gpio.h" +#else +#error "not support soc" #endif #define __GD32_PORT(port) GPIO##port - +#if defined SOC_SERIES_GD32VF103V #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ GPIO##port, GPIO_PIN_##pin, \ GPIO_PORT_SOURCE_GPIO##port, \ GPIO_PIN_SOURCE_##pin} +#elif defined SOC_SERIES_GD32VW55x +#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ + GPIO##port, GPIO_PIN_##pin, \ + EXTI_SOURCE_GPIO##port, \ + EXTI_SOURCE_PIN##pin} +#else +#endif + #define GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c index 328770af418..2b3f8881d15 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2021-08-20 BruceOu first implementation + * 2025-07-11 Wangshun adapt to GD32VV553H */ #include "drv_usart.h" @@ -155,11 +156,11 @@ void UART7_IRQHandler(void) static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART0 { - USART0, // uart peripheral index - USART0_IRQn, // uart iqrn - RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_PIN_9, // tx port, tx pin - GPIOA, GPIO_PIN_10, // rx port, rx pin + USART0, /* uart peripheral index */ + USART0_IRQn, /* uart iqrn */ + RCU_USART0, RCU_GPIOB, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOB, GPIO_PIN_15, /* tx port, tx pin */ + GPIOA, GPIO_PIN_8, /* rx port, rx pin */ &serial0, "uart0", }, @@ -167,11 +168,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART1 { - USART1, // uart peripheral index - USART1_IRQn, // uart iqrn - RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_PIN_2, // tx port, tx pin - GPIOA, GPIO_PIN_3, // rx port, rx pin + USART1, /* uart peripheral index */ + USART1_IRQn, /* uart iqrn */ + RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_2, /* tx port, tx pin */ + GPIOA, GPIO_PIN_3, /* rx port, rx pin */ &serial1, "uart1", }, @@ -179,11 +180,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART2 { - USART2, // uart peripheral index - USART2_IRQn, // uart iqrn - RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock - GPIOB, GPIO_PIN_10, // tx port, tx pin - GPIOB, GPIO_PIN_11, // rx port, rx pin + USART2, /* uart peripheral index */ + USART2_IRQn, /* uart iqrn */ + RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOB, GPIO_PIN_10, /* tx port, tx pin */ + GPIOB, GPIO_PIN_11, /* rx port, rx pin */ &serial2, "uart2", }, @@ -191,11 +192,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART3 { - UART3, // uart peripheral index - UART3_IRQn, // uart iqrn - RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_PIN_10, // tx port, tx pin - GPIOC, GPIO_PIN_11, // rx port, rx pin + UART3, /* uart peripheral index */ + UART3_IRQn, /* uart iqrn */ + RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_10, /* tx port, tx pin */ + GPIOC, GPIO_PIN_11, /* rx port, rx pin */ &serial3, "uart3", }, @@ -203,11 +204,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART4 { - UART4, // uart peripheral index - UART4_IRQn, // uart iqrn - RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_PIN_12, // tx port, tx pin - GPIOD, GPIO_PIN_2, // rx port, rx pin + UART4, /* uart peripheral index */ + UART4_IRQn, /* uart iqrn */ + RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_12, /* tx port, tx pin */ + GPIOD, GPIO_PIN_2, /* rx port, rx pin */ &serial4, "uart4", }, @@ -231,11 +232,19 @@ void gd32_uart_gpio_init(struct gd32_uart *uart) rcu_periph_clock_enable(uart->rx_gpio_clk); rcu_periph_clock_enable(uart->per_clk); - /* connect port to USARTx_Tx */ + /* connect port */ +#if defined SOC_SERIES_GD32VF103V gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); +#else + gpio_af_set(uart->tx_port, GPIO_AF_8, uart->tx_pin); + gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->tx_pin); + gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, uart->tx_pin); + + gpio_af_set(uart->rx_port, GPIO_AF_2, uart->rx_pin); + gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); + gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, uart->rx_pin); +#endif } /** @@ -319,7 +328,9 @@ static rt_err_t gd32_uart_control(struct rt_serial_device *serial, int cmd, void break; case RT_DEVICE_CTRL_SET_INT: +#ifdef SOC_SERIES_GD32VF103V eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); +#endif /* SOC_SERIES_GD32VF103V */ /* enable rx irq */ eclic_irq_enable(uart->irqn, 1, 0); /* enable interrupt */ @@ -442,7 +453,5 @@ int rt_hw_usart_init(void) return result; } - -//INIT_BOARD_EXPORT(rt_hw_usart_init); - #endif + diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h index 5c5c1af2ad9..6a6f75697e6 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,18 +20,18 @@ extern "C" { #endif /* GD32 uart driver */ -// Todo: compress uart info +/* Todo: compress uart info */ struct gd32_uart { - uint32_t uart_periph; //Todo: 3bits - IRQn_Type irqn; //Todo: 7bits - rcu_periph_enum per_clk; //Todo: 5bits - rcu_periph_enum tx_gpio_clk; //Todo: 5bits - rcu_periph_enum rx_gpio_clk; //Todo: 5bits - uint32_t tx_port; //Todo: 4bits - uint16_t tx_pin; //Todo: 4bits - uint32_t rx_port; //Todo: 4bits - uint16_t rx_pin; //Todo: 4bits + uint32_t uart_periph; /* Todo: 3bits */ + IRQn_Type irqn; /* Todo: 7bits */ + rcu_periph_enum per_clk; /* Todo: 5bits */ + rcu_periph_enum tx_gpio_clk; /* Todo: 5bits */ + rcu_periph_enum rx_gpio_clk; /* Todo: 5bits */ + uint32_t tx_port; /* Todo: 4bits */ + uint16_t tx_pin; /* Todo: 4bits */ + uint32_t rx_port; /* Todo: 4bits */ + uint16_t rx_pin; /* Todo: 4bits */ struct rt_serial_device * serial; char *device_name; }; @@ -43,3 +43,4 @@ int rt_hw_usart_init(void); #endif #endif /* __DRV_USART_H__ */ + From 294216b76824f9d0910e8673bfa297c4ea8b1a99 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Fri, 12 Dec 2025 15:58:12 +0800 Subject: [PATCH 16/20] [dm][graphic] support dm mode 1. Add backlight framework for graphic. 2. Add framebuffer and plane, power, EDID for graphic framework 3. Add boot logo render for graphic 4. Update lcd.h Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/graphic/Kconfig | 13 +- components/drivers/graphic/SConscript | 23 + components/drivers/graphic/backlight/Kconfig | 7 + .../drivers/graphic/backlight/SConscript | 14 + .../drivers/graphic/backlight/backlight.c | 231 +++ .../drivers/graphic/framebuffer/Kconfig | 8 + .../drivers/graphic/framebuffer/SConscript | 16 + components/drivers/graphic/graphic.c | 1495 +++++++++++++++++ components/drivers/graphic/graphic_primary.c | 381 +++++ components/drivers/graphic/graphic_simple.c | 295 ++++ components/drivers/graphic/logo/.gitignore | 1 + components/drivers/graphic/logo/Kconfig | 31 + components/drivers/graphic/logo/SConscript | 84 + components/drivers/graphic/logo/logo.c | 216 +++ components/drivers/graphic/logo/logo.html | 243 +++ components/drivers/include/drivers/graphic.h | 367 ++++ components/drivers/include/drivers/lcd.h | 33 + examples/test/dm_graphic_test.c | 310 ++++ examples/test/dm_hmi_test.c | 421 +++++ 19 files changed, 4188 insertions(+), 1 deletion(-) create mode 100644 components/drivers/graphic/SConscript create mode 100644 components/drivers/graphic/backlight/Kconfig create mode 100644 components/drivers/graphic/backlight/SConscript create mode 100644 components/drivers/graphic/backlight/backlight.c create mode 100644 components/drivers/graphic/framebuffer/Kconfig create mode 100644 components/drivers/graphic/framebuffer/SConscript create mode 100644 components/drivers/graphic/graphic.c create mode 100644 components/drivers/graphic/graphic_primary.c create mode 100644 components/drivers/graphic/graphic_simple.c create mode 100644 components/drivers/graphic/logo/.gitignore create mode 100644 components/drivers/graphic/logo/Kconfig create mode 100644 components/drivers/graphic/logo/SConscript create mode 100644 components/drivers/graphic/logo/logo.c create mode 100644 components/drivers/graphic/logo/logo.html create mode 100644 components/drivers/include/drivers/graphic.h create mode 100644 examples/test/dm_graphic_test.c create mode 100644 examples/test/dm_hmi_test.c diff --git a/components/drivers/graphic/Kconfig b/components/drivers/graphic/Kconfig index 5ce0835743e..768d594a998 100644 --- a/components/drivers/graphic/Kconfig +++ b/components/drivers/graphic/Kconfig @@ -1,3 +1,14 @@ config RT_USING_LCD - bool "Using LCD graphic drivers" + bool "Using LCD graphic drivers" if !RT_USING_DM default n + +menuconfig RT_USING_GRAPHIC + bool "Using Graphics device drivers" + depends on RT_USING_DM + default n + +if RT_USING_GRAPHIC + rsource "backlight/Kconfig" + rsource "framebuffer/Kconfig" + rsource "logo/Kconfig" +endif diff --git a/components/drivers/graphic/SConscript b/components/drivers/graphic/SConscript new file mode 100644 index 00000000000..300b71afd77 --- /dev/null +++ b/components/drivers/graphic/SConscript @@ -0,0 +1,23 @@ +from building import * + +group = [] +objs = [] + +if not GetDepend(['RT_USING_GRAPHIC']): + Return('group') + +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd + '/../include'] + +src = ['graphic.c', 'graphic_primary.c', 'graphic_simple.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/components/drivers/graphic/backlight/Kconfig b/components/drivers/graphic/backlight/Kconfig new file mode 100644 index 00000000000..1951e0c05ac --- /dev/null +++ b/components/drivers/graphic/backlight/Kconfig @@ -0,0 +1,7 @@ +menuconfig RT_GRAPHIC_BACKLIGHT + bool "Backlight support" + default n + +if RT_GRAPHIC_BACKLIGHT + osource "$(SOC_DM_GRAPHIC_BACKLIGHT_DIR)/Kconfig" +endif diff --git a/components/drivers/graphic/backlight/SConscript b/components/drivers/graphic/backlight/SConscript new file mode 100644 index 00000000000..6e29db51b3f --- /dev/null +++ b/components/drivers/graphic/backlight/SConscript @@ -0,0 +1,14 @@ +from building import * + +group = [] + +if not GetDepend(['RT_GRAPHIC_BACKLIGHT']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../../include'] + +src = ['backlight.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/components/drivers/graphic/backlight/backlight.c b/components/drivers/graphic/backlight/backlight.c new file mode 100644 index 00000000000..dce54b112b6 --- /dev/null +++ b/components/drivers/graphic/backlight/backlight.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include + +#define DBG_TAG "rtdm.backlight" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include + +static struct rt_dm_ida backlight_ida = RT_DM_IDA_INIT(GRAPHIC_BACKLIGHT); + +static rt_ssize_t _backlight_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_ssize_t res; + int brightness_len; + rt_uint32_t brightness; + char string[sizeof("4294967295")]; + struct rt_backlight_device *bl = rt_container_of(dev, struct rt_backlight_device, parent); + + if ((res = rt_backlight_get_brightness(bl, &brightness))) + { + return res; + } + + brightness_len = rt_sprintf(string, "%u", brightness); + + if (pos < brightness_len) + { + size = rt_min_t(rt_size_t, size, brightness_len - pos); + rt_strncpy(buffer, &string[pos], size); + + return size; + } + else + { + return 0; + } +} + +static rt_ssize_t _backlight_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + rt_ssize_t res; + rt_uint32_t brightness = atoi(buffer); + struct rt_backlight_device *bl = rt_container_of(dev, struct rt_backlight_device, parent); + + if (brightness > bl->props.max_brightness) + { + LOG_D("%s: brightness(%u) > max_brightness(%u)", + rt_dm_dev_get_name(dev), brightness, bl->props.max_brightness); + + return -RT_EINVAL; + } + + if ((res = rt_backlight_set_brightness(bl, brightness))) + { + return res; + } + + LOG_D("%s: brightness to %u", rt_dm_dev_get_name(dev), brightness); + + return size; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops _backlight_ops = +{ + .read = _backlight_read, + .write = _backlight_write, +}; +#endif + +rt_err_t rt_backlight_register(struct rt_backlight_device *bl) +{ + rt_err_t err; + int device_id; + const char *dev_name; + + if (!bl || !bl->ops) + { + return -RT_EINVAL; + } + + if ((device_id = rt_dm_ida_alloc(&backlight_ida)) < 0) + { + return -RT_EFULL; + } + + rt_dm_dev_set_name(&bl->parent, "backlight%u", device_id); + dev_name = rt_dm_dev_get_name(&bl->parent); + + rt_mutex_init(&bl->lock, dev_name, RT_IPC_FLAG_PRIO); + + bl->parent.type = RT_Device_Class_Char; +#ifdef RT_USING_DEVICE_OPS + bl->parent.ops = &_backlight_ops; +#else + bl->parent.read = _backlight_read; + bl->parent.write = _backlight_write; +#endif + bl->parent.master_id = backlight_ida.master_id; + bl->parent.device_id = device_id; + + if ((err = rt_device_register(&bl->parent, dev_name, RT_DEVICE_FLAG_RDWR))) + { + rt_dm_ida_free(&backlight_ida, device_id); + + return err; + } + + return RT_EOK; +} + +rt_err_t rt_backlight_unregister(struct rt_backlight_device *bl) +{ + if (!bl) + { + return -RT_EINVAL; + } + + rt_backlight_set_power(bl, RT_BACKLIGHT_POWER_POWERDOWN); + + rt_dm_ida_free(&backlight_ida, bl->parent.device_id); + + rt_device_unregister(&bl->parent); + + return RT_EOK; +} + +rt_err_t rt_backlight_set_power(struct rt_backlight_device *bl, enum rt_backlight_power power) +{ + rt_err_t err; + enum rt_backlight_power old_power; + + if (!bl || power >= RT_BACKLIGHT_POWER_NR) + { + return -RT_EINVAL; + } + + rt_mutex_take(&bl->lock, RT_WAITING_FOREVER); + + old_power = bl->props.power; + bl->props.power = power; + + if ((err = bl->ops->update_status(bl))) + { + bl->props.power = old_power; + } + + rt_mutex_release(&bl->lock); + + return err; +} + +rt_err_t rt_backlight_get_power(struct rt_backlight_device *bl, enum rt_backlight_power *out_power) +{ + if (!bl || !out_power) + { + return -RT_EINVAL; + } + + rt_mutex_take(&bl->lock, RT_WAITING_FOREVER); + + *out_power = bl->props.power; + + rt_mutex_release(&bl->lock); + + return RT_EOK; +} + +rt_err_t rt_backlight_set_brightness(struct rt_backlight_device *bl, rt_uint32_t brightness) +{ + rt_err_t err; + rt_uint32_t old_brightness; + + if (!bl || brightness > bl->props.max_brightness) + { + return -RT_EINVAL; + } + + rt_mutex_take(&bl->lock, RT_WAITING_FOREVER); + + old_brightness = bl->props.brightness; + bl->props.brightness = brightness; + + if ((err = bl->ops->update_status(bl))) + { + bl->props.brightness = old_brightness; + } + + rt_mutex_release(&bl->lock); + + return err; +} + +rt_err_t rt_backlight_get_brightness(struct rt_backlight_device *bl, rt_uint32_t *out_brightness) +{ + rt_err_t err; + + if (!bl || !out_brightness) + { + return -RT_EINVAL; + } + + rt_mutex_take(&bl->lock, RT_WAITING_FOREVER); + + if (bl->ops->get_brightness) + { + err = bl->ops->get_brightness(bl, out_brightness); + } + else + { + *out_brightness = rt_backlight_power_brightness(bl); + + err = RT_EOK; + } + + rt_mutex_release(&bl->lock); + + return err; +} diff --git a/components/drivers/graphic/framebuffer/Kconfig b/components/drivers/graphic/framebuffer/Kconfig new file mode 100644 index 00000000000..9144377d202 --- /dev/null +++ b/components/drivers/graphic/framebuffer/Kconfig @@ -0,0 +1,8 @@ +menuconfig RT_GRAPHIC_FB + bool "LCD and Frame buffer support" + select RT_USING_LCD + default y + +if RT_GRAPHIC_FB + osource "$(SOC_DM_GRAPHIC_FB_DIR)/Kconfig" +endif diff --git a/components/drivers/graphic/framebuffer/SConscript b/components/drivers/graphic/framebuffer/SConscript new file mode 100644 index 00000000000..55d76c540fc --- /dev/null +++ b/components/drivers/graphic/framebuffer/SConscript @@ -0,0 +1,16 @@ +from building import * + +group = [] + +if not GetDepend(['RT_GRAPHIC_FB']): + Return('group') + +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd + '/../../include'] + +src = [] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/drivers/graphic/graphic.c b/components/drivers/graphic/graphic.c new file mode 100644 index 00000000000..d1692c851e1 --- /dev/null +++ b/components/drivers/graphic/graphic.c @@ -0,0 +1,1495 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "rtdm.graphic" +#define DBG_LVL DBG_INFO +#include + +#define raw_to_graphic(dev) rt_container_of(dev, struct rt_graphic_device, parent) + +struct fb_format +{ + rt_uint32_t mode; + rt_uint32_t bits_per_pixel; + struct fb_bitfield red; + struct fb_bitfield green; + struct fb_bitfield blue; + struct fb_bitfield transp; +}; + +static const struct fb_format graphic_formats[] = +{ + { RTGRAPHIC_PIXEL_FORMAT_GRAY4, 4, }, + { RTGRAPHIC_PIXEL_FORMAT_GRAY16, 16, }, + { RTGRAPHIC_PIXEL_FORMAT_RGB332, 8, { 5, 3 }, { 2, 3 }, { 0, 2 }, }, + { RTGRAPHIC_PIXEL_FORMAT_RGB444, 12, { 8, 4 }, { 4, 4 }, { 0, 4 }, }, + { RTGRAPHIC_PIXEL_FORMAT_RGB565, 16, { 11, 5 }, { 5, 6 }, { 0, 5 }, }, + { RTGRAPHIC_PIXEL_FORMAT_RGB565P, 16, { 0, 5 }, { 5, 6 }, { 11, 5 }, }, + { RTGRAPHIC_PIXEL_FORMAT_BGR565, 16, { 0, 5 }, { 5, 6 }, { 11, 5 }, }, + { RTGRAPHIC_PIXEL_FORMAT_RGB666, 18, { 12, 6 }, { 6, 6 }, { 0, 6 }, }, + { RTGRAPHIC_PIXEL_FORMAT_RGB888, 24, { 16, 8 }, { 8, 8 }, { 0, 8 }, }, + { RTGRAPHIC_PIXEL_FORMAT_BGR888, 24, { 0, 8 }, { 8, 8 }, { 16, 8 }, }, + { RTGRAPHIC_PIXEL_FORMAT_ARGB888, 32, { 16, 8 }, { 8, 8 }, { 0, 8 }, { 24, 8 }, }, + { RTGRAPHIC_PIXEL_FORMAT_ABGR888, 32, { 0, 8 }, { 8, 8 }, { 16, 8 }, { 24, 8 }, }, +}; + +/* RT-Thread device max id is 255 */ +static rt_uint8_t fbcon_map[256] = {}; + +static struct rt_dm_ida graphic_ida = RT_DM_IDA_INIT(GRAPHIC_FRAMEBUFFER); + +rt_inline void spin_lock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_lock(&spinlock->lock); +} + +rt_inline void spin_unlock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_unlock(&spinlock->lock); +} + +static rt_bool_t plane_need_update(struct rt_graphic_plane *plane) +{ + if (plane->ops->update) + { + if (!plane->graphic->update_timer) + { + return RT_TRUE; + } + } + + return RT_FALSE; +} + +static struct rt_graphic_plane *plane_get_current(struct rt_graphic_device *gdev) +{ + if (gdev->ops->current_plane) + { + return gdev->ops->current_plane(gdev); + } + + return gdev->primary_plane; +} + +static rt_err_t plane_fb_remap(struct rt_graphic_plane *plane, + rt_uint32_t mode, struct rt_device_rect_info *rect) +{ + rt_err_t err; + + if (plane->ops->fb_cleanup && (err = plane->ops->fb_cleanup(plane))) + { + return err; + } + + if (!(err = plane->ops->fb_remap(plane, mode, rect))) + { + plane->mode = mode; + plane->x = rect->x; + plane->y = rect->y; + plane->width = rect->width; + plane->height = rect->height; + } + + return err; +} + +static rt_err_t plane_fb_pan_display(struct rt_graphic_plane *plane, + struct rt_device_rect_info *rect) +{ + void *framebuffer_end = plane->framebuffer; + rt_size_t byte_per_pixel = plane->bits_per_pixel / 8; + + framebuffer_end += rect->x * byte_per_pixel; + framebuffer_end += rect->y * plane->line_length; + framebuffer_end += rect->width * rect->height * byte_per_pixel; + + if (framebuffer_end < plane->framebuffer + plane->framebuffer_len) + { + return plane->ops->fb_pan_display(plane, rect); + } + + return -RT_EINVAL; +} + +static rt_err_t graphic_dpms_switch(struct rt_graphic_device *gdev, rt_uint32_t dpms) +{ + rt_err_t err; + + if (!(err = gdev->ops->dpms_switch(gdev, dpms))) + { + gdev->dpms = dpms; + } + + return err; +} + +static rt_err_t _graphic_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_graphic_device *gdev = raw_to_graphic(dev); + struct rt_graphic_plane *plane = gdev->primary_plane; + + if (dev->ref_count > 0 && (oflag & RT_DEVICE_OFLAG_WRONLY)) + { + return -RT_EBUSY; + } + + if (plane->ops->fb_pan_display) + { + struct rt_device_rect_info rect; + + rect.x = 0; + rect.y = 0; + rect.width = plane->width; + rect.height = plane->height; + + return plane->ops->fb_pan_display(plane, &rect); + } + + return RT_EOK; +} + +static rt_ssize_t _graphic_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_ssize_t res; + struct rt_graphic_device *gdev = raw_to_graphic(dev); + struct rt_graphic_plane *plane = gdev->primary_plane; + + res = rt_min_t(rt_ssize_t, plane->framebuffer_len - pos, size); + + if (res > 0) + { + rt_memcpy(buffer, plane->framebuffer + pos, res); + } + else + { + res = 0; + } + + return res; +} + +static rt_ssize_t _graphic_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + rt_ssize_t res; + struct rt_graphic_device *gdev = raw_to_graphic(dev); + struct rt_graphic_plane *plane = gdev->primary_plane; + + res = rt_min_t(rt_ssize_t, plane->framebuffer_len - pos, size); + + if (res > 0) + { + rt_memcpy(plane->framebuffer + pos, buffer, res); + } + else + { + res = 0; + } + + return res; +} + +static rt_err_t _graphic_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t err = RT_EOK; + rt_bool_t need_schedule = RT_FALSE; + struct rt_graphic_device *gdev = raw_to_graphic(dev); + +_retry: + if (need_schedule) + { + rt_thread_yield(); + } + + spin_lock(&gdev->lock); + + switch (cmd) + { + case RT_DEVICE_CTRL_CURSOR_SET_POSITION: + if (args) + { + struct rt_graphic_plane *plane = gdev->cursor_plane; + + if (plane) + { + rt_uint32_t position = (rt_uint32_t)(rt_ubase_t)args; + + plane->x = position >> 16; + plane->y = position & 0xffff; + + if (plane_need_update(plane)) + { + struct rt_device_rect_info rect; + + rect.x = plane->x; + rect.y = plane->y; + /* Ask driver to update position only */ + rect.width = 0; + rect.height = 0; + + err = plane->ops->update(plane, &rect); + } + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + break; + + case RT_DEVICE_CTRL_CURSOR_SET_TYPE: + if (args) + { + struct rt_graphic_plane *plane = gdev->cursor_plane; + + if (plane) + { + struct rt_device_rect_info rect = + { + .x = 0, + .y = 0, + .width = plane->width, + .height = plane->height, + }; + + if (!plane->framebuffer) + { + rt_uint32_t mode; + + if (plane->mode == RTGRAPHIC_PIXEL_FORMAT_MONO) + { + mode = plane->modes[0]; + } + else + { + mode = plane->mode; + } + + if ((err = plane_fb_remap(plane, mode, &rect))) + { + break; + } + } + + rt_memcpy(plane->framebuffer, args, plane->screen_len); + + /* Force to update */ + err = plane->ops->update(plane, &rect); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_RECT_UPDATE: + if (args) + { + struct rt_graphic_plane *plane = plane_get_current(gdev); + + if (plane_need_update(plane)) + { + err = plane->ops->update(plane, args); + } + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_POWERON: + if (gdev->ops->dpms_switch) + { + err = graphic_dpms_switch(gdev, RT_GRAPHIC_DPMS_ON); + } + #ifdef RT_GRAPHIC_BACKLIGHT + if (!err && gdev->backlight) + { + spin_unlock(&gdev->lock); + err = rt_backlight_set_power(gdev->backlight, RT_BACKLIGHT_POWER_NORMAL); + spin_lock(&gdev->lock); + } + #endif /* RT_GRAPHIC_BACKLIGHT */ + break; + + case RTGRAPHIC_CTRL_POWEROFF: + if (gdev->ops->dpms_switch) + { + err = graphic_dpms_switch(gdev, RT_GRAPHIC_DPMS_OFF); + } + #ifdef RT_GRAPHIC_BACKLIGHT + if (!err && gdev->backlight) + { + spin_unlock(&gdev->lock); + err = rt_backlight_set_power(gdev->backlight, RT_BACKLIGHT_POWER_POWERDOWN); + spin_lock(&gdev->lock); + } + #endif /* RT_GRAPHIC_BACKLIGHT */ + break; + + case RTGRAPHIC_CTRL_GET_INFO: + if (args) + { + struct rt_device_graphic_info *info = args; + struct rt_graphic_plane *plane = plane_get_current(gdev); + + info->pixel_format = plane->mode; + info->bits_per_pixel = plane->bits_per_pixel; + info->pitch = plane->line_length; + info->width = plane->width; + info->height = plane->height; + info->framebuffer = plane->framebuffer; + info->smem_len = plane->framebuffer_len; + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_SET_MODE: + if (args) + { + rt_uint32_t mode = (rt_uint32_t)(rt_ubase_t)args; + struct rt_graphic_plane *plane = plane_get_current(gdev); + + if (mode != plane->mode) + { + err = -RT_ENOSYS; + + if (plane->modes_nr > 1) + { + for (int i = 0; i < plane->modes_nr; ++i) + { + if (mode == plane->modes[i]) + { + struct rt_device_rect_info rect = + { + .x = plane->x, + .y = plane->y, + .width = plane->width, + .height = plane->height, + }; + + err = plane_fb_remap(plane, mode, &rect); + break; + } + } + } + } + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_GET_EXT: + if (args) + { + rt_memcpy(args, &gdev->edid, sizeof(gdev->edid)); + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_SET_BRIGHTNESS: + if (gdev->ops->set_brightness) + { + err = gdev->ops->set_brightness(gdev, (rt_uint32_t)(rt_ubase_t)args); + } + #ifdef RT_GRAPHIC_BACKLIGHT + if (!err && gdev->backlight) + { + spin_unlock(&gdev->lock); + + return rt_backlight_set_brightness(gdev->backlight, (rt_uint32_t)(rt_ubase_t)args); + } + #endif /* RT_GRAPHIC_BACKLIGHT */ + break; + + case RTGRAPHIC_CTRL_GET_BRIGHTNESS: + if (args) + { + if (gdev->ops->get_brightness) + { + err = gdev->ops->get_brightness(gdev, args); + } + else + { + *(rt_uint32_t *)args = RT_UINT32_MAX >> 1; + } + } + else + { + err = -RT_EINVAL; + } + #ifdef RT_GRAPHIC_BACKLIGHT + if (!err && gdev->backlight) + { + spin_unlock(&gdev->lock); + + return rt_backlight_get_brightness(gdev->backlight, args); + } + #endif /* RT_GRAPHIC_BACKLIGHT */ + break; + + case RTGRAPHIC_CTRL_GET_MODE: + if (args) + { + struct rt_graphic_plane *plane = plane_get_current(gdev); + + *(rt_uint32_t *)args = plane->mode; + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_GET_STATUS: + if (args) + { + if (gdev->ops->get_status) + { + err = gdev->ops->get_status(gdev, args); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_PAN_DISPLAY: + if (args) + { + struct rt_graphic_plane *plane = plane_get_current(gdev); + + if (plane->ops->fb_pan_display) + { + rt_size_t offset; + struct rt_device_rect_info rect; + + offset = (rt_size_t)(args - plane->framebuffer); + + rect.x = (offset % plane->line_length) / (plane->bits_per_pixel / 8); + rect.y = offset / plane->line_length; + rect.width = plane->width; + rect.height = plane->height; + + err = plane_fb_pan_display(plane, &rect); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + break; + + case RTGRAPHIC_CTRL_WAIT_VSYNC: + if (gdev->ops->wait_vsync) + { + err = gdev->ops->wait_vsync(gdev); + } + break; + + case RT_DEVICE_CTRL_NOTIFY_SET: + if (args) + { + if (rt_atomic_load(&gdev->event_notifying) == RT_TRUE) + { + need_schedule = RT_TRUE; + + spin_unlock(&gdev->lock); + goto _retry; + } + + rt_memcpy(&gdev->event_notify, args, sizeof(gdev->event_notify)); + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIOGET_VSCREENINFO: + if (args) + { + struct fb_var_screeninfo *var = args; + struct rt_graphic_plane *plane = plane_get_current(gdev); + + rt_memset(var, 0, sizeof(*var)); + + var->xres = plane->width; + var->yres = plane->height; + var->xres_virtual = plane->width; + var->yres_virtual = plane->height * (plane->framebuffer_len / plane->screen_len); + var->bits_per_pixel = plane->bits_per_pixel; + + if (plane == gdev->primary_plane) + { + var->width = gdev->edid.width_cm ? gdev->edid.width_cm * 10 : -1; + var->height = gdev->edid.height_cm ? gdev->edid.height_cm * 10 : -1; + } + else + { + var->width = -1; + var->height = -1; + } + + if (plane->mode == RTGRAPHIC_PIXEL_FORMAT_GRAY4 || + plane->mode == RTGRAPHIC_PIXEL_FORMAT_GRAY16) + { + var->grayscale = 1; + } + else + { + const struct fb_format *fmt = &graphic_formats[0]; + + for (int i = 0; i < RT_ARRAY_SIZE(graphic_formats); ++i, ++fmt) + { + if (fmt->mode == plane->mode) + { + rt_memcpy(&var->red, &fmt->red, sizeof(fmt->red)); + rt_memcpy(&var->green, &fmt->green, sizeof(fmt->green)); + rt_memcpy(&var->blue, &fmt->blue, sizeof(fmt->blue)); + rt_memcpy(&var->transp, &fmt->transp, sizeof(fmt->transp)); + + break; + } + } + } + + if (gdev->update_timer) + { + rt_uint64_t update_ps; + rt_tick_t update_tick; + + rt_timer_control(gdev->update_timer, RT_TIMER_CTRL_GET_TIME, &update_tick); + /* + * 1s update_ms * 1000 + * -------------------- = ----------------- (second/tick) + * RT_TICK_PER_SECOND update_tick + * + * 1000000ps = 1ms + */ + update_ps = (update_tick * 1000000) / (RT_TICK_PER_SECOND * 1000); + + var->pixclock = update_ps / (var->xres * var->yres); + } + else + { + var->pixclock = (RT_GRAPHIC_UPDATE_MS * 1000000) / (var->xres * var->yres); + } + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIOPUT_VSCREENINFO: + if (args) + { + rt_uint32_t mode; + struct fb_format fmt; + struct rt_device_rect_info rect; + struct fb_var_screeninfo *var = args; + struct rt_graphic_plane *plane = plane_get_current(gdev); + const rt_size_t cmp_offset = rt_offsetof(struct fb_format, bits_per_pixel); + const rt_size_t cmp_size = sizeof(struct fb_format) - cmp_offset; + + if (!plane->ops->fb_pan_display) + { + if (var->xres != plane->width || var->yres != plane->height || + var->xoffset != plane->x || var->yoffset != plane->y) + { + err = -RT_ENOSYS; + break; + } + } + + mode = plane->mode; + rect.x = plane->x; + rect.y = plane->y; + rect.width = plane->width; + rect.height = plane->height; + + fmt.bits_per_pixel = var->bits_per_pixel; + rt_memcpy(&fmt.red, &var->red, sizeof(fmt.red)); + rt_memcpy(&fmt.green, &var->green, sizeof(fmt.green)); + rt_memcpy(&fmt.blue, &var->blue, sizeof(fmt.blue)); + rt_memcpy(&fmt.transp, &var->transp, sizeof(fmt.transp)); + + for (int i = 0; i < RT_ARRAY_SIZE(graphic_formats); ++i) + { + void *cmp_to = ((void *)&fmt) + cmp_offset; + void *cmp_from = ((void *)&graphic_formats[i]) + cmp_offset; + + if (!rt_memcmp(cmp_to, cmp_from, cmp_size)) + { + mode = graphic_formats[i].mode; + break; + } + } + + err = -RT_ENOSYS; + + for (int i = 0; i < plane->modes_nr; ++i) + { + /* Check supported and commit */ + if (plane->modes[i] == mode && plane->mode != mode) + { + err = plane_fb_remap(plane, mode, &rect); + } + } + + if (!err && plane->ops->fb_pan_display) + { + rect.x = var->xoffset; + rect.y = var->yoffset; + rect.width = var->xres; + rect.height = var->yres; + + err = plane_fb_pan_display(plane, &rect); + } + + if (!err && var->rotate && plane->ops->prop_set) + { + err = plane->ops->prop_set(plane, RT_GRAPHIC_PLANE_PROP_ROTATE, + (void *)(rt_ubase_t)((var->rotate % 360) / 90)); + } + + if (!err && plane == gdev->primary_plane && plane->ops->update) + { + rt_uint32_t update_ms = 0; + + if (var->pixclock) + { + rt_uint64_t clock_cycles; + + clock_cycles = var->pixclock; + clock_cycles *= rect.width; + clock_cycles *= rect.height; + /* Seconds in pico seconds */ + clock_cycles /= 1000000000000ULL; + + update_ms = (rt_uint32_t)clock_cycles * 1000; + } + + err = rt_graphic_device_update_auto(gdev, update_ms); + } + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIOGET_FSCREENINFO: + if (args) + { + struct fb_fix_screeninfo *fix = args; + struct rt_graphic_plane *plane = plane_get_current(gdev); + + rt_memset(fix, 0, sizeof(*fix)); + + rt_snprintf(fix->id, rt_min_t(int, sizeof(fix->id), RT_NAME_MAX), + "%s", rt_dm_dev_get_name(&gdev->parent)); + + fix->smem_start = (unsigned long)rt_kmem_v2p(plane->framebuffer); + fix->smem_len = plane->framebuffer_len; + fix->mmio_start = fix->smem_start; + fix->mmio_len = plane->screen_len; + fix->line_length = plane->line_length; + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIOGET_PIXELINFO: + if (args) + { + struct rt_graphic_plane *plane = plane_get_current(gdev); + + *(rt_uint32_t *)args = plane->mode; + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIOPAN_DISPLAY: + if (args) + { + struct fb_var_screeninfo *var = args; + struct rt_graphic_plane *plane = plane_get_current(gdev); + + if (plane->ops->fb_pan_display) + { + struct rt_device_rect_info rect; + + rect.x = var->xoffset; + rect.y = var->yoffset; + rect.width = var->xres; + rect.height = var->yres; + + err = plane_fb_pan_display(plane, &rect); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIO_CURSOR: + err = -RT_EINVAL; + break; + + case FBIOGET_CON2FBMAP: + if (args) + { + struct fb_con2fbmap *con2fbmap = args; + + if (con2fbmap->console < RT_ARRAY_SIZE(fbcon_map)) + { + con2fbmap->framebuffer = fbcon_map[con2fbmap->console]; + } + else + { + err = -RT_EFULL; + } + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIOPUT_CON2FBMAP: + if (args) + { + struct fb_con2fbmap *con2fbmap = args; + + if (con2fbmap->console < RT_ARRAY_SIZE(fbcon_map) && + con2fbmap->framebuffer < RT_ARRAY_SIZE(fbcon_map)) + { + struct rt_device *vt; + + vt = rt_dm_device_find(MASTER_ID_TTY, con2fbmap->console); + + #ifdef RT_SERIAL_VIRTUAL + if (!vt) + { + vt = rt_device_find("vuart"); + } + #endif + + if (vt) + { + if (!(err = rt_device_open(vt, RT_DEVICE_OFLAG_RDWR))) + { + err = rt_device_control(vt, FBIOPUT_CON2FBMAP, con2fbmap); + + if (!err) + { + fbcon_map[con2fbmap->console] = con2fbmap->framebuffer; + } + + rt_device_close(vt); + } + } + else + { + err = -RT_EEMPTY; + } + } + else + { + err = -RT_EFULL; + } + } + else + { + err = -RT_EINVAL; + } + break; + + case FBIOBLANK: + if (gdev->ops->dpms_switch) + { + rt_uint32_t dpms; + + switch ((rt_uint32_t)(rt_ubase_t)args) + { + case FB_BLANK_UNBLANK: + /* Display: On, HSync: On, VSync: On */ + dpms = RT_GRAPHIC_DPMS_ON; + break; + + case FB_BLANK_NORMAL: + /* Display: Off, HSync: On, VSync: On */ + dpms = RT_GRAPHIC_DPMS_STANDBY; + break; + + case FB_BLANK_HSYNC_SUSPEND: + /* Display: Off, HSync: Off, VSync: On */ + dpms = RT_GRAPHIC_DPMS_STANDBY; + break; + + case FB_BLANK_VSYNC_SUSPEND: + /* Display: Off, HSync: On, VSync: Off */ + dpms = RT_GRAPHIC_DPMS_SUSPEND; + break; + + case FB_BLANK_POWERDOWN: + /* Display: Off, HSync: Off, VSync: Off */ + dpms = RT_GRAPHIC_DPMS_OFF; + break; + + default: + err = -RT_EINVAL; + break; + } + + if (!err) + { + graphic_dpms_switch(gdev, dpms); + } + } + break; + + case FBIO_WAITFORVSYNC: + if (gdev->ops->wait_vsync) + { + err = gdev->ops->wait_vsync(gdev); + } + break; + + case FBIO_ALLOC: + case FBIO_FREE: + case FBIOGET_GLYPH: + case FBIOGET_HWCINFO: + case FBIOPUT_MODEINFO: + case FBIOGET_DISPINFO: + LOG_D("FB IOCTL (%x) only used for SiS 300/630/730/540/315/550/650/740 frame buffer device", cmd); + /* Fall through */ + case FBIOGET_VBLANK: + case FBIOGETCMAP: /* fb_cmap */ + case FBIOPUTCMAP: /* fb_cmap */ + /* Fall through */ + default: + if (gdev->ops->control) + { + err = gdev->ops->control(gdev, cmd, args); + } + else + { + err = -RT_ENOSYS; + } + } + + spin_unlock(&gdev->lock); + + return err; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops _graphic_ops = +{ + .open = _graphic_open, + .read = _graphic_read, + .write = _graphic_write, + .control = _graphic_control, +}; +#endif + +static void graphic_ofw_init(struct rt_graphic_device *gdev) +{ +#ifdef RT_USING_OFW + struct rt_ofw_node *np = gdev->parent.ofw_node; + +#ifdef RT_GRAPHIC_BACKLIGHT + if (!gdev->backlight) + { + struct rt_ofw_node *bl_np = rt_ofw_parse_phandle(np, "backlight", 0); + + if (bl_np && (gdev->backlight = rt_ofw_data(bl_np))) + { + rt_device_open(&gdev->backlight->parent, RT_DEVICE_OFLAG_RDWR); + } + rt_ofw_node_put(bl_np); + } +#endif /* RT_GRAPHIC_BACKLIGHT */ + + (void)np; +#endif /* RT_USING_OFW */ +} + +static void graphic_edid_res(struct rt_graphic_device *gdev, + rt_uint32_t *out_width, rt_uint32_t *out_height) +{ + struct edid *edid = &gdev->edid; + struct detailed_timing *dt = &edid->detailed_timings[0]; + struct detailed_pixel_timing *dpt = &dt->data.pixel_data; + + *out_width = dpt->hactive_lo + ((dpt->hactive_hblank_hi & 0xf0) << 4); + *out_height = dpt->vactive_lo + ((dpt->vactive_vblank_hi & 0xf0) << 4); +} + +#ifdef RT_USING_PM +static rt_err_t _graphic_pm_dpms_switch(struct rt_graphic_device *gdev, rt_uint8_t mode) +{ + rt_err_t err; + + spin_lock(&gdev->lock); + + switch (mode) + { + case PM_SLEEP_MODE_NONE: + case PM_SLEEP_MODE_IDLE: + case PM_SLEEP_MODE_LIGHT: + case PM_SLEEP_MODE_DEEP: + err = graphic_dpms_switch(gdev, RT_GRAPHIC_DPMS_ON); + break; + + case PM_SLEEP_MODE_STANDBY: + err = graphic_dpms_switch(gdev, RT_GRAPHIC_DPMS_STANDBY); + break; + + case PM_SLEEP_MODE_SHUTDOWN: + err = graphic_dpms_switch(gdev, RT_GRAPHIC_DPMS_OFF); + break; + + default: + err = -RT_EINVAL; + break; + } + + spin_unlock(&gdev->lock); + + return err; +} + +static rt_err_t _graphic_pm_suspend(const struct rt_device *device, rt_uint8_t mode) +{ + struct rt_graphic_device *gdev = raw_to_graphic(device); + + return _graphic_pm_dpms_switch(gdev, mode); +} + +static void _graphic_pm_resume(const struct rt_device *device, rt_uint8_t mode) +{ + struct rt_graphic_device *gdev = raw_to_graphic(device); + + _graphic_pm_dpms_switch(gdev, mode); +} + +static const struct rt_device_pm_ops _graphic_pm_ops = +{ + .suspend = _graphic_pm_suspend, + .resume = _graphic_pm_resume, +}; +#endif /* RT_USING_PM */ + +rt_err_t rt_graphic_device_register(struct rt_graphic_device *gdev) +{ + rt_err_t err; + int device_id; + const char *dev_name; + + if (!gdev || !gdev->ops) + { + return -RT_EINVAL; + } + + if (!gdev->primary_plane) + { + LOG_E("%s: Not %s found", rt_dm_dev_get_name(&gdev->parent), "primary plane"); + + return -RT_EINVAL; + } + + if ((device_id = rt_dm_ida_alloc(&graphic_ida)) < 0) + { + return -RT_EFULL; + } + + rt_dm_dev_set_name(&gdev->parent, "fb%u", device_id); + dev_name = rt_dm_dev_get_name(&gdev->parent); + + rt_list_init(&gdev->overlay_nodes); + rt_dm_ida_init(&gdev->plane_ida, CUSTOM); + rt_spin_lock_init(&gdev->lock); + + graphic_ofw_init(gdev); + + if (!gdev->primary_plane->width || !gdev->primary_plane->height) + { + rt_uint32_t mode, width, height; + struct rt_device_rect_info rect; + + graphic_edid_res(gdev, &width, &height); + rect.x = 0; + rect.y = 0; + rect.width = width; + rect.height = height; + + if (gdev->primary_plane->mode == RTGRAPHIC_PIXEL_FORMAT_MONO) + { + mode = gdev->primary_plane->modes[0]; + } + else + { + mode = gdev->primary_plane->mode; + } + + err = plane_fb_remap(gdev->primary_plane, mode, &rect); + + if (err) + { + LOG_E("%s: Set %s error = %s", rt_dm_dev_get_name(&gdev->parent), + "primary plane", rt_strerror(err)); + + goto _fail; + } + } + + gdev->parent.type = RT_Device_Class_Graphic; +#ifdef RT_USING_DEVICE_OPS + gdev->parent.ops = &_graphic_ops; +#else + gdev->parent.open = _graphic_open; + gdev->parent.read = _graphic_read; + gdev->parent.write = _graphic_write; + gdev->parent.control = _graphic_control; +#endif + gdev->parent.master_id = graphic_ida.master_id; + gdev->parent.device_id = device_id; + + if ((err = rt_device_register(&gdev->parent, dev_name, RT_DEVICE_FLAG_RDWR))) + { + goto _fail; + } + +#ifdef RT_USING_PM + rt_pm_device_register(&gdev->parent, &_graphic_pm_ops); +#endif + + if ((err = rt_graphic_logo_render(gdev))) + { + LOG_D("Logo render error = %s", rt_strerror(err)); + } + + return RT_EOK; + +_fail: + rt_dm_ida_free(&graphic_ida, device_id); + + return err; +} + +rt_err_t rt_graphic_device_unregister(struct rt_graphic_device *gdev) +{ + const char *dev_name; + struct rt_graphic_plane *plane, *plane_next; + + if (!gdev) + { + return -RT_EINVAL; + } + + dev_name = rt_dm_dev_get_name(&gdev->parent); + + if (gdev->parent.ref_count) + { + LOG_E("%s: there is %u user", dev_name, gdev->parent.ref_count); + return -RT_EINVAL; + } + +#ifdef RT_USING_PM + rt_pm_device_unregister(&gdev->parent); +#endif + + rt_graphic_device_update_auto(gdev, 0); + + if (gdev->ops->dpms_switch) + { + graphic_dpms_switch(gdev, RT_GRAPHIC_DPMS_OFF); + } +#ifdef RT_GRAPHIC_BACKLIGHT + if (gdev->backlight) + { + rt_backlight_set_power(gdev->backlight, RT_BACKLIGHT_POWER_POWERDOWN); + rt_device_close(&gdev->backlight->parent); + } +#endif + + rt_list_for_each_entry_safe(plane, plane_next, &gdev->overlay_nodes, list) + { + rt_graphic_device_del_plane(gdev, plane); + rt_graphic_device_free_plane(plane); + } + + rt_graphic_device_del_plane(gdev, gdev->primary_plane); + rt_graphic_device_free_plane(gdev->primary_plane); + + if (gdev->cursor_plane) + { + rt_graphic_device_del_plane(gdev, gdev->cursor_plane); + rt_graphic_device_free_plane(gdev->cursor_plane); + } + + rt_dm_ida_free(&graphic_ida, gdev->parent.device_id); + + rt_device_unregister(&gdev->parent); + + return RT_EOK; +} + +struct rt_graphic_plane *rt_graphic_device_alloc_plane(struct rt_graphic_device *gdev, + rt_size_t priv_size, const struct rt_graphic_plane_ops *ops, + const rt_uint32_t *modes, rt_uint32_t modes_nr, rt_uint8_t type) +{ + struct rt_graphic_plane *plane = RT_NULL; + + if (!gdev || !ops || !modes || !modes_nr || type > RT_GRAPHIC_PLANE_TYPE_CURSOR) + { + return RT_NULL; + } + + plane = rt_calloc(1, sizeof(*plane) + priv_size); + + if (plane) + { + rt_list_init(&plane->list); + plane->type = type; + plane->modes_nr = modes_nr; + plane->modes = modes; + plane->mode = RTGRAPHIC_PIXEL_FORMAT_MONO; + plane->graphic = gdev; + plane->ops = ops; + } + + return plane; +} + +void rt_graphic_device_free_plane(struct rt_graphic_plane *plane) +{ + if (!plane) + { + return; + } + + rt_free(plane); +} + +rt_err_t rt_graphic_device_add_plane(struct rt_graphic_device *gdev, + struct rt_graphic_plane *plane) +{ + rt_err_t err = RT_EOK; + + if (!gdev || !plane) + { + return -RT_EINVAL; + } + + if (!plane->ops) + { + LOG_E("%s: %s have no plane ops", + rt_dm_dev_get_name(&gdev->parent), plane->name); + return -RT_EINVAL; + } + + plane->id = rt_dm_ida_alloc(&gdev->plane_ida); + + if (plane->id == RT_DM_IDA_NUM) + { + LOG_E("%s: %s is out of plane max(%d)", + rt_dm_dev_get_name(&gdev->parent), plane->name, RT_DM_IDA_NUM - 1); + return -RT_EFULL; + } + + if (plane->type == RT_GRAPHIC_PLANE_TYPE_PRIMARY) + { + if (gdev->primary_plane) + { + err = -RT_EINVAL; + goto _free_ida; + } + if (!plane->name[0]) + { + rt_strncpy(plane->name, "primary", sizeof(plane->name)); + } + gdev->primary_plane = plane; + } + else if (plane->type == RT_GRAPHIC_PLANE_TYPE_CURSOR) + { + if (gdev->cursor_plane) + { + err = -RT_EINVAL; + goto _free_ida; + } + if (!plane->name[0]) + { + rt_strncpy(plane->name, "cursor", sizeof(plane->name)); + } + gdev->cursor_plane = plane; + } + else if (plane->type == RT_GRAPHIC_PLANE_TYPE_OVERLAY) + { + if (!plane->name[0]) + { + rt_snprintf(plane->name, sizeof(plane->name), "overlay-%u", plane->id); + } + spin_lock(&gdev->lock); + rt_list_insert_before(&gdev->overlay_nodes, &plane->list); + rt_graphic_device_leave(gdev); + } + else + { + LOG_E("What the fuck plane type(%u)", plane->type); + RT_ASSERT(0); + } + +_free_ida: + if (err) + { + rt_dm_ida_free(&gdev->plane_ida, plane->id); + } + + return err; +} + +rt_err_t rt_graphic_device_del_plane(struct rt_graphic_device *gdev, + struct rt_graphic_plane *plane) +{ + if (!gdev || !plane) + { + return -RT_EINVAL; + } + + if (plane->ops->fb_cleanup) + { + /* Ignore error */ + plane->ops->fb_cleanup(plane); + } + + if (plane->type == RT_GRAPHIC_PLANE_TYPE_PRIMARY) + { + gdev->primary_plane = RT_NULL; + } + else if (plane->type == RT_GRAPHIC_PLANE_TYPE_CURSOR) + { + gdev->cursor_plane = RT_NULL; + } + else if (plane->type == RT_GRAPHIC_PLANE_TYPE_OVERLAY) + { + spin_lock(&gdev->lock); + rt_list_remove(&plane->list); + spin_unlock(&gdev->lock); + } + + rt_dm_ida_free(&gdev->plane_ida, plane->id); + + return RT_EOK; +} + +void rt_graphic_device_hotplug_event(struct rt_graphic_device *gdev) +{ + rt_err_t err; + rt_uint32_t width, height; + struct rt_device_rect_info rect; + + RT_ASSERT(gdev != RT_NULL); + + rt_graphic_device_enter(gdev); + + graphic_edid_res(gdev, &width, &height); + rect.x = 0; + rect.y = 0; + rect.width = width; + rect.height = height; + + err = plane_fb_remap(gdev->primary_plane, gdev->primary_plane->mode, &rect); + + if (err) + { + /* What the fuck? */ + LOG_E("%s: hotplug event process error = %s", + rt_dm_dev_get_name(&gdev->parent), rt_strerror(err)); + goto _out_lock; + } + +_out_lock: + rt_graphic_device_leave(gdev); + + rt_atomic_store(&gdev->event_notifying, RT_TRUE); + + if (gdev->event_notify.notify) + { + gdev->event_notify.notify(gdev->event_notify.dev); + } + + rt_atomic_store(&gdev->event_notifying, RT_FALSE); +} + +static void graphic_device_plane_update(struct rt_graphic_plane *plane, + struct rt_device_rect_info *rect) +{ + if (plane->ops->update) + { + plane->ops->update(plane, rect); + } +} + +static void graphic_device_update(void *param) +{ + struct rt_device_rect_info rect; + struct rt_graphic_plane *plane; + struct rt_graphic_device *gdev = param; + + rect.x = 0; + rect.y = 0; + + spin_lock(&gdev->lock); + + rect.width = gdev->primary_plane->width; + rect.height = gdev->primary_plane->height; + graphic_device_plane_update(gdev->primary_plane, &rect); + + rt_list_for_each_entry(plane, &gdev->overlay_nodes, list) + { + rect.width = plane->width; + rect.height = plane->height; + + graphic_device_plane_update(plane, &rect); + } + + if ((plane = gdev->cursor_plane)) + { + rect.x = plane->x; + rect.y = plane->y; + /* Ask driver to update position only */ + rect.width = 0; + rect.height = 0; + + graphic_device_plane_update(plane, &rect); + } + + spin_unlock(&gdev->lock); +} + +rt_err_t rt_graphic_device_update_auto(struct rt_graphic_device *gdev, rt_uint32_t update_ms) +{ + if (!gdev) + { + return -RT_EINVAL; + } + + if (update_ms) + { + if (!gdev->update_timer) + { + char name[RT_NAME_MAX]; + + rt_snprintf(name, sizeof(name), "update-%s", rt_dm_dev_get_name(&gdev->parent)); + + gdev->update_timer = rt_timer_create(name, &graphic_device_update, gdev, + rt_tick_from_millisecond(update_ms), + RT_TIMER_FLAG_PERIODIC); + + if (!gdev->update_timer) + { + return -RT_ENOMEM; + } + } + + rt_timer_start(gdev->update_timer); + } + else if (gdev->update_timer) + { + rt_timer_stop(gdev->update_timer); + rt_timer_delete(gdev->update_timer); + + gdev->update_timer = RT_NULL; + } + + return RT_EOK; +} + +void rt_graphic_device_enter(struct rt_graphic_device *gdev) +{ + RT_ASSERT(gdev != RT_NULL); + + spin_lock(&gdev->lock); + + if (gdev->update_timer) + { + rt_timer_stop(gdev->update_timer); + } +} + +void rt_graphic_device_leave(struct rt_graphic_device *gdev) +{ + RT_ASSERT(gdev != RT_NULL); + + if (gdev->update_timer) + { + rt_timer_start(gdev->update_timer); + } + + spin_unlock(&gdev->lock); +} + +rt_uint32_t rt_graphic_mode_bpp(rt_uint32_t mode) +{ + for (int i = 0; i < RT_ARRAY_SIZE(graphic_formats); ++i) + { + if (graphic_formats[i].mode == mode) + { + return graphic_formats[i].bits_per_pixel; + } + } + + return 0; +} diff --git a/components/drivers/graphic/graphic_primary.c b/components/drivers/graphic/graphic_primary.c new file mode 100644 index 00000000000..411931196fa --- /dev/null +++ b/components/drivers/graphic/graphic_primary.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "graphic.primary" +#define DBG_LVL DBG_INFO +#include + +static struct rt_graphic_device *primary_gdev = RT_NULL; + +#define framebuffer_drift(plane, x, y, bpp) \ + ((plane)->framebuffer + (x) * ((bpp) / 8) + (y) * (plane)->line_length) + +#define fixup_dir(a1, a2) \ + if ((a1) > (a2)) { (a1) ^= (a2); (a2) ^= (a1); (a1) ^= (a2); } + +static void graphic_primary_set_pixel_8bit(const char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint8_t *)framebuffer_drift(plane, x, y, 8) = *(rt_uint8_t *)pixel; +} + +static void graphic_primary_get_pixel_8bit(char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint8_t *)pixel = *(rt_uint8_t *)framebuffer_drift(plane, x, y, 8); +} + +static void graphic_primary_draw_hline_8bit(const char *pixel, int x1, int x2, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(x1, x2); + rt_memset(framebuffer_drift(plane, x1, y, 8), *(rt_uint8_t *)pixel, x2 - x1); +} + +static void graphic_primary_draw_vline_8bit(const char *pixel, int x, int y1, int y2) +{ + rt_uint8_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(y1, y2); + fb = framebuffer_drift(plane, x, y1, 8); + + for (; y1 < y2; ++y1) + { + *fb = *(rt_uint8_t *)pixel; + fb += plane->line_length; + } +} + +static void graphic_primary_blit_line_8bit(const char *pixel, int x, int y, rt_size_t size) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + rt_memcpy(framebuffer_drift(plane, x, y, 8), pixel, size); +} + +static struct rt_device_graphic_ops graphic_primary_8bit_ops = +{ + .set_pixel = graphic_primary_set_pixel_8bit, + .get_pixel = graphic_primary_get_pixel_8bit, + .draw_hline = graphic_primary_draw_hline_8bit, + .draw_vline = graphic_primary_draw_vline_8bit, + .blit_line = graphic_primary_blit_line_8bit, +}; + +static void graphic_primary_set_pixel_16bit(const char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint16_t *)framebuffer_drift(plane, x, y, 16) = *(rt_uint16_t *)pixel; +} + +static void graphic_primary_get_pixel_16bit(char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint16_t *)pixel = *(rt_uint16_t *)framebuffer_drift(plane, x, y, 16); +} + +static void graphic_primary_draw_hline_16bit(const char *pixel, int x1, int x2, int y) +{ + rt_uint16_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(x1, x2); + + fb = framebuffer_drift(plane, x1, y, 16); + + for (; x1 < x2; ++x1) + { + *fb++ = *(rt_uint16_t *)pixel; + } +} + +static void graphic_primary_draw_vline_16bit(const char *pixel, int x, int y1, int y2) +{ + rt_uint16_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(y1, y2); + + fb = framebuffer_drift(plane, x, y1, 16); + + for (; y1 < y2; ++y1) + { + *fb = *(rt_uint16_t *)pixel; + fb = (void *)fb + plane->line_length; + } +} + +static void graphic_primary_blit_line_16bit(const char *pixel, int x, int y, rt_size_t size) +{ + rt_uint16_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fb = framebuffer_drift(plane, x, y, 16); + + while (size --> 0) + { + *fb++ = *(rt_uint16_t *)pixel; + pixel += 2; + } +} + +static struct rt_device_graphic_ops graphic_primary_16bit_ops = +{ + .set_pixel = graphic_primary_set_pixel_16bit, + .get_pixel = graphic_primary_get_pixel_16bit, + .draw_hline = graphic_primary_draw_hline_16bit, + .draw_vline = graphic_primary_draw_vline_16bit, + .blit_line = graphic_primary_blit_line_16bit, +}; + +static void graphic_primary_set_pixel_24bit(const char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + rt_memcpy(framebuffer_drift(plane, x, y, 24), pixel, 3); +} + +static void graphic_primary_get_pixel_24bit(char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + rt_memcpy(pixel, framebuffer_drift(plane, x, y, 24), 3); +} + +static void graphic_primary_draw_hline_24bit(const char *pixel, int x1, int x2, int y) +{ + rt_uint8_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(x1, x2); + + fb = framebuffer_drift(plane, x1, y, 24); + + for (; x1 < x2; ++x1) + { + *fb++ = ((rt_uint8_t *)pixel)[0]; + *fb++ = ((rt_uint8_t *)pixel)[1]; + *fb++ = ((rt_uint8_t *)pixel)[2]; + } +} + +static void graphic_primary_draw_vline_24bit(const char *pixel, int x, int y1, int y2) +{ + rt_uint8_t *fb; + rt_size_t xlate; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(y1, y2); + + fb = framebuffer_drift(plane, x, y1, 24); + xlate = plane->line_length - 3; + + for (; y1 < y2; ++y1) + { + *fb++ = ((rt_uint8_t *)pixel)[0]; + *fb++ = ((rt_uint8_t *)pixel)[1]; + *fb++ = ((rt_uint8_t *)pixel)[2]; + + fb = (void *)fb + xlate; + } +} + +static void graphic_primary_blit_line_24bit(const char *pixel, int x, int y, rt_size_t size) +{ + rt_uint8_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fb = framebuffer_drift(plane, x, y, 24); + + while (size --> 0) + { + *fb++ = *(rt_uint8_t *)pixel++; + *fb++ = *(rt_uint8_t *)pixel++; + *fb++ = *(rt_uint8_t *)pixel++; + } +} + +static struct rt_device_graphic_ops graphic_primary_24bit_ops = +{ + .set_pixel = graphic_primary_set_pixel_24bit, + .get_pixel = graphic_primary_get_pixel_24bit, + .draw_hline = graphic_primary_draw_hline_24bit, + .draw_vline = graphic_primary_draw_vline_24bit, + .blit_line = graphic_primary_blit_line_24bit, +}; + +static void graphic_primary_set_pixel_32bit(const char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint32_t *)framebuffer_drift(plane, x, y, 32) = *(rt_uint32_t *)pixel; +} + +static void graphic_primary_get_pixel_32bit(char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint32_t *)pixel = *(rt_uint32_t *)framebuffer_drift(plane, x, y, 32); +} + +static void graphic_primary_draw_hline_32bit(const char *pixel, int x1, int x2, int y) +{ + rt_uint32_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(x1, x2); + + fb = framebuffer_drift(plane, x1, y, 32); + + for (; x1 < x2; ++x1) + { + *fb++ = *(rt_uint32_t *)pixel; + } +} + +static void graphic_primary_draw_vline_32bit(const char *pixel, int x, int y1, int y2) +{ + rt_uint32_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(y1, y2); + + fb = framebuffer_drift(plane, x, y1, 32); + + for (; y1 < y2; ++y1) + { + *fb = *(rt_uint32_t *)pixel; + fb = (void *)fb + plane->line_length; + } +} + +static void graphic_primary_blit_line_32bit(const char *pixel, int x, int y, rt_size_t size) +{ + rt_uint32_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fb = framebuffer_drift(plane, x, y, 32); + + while (size --> 0) + { + *fb++ = *(rt_uint32_t *)pixel; + pixel += 4; + } +} + +static struct rt_device_graphic_ops graphic_primary_32bit_ops = +{ + .set_pixel = graphic_primary_set_pixel_32bit, + .get_pixel = graphic_primary_get_pixel_32bit, + .draw_hline = graphic_primary_draw_hline_32bit, + .draw_vline = graphic_primary_draw_vline_32bit, + .blit_line = graphic_primary_blit_line_32bit, +}; + +static void graphic_primary_set_pixel_64bit(const char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint64_t *)framebuffer_drift(plane, x, y, 64) = *(rt_uint64_t *)pixel; +} + +static void graphic_primary_get_pixel_64bit(char *pixel, int x, int y) +{ + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + *(rt_uint64_t *)pixel = *(rt_uint64_t *)framebuffer_drift(plane, x, y, 64); +} + +static void graphic_primary_draw_hline_64bit(const char *pixel, int x1, int x2, int y) +{ + rt_uint64_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(x1, x2); + + fb = framebuffer_drift(plane, x1, y, 64); + + for (; x1 < x2; ++x1) + { + *fb++ = *(rt_uint64_t *)pixel; + } +} + +static void graphic_primary_draw_vline_64bit(const char *pixel, int x, int y1, int y2) +{ + rt_uint64_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fixup_dir(y1, y2); + + fb = framebuffer_drift(plane, x, y1, 64); + + for (; y1 < y2; ++y1) + { + *fb = *(rt_uint64_t *)pixel; + fb = (void *)fb + plane->line_length; + } +} + +static void graphic_primary_blit_line_64bit(const char *pixel, int x, int y, rt_size_t size) +{ + rt_uint64_t *fb; + struct rt_graphic_plane *plane = primary_gdev->primary_plane; + + fb = framebuffer_drift(plane, x, y, 64); + + while (size --> 0) + { + *fb++ = *(rt_uint64_t *)pixel; + pixel += 8; + } +} + +static struct rt_device_graphic_ops graphic_primary_64bit_ops = +{ + .set_pixel = graphic_primary_set_pixel_64bit, + .get_pixel = graphic_primary_get_pixel_64bit, + .draw_hline = graphic_primary_draw_hline_64bit, + .draw_vline = graphic_primary_draw_vline_64bit, + .blit_line = graphic_primary_blit_line_64bit, +}; + +struct rt_device_graphic_ops *rt_graphic_device_switch_primary(struct rt_graphic_device *gdev) +{ + primary_gdev = gdev; + + RT_ASSERT(primary_gdev != RT_NULL); + RT_ASSERT(primary_gdev->primary_plane != RT_NULL); + + switch (rt_graphic_mode_bpp(primary_gdev->primary_plane->mode)) + { + case 32: return &graphic_primary_32bit_ops; + case 24: return &graphic_primary_24bit_ops; + case 16: return &graphic_primary_16bit_ops; + case 64: return &graphic_primary_64bit_ops; + case 8: return &graphic_primary_8bit_ops; + default: + LOG_E("What the fuck format(%u)", primary_gdev->primary_plane->mode); + RT_ASSERT(0); + break; + } + + return RT_NULL; +} diff --git a/components/drivers/graphic/graphic_simple.c b/components/drivers/graphic/graphic_simple.c new file mode 100644 index 00000000000..141fc9d9131 --- /dev/null +++ b/components/drivers/graphic/graphic_simple.c @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "graphic.simple" +#define DBG_LVL DBG_INFO +#include + +static rt_uint32_t edid_dpi_to_mm(rt_uint32_t dpi, rt_uint32_t res) +{ + return res * 254 / 10 / dpi; +} + +static void edid_checksum(rt_uint8_t *edid, rt_size_t len) +{ + rt_uint32_t sum = 0; + + for (int i = 0; i < len; ++i) + { + sum += edid[i]; + } + + sum &= 0xff; + + if (sum) + { + edid[len] = 0x100 - sum; + } +} + +static void fill_edid(struct rt_graphic_device *gdev, + rt_uint32_t width, rt_uint32_t height, rt_uint32_t refresh_hz) +{ + union + { + rt_uint32_t u32; + rt_uint16_t u16; + } value; + int dt_idx = 0; + int width_mm, height_mm; + rt_uint64_t clock; + rt_uint32_t xfront, xsync, xblank, yfront, ysync, yblank; + struct edid *edid = &gdev->edid; + struct detailed_timing *dt; + struct detailed_pixel_timing *dpt; + struct detailed_non_pixel *dnp; + + refresh_hz = refresh_hz ? : 75000; + width_mm = edid_dpi_to_mm(100, width); + height_mm = edid_dpi_to_mm(100, height); + + /* EDID: timings */ + xfront = width * 25 / 100; + xsync = width * 3 / 100; + xblank = width * 35 / 100; + yfront = height * 5 / 1000; + ysync = height * 5 / 1000; + yblank = height * 35 / 1000; + clock = ((rt_uint64_t)refresh_hz * (width + xblank) * (height + yblank)) / 10000000; + + if (width >= 4096 || height >= 4096 || clock >= 65536) + { + LOG_E("%s: Large screen %ux%u@%uHz is not supported in simple", + rt_dm_dev_get_name(&gdev->parent), width, height, clock); + + RT_ASSERT(0); + } + + /* EDID: extensions */ + + /* EDID: header information */ + edid->header[0] = 0x00; + edid->header[1] = 0xff; + edid->header[2] = 0xff; + edid->header[3] = 0xff; + edid->header[4] = 0xff; + edid->header[5] = 0xff; + edid->header[6] = 0xff; + edid->header[7] = 0x00; + + /* Vendor id */ + value.u16 = rt_cpu_to_be16( + ((('R' - '@') & 0x1f) << 10) | + ((('T' - '@') & 0x1f) << 5) | + ((('T' - '@') & 0x1f) << 0)); + rt_memcpy(edid->mfg_id, &value.u16, sizeof(edid->mfg_id)); + + /* Product code */ + value.u16 = rt_cpu_to_le16(0x1234); + rt_memcpy(edid->prod_code, &value.u16, sizeof(edid->prod_code)); + + /* Serial number */ + edid->serial = rt_cpu_to_le32(0); + + /* Manufacture week and year */ + edid->mfg_week = 42; + edid->mfg_year = 2014 - 1990; + + /* Version */ + edid->version = 1; + edid->revision = 4; + + /* EDID: basic display parameters */ + + /* Video input: digital, 8bpc, displayport */ + edid->input = 0xa5; + + /* Screen size */ + edid->width_cm = width_mm / 10; + edid->height_cm = height_mm / 10; + + /* Gamma: 2.2 */ + edid->gamma = 220 - 100; + + /* Features: STD sRGB, preferred timing */ + edid->features = 0x06; + + /* EDID: chromaticity coordinates */ + + /* + * STD sRGB colorspace: + * X Y + * red: 0.6400, 0.3300 + * green: 0.3000, 0.6000 + * blue: 0.1500, 0.0600 + * white point: 0.3127, 0.3290 + * + * value = (uint32_t)(value * 1024 + 0.5) + * + * red_x = 0.6400 * 1024 + 0.5 = 655.86 => 655 + * red_y = 0.3300 * 1024 + 0.5 = 338.42 => 338 + * green_x = 0.3000 * 1024 + 0.5 = 307.7 => 307 + * green_y = 0.6000 * 1024 + 0.5 = 614.9 => 614 + * blue_x = 0.1500 * 1024 + 0.5 = 154.1 => 154 + * blue_y = 0.0600 * 1024 + 0.5 = 61.94 => 61 + * white_x = 0.3127 * 1024 + 0.5 = 320.7048 => 320 + * white_y = 0.3290 * 1024 + 0.5 = 337.396 => 337 + */ + edid->red_green_lo = (((655 & 0x03) << 6) | /* red_x */ + ((338 & 0x03) << 4) | /* red_y */ + ((307 & 0x03) << 2) | /* green_x */ + ((614 & 0x03) << 0)); /* green_y */ + edid->black_white_lo = (((154 & 0x03) << 6) | /* blue_x */ + ((154 & 0x03) << 4) | /* blue_y */ + ((320 & 0x03) << 2) | /* white_x */ + ((337 & 0x03) << 0)); /* white_y */ + edid->red_x = 655 >> 2; /* red_x */ + edid->red_y = 338 >> 2; /* red_y */ + edid->green_x = 307 >> 2; /* green_x */ + edid->green_y = 614 >> 2; /* green_y */ + edid->blue_x = 154 >> 2; /* blue_x */ + edid->blue_y = 154 >> 2; /* blue_y */ + edid->white_x = 320 >> 2; /* white_x */ + edid->white_y = 337 >> 2; /* white_y */ + + /* EDID: established timing bitmap */ + /* EDID: standard timing information */ + + /* EDID: descriptor blocks */ + dt = &edid->detailed_timings[dt_idx++]; + dpt = &dt->data.pixel_data; + + dt->pixel_clock = rt_cpu_to_le16(clock); + dpt->hactive_lo = width & 0xff; + dpt->hblank_lo = xblank & 0xff; + dpt->hactive_hblank_hi = (((width & 0xf00) >> 4) | ((xblank & 0xf00) >> 8)); + + dpt->vactive_lo = height & 0xff; + dpt->vblank_lo = yblank & 0xff; + dpt->vactive_vblank_hi = (((height & 0xf00) >> 4) | ((yblank & 0xf00) >> 8)); + + dpt->hsync_offset_lo = xfront & 0xff; + dpt->hsync_pulse_width_lo = xsync & 0xff; + + dpt->vsync_offset_pulse_width_lo = (((yfront & 0x00f) << 4) | + ((ysync & 0x00f) << 0)); + dpt->hsync_vsync_offset_pulse_width_hi = (((xfront & 0x300) >> 2) | + ((xsync & 0x300) >> 4) | + ((yfront & 0x030) >> 2) | + ((ysync & 0x030) >> 4)); + + dpt->width_mm_lo = width_mm & 0xff; + dpt->height_mm_lo = height_mm & 0xff; + dpt->width_height_mm_hi = (((width_mm & 0xf00) >> 4) | + ((height_mm & 0xf00) >> 8)); + + dpt->misc = 0x18; + + /* XTRA3 STD */ + dt = &edid->detailed_timings[dt_idx++]; + dnp = &dt->data.other_data; + dnp->type = EDID_DETAIL_EST_TIMINGS; + dnp->data.timings[0].hsize = 10; + + /* Ranges */ + dt = &edid->detailed_timings[dt_idx++]; + dnp = &dt->data.other_data; + dnp->type = EDID_DETAIL_MONITOR_RANGE; + dnp->data.range.min_vfreq = 50; + dnp->data.range.max_vfreq = 125; + dnp->data.range.min_hfreq_khz = 30; + dnp->data.range.max_hfreq_khz = 160; + dnp->data.range.pixel_clock_mhz = 2550 / 10; + dnp->data.range.flags = 0x01; + rt_memcpy(&dnp->data.range.flags + 1, "\n ", 7); + + while (dt_idx < RT_ARRAY_SIZE(edid->detailed_timings)) + { + /* Dummy */ + dt = &edid->detailed_timings[dt_idx++]; + dnp = &dt->data.other_data; + dnp->type = 0x10; + } + + /* EDID: display id extensions */ + + /* EDID: checksum */ + edid_checksum((void *)edid, 127); +} + +rt_err_t rt_graphic_device_simple_edid(struct rt_graphic_device *gdev, + rt_uint32_t width, rt_uint32_t height, rt_uint32_t refresh_hz) +{ + if (!gdev || !width || !height) + { + return -RT_EINVAL; + } + + fill_edid(gdev, width, height, refresh_hz); + + return RT_EOK; +} + +static const struct rt_graphic_device_ops graphic_device_simple_ops = +{ +}; + +rt_err_t rt_graphic_device_simple_register(struct rt_graphic_device *gdev, + rt_uint32_t width, rt_uint32_t height, rt_uint32_t refresh_hz, + const struct rt_graphic_plane_ops *plane_ops, + const rt_uint32_t *modes, rt_uint32_t modes_nr) +{ + rt_err_t err; + struct rt_graphic_plane *plane; + + if (!gdev || !width || !height || !plane_ops || !modes || !modes_nr) + { + return -RT_EINVAL; + } + + if (!gdev->ops) + { + gdev->ops = &graphic_device_simple_ops; + } + + plane = rt_graphic_device_alloc_plane(gdev, 0, plane_ops, modes, modes_nr, + RT_GRAPHIC_PLANE_TYPE_PRIMARY); + + if (!plane) + { + return -RT_EINVAL; + } + + if ((err = rt_graphic_device_add_plane(gdev, plane))) + { + goto _free_plane; + } + + rt_graphic_device_simple_edid(gdev, width, height, refresh_hz); + + err = rt_graphic_device_register(gdev); + +_free_plane: + if (err) + { + rt_free(plane); + } + + return err; +} + +rt_err_t rt_graphic_device_simple_unregister(struct rt_graphic_device *gdev) +{ + return rt_graphic_device_unregister(gdev); +} diff --git a/components/drivers/graphic/logo/.gitignore b/components/drivers/graphic/logo/.gitignore new file mode 100644 index 00000000000..e524629a37f --- /dev/null +++ b/components/drivers/graphic/logo/.gitignore @@ -0,0 +1 @@ +logo.inc \ No newline at end of file diff --git a/components/drivers/graphic/logo/Kconfig b/components/drivers/graphic/logo/Kconfig new file mode 100644 index 00000000000..45bcfe3f59d --- /dev/null +++ b/components/drivers/graphic/logo/Kconfig @@ -0,0 +1,31 @@ +menuconfig RT_GRAPHIC_LOGO + bool "Startup Logo" + select RT_GRAPHIC_FB + default y + +choice + prompt "Rendering image(ppm)" + default RT_GRAPHIC_LOGO_RT_THREAD_CLUT224 + depends on RT_GRAPHIC_LOGO + + config RT_GRAPHIC_LOGO_NONE + bool "None logo (Change in runtime)" + + osource "$(SOC_DM_GRAPHIC_LOGO_DIR)/Kconfig" +endchoice + +# Provide the logos path for the BSP path: +# +# RT_GRAPHIC_LOGO_ in Kconfig: +# +# config RT_GRAPHIC_LOGO_ +# bool " logo" +# +# RT_GRAPHIC_LOGO__PATH in Kconfig.path: +# +# if RT_GRAPHIC_LOGO_ +# config RT_GRAPHIC_LOGO__PATH +# string +# default "dm/graphic/logo/[filename].ppm" +# endif +osource "$(SOC_DM_GRAPHIC_LOGO_DIR)/Kconfig.path" diff --git a/components/drivers/graphic/logo/SConscript b/components/drivers/graphic/logo/SConscript new file mode 100644 index 00000000000..622ada04490 --- /dev/null +++ b/components/drivers/graphic/logo/SConscript @@ -0,0 +1,84 @@ +from building import * +import os, re + +group = [] + +if not GetDepend(['RT_GRAPHIC_LOGO']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../../include'] +CPPDEFINES = [] + +src = ['logo.c'] + +logo_path = None +logo_width = 0 +logo_height = 0 +logo_max_val = 0 + +if logo_path == None: + # Find in BSP + paths = None + for key in BuildOptions.keys(): + if re.match(r'RT_GRAPHIC_LOGO_.*_PATH', key): + paths = BuildOptions[key] + break + + if paths != None and len(paths) > 0: + logo_path = Dir('#').abspath + '/' + paths[1:-1] + if not os.path.exists(logo_path): + print("Logo file '{}' not found!".format(logo_path)) + exit(-1) + +if logo_path != None: + with open(logo_path, 'rb') as ppm: + data = ppm.read().split(b'\n') + + # PPM: + magic = data[0].decode('utf-8') + + # PPM: + offset = 1 + while True: + comment = str(data[offset].decode('utf-8')) + if comment[0] != '#': + break + offset += 1 + + # PPM: + logo_width, logo_height = map(int, data[offset].split()) + + # PPM: + logo_max_val = int(data[offset + 1]) + + # PPM: + ppm.seek(0) + pixels = b''.join(ppm.readlines()[offset + 2:]) + ppm.close() + + if magic == 'P1' or magic == 'P2' or magic == 'P3': + # ASCII + pixels = re.sub(b'\\s+', b'\n', pixels.strip()).decode('utf-8').split('\n') + + logo = open(cwd + '/logo.inc', "w") + + for dy in range(logo_height): + for dx in range(logo_width): + index = (dy * logo_width + dx) * 3 + # Red + logo.write(str(pixels[index]).rjust(4) + ",") + # Green + logo.write(str(pixels[index + 1]).rjust(4) + ",") + # Blue + logo.write(str(pixels[index + 2]).rjust(4) + ",") + logo.write("\n") + + logo.close() + +CPPDEFINES += ['__STARTUP_LOGO_WIDTH__=' + str(logo_width)] +CPPDEFINES += ['__STARTUP_LOGO_HEIGHT__=' + str(logo_height)] +CPPDEFINES += ['__STARTUP_LOGO_COLOR_MAX__=' + str(logo_max_val)] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/components/drivers/graphic/logo/logo.c b/components/drivers/graphic/logo/logo.c new file mode 100644 index 00000000000..34597c8c03a --- /dev/null +++ b/components/drivers/graphic/logo/logo.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "graphic.logo" +#define DBG_LVL DBG_INFO +#include + +#if __STARTUP_LOGO_WIDTH__ && __STARTUP_LOGO_HEIGHT__ && __STARTUP_LOGO_COLOR_MAX__ +static rt_uint8_t builtin_logo[] = +{ + #include "logo.inc" +}; + +static void *startup_logo = builtin_logo; +#else +static void *startup_logo = RT_NULL; +#endif +static int startup_logo_width = __STARTUP_LOGO_WIDTH__; +static int startup_logo_height = __STARTUP_LOGO_HEIGHT__; +static int startup_logo_color_max = __STARTUP_LOGO_COLOR_MAX__; + +rt_err_t rt_graphic_logo_change(void *data, int width, int height, int color_max) +{ + if (!data && !width && !height && !color_max) + { + /* Disable logo */ + startup_logo = RT_NULL; + } + else if (data && width > 0 && height > 0 && color_max > 0) + { + startup_logo = data; + startup_logo_width = width; + startup_logo_height = height; + startup_logo_color_max = color_max; + } + else + { + return -RT_EINVAL; + } + + return RT_EOK; +} + +static rt_ubase_t to_grayscale(rt_ubase_t red, rt_ubase_t green, rt_ubase_t blue) +{ + return (299 * red + 587 * green + 114 * blue) / 1000; +} + +static rt_ubase_t to_color(rt_ubase_t color, rt_ubase_t in_color_max, rt_ubase_t out_color_max) +{ + return color * out_color_max / in_color_max; +} + +static rt_ubase_t gray_reordering(rt_ubase_t red, rt_ubase_t red_off, + rt_ubase_t green, rt_ubase_t green_off, + rt_ubase_t blue, rt_ubase_t blue_off, + rt_ubase_t in_color_max, rt_ubase_t out_color_max) +{ + return to_grayscale(to_color(red, in_color_max, out_color_max), + to_color(green, in_color_max, out_color_max), + to_color(blue, in_color_max, out_color_max)); +} + +static rt_ubase_t rgb_reordering(rt_ubase_t red, rt_ubase_t red_off, + rt_ubase_t green, rt_ubase_t green_off, + rt_ubase_t blue, rt_ubase_t blue_off, + rt_ubase_t in_color_max, rt_ubase_t out_color_max) +{ + return (to_color(red, in_color_max, out_color_max) << red_off) | + (to_color(green, in_color_max, out_color_max) << green_off) | + (to_color(blue, in_color_max, out_color_max) << blue_off); +} + +rt_err_t rt_graphic_logo_render(struct rt_graphic_device *gdev) +{ + rt_err_t err; + int fb_color_max; + rt_ubase_t xlate, none_alpha; + rt_ubase_t red_off, green_off, blue_off; + rt_ubase_t red_mask, green_mask, blue_mask; + rt_uint8_t *logo, *fb, bytes_per_pixel; + rt_ubase_t (*color_reordering)(rt_ubase_t, rt_ubase_t, + rt_ubase_t, rt_ubase_t, + rt_ubase_t, rt_ubase_t, + rt_ubase_t, rt_ubase_t); + struct fb_var_screeninfo var; + struct rt_device_rect_info rect; + struct rt_device_graphic_info info; + struct rt_device *fbdev = &gdev->parent; + + if (!startup_logo) + { + return RT_EOK; + } + + if ((err = rt_device_open(fbdev, 0))) + { + return err; + } + + if ((err = rt_device_control(fbdev, FBIOGET_VSCREENINFO, &var))) + { + LOG_E("Get framebuffer %s error = %s", "var", rt_strerror(err)); + + goto _close_fbdev; + } + + if (startup_logo_width > var.xres || startup_logo_height > var.yres) + { + LOG_E("PPM logo[%u, %u] Out of screen[%u, %u]", + startup_logo_width, startup_logo_height, var.xres, var.yres); + + err = -RT_EINVAL; + goto _close_fbdev; + } + + if ((err = rt_device_control(fbdev, RTGRAPHIC_CTRL_GET_INFO, &info))) + { + LOG_E("Get framebuffer %s error = %s", "info", rt_strerror(err)); + + goto _close_fbdev; + } + + if ((err = rt_device_control(fbdev, RTGRAPHIC_CTRL_POWERON, RT_NULL))) + { + LOG_E("Power on graphic device error = %s", rt_strerror(err)); + + goto _close_fbdev; + } + + if (var.grayscale) + { + color_reordering = &gray_reordering; + } + else + { + color_reordering = &rgb_reordering; + } + + bytes_per_pixel = var.bits_per_pixel / 8; + xlate = (var.xres - startup_logo_width) * bytes_per_pixel; + + rect.x = (var.xres - startup_logo_width) >> 1; + rect.y = (var.yres - startup_logo_height) >> 1; + rect.width = startup_logo_width, + rect.height = startup_logo_height, + + fb = (void *)info.framebuffer; + fb += rect.x * bytes_per_pixel + rect.y * info.pitch; + + logo = startup_logo; + + red_off = var.red.offset; + red_mask = RT_GENMASK(var.red.length - 1, 0); + green_off = var.green.offset; + green_mask = RT_GENMASK(var.green.length - 1, 0); + blue_off = var.blue.offset; + blue_mask = RT_GENMASK(var.blue.length - 1, 0); + + fb_color_max = rt_max_t(int, rt_max_t(int, red_mask, green_mask), blue_mask); + + if (var.transp.length) + { + none_alpha = RT_GENMASK(var.transp.length - 1, 0) << var.transp.offset; + } + else + { + none_alpha = 0; + } + + for (int dy = 0; dy < startup_logo_height; ++dy) + { + for (int dx = 0; dx < startup_logo_width; ++dx) + { + rt_ubase_t color = color_reordering(logo[0], red_off, + logo[1], green_off, + logo[2], blue_off, + fb_color_max, startup_logo_color_max) | + none_alpha; + + rt_memcpy(fb, &color, bytes_per_pixel); + + fb += bytes_per_pixel; + logo += 3; + } + + fb += xlate; + } + + rt_device_control(fbdev, RTGRAPHIC_CTRL_RECT_UPDATE, &rect); + rt_device_control(fbdev, RTGRAPHIC_CTRL_WAIT_VSYNC, RT_NULL); + + /* Complete */ + startup_logo = RT_NULL; + + /* + * Should recycle here, logo takes up too much memory + * if builtin is not RT_GRAPHIC_LOGO_NONE. + */ + +_close_fbdev: + rt_device_close(fbdev); + + return err; +} diff --git a/components/drivers/graphic/logo/logo.html b/components/drivers/graphic/logo/logo.html new file mode 100644 index 00000000000..81e78c4aa1e --- /dev/null +++ b/components/drivers/graphic/logo/logo.html @@ -0,0 +1,243 @@ + + + + + + + + + Logo PPM Previews + + + +

+
+
+
+
+ + + + +
+
+
+ +
+
+ +
+
+
+ +
+
+
+ + + diff --git a/components/drivers/include/drivers/graphic.h b/components/drivers/include/drivers/graphic.h new file mode 100644 index 00000000000..df9b22729f0 --- /dev/null +++ b/components/drivers/include/drivers/graphic.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __GRAPHIC_DM_H__ +#define __GRAPHIC_DM_H__ + +#include +#include +#include +#include +#include +#include + +#undef rt_graphix_ops +#define rt_graphix_ops(dev) \ + rt_graphic_device_switch_primary(rt_container_of(dev, struct rt_graphic_device, parent)) + +rt_packed(struct est_timings +{ + rt_uint8_t t1; + rt_uint8_t t2; + rt_uint8_t mfg_rsvd; +}); + +rt_packed(struct std_timing +{ + /* Need to multiply by 8 then add 248 */ + rt_uint8_t hsize; + rt_uint8_t vfreq_aspect; +}); + +rt_packed(struct detailed_pixel_timing +{ + rt_uint8_t hactive_lo; + rt_uint8_t hblank_lo; + rt_uint8_t hactive_hblank_hi; + rt_uint8_t vactive_lo; + rt_uint8_t vblank_lo; + rt_uint8_t vactive_vblank_hi; + rt_uint8_t hsync_offset_lo; + rt_uint8_t hsync_pulse_width_lo; + rt_uint8_t vsync_offset_pulse_width_lo; + rt_uint8_t hsync_vsync_offset_pulse_width_hi; + rt_uint8_t width_mm_lo; + rt_uint8_t height_mm_lo; + rt_uint8_t width_height_mm_hi; + rt_uint8_t hborder; + rt_uint8_t vborder; + rt_uint8_t misc; +}); + +rt_packed(struct detailed_data_string +{ + rt_uint8_t str[13]; +}); + +rt_packed(struct detailed_data_monitor_range +{ + rt_uint8_t min_vfreq; + rt_uint8_t max_vfreq; + rt_uint8_t min_hfreq_khz; + rt_uint8_t max_hfreq_khz; + /* Need to multiply by 10 */ + rt_uint8_t pixel_clock_mhz; + rt_uint8_t flags; + + union + { + rt_packed(struct + { + rt_uint8_t reserved; + /* Need to multiply by 2 */ + rt_uint8_t hfreq_start_khz; + /* Need to divide by 2 */ + rt_uint8_t c; + rt_le16_t m; + rt_uint8_t k; + /* Need to divide by 2 */ + rt_uint8_t j; + }) gtf2; + rt_packed(struct + { + rt_uint8_t version; + /* High 6 bits: extra clock resolution */ + rt_uint8_t data1; + /* Plus low 2 of above: max hactive */ + rt_uint8_t data2; + rt_uint8_t supported_aspects; + /* Preferred aspect and blanking support */ + rt_uint8_t flags; + rt_uint8_t supported_scalings; + rt_uint8_t preferred_refresh; + }) cvt; + } formula; +}); + +rt_packed(struct detailed_data_wpindex +{ + /* Lower 2 bits each */ + rt_uint8_t white_yx_lo; + rt_uint8_t white_x_hi; + rt_uint8_t white_y_hi; + /* Need to divide by 100 then add 1 */ + rt_uint8_t gamma; +}); + +rt_packed(struct cvt_timing +{ + rt_uint8_t code[3]; +}); + +rt_packed(struct detailed_non_pixel +{ + rt_uint8_t pad1; +#define EDID_DETAIL_EST_TIMINGS 0xf7 +#define EDID_DETAIL_CVT_3BYTE 0xf8 +#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 +#define EDID_DETAIL_STD_MODES 0xfa +#define EDID_DETAIL_MONITOR_CPDATA 0xfb +#define EDID_DETAIL_MONITOR_NAME 0xfc +#define EDID_DETAIL_MONITOR_RANGE 0xfd +#define EDID_DETAIL_MONITOR_STRING 0xfe +#define EDID_DETAIL_MONITOR_SERIAL 0xff + rt_uint8_t type; + rt_uint8_t pad2; + union + { + struct detailed_data_string str; + struct detailed_data_monitor_range range; + struct detailed_data_wpindex color; + struct std_timing timings[6]; + struct cvt_timing cvt[4]; + } data; +}); + +rt_packed(struct detailed_timing +{ + /* Need to multiply by 10 KHz */ + rt_le16_t pixel_clock; + + union + { + struct detailed_pixel_timing pixel_data; + struct detailed_non_pixel other_data; + } data; +}); + +rt_packed(struct edid +{ + rt_uint8_t header[8]; + + /* Vendor & product info */ + rt_uint8_t mfg_id[2]; + rt_uint8_t prod_code[2]; + rt_le32_t serial; + rt_uint8_t mfg_week; + rt_uint8_t mfg_year; + + /* EDID version */ + rt_uint8_t version; + rt_uint8_t revision; + + /* Display info */ + rt_uint8_t input; + rt_uint8_t width_cm; + rt_uint8_t height_cm; + rt_uint8_t gamma; + rt_uint8_t features; + + /* Color characteristics */ + rt_uint8_t red_green_lo; + rt_uint8_t black_white_lo; + rt_uint8_t red_x; + rt_uint8_t red_y; + rt_uint8_t green_x; + rt_uint8_t green_y; + rt_uint8_t blue_x; + rt_uint8_t blue_y; + rt_uint8_t white_x; + rt_uint8_t white_y; + + /* Est. timings and mfg rsvd timings */ + struct est_timings established_timings; + + /* Standard timings 1-8 */ + struct std_timing standard_timings[8]; + + /* Detailing timings 1-4, 18 * 4 = 72 bytes */ + struct detailed_timing detailed_timings[4]; + + /* Number of 128 byte ext. blocks */ + rt_uint8_t extensions; + + /* Checksum */ + rt_uint8_t checksum; +}); + +struct rt_graphic_device; +struct rt_graphic_device_ops; +struct rt_graphic_plane_ops; + +enum rt_graphic_plane_prop +{ + RT_GRAPHIC_PLANE_PROP_Z = 0, + RT_GRAPHIC_PLANE_PROP_ROTATE, + RT_GRAPHIC_PLANE_PROP_ALPHA, + + RT_GRAPHIC_PLANE_PROP_MAX, +}; + +struct rt_graphic_plane +{ + rt_list_t list; + char name[RT_NAME_MAX]; + + int id; +#define RT_GRAPHIC_PLANE_TYPE_OVERLAY 0 +#define RT_GRAPHIC_PLANE_TYPE_PRIMARY 1 /* Only one, add before register */ +#define RT_GRAPHIC_PLANE_TYPE_CURSOR 2 /* Only one */ + rt_uint8_t type; + + rt_uint32_t x; + rt_uint32_t y; + rt_uint32_t z; + rt_uint32_t width; + rt_uint32_t height; +#define RT_GRAPHIC_PLANE_ROTATE_0 0 /* +0 degrees */ +#define RT_GRAPHIC_PLANE_ROTATE_90 1 /* +90 degrees */ +#define RT_GRAPHIC_PLANE_ROTATE_180 2 /* +180 degrees */ +#define RT_GRAPHIC_PLANE_ROTATE_270 3 /* +270 degrees */ + rt_uint8_t rotate; + rt_uint8_t alpha; /* 0 ~ 100 */ + + rt_uint32_t line_length; + rt_uint32_t bits_per_pixel; + + /* Support color modes: RTGRAPHIC_PIXEL_FORMAT_* */ + rt_uint32_t mode; + rt_uint32_t modes_nr; + const rt_uint32_t *modes; + + /* fb count = framebuffer_len / screen_len */ + void *framebuffer; + rt_size_t screen_len; + rt_size_t framebuffer_len; + + struct rt_graphic_device *graphic; + const struct rt_graphic_plane_ops *ops; + + rt_uint8_t priv[0]; +}; + +struct rt_graphic_plane_ops +{ + rt_err_t (*update)(struct rt_graphic_plane *plane, struct rt_device_rect_info *rect); + rt_err_t (*fb_remap)(struct rt_graphic_plane *plane, rt_uint32_t mode, struct rt_device_rect_info *rect); + rt_err_t (*fb_pan_display)(struct rt_graphic_plane *plane, struct rt_device_rect_info *rect); + rt_err_t (*fb_cleanup)(struct rt_graphic_plane *plane); + rt_err_t (*prop_set)(struct rt_graphic_plane *plane, enum rt_graphic_plane_prop prop, void *value); +}; + +struct rt_graphic_device +{ + struct rt_device parent; + + const struct rt_graphic_device_ops *ops; + + /* Display Power Manage System */ +#define RT_GRAPHIC_DPMS_ON 0 +#define RT_GRAPHIC_DPMS_STANDBY 1 +#define RT_GRAPHIC_DPMS_SUSPEND 2 +#define RT_GRAPHIC_DPMS_OFF 3 + rt_uint32_t dpms; + + rt_list_t overlay_nodes; + struct rt_graphic_plane *primary_plane; + struct rt_graphic_plane *cursor_plane; + struct rt_dm_ida plane_ida; + + /* Display information */ + struct edid edid; + +#ifdef RT_GRAPHIC_BACKLIGHT + struct rt_backlight_device *backlight; +#endif +#define RT_GRAPHIC_UPDATE_MS 16 + struct rt_timer *update_timer; + + rt_atomic_t event_notifying; + struct rt_device_notify event_notify; + + struct rt_spinlock lock; +}; + +struct rt_graphic_device_ops +{ + rt_err_t (*dpms_switch)(struct rt_graphic_device *gdev, rt_uint32_t dpms); + + rt_err_t (*set_brightness)(struct rt_graphic_device *gdev, rt_uint32_t brightness); + rt_err_t (*get_brightness)(struct rt_graphic_device *gdev, rt_uint32_t *out_brightness); + + rt_err_t (*get_status)(struct rt_graphic_device *gdev, rt_uint32_t *out_status); + + rt_err_t (*wait_vsync)(struct rt_graphic_device *gdev); + + rt_err_t (*control)(struct rt_graphic_device *gdev, int cmd, void *args); + + /* Switching planes supported by device driver */ + struct rt_graphic_plane *(*current_plane)(struct rt_graphic_device *gdev); +}; + +rt_err_t rt_graphic_device_register(struct rt_graphic_device *gdev); +rt_err_t rt_graphic_device_unregister(struct rt_graphic_device *gdev); + +struct rt_graphic_plane *rt_graphic_device_alloc_plane(struct rt_graphic_device *gdev, + rt_size_t priv_size, const struct rt_graphic_plane_ops *ops, + const rt_uint32_t *modes, rt_uint32_t modes_nr, rt_uint8_t type); +void rt_graphic_device_free_plane(struct rt_graphic_plane *plane); + +rt_err_t rt_graphic_device_add_plane(struct rt_graphic_device *gdev, + struct rt_graphic_plane *plane); +rt_err_t rt_graphic_device_del_plane(struct rt_graphic_device *gdev, + struct rt_graphic_plane *plane); + +void rt_graphic_device_hotplug_event(struct rt_graphic_device *gdev); + +rt_err_t rt_graphic_device_update_auto(struct rt_graphic_device *gdev, rt_uint32_t update_ms); + +void rt_graphic_device_enter(struct rt_graphic_device *gdev); +void rt_graphic_device_leave(struct rt_graphic_device *gdev); + +rt_uint32_t rt_graphic_mode_bpp(rt_uint32_t mode); + +struct rt_device_graphic_ops *rt_graphic_device_switch_primary(struct rt_graphic_device *gdev); + +rt_err_t rt_graphic_device_simple_edid(struct rt_graphic_device *gdev, + rt_uint32_t width, rt_uint32_t height, rt_uint32_t refresh_hz); + +rt_err_t rt_graphic_device_simple_register(struct rt_graphic_device *gdev, + rt_uint32_t width, rt_uint32_t height, rt_uint32_t refresh_hz, + const struct rt_graphic_plane_ops *plane_ops, + const rt_uint32_t *modes, rt_uint32_t modes_nr); +rt_err_t rt_graphic_device_simple_unregister(struct rt_graphic_device *gdev); + +#ifdef RT_GRAPHIC_LOGO +rt_err_t rt_graphic_logo_change(void *data, int width, int height, int color_max); +rt_err_t rt_graphic_logo_render(struct rt_graphic_device *gdev); +#else +rt_inline rt_err_t rt_graphic_logo_change(void *data, int width, int height, int color_max) +{ + return RT_EOK; +} + +rt_inline rt_err_t rt_graphic_logo_render(struct rt_graphic_device *gdev) +{ + return RT_EOK; +} +#endif /* RT_GRAPHIC_LOGO */ + +#endif /* __GRAPHIC_DM_H__ */ diff --git a/components/drivers/include/drivers/lcd.h b/components/drivers/include/drivers/lcd.h index f2dcdce4451..11fa8e6dccc 100644 --- a/components/drivers/include/drivers/lcd.h +++ b/components/drivers/include/drivers/lcd.h @@ -11,6 +11,8 @@ #ifndef RT_LCD_H__ #define RT_LCD_H__ +#include + /* ioctls 0x46 is 'F' */ @@ -109,4 +111,35 @@ struct fb_fix_screeninfo uint16_t reserved[2]; /* Reserved for future compatibility */ }; +struct fb_cmap +{ + uint32_t start; /* First entry */ + uint32_t len; /* Number of entries */ + uint16_t *red; /* Red values */ + uint16_t *green; + uint16_t *blue; + uint16_t *transp; /* transparency, can be NULL */ +}; + +struct fb_con2fbmap +{ + uint32_t console; + uint32_t framebuffer; +}; + +/* VESA Blanking Levels */ +#define VESA_NO_BLANKING 0 +#define VESA_VSYNC_SUSPEND 1 +#define VESA_HSYNC_SUSPEND 2 +#define VESA_POWERDOWN 3 + +enum +{ + FB_BLANK_UNBLANK = VESA_NO_BLANKING, /* screen: unblanked, hsync: on, vsync: on */ + FB_BLANK_NORMAL = VESA_NO_BLANKING + 1, /* screen: blanked, hsync: on, vsync: on */ + FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1, /* screen: blanked, hsync: on, vsync: off */ + FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1, /* screen: blanked, hsync: off, vsync: on */ + FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1, /* screen: blanked, hsync: off, vsync: off */ +}; + #endif diff --git a/examples/test/dm_graphic_test.c b/examples/test/dm_graphic_test.c new file mode 100644 index 00000000000..a6894ddc6e6 --- /dev/null +++ b/examples/test/dm_graphic_test.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include + +#include + +#ifdef RT_USING_GRAPHIC +typedef rt_int32_t fixed; /* Q16.16 */ + +#define FIX_ONE 65536 +#define FIX_06 19661 /* 0.3 */ +#define FIX_35 22938 /* 0.35 */ +#define FIX_14 917504 /* 14.0 */ +#define FIX_286 187432 /* 2.86 */ +#define FIX_75 49152 /* 0.75 */ +#define FIX_1_3 21845 +#define FIX_2_3 43690 +#define FIX_6 393216 +#define FIX_3 196608 +#define FIX_255 16711680 /* 255 */ + +#define FMUL(a,b) ((fixed)(((rt_int64_t)(a) * (b)) >> 16)) +#define FDIV(a,b) ((fixed)(((rt_int64_t)(a) << 16) / (b))) + +typedef struct { fixed x, y, z; } vec3f; + +rt_inline fixed fix_floor(fixed x) +{ + return x & 0xffff0000; +} + +rt_inline fixed fix_fract(fixed x) +{ + return x & 0x0000ffff; +} + +rt_inline fixed fix_abs(fixed x) +{ + return rt_abs(x); +} + +rt_inline fixed fix_clamp(fixed x, fixed a, fixed b) +{ + return rt_clamp(x, a, b); +} + +static vec3f clamp3(vec3f v, fixed a, fixed b) +{ + vec3f r = + { + .x = fix_clamp(v.x, a, b), + .y = fix_clamp(v.y, a, b), + .z = fix_clamp(v.z, a, b), + }; + + return r; +} + +static vec3f mix3(vec3f A, vec3f B, fixed t) +{ + fixed omt = FIX_ONE - t; + vec3f r = + { + .x = FMUL(A.x, omt) + FMUL(B.x, t), + .y = FMUL(A.y, omt) + FMUL(B.y, t), + .z = FMUL(A.z, omt) + FMUL(B.z, t), + }; + + return r; +} + +static vec3f hsv2rgb(vec3f c) +{ + vec3f t, r, base, mixed; + fixed pX = FMUL(fix_fract(c.x + FIX_ONE), FIX_6); + fixed pY = FMUL(fix_fract(c.x + FIX_2_3), FIX_6); + fixed pZ = FMUL(fix_fract(c.x + FIX_1_3), FIX_6); + + pX = fix_abs(pX - FIX_3); + pY = fix_abs(pY - FIX_3); + pZ = fix_abs(pZ - FIX_3); + + t.x = pX - FIX_ONE; + t.y = pY - FIX_ONE; + t.z = pZ - FIX_ONE; + t = clamp3(t, 0, FIX_ONE); + + base.x = FIX_ONE; + base.y = FIX_ONE; + base.z = FIX_ONE; + + mixed = mix3(base, t, c.y); + + r.x = FMUL(c.z, mixed.x); + r.y = FMUL(c.z, mixed.y); + r.z = FMUL(c.z, mixed.z); + + return r; +} + +static void shader_frame(int px, int py, int width, int height, int frame, + rt_uint8_t *r, rt_uint8_t *g, rt_uint8_t *b) +{ + vec3f col; + fixed uv_x, uv_y, shift, size_computed, st, x; + + uv_x = FDIV((fixed)(px << 16), (fixed)(width << 16)); + uv_y = FDIV((fixed)(py << 16), (fixed)(width << 16)); + + shift = fix_fract(FDIV(FMUL((frame << 16), FIX_06), FIX_286)); + shift = FMUL(shift, FIX_286); + + size_computed = FMUL(uv_x + shift - uv_y, FIX_35); + + st = FMUL(size_computed, FIX_14); + x = FDIV(fix_floor(st), FIX_14); + + col = hsv2rgb((vec3f){ x, FIX_75, FIX_ONE }); + + *r = (rt_uint8_t)((FMUL(col.x, FIX_255) >> 16) & 255); + *g = (rt_uint8_t)((FMUL(col.y, FIX_255) >> 16) & 255); + *b = (rt_uint8_t)((FMUL(col.z, FIX_255) >> 16) & 255); +} + +static void conv_gray4(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + rt_uint8_t gray = (r * 30 + g * 59 + b * 11) / 100; + *(rt_uint8_t *)pixel = gray >> 4; +} + +static void conv_gray16(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + rt_uint16_t gray = (r * 30 + g * 59 + b * 11) / 100; + rt_uint16_t out = (gray << 8) | gray; + *(rt_uint16_t *)pixel = out; +} + +static void conv_rgb332(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + *(rt_uint8_t*)pixel = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); +} + +static void conv_rgb444(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + *(rt_uint16_t *)pixel = ((r >> 4) << 8) | ((g >> 4) << 4) | (b >> 4); +} + +static void conv_rgb565(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + *(rt_uint16_t *)pixel = ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3); +} + +static void conv_rgb565p(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + *(rt_uint16_t *)pixel = ((g >> 2) << 10) | ((r >> 3) << 5) | (b >> 3); +} + +static void conv_bgr565(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + *(rt_uint16_t *)pixel = ((b >> 3) << 11) | ((g >> 2) << 5) | (r >> 3); +} + +static void conv_rgb666(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + rt_uint8_t *p = (rt_uint8_t *)pixel; + + p[0] = r & 0xfc; + p[1] = g & 0xfc; + p[2] = b & 0xfc; +} + +static void conv_rgb888(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + rt_uint8_t *p = (rt_uint8_t *)pixel; + + p[0] = r; + p[1] = g; + p[2] = b; +} + +static void conv_bgr888(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + rt_uint8_t *p = (rt_uint8_t*)pixel; + p[0] = b; + p[1] = g; + p[2] = r; +} + +static void conv_argb888(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + *(rt_uint32_t *)pixel = (0xffU << 24) | (r << 16) | (g << 8) | b; +} + +static void conv_abgr888(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) +{ + *(rt_uint32_t *)pixel = (0xffU << 24) | (b << 16) | (g << 8) | r; +} + +static void (*conv_funcs[])(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel) = +{ + [RTGRAPHIC_PIXEL_FORMAT_GRAY4] = conv_gray4, + [RTGRAPHIC_PIXEL_FORMAT_GRAY16] = conv_gray16, + [RTGRAPHIC_PIXEL_FORMAT_RGB332] = conv_rgb332, + [RTGRAPHIC_PIXEL_FORMAT_RGB444] = conv_rgb444, + [RTGRAPHIC_PIXEL_FORMAT_RGB565] = conv_rgb565, + [RTGRAPHIC_PIXEL_FORMAT_RGB565P] = conv_rgb565p, + [RTGRAPHIC_PIXEL_FORMAT_BGR565] = conv_bgr565, + [RTGRAPHIC_PIXEL_FORMAT_RGB666] = conv_rgb666, + [RTGRAPHIC_PIXEL_FORMAT_RGB888] = conv_rgb888, + [RTGRAPHIC_PIXEL_FORMAT_BGR888] = conv_bgr888, + [RTGRAPHIC_PIXEL_FORMAT_ARGB888] = conv_argb888, + [RTGRAPHIC_PIXEL_FORMAT_ABGR888] = conv_abgr888, +}; + +rt_err_t graphic_start(const char *gdev, int count) +{ + rt_err_t err; + rt_uint8_t *vfb, *fb, *pixel, bpp; + struct rt_device_graphic_info info; + struct rt_device *dev = rt_device_find(gdev); + void (*conv_func)(rt_uint8_t r, rt_uint8_t g, rt_uint8_t b, void *pixel); + + if (!dev) + { + return -RT_EINVAL; + } + + if ((err = rt_device_open(dev, 0))) + { + return err; + } + + if ((err = rt_device_control(dev, RTGRAPHIC_CTRL_GET_INFO, &info))) + { + goto _end; + } + + if (!(vfb = rt_malloc(info.smem_len))) + { + err = -RT_ENOMEM; + goto _end; + } + + bpp = info.bits_per_pixel / 8; + conv_func = conv_funcs[info.pixel_format]; + + for (int frame = 0; frame < count; ++frame) + { + fb = vfb; + + for (int y = 0; y < info.height; ++y) + { + pixel = fb; + + for (int x = 0; x < info.width; ++x) + { + rt_uint8_t r, g, b; + + shader_frame(x, y, info.width, info.height, frame, &r, &g, &b); + + conv_func(r, g, b, pixel); + + pixel += bpp; + } + + fb += info.pitch; + } + + rt_memcpy(info.framebuffer, vfb, info.smem_len); + } + + rt_free(vfb); + +_end: + rt_device_close(dev); + + return err; +} + +#ifdef RT_USING_FINSH +#include + +static int _graphic_start(int argc, char**argv) +{ + int count = 10; + const char *gdev = "fb0"; + + if (argc > 1) + { + gdev = argv[1]; + } + if (argc > 2) + { + count = atoi(argv[2]); + } + + return (int)graphic_start(gdev, count); +} +MSH_CMD_EXPORT_ALIAS(_graphic_start, graphic_start, fixed resolution only e.g: graphic_start("fb0", 10)); +#endif /* RT_USING_FINSH */ +#endif /* RT_USING_GRAPHIC */ diff --git a/examples/test/dm_hmi_test.c b/examples/test/dm_hmi_test.c new file mode 100644 index 00000000000..b8fea78ad6c --- /dev/null +++ b/examples/test/dm_hmi_test.c @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include + +#include +#include + +#if defined(RT_USING_GRAPHIC) && defined(RT_USING_INPUT) + +#define CURSOR_WIDTH 64 +#define CURSOR_HEIGHT 64 + +struct hmi_info +{ + struct rt_device *gdev; + struct rt_device *idev; + + struct rt_device_graphic_info info; + struct rt_device_notify event_notify; + struct rt_input_handler handler; + + rt_bool_t event; + rt_bool_t vsync; + rt_bool_t keydown; + + rt_uint32_t x, y; + rt_uint32_t dx, dy; + rt_uint32_t bytes_per_pixel; + rt_ubase_t line[2]; + rt_ubase_t colors[4]; + + void *backend_framebuffer; +}; + +static rt_bool_t hmi_working; + +static struct rt_input_device *to_input_device(struct rt_device *idev) +{ + return rt_container_of(idev, struct rt_input_device, parent); +} + +static rt_ubase_t to_color(rt_uint8_t color255, rt_ubase_t color_max) +{ + return (rt_ubase_t)color255 * color_max / 255; +} + +static void hmi_reset(struct hmi_info *hmi) +{ + void *cursor; + rt_ubase_t none_alpha; + rt_ubase_t red_off, green_off, blue_off, alpha_off; + rt_ubase_t red_mask, green_mask, blue_mask, alpha_mask; + struct fb_var_screeninfo var; + + if (hmi->backend_framebuffer) + { + rt_free(hmi->backend_framebuffer); + } + + rt_device_control(hmi->gdev, FBIOGET_VSCREENINFO, &var); + rt_device_control(hmi->gdev, RTGRAPHIC_CTRL_GET_INFO, &hmi->info); + + hmi->backend_framebuffer = rt_malloc(hmi->info.smem_len); + + hmi->bytes_per_pixel = hmi->info.bits_per_pixel / 8; + red_off = var.red.offset; + red_mask = RT_GENMASK(var.red.length - 1, 0); + green_off = var.green.offset; + green_mask = RT_GENMASK(var.green.length - 1, 0); + blue_off = var.blue.offset; + blue_mask = RT_GENMASK(var.blue.length - 1, 0); + + if (var.transp.length) + { + alpha_off = var.transp.offset; + alpha_mask = RT_GENMASK(var.transp.length - 1, 0); + } + else + { + alpha_off = 0; + alpha_mask = 0; + } + + if ((cursor = rt_malloc(CURSOR_WIDTH * CURSOR_HEIGHT * hmi->bytes_per_pixel))) + { + rt_uint8_t *stream = cursor; + rt_ubase_t color = ((to_color(0x82, red_mask)) << red_off) | + (to_color(0x50, green_mask) << green_off) | + (to_color(0xdf, blue_mask) << blue_off) | + (to_color(0xcc, alpha_mask) << alpha_off); + + for (int y = 0; y < CURSOR_HEIGHT; ++y) + { + for (int x = 0; x < CURSOR_WIDTH; ++x) + { + rt_memcpy(stream, &color, hmi->bytes_per_pixel); + stream += hmi->bytes_per_pixel; + } + } + + rt_device_control(hmi->gdev, RT_DEVICE_CTRL_CURSOR_SET_TYPE, cursor); + rt_free(cursor); + } + + none_alpha = alpha_mask << alpha_off; + + hmi->line[0] = ~0UL; + hmi->line[1] = none_alpha; + + hmi->colors[0] = ((to_color(0xff, red_mask)) << red_off) | + (to_color(0x4b, green_mask) << green_off) | + (to_color(0x00, blue_mask) << blue_off) | none_alpha; + hmi->colors[1] = ((to_color(0x7f, red_mask)) << red_off) | + (to_color(0xdb, green_mask) << green_off) | + (to_color(0x3b, blue_mask) << blue_off) | none_alpha; + hmi->colors[2] = ((to_color(0x00, red_mask)) << red_off) | + (to_color(0xa4, green_mask) << green_off) | + (to_color(0xef, blue_mask) << blue_off) | none_alpha; + hmi->colors[3] = ((to_color(0xff, red_mask)) << red_off) | + (to_color(0xb8, green_mask) << green_off) | + (to_color(0x1c, blue_mask) << blue_off) | none_alpha; + + hmi->event = RT_FALSE; +} + +static void hmi_graphic_notify(rt_device_t dev) +{ + struct hmi_info *hmi = (void *)dev; + + hmi->event = RT_TRUE; +} + +static rt_bool_t hmi_input_callback(struct rt_input_handler *handler, + struct rt_input_event *ev) +{ + struct hmi_info *hmi = handler->priv; + + if (ev->type == EV_ABS) + { + if (ev->code == 0) + { + hmi->dx = (ev->value * hmi->info.width) / + (handler->idev->absinfo->maximum - handler->idev->absinfo->minimum); + } + else if (ev->code == 1) + { + hmi->dy = (ev->value * hmi->info.height) / + (handler->idev->absinfo->maximum - handler->idev->absinfo->minimum); + } + } + else if (ev->type == EV_KEY) + { + if (ev->code == BTN_LEFT) + { + if (hmi->keydown && ev->value == 0) + { + /* Swap lines color */ + hmi->line[0] ^= hmi->line[1]; + hmi->line[1] ^= hmi->line[0]; + hmi->line[0] ^= hmi->line[1]; + + hmi->keydown = RT_FALSE; + hmi->vsync = RT_FALSE; + } + else + { + hmi->keydown = RT_TRUE; + } + } + } + else if (ev->type == EV_SYN) + { + hmi->vsync = RT_FALSE; + } + + return RT_TRUE; +} + +static void hmi_loop(void *param) +{ + struct hmi_info *hmi = param; + struct rt_device_rect_info rect; + struct rt_device_graphic_ops *gops; + + /* Graphic device event */ + hmi->event_notify.notify = &hmi_graphic_notify; + hmi->event_notify.dev = (void *)hmi; + rt_device_control(hmi->gdev, RT_DEVICE_CTRL_NOTIFY_SET, &hmi->event_notify); + + /* Input device event */ + hmi->handler.idev = to_input_device(hmi->idev); + hmi->handler.identify = RT_NULL; + hmi->handler.callback = &hmi_input_callback; + hmi->handler.priv = hmi; + rt_input_add_handler(&hmi->handler); + + hmi->backend_framebuffer = RT_NULL; + hmi_reset(hmi); + + hmi->dx = hmi->info.width >> 1; + hmi->dy = hmi->info.height >> 1; + + rect.x = 0; + rect.y = 0; + + gops = rt_graphix_ops(hmi->gdev); + rt_device_control(hmi->gdev, RTGRAPHIC_CTRL_POWERON, RT_NULL); + + while (hmi_working) + { + rt_ubase_t pos; + + /* Wait graphic change */ + if (hmi->event) + { + hmi_reset(hmi); + } + + hmi->x = hmi->dx; + hmi->y = hmi->dy; + + rect.width = hmi->info.width; + rect.height = hmi->info.height; + pos = RTGRAPHIC_PIXEL_POSITION(hmi->x, hmi->y); + + for (int i = 0; i < RT_ARRAY_SIZE(hmi->colors); ++i) + { + rt_uint32_t x1, y1, x2, y2; + void *fb = hmi->backend_framebuffer ? : hmi->info.framebuffer; + + switch (i) + { + case 0: + x1 = 0; + y1 = 0; + x2 = hmi->x; + y2 = hmi->y; + break; + + case 1: + x1 = hmi->x; + y1 = 0; + x2 = hmi->info.width; + y2 = hmi->y; + break; + + case 2: + x1 = 0; + y1 = hmi->y; + x2 = hmi->x; + y2 = hmi->info.height; + break; + + case 3: + x1 = hmi->x; + y1 = hmi->y; + x2 = hmi->info.width; + y2 = hmi->info.height; + break; + } + + fb += x1 * hmi->bytes_per_pixel + y1 * hmi->info.pitch; + + for (int y = y1; y < y2; ++y) + { + void *fb_entry = fb; + + for (int x = x1; x < x2; ++x) + { + rt_memcpy(fb, &hmi->colors[i], hmi->bytes_per_pixel); + fb += hmi->bytes_per_pixel; + } + + fb = fb_entry + hmi->info.pitch; + } + } + + if (hmi->backend_framebuffer) + { + rt_memcpy(hmi->info.framebuffer, hmi->backend_framebuffer, hmi->info.smem_len); + } + + gops->draw_hline((void *)&hmi->line[0], 0, rect.width, hmi->y); + gops->draw_vline((void *)&hmi->line[1], hmi->x, 0, rect.height); + + rt_device_control(hmi->gdev, RTGRAPHIC_CTRL_RECT_UPDATE, &rect); + rt_device_control(hmi->gdev, RT_DEVICE_CTRL_CURSOR_SET_POSITION, (void *)pos); + + /* Next position */ + hmi->vsync = RT_TRUE; + rt_hw_wmb(); + + while (hmi_working && hmi->vsync) + { + rt_thread_mdelay(1); + } + } + + rt_device_control(hmi->gdev, RTGRAPHIC_CTRL_POWEROFF, RT_NULL); + + rt_memset(&hmi->event_notify, 0, sizeof(hmi->event_notify)); + rt_device_control(hmi->gdev, RT_DEVICE_CTRL_NOTIFY_SET, &hmi->event_notify); + + rt_input_del_handler(&hmi->handler); + + rt_device_close(hmi->gdev); + rt_device_close(hmi->idev); + + if (hmi->backend_framebuffer) + { + rt_free(hmi->backend_framebuffer); + } + rt_free(hmi); + + rt_thread_delete(rt_thread_self()); +} + +rt_err_t hmi_start(const char *gdev, const char *idev) +{ + rt_err_t err; + struct hmi_info *hmi; + struct rt_thread *loop; + + if (hmi_working) + { + rt_kprintf("HMI is running\n"); + return -RT_EBUSY; + } + + hmi = rt_malloc(sizeof(*hmi)); + + if (!hmi) + { + return -RT_ENOMEM; + } + + hmi->gdev = rt_device_find(gdev); + hmi->idev = rt_device_find(idev); + + if (!hmi->gdev || !hmi->idev) + { + rt_free(hmi); + return -RT_EINVAL; + } + + if (!rt_bitmap_test_bit(to_input_device(hmi->idev)->cap, EV_ABS)) + { + rt_kprintf("%s is not a ABS input\n", idev); + rt_free(hmi); + return -RT_EINVAL; + } + + if ((err = rt_device_open(hmi->gdev, 0))) + { + rt_free(hmi); + return err; + } + + if ((err = rt_device_open(hmi->idev, 0))) + { + rt_device_close(hmi->gdev); + rt_free(hmi); + return err; + } + + loop = rt_thread_create("HMI", hmi_loop, hmi, + DM_THREAD_STACK_SIZE, + RT_THREAD_PRIORITY_MAX / 3, + rt_tick_from_millisecond(RT_GRAPHIC_UPDATE_MS)); + + if (!loop) + { + rt_device_close(hmi->gdev); + rt_device_close(hmi->idev); + rt_free(hmi); + return -RT_ENOMEM; + } + + hmi_working = RT_TRUE; + rt_thread_startup(loop); + + return RT_EOK; +} + +rt_err_t hmi_stop(void) +{ + hmi_working = RT_FALSE; + return RT_EOK; +} + +#ifdef RT_USING_FINSH +static int _hmi_start(int argc, char**argv) +{ + const char *gdev = "fb0", *idev = "input0"; + + if (argc == 3) + { + gdev = argv[1]; + idev = argv[2]; + } + + return (int)hmi_start(gdev, idev); +} +MSH_CMD_EXPORT_ALIAS(_hmi_start, hmi_start, e.g: hmi_start("fb0", "input0")); + +static int _hmi_stop(void) +{ + return (int)hmi_stop(); +} +MSH_CMD_EXPORT_ALIAS(_hmi_stop, hmi_stop, e.g: hmi_exit()); +#endif /* RT_USING_FINSH */ +#endif /* RT_USING_GRAPHIC && RT_USING_INPUT */ From 5020c0b2340b0016c3a50206caaf4f2eb3cf8786 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Fri, 12 Dec 2025 16:03:34 +0800 Subject: [PATCH 17/20] [dm][graphic] add new drivers and logo 1. Generic GPIO based backlight driver 2. Generic PWM based backlight driver 3. Simple framebuffer support 4. Standard 224-color RT-Thread logo 5. Standard 224-color RT-Thread white logo Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/graphic/backlight/Kconfig | 15 + .../drivers/graphic/backlight/SConscript | 6 + .../graphic/backlight/backlight-gpio.c | 135 ++ .../drivers/graphic/backlight/backlight-pwm.c | 569 ++++++ .../drivers/graphic/framebuffer/Kconfig | 6 + .../drivers/graphic/framebuffer/SConscript | 3 + .../drivers/graphic/framebuffer/fb-simple.c | 381 ++++ components/drivers/graphic/logo/Kconfig | 6 + components/drivers/graphic/logo/SConscript | 6 + .../graphic/logo/logo-rt-thread-clut224.ppm | 1597 +++++++++++++++++ .../logo/logo-rt-thread-white-clut224.ppm | 1597 +++++++++++++++++ 11 files changed, 4321 insertions(+) create mode 100644 components/drivers/graphic/backlight/backlight-gpio.c create mode 100644 components/drivers/graphic/backlight/backlight-pwm.c create mode 100644 components/drivers/graphic/framebuffer/fb-simple.c create mode 100644 components/drivers/graphic/logo/logo-rt-thread-clut224.ppm create mode 100644 components/drivers/graphic/logo/logo-rt-thread-white-clut224.ppm diff --git a/components/drivers/graphic/backlight/Kconfig b/components/drivers/graphic/backlight/Kconfig index 1951e0c05ac..a0c85a32fc6 100644 --- a/components/drivers/graphic/backlight/Kconfig +++ b/components/drivers/graphic/backlight/Kconfig @@ -2,6 +2,21 @@ menuconfig RT_GRAPHIC_BACKLIGHT bool "Backlight support" default n +config RT_GRAPHIC_BACKLIGHT_GPIO + bool "Generic GPIO based backlight driver" + depends on RT_GRAPHIC_BACKLIGHT + depends on RT_USING_PIN + default n + +config RT_GRAPHIC_BACKLIGHT_PWM + bool "Generic PWM based backlight driver" + depends on RT_GRAPHIC_BACKLIGHT + depends on RT_USING_OFW + depends on RT_USING_PIN + depends on RT_USING_PWM + depends on RT_USING_REGULATOR + default n + if RT_GRAPHIC_BACKLIGHT osource "$(SOC_DM_GRAPHIC_BACKLIGHT_DIR)/Kconfig" endif diff --git a/components/drivers/graphic/backlight/SConscript b/components/drivers/graphic/backlight/SConscript index 6e29db51b3f..204867b44cc 100644 --- a/components/drivers/graphic/backlight/SConscript +++ b/components/drivers/graphic/backlight/SConscript @@ -10,5 +10,11 @@ CPPPATH = [cwd + '/../../include'] src = ['backlight.c'] +if GetDepend(['RT_GRAPHIC_BACKLIGHT_GPIO']): + src += ['backlight-gpio.c'] + +if GetDepend(['RT_GRAPHIC_BACKLIGHT_PWM']): + src += ['backlight-pwm.c'] + group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/components/drivers/graphic/backlight/backlight-gpio.c b/components/drivers/graphic/backlight/backlight-gpio.c new file mode 100644 index 00000000000..b46a99fcf64 --- /dev/null +++ b/components/drivers/graphic/backlight/backlight-gpio.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "backlight.gpio" +#define DBG_LVL DBG_INFO +#include + +struct gpio_backlight +{ + struct rt_backlight_device parent; + + rt_base_t pin; + rt_uint8_t active_val; +}; + +#define raw_to_gpio_backlight(raw) rt_container_of(raw, struct gpio_backlight, parent) + +static rt_err_t gpio_backlight_update_status(struct rt_backlight_device *bl) +{ + rt_uint8_t brightness; + struct gpio_backlight *gbl = raw_to_gpio_backlight(bl); + + rt_pin_mode(gbl->pin, PIN_MODE_OUTPUT); + + brightness = rt_backlight_power_brightness(bl); + + if (!gbl->active_val) + { + brightness = !brightness; + } + + rt_pin_write(gbl->pin, brightness); + + return RT_EOK; +} + +static struct rt_backlight_ops gpio_backlight_ops = +{ + .update_status = gpio_backlight_update_status, +}; + +static rt_err_t gpio_backlight_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + rt_bool_t def_value; + struct rt_device *dev = &pdev->parent; + struct gpio_backlight *gbl = rt_calloc(1, sizeof(*gbl)); + + if (!gbl) + { + return -RT_ENOMEM; + } + + def_value = rt_dm_dev_prop_read_bool(dev, "default-on"); + + gbl->pin = rt_pin_get_named_pin(dev, RT_NULL, 0, RT_NULL, &gbl->active_val); + + if (gbl->pin < 0) + { + err = gbl->pin; + + goto _fail; + } + + /* Set the initial power state */ + if (!dev->ofw_node || !rt_dm_dev_prop_read_bool(dev, "phandle")) + { + gbl->parent.props.power = def_value ? + RT_BACKLIGHT_POWER_UNBLANK : RT_BACKLIGHT_POWER_POWERDOWN; + } + else if (rt_pin_read(gbl->pin) != gbl->active_val) + { + gbl->parent.props.power = RT_BACKLIGHT_POWER_POWERDOWN; + } + else + { + gbl->parent.props.power = RT_BACKLIGHT_POWER_UNBLANK; + } + + gbl->parent.props.max_brightness = 1; + gbl->parent.ops = &gpio_backlight_ops; + + if ((err = rt_backlight_register(&gbl->parent))) + { + goto _fail; + } + + rt_pin_mode(gbl->pin, PIN_MODE_OUTPUT); + rt_backlight_set_brightness(&gbl->parent, 1); + + return RT_EOK; + +_fail: + rt_free(gbl); + + return err; +} + +static rt_err_t gpio_backlight_remove(struct rt_platform_device *pdev) +{ + struct gpio_backlight *gbl = pdev->parent.user_data; + + rt_backlight_unregister(&gbl->parent); + + rt_free(gbl); + + return RT_EOK; +} + +static const struct rt_ofw_node_id gpio_backlight_ofw_ids[] = +{ + { .compatible = "gpio-backlight" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver gpio_backlight_driver = +{ + .name = "gpio-backlight", + .ids = gpio_backlight_ofw_ids, + + .probe = gpio_backlight_probe, + .remove = gpio_backlight_remove, +}; +RT_PLATFORM_DRIVER_EXPORT(gpio_backlight_driver); diff --git a/components/drivers/graphic/backlight/backlight-pwm.c b/components/drivers/graphic/backlight/backlight-pwm.c new file mode 100644 index 00000000000..7972cce6f28 --- /dev/null +++ b/components/drivers/graphic/backlight/backlight-pwm.c @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "backlight.pwm" +#define DBG_LVL DBG_INFO +#include + +struct pwm_backlight +{ + struct rt_backlight_device parent; + + rt_uint32_t lth_brightness; + rt_uint32_t *levels; + + rt_base_t enable_pin; + rt_uint8_t active_val; + + rt_uint32_t scale; + rt_uint32_t post_pwm_on_delay; + rt_uint32_t pwm_off_delay; + rt_uint32_t dft_brightness; + rt_uint32_t max_brightness; + + rt_bool_t enabled; + struct rt_device_pwm *pwm_dev; + struct rt_pwm_configuration pwm_conf; + + struct rt_regulator *power_supply; +}; + +#define raw_to_pwm_backlight(raw) rt_container_of(raw, struct pwm_backlight, parent) + +static void pwm_backlight_power_on(struct pwm_backlight *pbl) +{ + rt_err_t err; + + if (pbl->enabled) + { + return; + } + + if (pbl->power_supply) + { + if ((err = rt_regulator_enable(pbl->power_supply))) + { + LOG_E("Enable power supply error = %s", rt_strerror(err)); + } + } + + if (pbl->post_pwm_on_delay) + { + rt_thread_mdelay(pbl->post_pwm_on_delay); + } + + if (pbl->enable_pin >= 0) + { + rt_pin_write(pbl->enable_pin, pbl->active_val); + } + + pbl->enabled = RT_TRUE; +} + +static void pwm_backlight_power_off(struct pwm_backlight *pbl) +{ + if (!pbl->enabled) + { + return; + } + + if (pbl->enable_pin >= 0) + { + rt_pin_write(pbl->enable_pin, !pbl->active_val); + } + + if (pbl->pwm_off_delay) + { + rt_thread_mdelay(pbl->pwm_off_delay); + } + + if (pbl->power_supply) + { + rt_regulator_disable(pbl->power_supply); + } + + pbl->enabled = RT_FALSE; +} + +static int compute_duty_cycle(struct pwm_backlight *pbl, rt_uint32_t brightness, + rt_uint32_t period) +{ + rt_uint64_t duty_cycle; + rt_uint32_t lth = pbl->lth_brightness; + + if (pbl->levels) + { + duty_cycle = pbl->levels[brightness]; + } + else + { + duty_cycle = brightness; + } + + duty_cycle *= period - lth; + rt_do_div(duty_cycle, pbl->scale); + + return duty_cycle + lth; +} + +static rt_err_t pwm_backlight_update_status(struct rt_backlight_device *bl) +{ + rt_uint32_t brightness, duty_cycle; + struct rt_pwm_configuration pwm_conf = {}; + struct pwm_backlight *pbl = raw_to_pwm_backlight(bl); + + rt_pwm_get(pbl->pwm_dev, &pwm_conf); + brightness = rt_backlight_power_brightness(bl); + + if (brightness > 0) + { + duty_cycle = compute_duty_cycle(pbl, brightness, pwm_conf.period); + pwm_conf.pulse = duty_cycle; + rt_pwm_set(pbl->pwm_dev, pwm_conf.channel, pwm_conf.period, pwm_conf.pulse); + + rt_pwm_enable(pbl->pwm_dev, pbl->pwm_conf.channel); + + pwm_backlight_power_on(pbl); + } + else + { + pwm_backlight_power_off(pbl); + + pwm_conf.pulse = 0; + rt_pwm_set(pbl->pwm_dev, pwm_conf.channel, pwm_conf.period, pwm_conf.pulse); + + if (pbl->power_supply || pbl->enable_pin >= 0) + { + rt_pwm_disable(pbl->pwm_dev, pbl->pwm_conf.channel); + } + } + + return RT_EOK; +} + +static struct rt_backlight_ops pwm_backlight_ops = +{ + .update_status = pwm_backlight_update_status, +}; + +#define PWM_LUMINANCE_SHIFT 16 +#define PWM_LUMINANCE_SCALE (1 << PWM_LUMINANCE_SHIFT) /* luminance scale */ + +rt_inline int period_fls(int period) +{ + return period ? sizeof(period) * 8 - __rt_clz(period) : 0; +} + +static rt_err_t pwm_backlight_brightness_default(struct pwm_backlight *pbl, + rt_uint32_t period) +{ + rt_uint32_t lightness; + rt_uint64_t res, cie1931; + + pbl->max_brightness = rt_min((int)RT_DIV_ROUND_UP(period, period_fls(period)), 4096); + + pbl->levels = rt_calloc(pbl->max_brightness, sizeof(*pbl->levels)); + + if (!pbl->levels) + { + return -RT_ENOMEM; + } + + /* Fill the table using the cie1931 algorithm */ + for (int i = 0; i < pbl->max_brightness; ++i) + { + lightness = (i * PWM_LUMINANCE_SCALE) / pbl->max_brightness * 100; + + if (lightness <= (8 * PWM_LUMINANCE_SCALE)) + { + cie1931 = RT_DIV_ROUND_CLOSEST(lightness * 10, 9033); + } + else + { + cie1931 = (lightness + (16 * PWM_LUMINANCE_SCALE)) / 116; + cie1931 *= cie1931 * cie1931; + cie1931 += 1ULL << (2 * PWM_LUMINANCE_SHIFT - 1); + cie1931 >>= 2 * PWM_LUMINANCE_SHIFT; + } + + res = cie1931 * period; + res = RT_DIV_ROUND_CLOSEST_ULL(res, PWM_LUMINANCE_SCALE); + + if (res > RT_UINT32_MAX) + { + return -RT_EINVAL; + } + + pbl->levels[i] = (rt_uint32_t)res; + } + + pbl->dft_brightness = pbl->max_brightness / 2; + pbl->max_brightness--; + + return 0; +} + +static rt_err_t pwm_backlight_ofw_parse(struct pwm_backlight *pbl, + struct rt_ofw_node *np) +{ + rt_err_t err; + rt_ssize_t length; + rt_uint32_t *table, value; + rt_uint32_t num_levels, num_steps = 0; + struct rt_ofw_prop *prop; + + /* + * These values are optional and set as 0 by default, the out values + * are modified only if a valid u32 value can be decoded. + */ + rt_ofw_prop_read_u32(np, "post-pwm-on-delay-ms", &pbl->post_pwm_on_delay); + rt_ofw_prop_read_u32(np, "pwm-off-delay-ms", &pbl->pwm_off_delay); + + /* + * Determine the number of brightness levels, if this property is not + * set a default table of brightness levels will be used. + */ + prop = rt_ofw_get_prop(np, "brightness-levels", &length); + + if (!prop) + { + return RT_EOK; + } + + num_levels = length / sizeof(rt_uint32_t); + + if (!num_levels) + { + return RT_EOK; + } + + pbl->levels = rt_calloc(num_levels, sizeof(*pbl->levels)); + + if (!pbl->levels) + { + return -RT_ENOMEM; + } + + if ((err = rt_ofw_prop_read_u32_array_index(np, "brightness-levels", + 0, num_levels, pbl->levels)) < 0) + { + goto _fail; + } + + if ((err = rt_ofw_prop_read_u32(np, "default-brightness-level", &value))) + { + goto _fail; + } + + pbl->dft_brightness = value; + + /* + * This property is optional, if is set enables linear + * interpolation between each of the values of brightness levels + * and creates a new pre-computed table. + */ + rt_ofw_prop_read_u32(np, "num-interpolated-steps", &num_steps); + + /* + * Make sure that there is at least two entries in the + * brightness-levels table, otherwise we can't interpolate + * between two points. + */ + if (num_steps) + { + rt_int64_t dy; + rt_uint32_t x1, x2, x, dx, y1, y2; + rt_uint32_t num_input_levels = num_levels; + + if (num_input_levels < 2) + { + LOG_E("Can't interpolate"); + + err = -RT_EINVAL; + goto _fail; + } + + num_levels = (num_input_levels - 1) * num_steps + 1; + + table = rt_calloc(num_levels, sizeof(*table)); + + if (!table) + { + err = -RT_ENOMEM; + goto _fail; + } + + /* + * Fill the interpolated table[x] = y + * by draw lines between each (x1, y1) to (x2, y2). + */ + dx = num_steps; + + for (int i = 0; i < num_input_levels - 1; ++i) + { + x1 = i * dx; + x2 = x1 + dx; + y1 = pbl->levels[i]; + y2 = pbl->levels[i + 1]; + dy = (rt_int64_t)y2 - y1; + + for (x = x1; x < x2; ++x) + { + table[x] = y1 + (rt_int64_t)(dy * (x - x1)) / (rt_int64_t)dx; + } + } + + /* Fill in the last point, since no line starts here. */ + table[x2] = y2; + + rt_free(pbl->levels); + pbl->levels = table; + } + + pbl->max_brightness = num_levels - 1; + + return RT_EOK; + +_fail: + rt_free(pbl->levels); + + return err; +} + +static enum rt_backlight_power pwm_backlight_initial_power_state( + struct pwm_backlight *pbl, struct rt_device *dev) +{ + rt_bool_t active = RT_TRUE; + + if (pbl->enable_pin >= 0 && rt_pin_read(pbl->enable_pin) != pbl->active_val) + { + active = RT_FALSE; + } + + if (pbl->power_supply && !rt_regulator_is_enabled(pbl->power_supply)) + { + active = RT_FALSE; + } + + /* Synchronize the enable_gpio with the observed state of the hardware. */ + rt_pin_mode(pbl->enable_pin, PIN_MODE_OUTPUT); + rt_pin_write(pbl->enable_pin, active ? pbl->active_val : !pbl->active_val); + + /* Not booted with device tree or no phandle link to the node */ + if (!dev->ofw_node || rt_dm_dev_prop_read_bool(dev, "phandle")) + { + return RT_BACKLIGHT_POWER_UNBLANK; + } + + return active ? RT_BACKLIGHT_POWER_UNBLANK: RT_BACKLIGHT_POWER_POWERDOWN; +} + +static rt_err_t pwm_backlight_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + enum rt_backlight_power power; + struct rt_ofw_cell_args pwm_args; + struct rt_device *dev = &pdev->parent; + struct rt_ofw_node *np = dev->ofw_node, *pwm_np; + struct pwm_backlight *pbl = rt_calloc(1, sizeof(*pbl)); + + if (!pbl) + { + return -RT_ENOMEM; + } + + if ((err = pwm_backlight_ofw_parse(pbl, dev->ofw_node))) + { + goto _fail; + } + + pbl->enable_pin = rt_pin_get_named_pin(dev, "enable", 0, RT_NULL, &pbl->active_val); + + if (pbl->enable_pin < 0 && pbl->enable_pin != PIN_NONE) + { + err = pbl->enable_pin; + + goto _fail; + } + + pbl->power_supply = rt_regulator_get(dev, "power"); + + if (rt_is_err(pbl->power_supply)) + { + err = rt_ptr_err(pbl->power_supply); + + goto _fail; + } + + if (rt_ofw_parse_phandle_cells(np, "pwms", "#pwm-cells", 0, &pwm_args)) + { + err = -RT_EINVAL; + goto _fail; + } + + pwm_np = pwm_args.data; + + if (!rt_ofw_data(pwm_np)) + { + rt_platform_ofw_request(pwm_np); + } + + pbl->pwm_dev = rt_ofw_data(pwm_np); + rt_ofw_node_put(pwm_np); + + if (!pbl->pwm_dev) + { + err = -RT_EINVAL; + goto _fail; + } + + pbl->pwm_conf.channel = pwm_args.args[0]; + pbl->pwm_conf.period = pwm_args.args[1]; + + rt_pwm_set_period(pbl->pwm_dev, pbl->pwm_conf.channel, pbl->pwm_conf.period); + + if (pbl->levels) + { + for (int i = 0; i <= pbl->max_brightness; ++i) + { + if (pbl->levels[i] > pbl->scale) + { + pbl->scale = pbl->levels[i]; + } + } + } + else if (!pbl->max_brightness) + { + struct rt_pwm_configuration pwm_conf = {}; + + rt_pwm_get(pbl->pwm_dev, &pwm_conf); + + /* Make levels */ + if ((err = pwm_backlight_brightness_default(pbl, pbl->pwm_conf.period))) + { + LOG_E("Setup default brightness table error = %s", rt_strerror(err)); + + goto _fail; + } + + for (int i = 0; i <= pbl->max_brightness; ++i) + { + if (pbl->levels[i] > pbl->scale) + { + pbl->scale = pbl->levels[i]; + } + } + } + else + { + pbl->scale = pbl->max_brightness; + } + + pbl->parent.props.max_brightness = pbl->max_brightness; + pbl->parent.ops = &pwm_backlight_ops; + + if ((err = rt_backlight_register(&pbl->parent))) + { + goto _fail; + } + + power = pwm_backlight_initial_power_state(pbl, dev); + rt_backlight_set_power(&pbl->parent, power); + + if (pbl->dft_brightness > pbl->max_brightness) + { + LOG_W("Invalid default brightness level: %u, using %u", + pbl->dft_brightness, pbl->max_brightness); + + pbl->dft_brightness = pbl->max_brightness; + } + rt_backlight_set_brightness(&pbl->parent, pbl->dft_brightness); + + return RT_EOK; + +_fail: + if (!rt_is_err_or_null(pbl->power_supply)) + { + rt_regulator_put(pbl->power_supply); + } + + if (pbl->levels) + { + rt_free(pbl->levels); + } + + rt_free(pbl); + + return err; +} + +static rt_err_t pwm_backlight_remove(struct rt_platform_device *pdev) +{ + struct rt_pwm_configuration pwm_conf = {}; + struct pwm_backlight *pbl = pdev->parent.user_data; + + rt_backlight_unregister(&pbl->parent); + + pwm_backlight_power_off(pbl); + + rt_regulator_put(pbl->power_supply); + + rt_pwm_get(pbl->pwm_dev, &pwm_conf); + pwm_conf.pulse = 0; + + rt_pwm_set(pbl->pwm_dev, pwm_conf.channel, pwm_conf.period, pwm_conf.pulse); + rt_pwm_disable(pbl->pwm_dev, pbl->pwm_conf.channel); + + if (pbl->levels) + { + rt_free(pbl->levels); + } + + rt_free(pbl); + + return RT_EOK; +} + +static rt_err_t pwm_backlight_shutdown(struct rt_platform_device *pdev) +{ + struct rt_pwm_configuration pwm_conf = {}; + struct pwm_backlight *pbl = pdev->parent.user_data; + + pwm_backlight_power_off(pbl); + + rt_pwm_get(pbl->pwm_dev, &pwm_conf); + pwm_conf.pulse = 0; + + rt_pwm_set(pbl->pwm_dev, pwm_conf.channel, pwm_conf.period, pwm_conf.pulse); + rt_pwm_disable(pbl->pwm_dev, pbl->pwm_conf.channel); + + return RT_EOK; +} + +static const struct rt_ofw_node_id pwm_backlight_ofw_ids[] = +{ + { .compatible = "pwm-backlight" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver pwm_backlight_driver = +{ + .name = "pwm-backlight", + .ids = pwm_backlight_ofw_ids, + + .probe = pwm_backlight_probe, + .remove = pwm_backlight_remove, + .shutdown = pwm_backlight_shutdown, +}; +RT_PLATFORM_DRIVER_EXPORT(pwm_backlight_driver); diff --git a/components/drivers/graphic/framebuffer/Kconfig b/components/drivers/graphic/framebuffer/Kconfig index 9144377d202..d13c9bf1427 100644 --- a/components/drivers/graphic/framebuffer/Kconfig +++ b/components/drivers/graphic/framebuffer/Kconfig @@ -3,6 +3,12 @@ menuconfig RT_GRAPHIC_FB select RT_USING_LCD default y +config RT_GRAPHIC_FB_SIMPLE + bool "Simple framebuffer support" + depends on RT_GRAPHIC_FB + depends on RT_USING_OFW + default y + if RT_GRAPHIC_FB osource "$(SOC_DM_GRAPHIC_FB_DIR)/Kconfig" endif diff --git a/components/drivers/graphic/framebuffer/SConscript b/components/drivers/graphic/framebuffer/SConscript index 55d76c540fc..0323df1cd3a 100644 --- a/components/drivers/graphic/framebuffer/SConscript +++ b/components/drivers/graphic/framebuffer/SConscript @@ -11,6 +11,9 @@ CPPPATH = [cwd + '/../../include'] src = [] +if GetDepend(['RT_GRAPHIC_FB_SIMPLE']): + src += ['fb-simple.c'] + group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/components/drivers/graphic/framebuffer/fb-simple.c b/components/drivers/graphic/framebuffer/fb-simple.c new file mode 100644 index 00000000000..55f80542cf7 --- /dev/null +++ b/components/drivers/graphic/framebuffer/fb-simple.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "fb.simple" +#define DBG_LVL DBG_INFO +#include + +struct simplefb_format +{ + const char *name; + rt_uint32_t mode; + rt_uint32_t bits_per_pixel; +}; + +struct simplefb_params +{ + rt_uint32_t width; + rt_uint32_t height; + rt_uint32_t stride; + struct simplefb_format *format; +}; + +struct simplefb +{ + struct rt_graphic_device parent; + + void *screen_base; + rt_size_t screen_size; + rt_size_t stride; + +#ifdef RT_USING_CLK + rt_bool_t clk_arr_enabled; + struct rt_clk_array *clk_arr; +#endif +#ifdef RT_USING_REGULATOR + rt_bool_t supplys_enabled; + rt_size_t supplys_nr; + struct rt_regulator **supplys; +#endif +}; + +#ifdef RT_USING_CLK +static rt_err_t simplefb_clk_probe(struct simplefb *sfb, + struct rt_platform_device *pdev) +{ + sfb->clk_arr = rt_clk_get_array(&pdev->parent); + + if (rt_is_err(sfb->clk_arr)) + { + return rt_ptr_err(sfb->clk_arr); + } + + return RT_EOK; +} + +static void simplefb_clk_enable(struct simplefb *sfb) +{ + rt_clk_array_prepare_enable(sfb->clk_arr); + sfb->clk_arr_enabled = RT_TRUE; +} + +static void simplefb_clk_remove(struct simplefb *sfb) +{ + if (!rt_is_err_or_null(sfb->clk_arr)) + { + if (sfb->clk_arr_enabled) + { + rt_clk_array_disable_unprepare(sfb->clk_arr); + } + + rt_clk_array_put(sfb->clk_arr); + } +} +#else +static rt_err_t simplefb_clk_probe(struct simplefb *sfb, + struct rt_platform_device *pdev) { return RT_EOK; } +static void simplefb_clk_enable(struct simplefb *sfb) { } +static void simplefb_clk_remove(struct simplefb *sfb) { } +#endif /* RT_USING_CLK */ + +#ifdef RT_USING_REGULATOR +#define SUPPLY_SUFFIX "-supply" + +static rt_err_t simplefb_regulator_probe(struct simplefb *sfb, + struct rt_platform_device *pdev) +{ + int i = 0; + const char *name; + struct rt_device *dev = &pdev->parent; + struct rt_ofw_prop *prop; + struct rt_ofw_node *np = dev->ofw_node; + + rt_ofw_foreach_prop(np, prop) + { + name = rt_strstr(prop->name, SUPPLY_SUFFIX); + + if (name && name != prop->name) + { + ++sfb->supplys_nr; + } + } + + sfb->supplys = rt_calloc(sfb->supplys_nr, sizeof(sfb->supplys[0])); + + if (!sfb->supplys) + { + return -RT_ENOMEM; + } + + rt_ofw_foreach_prop(np, prop) + { + name = rt_strstr(prop->name, SUPPLY_SUFFIX); + + if (name && name != prop->name) + { + char name[32]; + int len = name - prop->name; + + rt_strncpy(name, prop->name, len); + name[len] = '\0'; + + sfb->supplys[i] = rt_regulator_get(dev, (const char *)name); + + if (rt_is_err(sfb->supplys[i])) + { + return rt_ptr_err(sfb->supplys[i]); + } + + ++i; + } + } + + return RT_EOK; +} + +static void simplefb_regulator_enable(struct simplefb *sfb) +{ + if (sfb->supplys) + { + for (int i = 0; i < sfb->supplys_nr; ++i) + { + rt_regulator_enable(sfb->supplys[i]); + } + + sfb->supplys_enabled = RT_TRUE; + } +} + +static void simplefb_regulator_remove(struct simplefb *sfb) +{ + if (sfb->supplys && sfb->supplys_enabled) + { + for (int i = 0; i < sfb->supplys_nr; ++i) + { + struct rt_regulator *supply = sfb->supplys[i]; + + if (!rt_is_err(supply)) + { + rt_regulator_disable(supply); + rt_regulator_put(supply); + } + } + + rt_free(sfb->supplys); + } +} +#else +static rt_err_t simplefb_regulator_probe(struct simplefb *sfb, + struct rt_platform_device *pdev) +{ + return RT_EOK; +} + +static void simplefb_regulator_enable(struct simplefb *sfb) +{ +} + +static void simplefb_regulator_remove(struct simplefb *sfb) +{ +} +#endif /* RT_USING_REGULATOR */ + +static struct simplefb_format simplefb_formats[] = +{ + { "r5g6b5", RTGRAPHIC_PIXEL_FORMAT_RGB565, 16 }, + { "r8g8b8", RTGRAPHIC_PIXEL_FORMAT_RGB888, 24 }, + { "x8r8g8b8", RTGRAPHIC_PIXEL_FORMAT_ARGB888, 32 }, + { "a8r8g8b8", RTGRAPHIC_PIXEL_FORMAT_ARGB888, 32 }, + { "x8b8g8r8", RTGRAPHIC_PIXEL_FORMAT_ABGR888, 32 }, + { "a8b8g8r8", RTGRAPHIC_PIXEL_FORMAT_ABGR888, 32 }, +}; + +static rt_err_t simplefb_params_parse(struct simplefb_params *params, + struct rt_platform_device *pdev) +{ + rt_err_t err; + const char *format; + struct rt_device *dev = &pdev->parent; + + if ((err = rt_dm_dev_prop_read_u32(dev, "width", ¶ms->width))) + { + LOG_E("Can't parse width property"); + + return err; + } + + if ((err = rt_dm_dev_prop_read_u32(dev, "height", ¶ms->height))) + { + LOG_E("Can't parse height property"); + + return err; + } + + if ((err = rt_dm_dev_prop_read_u32(dev, "stride", ¶ms->stride))) + { + LOG_E("Can't parse stride property"); + + return err; + } + + if ((err = rt_dm_dev_prop_read_string(dev, "format", &format))) + { + LOG_E("Can't parse format property"); + + return err; + } + + for (int i = 0; i < RT_ARRAY_SIZE(simplefb_formats); ++i) + { + if (rt_strcmp(format, simplefb_formats[i].name)) + { + continue; + } + + params->format = &simplefb_formats[i]; + + return RT_EOK; + } + + LOG_E("Unsupport format value"); + + return -RT_EINVAL; +} + +static rt_err_t simplefb_plane_fb_remap(struct rt_graphic_plane *plane, + rt_uint32_t mode, struct rt_device_rect_info *rect) +{ + struct simplefb *sfb = rt_container_of(plane->graphic, struct simplefb, parent); + + plane->line_length = sfb->stride; + plane->bits_per_pixel = rt_graphic_mode_bpp(mode); + + plane->framebuffer = sfb->screen_base; + plane->screen_len = sfb->screen_size; + plane->framebuffer_len = sfb->screen_size; + + return RT_EOK; +} + +static const struct rt_graphic_plane_ops simplefb_plane_ops = +{ + .fb_remap = simplefb_plane_fb_remap, +}; + +static rt_err_t simplefb_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + rt_uint64_t addr, size; + struct simplefb_params params = {}; + struct simplefb *sfb = rt_calloc(1, sizeof(*sfb)); + + if (!sfb) + { + return -RT_ENOMEM; + } + + if ((err = simplefb_params_parse(¶ms, pdev))) + { + goto _fail; + } + + sfb->stride = params.stride; + + if ((err = rt_dm_dev_get_address(&pdev->parent, 0, &addr, &size))) + { + goto _fail; + } + + sfb->screen_size = (rt_size_t)size; + sfb->screen_base = rt_ioremap_wt((void *)addr, sfb->screen_size); + + if (!sfb->screen_base) + { + err = -RT_EIO; + goto _fail; + } + + if ((err = simplefb_clk_probe(sfb, pdev))) + { + LOG_E("Get %s error = %s", "clk", rt_strerror(err)); + + goto _fail; + } + + if ((err = simplefb_regulator_probe(sfb, pdev))) + { + LOG_E("Get %s error = %s", "regulator", rt_strerror(err)); + + goto _fail; + } + + simplefb_clk_enable(sfb); + simplefb_regulator_enable(sfb); + + if ((err = rt_graphic_device_simple_register(&sfb->parent, + params.width, params.height, 0, &simplefb_plane_ops, + ¶ms.format->mode, 1))) + { + goto _fail; + } + + pdev->parent.user_data = sfb; + + return RT_EOK; + +_fail: + if (sfb->screen_base) + { + rt_iounmap(sfb->screen_base); + } + + simplefb_clk_remove(sfb); + simplefb_regulator_remove(sfb); + + rt_free(sfb); + + return err; +} + +static rt_err_t simplefb_remove(struct rt_platform_device *pdev) +{ + struct simplefb *sfb = pdev->parent.user_data; + + rt_graphic_device_simple_unregister(&sfb->parent); + + simplefb_clk_remove(sfb); + simplefb_regulator_remove(sfb); + + rt_iounmap(sfb->screen_base); + + rt_free(sfb); + + return RT_EOK; +} + +static const struct rt_ofw_node_id simplefb_ofw_ids[] = +{ + { .compatible = "simple-framebuffer" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver simplefb_driver = +{ + .name = "simple-framebuffer", + .ids = simplefb_ofw_ids, + + .probe = simplefb_probe, + .remove = simplefb_remove, +}; +RT_PLATFORM_DRIVER_EXPORT(simplefb_driver); diff --git a/components/drivers/graphic/logo/Kconfig b/components/drivers/graphic/logo/Kconfig index 45bcfe3f59d..5bce06c8129 100644 --- a/components/drivers/graphic/logo/Kconfig +++ b/components/drivers/graphic/logo/Kconfig @@ -11,6 +11,12 @@ choice config RT_GRAPHIC_LOGO_NONE bool "None logo (Change in runtime)" + config RT_GRAPHIC_LOGO_RT_THREAD_CLUT224 + bool "Standard 224-color RT-Thread logo" + + config RT_GRAPHIC_LOGO_RT_THREAD_WHITE_CLUT224 + bool "Standard 224-color RT-Thread white logo" + osource "$(SOC_DM_GRAPHIC_LOGO_DIR)/Kconfig" endchoice diff --git a/components/drivers/graphic/logo/SConscript b/components/drivers/graphic/logo/SConscript index 622ada04490..a481a4d557b 100644 --- a/components/drivers/graphic/logo/SConscript +++ b/components/drivers/graphic/logo/SConscript @@ -17,6 +17,12 @@ logo_width = 0 logo_height = 0 logo_max_val = 0 +if GetDepend(['RT_GRAPHIC_LOGO_RT_THREAD_CLUT224']): + logo_path = cwd + '/logo-rt-thread-clut224.ppm' + +if GetDepend(['RT_GRAPHIC_LOGO_RT_THREAD_WHITE_CLUT224']): + logo_path = cwd + '/logo-rt-thread-white-clut224.ppm' + if logo_path == None: # Find in BSP paths = None diff --git a/components/drivers/graphic/logo/logo-rt-thread-clut224.ppm b/components/drivers/graphic/logo/logo-rt-thread-clut224.ppm new file mode 100644 index 00000000000..43bf8e44e90 --- /dev/null +++ b/components/drivers/graphic/logo/logo-rt-thread-clut224.ppm @@ -0,0 +1,1597 @@ +P3 +# Standard 224-color RT-Thread logo +212 59 +255 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 8 9 +7 23 23 10 39 40 16 61 62 21 79 81 26 98 100 30 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92 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 23 23 +176 176 176 202 202 202 200 200 200 201 201 201 197 197 197 58 58 58 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 23 23 23 176 176 176 202 202 202 200 200 200 +201 201 201 196 196 196 57 57 57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 99 99 +203 203 203 200 200 200 200 200 200 203 203 203 149 149 149 7 7 7 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 131 131 131 +204 204 204 200 200 200 200 200 200 204 204 204 122 122 122 0 0 0 3 3 3 135 135 135 +204 204 204 200 200 200 200 200 200 203 203 203 110 110 110 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 26 26 26 105 105 105 173 173 173 199 199 199 200 200 200 200 200 200 +200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 +200 200 200 200 200 200 201 201 201 193 193 193 50 50 50 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 39 39 39 123 123 123 182 182 182 200 200 200 200 200 200 200 200 200 +200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 +200 200 200 200 200 200 202 202 202 173 173 173 21 21 21 0 0 0 0 0 0 0 0 0 +0 0 0 2 2 2 55 55 55 138 138 138 189 189 189 201 201 201 200 200 200 200 200 200 +200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 +200 200 200 200 200 200 202 202 202 164 164 164 From 24712cab97ab4cdb766844504cacb16d8eaa4a3d Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Sat, 13 Dec 2025 01:21:48 +0800 Subject: [PATCH 18/20] [dm][core] add common machine power interface Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/core/SConscript | 2 +- components/drivers/core/power.c | 311 ++++++++++++++++++ .../drivers/include/drivers/core/power.h | 47 +++ components/drivers/include/rtdevice.h | 1 + 4 files changed, 360 insertions(+), 1 deletion(-) create mode 100644 components/drivers/core/power.c create mode 100644 components/drivers/include/drivers/core/power.h diff --git a/components/drivers/core/SConscript b/components/drivers/core/SConscript index 216f9a03483..392487c6aa3 100644 --- a/components/drivers/core/SConscript +++ b/components/drivers/core/SConscript @@ -8,7 +8,7 @@ if GetDepend(['RT_USING_DEV_BUS']) or GetDepend(['RT_USING_DM']): src = src + ['bus.c'] if GetDepend(['RT_USING_DM']): - src = src + ['dm.c', 'driver.c', 'numa.c', 'platform.c', 'power_domain.c'] + src = src + ['dm.c', 'driver.c', 'numa.c', 'platform.c', 'power.c', 'power_domain.c'] if GetDepend(['RT_USING_DFS']): src += ['mnt.c']; diff --git a/components/drivers/core/power.c b/components/drivers/core/power.c new file mode 100644 index 00000000000..038e37c5072 --- /dev/null +++ b/components/drivers/core/power.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-09-24 GuEe-GUI the first version + */ + +#include + +#define DBG_TAG "rtdm.power" +#define DBG_LVL DBG_INFO +#include + +struct power_off_track +{ + rt_slist_t list; + + struct rt_device *dev; + rt_err_t (*callback)(struct rt_device *); +}; + +void (*rt_dm_machine_shutdown)(void) = RT_NULL; +void (*rt_dm_machine_reset)(void) = RT_NULL; + +static RT_DEFINE_SPINLOCK(_power_off_lock); +static rt_slist_t _power_off_handler_nodes[RT_DM_POWER_OFF_MODE_NR][RT_DM_POWER_OFF_PRIO_NR] = +{ + [0 ... RT_DM_POWER_OFF_MODE_NR - 1] = + { + [0 ... RT_DM_POWER_OFF_PRIO_NR - 1] = + { + RT_NULL, + } + } +}; + +static rt_used char * const _mode_name[] = +{ + [RT_DM_POWER_OFF_MODE_SHUTDOWN] = "SHUTDOWN", + [RT_DM_POWER_OFF_MODE_RESET] = "RESET", +}; + +rt_err_t rt_dm_power_off_handler(struct rt_device *dev, int mode, int priority, + rt_err_t (*callback)(struct rt_device *dev)) +{ + struct power_off_track *track; + + RT_ASSERT(mode < RT_DM_POWER_OFF_MODE_NR); + RT_ASSERT(priority < RT_DM_POWER_OFF_PRIO_NR); + + track = rt_malloc(sizeof(*track)); + + if (!track) + { + return -RT_ENOMEM; + } + + rt_slist_init(&track->list); + track->dev = dev; + track->callback = callback; + + rt_hw_spin_lock(&_power_off_lock.lock); + + rt_slist_insert(&_power_off_handler_nodes[mode][priority], &track->list); + + rt_hw_spin_unlock(&_power_off_lock.lock); + + return RT_EOK; +} + +static void dm_power_off_handler(int mode) +{ + struct power_off_track *track; + + rt_hw_spin_lock(&_power_off_lock.lock); + + for (int i = 0; i < RT_DM_POWER_OFF_PRIO_NR; ++i) + { + rt_slist_t *nodes = &_power_off_handler_nodes[mode][i]; + + rt_slist_for_each_entry(track, nodes, list) + { + rt_err_t err; + struct rt_device *dev = track->dev; + + if ((err = track->callback(dev))) + { + LOG_E("%s: %s fail error = %s", dev ? rt_dm_dev_get_name(dev) : RT_NULL, + _mode_name[mode], rt_strerror(err)); + } + } + } + + rt_hw_spin_unlock(&_power_off_lock.lock); +} + +struct reboot_mode_track +{ + rt_slist_t list; + + struct rt_device *dev; + rt_err_t (*callback)(struct rt_device *, char *cmd); +}; + +static char *_reboot_mode_cmd = "normal"; +static RT_DEFINE_SPINLOCK(_reboot_mode_lock); +static rt_slist_t _reboot_mode_handler_nodes = { RT_NULL }; + +rt_err_t rt_dm_reboot_mode_register(struct rt_device *dev, + rt_err_t (*callback)(struct rt_device *, char *cmd)) +{ + struct reboot_mode_track *track; + + track = rt_malloc(sizeof(*track)); + + if (!track) + { + return -RT_ENOMEM; + } + + rt_slist_init(&track->list); + track->dev = dev; + track->callback = callback; + + rt_hw_spin_lock(&_reboot_mode_lock.lock); + + rt_slist_insert(&_reboot_mode_handler_nodes, &track->list); + + rt_hw_spin_unlock(&_reboot_mode_lock.lock); + + return RT_EOK; +} + +rt_err_t rt_dm_reboot_mode_unregister(struct rt_device *dev) +{ + struct reboot_mode_track *track, *target_track = RT_NULL; + + rt_hw_spin_lock(&_reboot_mode_lock.lock); + + rt_slist_for_each_entry(track, &_reboot_mode_handler_nodes, list) + { + if (track->dev == dev) + { + target_track = track; + rt_slist_remove(&_reboot_mode_handler_nodes, &track->list); + break; + } + } + + rt_hw_spin_unlock(&_reboot_mode_lock.lock); + + if (target_track) + { + rt_free(target_track); + } + + return target_track ? RT_EOK : -RT_EEMPTY; +} + +static rt_err_t dm_reboot_notifiy(struct rt_device *request_dev) +{ + struct reboot_mode_track *track; + + rt_hw_spin_lock(&_reboot_mode_lock.lock); + + rt_slist_for_each_entry(track, &_reboot_mode_handler_nodes, list) + { + rt_err_t err; + struct rt_device *dev = track->dev; + + if ((err = track->callback(dev, _reboot_mode_cmd))) + { + LOG_E("%s: %s fail error = %s", dev ? rt_dm_dev_get_name(dev) : RT_NULL, + "reboot mode apply", rt_strerror(err)); + } + } + + rt_hw_spin_unlock(&_reboot_mode_lock.lock); + + return RT_EOK; +} + +static int reboot_mode_init(void) +{ + return rt_dm_power_off_handler(RT_NULL, RT_DM_POWER_OFF_MODE_RESET, + RT_DM_POWER_OFF_PRIO_HIGH, &dm_reboot_notifiy); +} +INIT_CORE_EXPORT(reboot_mode_init); + +void rt_hw_cpu_reset_mode(char *cmd) +{ + static RT_DEFINE_SPINLOCK(pe_lock); + + rt_hw_spin_lock(&pe_lock.lock); + + _reboot_mode_cmd = cmd ? : _reboot_mode_cmd; + + rt_hw_cpu_reset(); + + /* Unreachable */ + rt_hw_spin_unlock(&pe_lock.lock); +} + +static struct rt_thread power_task; +static void power_task_async(void (*fn)(void)); + +rt_inline rt_bool_t power_need_async(void) +{ + struct rt_thread *tid = rt_thread_self(); + + return tid && tid != &power_task && rt_interrupt_get_nest(); +} + +void rt_hw_cpu_shutdown(void) +{ + register rt_ubase_t level; + + if (power_need_async()) + { + power_task_async(&rt_hw_cpu_shutdown); + + return; + } + + dm_power_off_handler(RT_DM_POWER_OFF_MODE_SHUTDOWN); + + LOG_I("Shutdown"); + + /* Machine shutdown */ + if (rt_dm_machine_shutdown) + { + rt_dm_machine_shutdown(); + } + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, shutdown, shutdown machine); + +void rt_hw_cpu_reset(void) +{ + register rt_ubase_t level; + + if (power_need_async()) + { + power_task_async(&rt_hw_cpu_reset); + + return; + } + + dm_power_off_handler(RT_DM_POWER_OFF_MODE_RESET); + + LOG_I("Reset"); + + /* Machine reset */ + if (rt_dm_machine_reset) + { + rt_dm_machine_reset(); + } + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +static int reset(int args, char**argv) +{ + if (args > 1) + { + rt_hw_cpu_reset_mode(argv[1]); + } + else + { + rt_hw_cpu_reset(); + } + + return 0; +} +MSH_CMD_EXPORT(reset, reset machine); + +static void power_task_entry(void *param) +{ + void (*fn)(void) = rt_thread_self()->parameter; + + fn(); +} + +static void power_task_async(void (*fn)(void)) +{ + power_task.parameter = fn; + + rt_thread_startup(&power_task); +} + +static int power_init(void) +{ + static rt_uint8_t power_task_stack[DM_THREAD_STACK_SIZE]; + + return rt_thread_init(&power_task, "pwr", power_task_entry, RT_NULL, + &power_task_stack, sizeof(power_task_stack), + RT_THREAD_PRIORITY_MAX / 2, 32); +} +INIT_CORE_EXPORT(power_init); diff --git a/components/drivers/include/drivers/core/power.h b/components/drivers/include/drivers/core/power.h new file mode 100644 index 00000000000..2d4f3c3fb82 --- /dev/null +++ b/components/drivers/include/drivers/core/power.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-09-24 GuEe-GUI the first version + */ + +#ifndef __RT_DM_POWER_H__ +#define __RT_DM_POWER_H__ + +#include + +enum rt_dm_power_off_mode +{ + RT_DM_POWER_OFF_MODE_SHUTDOWN, + RT_DM_POWER_OFF_MODE_RESET, + + RT_DM_POWER_OFF_MODE_NR, +}; + +enum rt_dm_power_off_priority +{ + RT_DM_POWER_OFF_PRIO_PLATFORM, + RT_DM_POWER_OFF_PRIO_LOW, + RT_DM_POWER_OFF_PRIO_DEFAULT, + RT_DM_POWER_OFF_PRIO_HIGH, + RT_DM_POWER_OFF_PRIO_FIRMWARE, + + RT_DM_POWER_OFF_PRIO_NR, +}; + +rt_err_t rt_dm_power_off_handler(struct rt_device *dev, int mode, int priority, + rt_err_t (*callback)(struct rt_device *)); + +rt_err_t rt_dm_reboot_mode_register(struct rt_device *dev, + rt_err_t (*callback)(struct rt_device *, char *cmd)); +rt_err_t rt_dm_reboot_mode_unregister(struct rt_device *dev); + +void rt_hw_cpu_reset_mode(char *cmd); + +extern void (*rt_dm_machine_shutdown)(void); +extern void (*rt_dm_machine_reset)(void); + +#endif /* __RT_DM_POWER_H__ */ diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index 89af4b933c0..cd4ef4f4447 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -42,6 +42,7 @@ extern "C" { #ifdef RT_USING_DM #include "drivers/core/dm.h" #include "drivers/core/numa.h" +#include "drivers/core/power.h" #include "drivers/core/power_domain.h" #include "drivers/platform.h" From de8f63ee9e7fa8103fcc3e972b7f4601f9c769d8 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Mon, 15 Dec 2025 15:40:17 +0800 Subject: [PATCH 19/20] [dm][scsi] Add parallel_io option for SCSI host Some SCSI supported parallel_io = RT_TRUE, like UFS. Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/include/drivers/scsi.h | 1 + components/drivers/scsi/scsi_cdrom.c | 2 +- components/drivers/scsi/scsi_sd.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/components/drivers/include/drivers/scsi.h b/components/drivers/include/drivers/scsi.h index 7b6baaf54e5..9870f308bc7 100644 --- a/components/drivers/include/drivers/scsi.h +++ b/components/drivers/include/drivers/scsi.h @@ -372,6 +372,7 @@ struct rt_scsi_host rt_size_t max_id; rt_size_t max_lun; + rt_bool_t parallel_io; rt_list_t lun_nodes; }; diff --git a/components/drivers/scsi/scsi_cdrom.c b/components/drivers/scsi/scsi_cdrom.c index 93608d1e37c..5549580b621 100644 --- a/components/drivers/scsi/scsi_cdrom.c +++ b/components/drivers/scsi/scsi_cdrom.c @@ -91,7 +91,7 @@ rt_err_t scsi_cdrom_probe(struct rt_scsi_device *sdev) scdrom->sdev = sdev; scdrom->parent.ida = &scsi_cdrom_ida; scdrom->parent.read_only = RT_TRUE; - scdrom->parent.parallel_io = RT_FALSE; + scdrom->parent.parallel_io = sdev->host->parallel_io; scdrom->parent.ops = &scsi_cdrom_ops; scdrom->parent.max_partitions = RT_BLK_PARTITION_NONE; diff --git a/components/drivers/scsi/scsi_sd.c b/components/drivers/scsi/scsi_sd.c index cc509a72154..4a3c501f3ce 100644 --- a/components/drivers/scsi/scsi_sd.c +++ b/components/drivers/scsi/scsi_sd.c @@ -205,7 +205,7 @@ rt_err_t scsi_sd_probe(struct rt_scsi_device *sdev) sdev->priv = ssd; ssd->sdev = sdev; ssd->parent.ida = &scsi_sd_ida; - ssd->parent.parallel_io = RT_FALSE; + ssd->parent.parallel_io = sdev->host->parallel_io; ssd->parent.ops = &scsi_sd_ops; ssd->parent.max_partitions = RT_BLK_PARTITION_MAX; From b425d69fabfc244a768e2e2dda09d90f409f2f50 Mon Sep 17 00:00:00 2001 From: Chuan Date: Sun, 14 Dec 2025 22:13:55 +0800 Subject: [PATCH 20/20] [utest][mm_api]:Add standardized documentation for MM API lwp Test --- examples/utest/testcases/mm/mm_lwp_tc.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/examples/utest/testcases/mm/mm_lwp_tc.c b/examples/utest/testcases/mm/mm_lwp_tc.c index 6f9bb112bf9..d38a27341dc 100644 --- a/examples/utest/testcases/mm/mm_lwp_tc.c +++ b/examples/utest/testcases/mm/mm_lwp_tc.c @@ -6,6 +6,42 @@ * Change Logs: * Date Author Notes * 2023-03-27 WangXiaoyao testcase for lwp + * 2025-12-14 ChuanN-sudo Add standardized utest documentation block + */ + +/** + * Test Case Name: MM API lwp Test + * + * Test Objectives: + * - Verify LWP user space virtual area mapping functionality. + * - Test user memory accessibility checking mechanisms. + * - Test core APIs: lwp_create(), lwp_user_space_init(), lwp_map_user_varea(), + * lwp_map_user_varea_ext(), lwp_user_accessible_ext(), lwp_ref_dec() + * + * Test Scenarios: + * - User Map Varea Test (user_map_varea_tc): + * - test_user_map_varea(): Creates LWP, initializes user space, maps virtual area with default flags, verifies varea properties (cached, private mapping). + * - test_user_map_varea_ext(): Creates LWP, maps virtual area with NOCACHE flag, verifies uncached memory attributes. + * - Accessible Test (accessible_tc): + * - test_user_accessible(): Creates LWP with user stack, tests accessibility checks for unmapped and mapped memory regions. + * + * Verification Metrics: + * - Virtual areas should be correctly inserted with proper ordering. + * - Default mapping should have cached attributes (MMU_MAP_U_RWCB). + * - NOCACHE mapping should have uncached attributes (MMU_MAP_U_RW). + * - Virtual addresses should be within user space range. + * - Accessibility check should return false for unmapped memory, true for mapped memory. + * + * Dependencies: + * - Hardware requirements: QEMU emulator or any hardware platform that supports RT-Thread with MMU. + * - Software configuration: + * - RT_UTEST_MM_LWP must be enabled (enable via: RT-Thread Utestcases -> RT-Thread Utestcases -> Memory Management Subsystem Testcase -> Enable Utest for MM API in lwp). + * - RT_USING_SMART must be enabled (enable via: Enable RT-Thread Kernel -> RT-Thread Smart (microkernel on kernel/userland)). + * - Environmental Assumptions: MMU support must be available on the target platform. + * + * Expected Results: + * - Final output: "[ PASSED ] [ result ] testcase (testcases.lwp.mm_tc)" + * - No assertion failures during test execution. */ #include "common.h"